stm32/wpan: convert to new ipcc

1 files changed, 189 insertions, 85 deletions

diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 28f51baa5..609c4d2c3 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -1,7 +1,77 @@
+use core::future::poll_fn;
+use core::task::Poll;
+
+use atomic_polyfill::{compiler_fence, Ordering};
+
 use self::sealed::Instance;
+use crate::interrupt;
+use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::IPCC;
 use crate::rcc::sealed::RccPeripheral;
 
+/// Interrupt handler.
+pub struct ReceiveInterruptHandler {}
+
+impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for ReceiveInterruptHandler {
+    unsafe fn on_interrupt() {
+        let regs = IPCC::regs();
+
+        let channels = [
+            IpccChannel::Channel1,
+            IpccChannel::Channel2,
+            IpccChannel::Channel3,
+            IpccChannel::Channel4,
+            IpccChannel::Channel5,
+            IpccChannel::Channel6,
+        ];
+
+        // Status register gives channel occupied status. For rx, use cpu1.
+        let sr = unsafe { regs.cpu(1).sr().read() };
+        regs.cpu(0).mr().modify(|w| {
+            for channel in channels {
+                if sr.chf(channel as usize) {
+                    // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
+                    w.set_chom(channel as usize, true);
+
+                    // There shouldn't be a race because the channel is masked only if the interrupt has fired
+                    IPCC::state().rx_waker_for(channel).wake();
+                }
+            }
+        })
+    }
+}
+
+pub struct TransmitInterruptHandler {}
+
+impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for TransmitInterruptHandler {
+    unsafe fn on_interrupt() {
+        let regs = IPCC::regs();
+
+        let channels = [
+            IpccChannel::Channel1,
+            IpccChannel::Channel2,
+            IpccChannel::Channel3,
+            IpccChannel::Channel4,
+            IpccChannel::Channel5,
+            IpccChannel::Channel6,
+        ];
+
+        // Status register gives channel occupied status. For tx, use cpu0.
+        let sr = unsafe { regs.cpu(0).sr().read() };
+        regs.cpu(0).mr().modify(|w| {
+            for channel in channels {
+                if !sr.chf(channel as usize) {
+                    // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
+                    w.set_chfm(channel as usize, true);
+
+                    // There shouldn't be a race because the channel is masked only if the interrupt has fired
+                    IPCC::state().tx_waker_for(channel).wake();
+                }
+            }
+        });
+    }
+}
+
 #[non_exhaustive]
 #[derive(Clone, Copy, Default)]
 pub struct Config {
@@ -20,13 +90,6 @@ pub enum IpccChannel {
     Channel6 = 5,
 }
 
-pub mod sealed {
-    pub trait Instance: crate::rcc::RccPeripheral {
-        fn regs() -> crate::pac::ipcc::Ipcc;
-        fn set_cpu2(enabled: bool);
-    }
-}
-
 pub struct Ipcc;
 
 impl Ipcc {
@@ -45,129 +108,170 @@ impl Ipcc {
                 w.set_txfie(true);
             })
         }
-    }
 
-    pub fn c1_set_rx_channel(channel: IpccChannel, enabled: bool) {
-        let regs = IPCC::regs();
+        // enable interrupts
+        crate::interrupt::typelevel::IPCC_C1_RX::unpend();
+        crate::interrupt::typelevel::IPCC_C1_TX::unpend();
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
+        unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
+        unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
     }
 
-    pub fn c1_get_rx_channel(channel: IpccChannel) -> bool {
+    /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
+    pub async fn send(channel: IpccChannel, f: impl FnOnce()) {
         let regs = IPCC::regs();
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { !regs.cpu(0).mr().read().chom(channel as usize) }
-    }
+        Self::flush(channel).await;
+        compiler_fence(Ordering::SeqCst);
 
-    #[allow(dead_code)]
-    pub fn c2_set_rx_channel(channel: IpccChannel, enabled: bool) {
-        let regs = IPCC::regs();
-
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { regs.cpu(1).mr().modify(|w| w.set_chom(channel as usize, !enabled)) }
-    }
+        f();
 
-    #[allow(dead_code)]
-    pub fn c2_get_rx_channel(channel: IpccChannel) -> bool {
-        let regs = IPCC::regs();
+        compiler_fence(Ordering::SeqCst);
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { !regs.cpu(1).mr().read().chom(channel as usize) }
+        trace!("ipcc: ch {}: send data", channel as u8);
+        unsafe { regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true)) }
     }
 
-    pub fn c1_set_tx_channel(channel: IpccChannel, enabled: bool) {
+    /// Wait for the tx channel to become clear
+    pub async fn flush(channel: IpccChannel) {
         let regs = IPCC::regs();
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
-    }
+        // This is a race, but is nice for debugging
+        if unsafe { regs.cpu(0).sr().read() }.chf(channel as usize) {
+            trace!("ipcc: ch {}:  wait for tx free", channel as u8);
+        }
 
-    pub fn c1_get_tx_channel(channel: IpccChannel) -> bool {
-        let regs = IPCC::regs();
+        poll_fn(|cx| {
+            IPCC::state().tx_waker_for(channel).register(cx.waker());
+            // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
+            unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, false)) }
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { !regs.cpu(0).mr().read().chfm(channel as usize) }
-    }
+            compiler_fence(Ordering::SeqCst);
 
-    #[allow(dead_code)]
-    pub fn c2_set_tx_channel(channel: IpccChannel, enabled: bool) {
-        let regs = IPCC::regs();
+            if !unsafe { regs.cpu(0).sr().read() }.chf(channel as usize) {
+                // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
+                unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true)) }
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { regs.cpu(1).mr().modify(|w| w.set_chfm(channel as usize, !enabled)) }
+                Poll::Ready(())
+            } else {
+                Poll::Pending
+            }
+        })
+        .await;
     }
 
-    #[allow(dead_code)]
-    pub fn c2_get_tx_channel(channel: IpccChannel) -> bool {
+    /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
+    pub async fn receive<R>(channel: IpccChannel, mut f: impl FnMut() -> Option<R>) -> R {
         let regs = IPCC::regs();
 
-        // If bit is set to 1 then interrupt is disabled
-        unsafe { !regs.cpu(1).mr().read().chfm(channel as usize) }
-    }
+        loop {
+            // This is a race, but is nice for debugging
+            if !unsafe { regs.cpu(1).sr().read() }.chf(channel as usize) {
+                trace!("ipcc: ch {}:  wait for rx occupied", channel as u8);
+            }
 
-    /// clears IPCC receive channel status for CPU1
-    pub fn c1_clear_flag_channel(channel: IpccChannel) {
-        let regs = IPCC::regs();
+            poll_fn(|cx| {
+                IPCC::state().rx_waker_for(channel).register(cx.waker());
+                // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
+                unsafe { regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, false)) }
 
-        trace!("ipcc: ch {}: clear rx", channel as u8);
-        unsafe { regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true)) }
-    }
+                compiler_fence(Ordering::SeqCst);
 
-    #[allow(dead_code)]
-    /// clears IPCC receive channel status for CPU2
-    pub fn c2_clear_flag_channel(channel: IpccChannel) {
-        let regs = IPCC::regs();
+                if unsafe { regs.cpu(1).sr().read() }.chf(channel as usize) {
+                    // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
+                    unsafe { regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true)) }
 
-        unsafe { regs.cpu(1).scr().write(|w| w.set_chc(channel as usize, true)) }
-    }
+                    Poll::Ready(())
+                } else {
+                    Poll::Pending
+                }
+            })
+            .await;
 
-    pub fn c1_set_flag_channel(channel: IpccChannel) {
-        let regs = IPCC::regs();
+            trace!("ipcc: ch {}:  read data", channel as u8);
+            compiler_fence(Ordering::SeqCst);
 
-        unsafe { regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true)) }
-    }
+            match f() {
+                Some(ret) => return ret,
+                None => {}
+            }
 
-    #[allow(dead_code)]
-    pub fn c2_set_flag_channel(channel: IpccChannel) {
-        let regs = IPCC::regs();
+            trace!("ipcc: ch {}: clear rx", channel as u8);
+            compiler_fence(Ordering::SeqCst);
+            // If the channel is clear and the read function returns none, fetch more data
+            unsafe { regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true)) }
+        }
+    }
+}
 
-        unsafe { regs.cpu(1).scr().write(|w| w.set_chs(channel as usize, true)) }
+impl sealed::Instance for crate::peripherals::IPCC {
+    fn regs() -> crate::pac::ipcc::Ipcc {
+        crate::pac::IPCC
     }
 
-    pub fn c1_is_active_flag(channel: IpccChannel) -> bool {
-        let regs = IPCC::regs();
+    fn set_cpu2(enabled: bool) {
+        unsafe { crate::pac::PWR.cr4().modify(|w| w.set_c2boot(enabled)) }
+    }
 
-        unsafe { regs.cpu(0).sr().read().chf(channel as usize) }
+    fn state() -> &'static self::sealed::State {
+        static STATE: self::sealed::State = self::sealed::State::new();
+        &STATE
     }
+}
 
-    pub fn c2_is_active_flag(channel: IpccChannel) -> bool {
-        let regs = IPCC::regs();
+pub(crate) mod sealed {
+    use embassy_sync::waitqueue::AtomicWaker;
 
-        unsafe { regs.cpu(1).sr().read().chf(channel as usize) }
-    }
+    use super::*;
 
-    pub fn is_tx_pending(channel: IpccChannel) -> bool {
-        !Self::c1_is_active_flag(channel) && Self::c1_get_tx_channel(channel)
+    pub struct State {
+        rx_wakers: [AtomicWaker; 6],
+        tx_wakers: [AtomicWaker; 6],
     }
 
-    pub fn is_rx_pending(channel: IpccChannel) -> bool {
-        Self::c2_is_active_flag(channel) && Self::c1_get_rx_channel(channel)
-    }
-}
+    impl State {
+        pub const fn new() -> Self {
+            const WAKER: AtomicWaker = AtomicWaker::new();
 
-impl sealed::Instance for crate::peripherals::IPCC {
-    fn regs() -> crate::pac::ipcc::Ipcc {
-        crate::pac::IPCC
+            Self {
+                rx_wakers: [WAKER; 6],
+                tx_wakers: [WAKER; 6],
+            }
+        }
+
+        pub fn rx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
+            match channel {
+                IpccChannel::Channel1 => &self.rx_wakers[0],
+                IpccChannel::Channel2 => &self.rx_wakers[1],
+                IpccChannel::Channel3 => &self.rx_wakers[2],
+                IpccChannel::Channel4 => &self.rx_wakers[3],
+                IpccChannel::Channel5 => &self.rx_wakers[4],
+                IpccChannel::Channel6 => &self.rx_wakers[5],
+            }
+        }
+
+        pub fn tx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
+            match channel {
+                IpccChannel::Channel1 => &self.tx_wakers[0],
+                IpccChannel::Channel2 => &self.tx_wakers[1],
+                IpccChannel::Channel3 => &self.tx_wakers[2],
+                IpccChannel::Channel4 => &self.tx_wakers[3],
+                IpccChannel::Channel5 => &self.tx_wakers[4],
+                IpccChannel::Channel6 => &self.tx_wakers[5],
+            }
+        }
     }
 
-    fn set_cpu2(enabled: bool) {
-        unsafe { crate::pac::PWR.cr4().modify(|w| w.set_c2boot(enabled)) }
+    pub trait Instance: crate::rcc::RccPeripheral {
+        fn regs() -> crate::pac::ipcc::Ipcc;
+        fn set_cpu2(enabled: bool);
+        fn state() -> &'static State;
     }
 }
 
 unsafe fn _configure_pwr() {
+    // TODO: move this to RCC
+
     let pwr = crate::pac::PWR;
     let rcc = crate::pac::RCC;