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authorLiu Hancheng <[email protected]>2025-01-05 20:00:15 +0800
committerLiu Hancheng <[email protected]>2025-01-05 20:00:15 +0800
commite15e30add2c483b0154af1c8b6f7fcbf0bcd7d7d (patch)
tree20d11ec1b91134ecee9c520b6b55925fd16c8bd2 /embassy-stm32/src/qspi
parentad2f7c329bbbefc0e3be38b36627705a5f42427b (diff)
fix: fix qspi waiting condition
Diffstat (limited to 'embassy-stm32/src/qspi')
-rw-r--r--embassy-stm32/src/qspi/mod.rs7
1 files changed, 5 insertions, 2 deletions
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 0c65d0556..ffa9798b8 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -172,7 +172,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
172 }); 172 });
173 173
174 for b in buf { 174 for b in buf {
175 while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {} 175 while !T::REGS.sr().read().tcf() && (T::REGS.sr().read().flevel() == 0) {}
176 *b = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() }; 176 *b = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() };
177 } 177 }
178 178
@@ -402,7 +402,10 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
402 402
403 // STM32H7 does not have dmaen 403 // STM32H7 does not have dmaen
404 #[cfg(not(stm32h7))] 404 #[cfg(not(stm32h7))]
405 T::REGS.cr().modify(|v| v.set_dmaen(true)); 405 T::REGS.cr().modify(|v| {
406 v.set_en(true);
407 v.set_dmaen(true)
408 });
406 transfer 409 transfer
407 } 410 }
408 411