diff options
| author | pbert <[email protected]> | 2023-10-11 21:38:41 +0200 |
|---|---|---|
| committer | pbert <[email protected]> | 2023-10-12 11:04:44 +0200 |
| commit | ecdd7c0e2f9dcc07e53e136557140d3ccc6a5ee1 (patch) | |
| tree | 6db9bf875d3e83d94f6bf8e8a2e7ff03a83c5bb4 /embassy-stm32/src/qspi | |
| parent | d7d79f3068a4a2d883b078b8900ad194f7c98203 (diff) | |
enable clock first
Diffstat (limited to 'embassy-stm32/src/qspi')
| -rw-r--r-- | embassy-stm32/src/qspi/mod.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs index 1c8bcbae9..4b0e8ecef 100644 --- a/embassy-stm32/src/qspi/mod.rs +++ b/embassy-stm32/src/qspi/mod.rs | |||
| @@ -177,7 +177,7 @@ impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> { | |||
| 177 | ) -> Self { | 177 | ) -> Self { |
| 178 | into_ref!(peri, dma); | 178 | into_ref!(peri, dma); |
| 179 | 179 | ||
| 180 | T::reset_and_enable(); | 180 | T::enable_and_reset(); |
| 181 | 181 | ||
| 182 | while T::REGS.sr().read().busy() {} | 182 | while T::REGS.sr().read().busy() {} |
| 183 | 183 | ||