Fix dma nvic issues on dual core lines

This commit addresses #3256 by disabling dma NVIC interrupt enablement at startup.
Instead, per-channel NVIC interrupt enablement is now done with the rest of the dma channel configuration.
This ensures that each core will only handle the interrupts of the DMA channels that it uses.

1 files changed, 2 insertions, 0 deletions

diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index 61f687d30..58056301a 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -63,6 +63,7 @@ pub struct Pll {
 /// Used to calculate flash waitstates. See
 /// RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock frequency
 #[cfg(stm32f2)]
+#[derive(Clone, Copy)]
 pub enum VoltageScale {
     /// 2.7 to 3.6 V
     Range0,
@@ -76,6 +77,7 @@ pub enum VoltageScale {
 
 /// Configuration of the core clocks
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
     pub hsi: bool,
     pub hse: Option<Hse>,