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authorobe1line <[email protected]>2025-07-21 14:31:48 +1000
committerGitHub <[email protected]>2025-07-21 14:31:48 +1000
commitac996e7e0a08f0a8914c76e4ee040e75a4b2b19b (patch)
tree6549f7ab30fd860276f9dca1d0815b8610b968a5 /embassy-stm32/src/rcc
parent6bfdbf0ed827da7ab447359f97799cc1b707fde9 (diff)
Added ccipr1 conditional for STM32C071
Diffstat (limited to 'embassy-stm32/src/rcc')
-rw-r--r--embassy-stm32/src/rcc/c0.rs8
1 files changed, 6 insertions, 2 deletions
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index cac2a9149..5a584d993 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -192,8 +192,12 @@ pub(crate) unsafe fn init(config: Config) {
192 lse: None, 192 lse: None,
193 ); 193 );
194 194
195 RCC.ccipr() 195 #[cfg(not(any(stm32c071)))]
196 .modify(|w| w.set_adc1sel(stm32_metapac::rcc::vals::Adcsel::SYS)); 196 let r = RCC.ccipr();
197 #[cfg(any(stm32c071))]
198 let r = RCC.ccipr1();
199
200 r.modify(|w| w.set_adc1sel(stm32_metapac::rcc::vals::Adcsel::SYS));
197} 201}
198 202
199mod max { 203mod max {