update metapac after stm32-data PR323

and refactor a few code with cargo clippy

2 files changed, 8 insertions, 8 deletions

diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 91f08fae4..1eda097a7 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Init, Osel, Pol};
+use stm32_metapac::rtc::vals::{Osel, Pol};
 
 use super::sealed;
 use crate::pac::rtc::Rtc;
@@ -49,7 +49,7 @@ impl super::Rtc {
             clock_drift = RTC_CALR_MAX_PPM;
         }
 
-        clock_drift = clock_drift / RTC_CALR_RESOLUTION_PPM;
+        clock_drift /= RTC_CALR_RESOLUTION_PPM;
 
         self.write(false, |rtc| {
             rtc.calr().write(|w| {
@@ -107,7 +107,7 @@ impl super::Rtc {
         // true if initf bit indicates RTC peripheral is in init mode
         if init_mode && !r.isr().read().initf() {
             // to update calendar date/time, time format, and prescaler configuration, RTC must be in init mode
-            r.isr().modify(|w| w.set_init(Init::INITMODE));
+            r.isr().modify(|w| w.set_init(true));
             // wait till init state entered
             // ~2 RTCCLK cycles
             while !r.isr().read().initf() {}
@@ -116,7 +116,7 @@ impl super::Rtc {
         let result = f(&r);
 
         if init_mode {
-            r.isr().modify(|w| w.set_init(Init::FREERUNNINGMODE)); // Exits init mode
+            r.isr().modify(|w| w.set_init(false)); // Exits init mode
         }
 
         // Re-enable write protection.
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index d2d0d9309..902776b0a 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
+use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Key, Osel, Pol, TampalrmType};
 
 use super::{sealed, RtcCalibrationCyclePeriod};
 use crate::pac::rtc::Rtc;
@@ -26,7 +26,7 @@ impl super::Rtc {
             rtc.cr().modify(|w| {
                 w.set_out2en(false);
                 w.set_tampalrm_type(TampalrmType::PUSHPULL);
-                w.set_tampalrm_pu(TampalrmPu::NOPULLUP);
+                w.set_tampalrm_pu(false);
             });
         });
     }
@@ -106,7 +106,7 @@ impl super::Rtc {
         r.wpr().write(|w| w.set_key(Key::DEACTIVATE2));
 
         if init_mode && !r.icsr().read().initf() {
-            r.icsr().modify(|w| w.set_init(Init::INITMODE));
+            r.icsr().modify(|w| w.set_init(true));
             // wait till init state entered
             // ~2 RTCCLK cycles
             while !r.icsr().read().initf() {}
@@ -115,7 +115,7 @@ impl super::Rtc {
         let result = f(&r);
 
         if init_mode {
-            r.icsr().modify(|w| w.set_init(Init::FREERUNNINGMODE)); // Exits init mode
+            r.icsr().modify(|w| w.set_init(false)); // Exits init mode
         }
 
         // Re-enable write protection.