stm32/spi: update for new version numbering, add i2s support for all versions.

1 files changed, 67 insertions, 67 deletions

diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 4c5308eba..a49ebcbee 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -174,7 +174,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
         self.info.rcc.enable_and_reset();
 
         let regs = self.info.regs;
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         {
             regs.cr2().modify(|w| {
                 w.set_ssoe(false);
@@ -198,7 +198,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_dff(<u8 as SealedWord>::CONFIG)
             });
         }
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         {
             regs.cr2().modify(|w| {
                 let (ds, frxth) = <u8 as SealedWord>::CONFIG;
@@ -220,7 +220,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_spe(true);
             });
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
             regs.ifcr().write(|w| w.0 = 0xffff_ffff);
             regs.cfg2().modify(|w| {
@@ -274,7 +274,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             }
         }
 
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         self.info.regs.cr1().modify(|w| {
             w.set_cpha(cpha);
             w.set_cpol(cpol);
@@ -282,7 +282,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             w.set_lsbfirst(lsbfirst);
         });
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         {
             self.info.regs.cr1().modify(|w| {
                 w.set_spe(false);
@@ -306,11 +306,11 @@ impl<'d, M: PeriMode> Spi<'d, M> {
 
     /// Get current SPI configuration.
     pub fn get_current_config(&self) -> Config {
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         let cfg = self.info.regs.cr1().read();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let cfg = self.info.regs.cfg2().read();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let cfg1 = self.info.regs.cfg1().read();
 
         let polarity = if cfg.cpol() == vals::Cpol::IDLE_LOW {
@@ -335,9 +335,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             Some(pin) => pin.pull(),
         };
 
-        #[cfg(any(spi_v1, spi_f1, spi_v2))]
+        #[cfg(any(spi_v1, spi_v2, spi_v3))]
         let br = cfg.br();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let br = cfg1.mbr();
 
         let frequency = compute_frequency(self.kernel_clock, br);
@@ -360,16 +360,16 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             w.set_spe(false);
         });
 
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         self.info.regs.cr1().modify(|reg| {
             reg.set_dff(word_size);
         });
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         self.info.regs.cr2().modify(|w| {
             w.set_frxth(word_size.1);
             w.set_ds(word_size.0);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cfg1().modify(|w| {
             w.set_dsize(word_size);
         });
@@ -380,7 +380,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// Blocking write.
     pub fn blocking_write<W: Word>(&mut self, words: &[W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -391,7 +391,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             // This is the case when the SPI has been created with `new_(blocking_?)txonly_nosck`.
             // See https://github.com/embassy-rs/embassy/issues/2902
             // This is not documented as an errata by ST, and I've been unable to find anything online...
-            #[cfg(not(any(spi_v1, spi_f1)))]
+            #[cfg(not(any(spi_v1, spi_v2)))]
             write_word(self.info.regs, *word)?;
 
             // if we're doing tx only, after writing the last byte to FIFO we have to wait
@@ -401,14 +401,14 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             // Luckily this doesn't affect SPIv2+.
             // See http://efton.sk/STM32/gotcha/g68.html
             // ST doesn't seem to document this in errata sheets (?)
-            #[cfg(any(spi_v1, spi_f1))]
+            #[cfg(any(spi_v1, spi_v2))]
             transfer_word(self.info.regs, *word)?;
         }
 
         // wait until last word is transmitted. (except on v1, see above)
-        #[cfg(not(any(spi_v1, spi_f1, spi_v2)))]
+        #[cfg(not(any(spi_v1, spi_v2, spi_v3)))]
         while !self.info.regs.sr().read().txc() {}
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         while self.info.regs.sr().read().bsy() {}
 
         Ok(())
@@ -417,7 +417,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// Blocking read.
     pub fn blocking_read<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -433,7 +433,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// This writes the contents of `data` on MOSI, and puts the received data on MISO in `data`, at the same time.
     pub fn blocking_transfer_in_place<W: Word>(&mut self, words: &mut [W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -452,7 +452,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     /// If `write` is shorter it is padded with zero bytes.
     pub fn blocking_transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
         // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| w.set_spe(false));
         self.set_word_size(W::CONFIG);
         self.info.regs.cr1().modify(|w| w.set_spe(true));
@@ -572,7 +572,7 @@ impl<'d> Spi<'d, Async> {
         peri: Peri<'d, T>,
         sck: Peri<'d, impl SckPin<T>>,
         miso: Peri<'d, impl MisoPin<T>>,
-        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: Peri<'d, impl TxDma<T>>,
+        #[cfg(any(spi_v1, spi_v2, spi_v3))] tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Self {
@@ -581,9 +581,9 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             None,
             new_pin!(miso, AfType::input(config.miso_pull)),
-            #[cfg(any(spi_v1, spi_f1, spi_v2))]
+            #[cfg(any(spi_v1, spi_v2, spi_v3))]
             new_dma!(tx_dma),
-            #[cfg(any(spi_v3, spi_v4, spi_v5))]
+            #[cfg(any(spi_v4, spi_v5, spi_v6))]
             None,
             new_dma!(rx_dma),
             config,
@@ -677,7 +677,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -690,7 +690,7 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// SPI read, using DMA.
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
         if data.is_empty() {
             return Ok(());
@@ -710,7 +710,7 @@ impl<'d> Spi<'d, Async> {
             prev
         });
 
-        #[cfg(spi_v3)]
+        #[cfg(spi_v4)]
         let i2scfg = regs.i2scfgr().modify(|w| {
             w.i2smod().then(|| {
                 let prev = w.i2scfg();
@@ -766,7 +766,7 @@ impl<'d> Spi<'d, Async> {
             w.set_tsize(0);
         });
 
-        #[cfg(spi_v3)]
+        #[cfg(spi_v4)]
         if let Some(i2scfg) = i2scfg {
             regs.i2scfgr().modify(|w| {
                 w.set_i2scfg(i2scfg);
@@ -777,7 +777,7 @@ impl<'d> Spi<'d, Async> {
     }
 
     /// SPI read, using DMA.
-    #[cfg(any(spi_v1, spi_f1, spi_v2))]
+    #[cfg(any(spi_v1, spi_v2, spi_v3))]
     pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
         if data.is_empty() {
             return Ok(());
@@ -790,7 +790,7 @@ impl<'d> Spi<'d, Async> {
         self.set_word_size(W::CONFIG);
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         flush_rx_fifo(self.info.regs);
 
         set_rxdmaen(self.info.regs, true);
@@ -813,7 +813,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -838,7 +838,7 @@ impl<'d> Spi<'d, Async> {
         self.set_word_size(W::CONFIG);
 
         // SPIv3 clears rxfifo on SPE=0
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         flush_rx_fifo(self.info.regs);
 
         set_rxdmaen(self.info.regs, true);
@@ -858,7 +858,7 @@ impl<'d> Spi<'d, Async> {
         self.info.regs.cr1().modify(|w| {
             w.set_spe(true);
         });
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         self.info.regs.cr1().modify(|w| {
             w.set_cstart(true);
         });
@@ -898,9 +898,9 @@ impl<'d, M: PeriMode> Drop for Spi<'d, M> {
     }
 }
 
-#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+#[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
 use vals::Br;
-#[cfg(any(spi_v3, spi_v4, spi_v5))]
+#[cfg(any(spi_v4, spi_v5, spi_v6))]
 use vals::Mbr as Br;
 
 fn compute_baud_rate(kernel_clock: Hertz, freq: Hertz) -> Br {
@@ -941,21 +941,21 @@ pub(crate) trait RegsExt {
 
 impl RegsExt for Regs {
     fn tx_ptr<W>(&self) -> *mut W {
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         let dr = self.dr();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let dr = self.dr16();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let dr = self.txdr32();
         dr.as_ptr() as *mut W
     }
 
     fn rx_ptr<W>(&self) -> *mut W {
-        #[cfg(any(spi_v1, spi_f1))]
+        #[cfg(any(spi_v1, spi_v2))]
         let dr = self.dr();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let dr = self.dr16();
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         let dr = self.rxdr32();
         dr.as_ptr() as *mut W
     }
@@ -965,22 +965,22 @@ fn check_error_flags(sr: regs::Sr, ovr: bool) -> Result<(), Error> {
     if sr.ovr() && ovr {
         return Err(Error::Overrun);
     }
-    #[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v1, spi_v4, spi_v5, spi_v6)))]
     if sr.fre() {
         return Err(Error::Framing);
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     if sr.tifre() {
         return Err(Error::Framing);
     }
     if sr.modf() {
         return Err(Error::ModeFault);
     }
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     if sr.crcerr() {
         return Err(Error::Crc);
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     if sr.crce() {
         return Err(Error::Crc);
     }
@@ -994,11 +994,11 @@ fn spin_until_tx_ready(regs: Regs, ovr: bool) -> Result<(), Error> {
 
         check_error_flags(sr, ovr)?;
 
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         if sr.txe() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         if sr.txp() {
             return Ok(());
         }
@@ -1011,11 +1011,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 
         check_error_flags(sr, true)?;
 
-        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
         if sr.rxne() {
             return Ok(());
         }
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         if sr.rxp() {
             return Ok(());
         }
@@ -1023,46 +1023,46 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
 }
 
 pub(crate) fn flush_rx_fifo(regs: Regs) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     while regs.sr().read().rxne() {
-        #[cfg(not(spi_v2))]
+        #[cfg(not(spi_v3))]
         let _ = regs.dr().read();
-        #[cfg(spi_v2)]
+        #[cfg(spi_v3)]
         let _ = regs.dr16().read();
     }
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     while regs.sr().read().rxp() {
         let _ = regs.rxdr32().read();
     }
 }
 
 pub(crate) fn set_txdmaen(regs: Regs, val: bool) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_txdmaen(val);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_txdmaen(val);
     });
 }
 
 pub(crate) fn set_rxdmaen(regs: Regs, val: bool) {
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_rxdmaen(val);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_rxdmaen(val);
     });
 }
 
 fn finish_dma(regs: Regs) {
-    #[cfg(spi_v2)]
+    #[cfg(spi_v3)]
     while regs.sr().read().ftlvl().to_bits() > 0 {}
 
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     {
         if regs.cr2().read().tsize() == 0 {
             while !regs.sr().read().txc() {}
@@ -1070,7 +1070,7 @@ fn finish_dma(regs: Regs) {
             while !regs.sr().read().eot() {}
         }
     }
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     while regs.sr().read().bsy() {}
 
     // Disable the spi peripheral
@@ -1080,12 +1080,12 @@ fn finish_dma(regs: Regs) {
 
     // The peripheral automatically disables the DMA stream on completion without error,
     // but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
-    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+    #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
     regs.cr2().modify(|reg| {
         reg.set_txdmaen(false);
         reg.set_rxdmaen(false);
     });
-    #[cfg(any(spi_v3, spi_v4, spi_v5))]
+    #[cfg(any(spi_v4, spi_v5, spi_v6))]
     regs.cfg1().modify(|reg| {
         reg.set_txdmaen(false);
         reg.set_rxdmaen(false);
@@ -1098,7 +1098,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
     unsafe {
         ptr::write_volatile(regs.tx_ptr(), tx_word);
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         regs.cr1().modify(|reg| reg.set_cstart(true));
     }
 
@@ -1117,7 +1117,7 @@ fn write_word<W: Word>(regs: Regs, tx_word: W) -> Result<(), Error> {
     unsafe {
         ptr::write_volatile(regs.tx_ptr(), tx_word);
 
-        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
         regs.cr1().modify(|reg| reg.set_cstart(true));
     }
     Ok(())
@@ -1225,7 +1225,7 @@ macro_rules! impl_word {
     };
 }
 
-#[cfg(any(spi_v1, spi_f1))]
+#[cfg(any(spi_v1, spi_v2))]
 mod word_impl {
     use super::*;
 
@@ -1235,7 +1235,7 @@ mod word_impl {
     impl_word!(u16, vals::Dff::BITS16);
 }
 
-#[cfg(spi_v2)]
+#[cfg(spi_v3)]
 mod word_impl {
     use super::*;
 
@@ -1256,7 +1256,7 @@ mod word_impl {
     impl_word!(u16, (vals::Ds::BITS16, vals::Frxth::HALF));
 }
 
-#[cfg(any(spi_v3, spi_v4, spi_v5))]
+#[cfg(any(spi_v4, spi_v5, spi_v6))]
 mod word_impl {
     use super::*;