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authorJan Špaček <[email protected]>2024-05-26 15:33:29 +0200
committerJan Špaček <[email protected]>2024-06-01 19:46:39 +0200
commitca3c15658dfb75945506c15070fd0deeb1583aa3 (patch)
tree4e30c9ea8d9b543374457e274905171d51733ac3 /embassy-stm32/src/spi
parente61136fa4ab0261ec9d9e262e1c3295d4549fa5f (diff)
stm32/spi: move init code to function that's not generic in T
Diffstat (limited to 'embassy-stm32/src/spi')
-rw-r--r--embassy-stm32/src/spi/mod.rs39
1 files changed, 20 insertions, 19 deletions
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 5d6277c33..fb8e79ad8 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -13,7 +13,7 @@ use crate::dma::{slice_ptr_parts, word, ChannelAndRequest};
13use crate::gpio::{AFType, AnyPin, Pull, SealedPin as _, Speed}; 13use crate::gpio::{AFType, AnyPin, Pull, SealedPin as _, Speed};
14use crate::mode::{Async, Blocking, Mode as PeriMode}; 14use crate::mode::{Async, Blocking, Mode as PeriMode};
15use crate::pac::spi::{regs, vals, Spi as Regs}; 15use crate::pac::spi::{regs, vals, Spi as Regs};
16use crate::rcc::{self, RccInfo, SealedRccPeripheral}; 16use crate::rcc::{RccInfo, SealedRccPeripheral};
17use crate::time::Hertz; 17use crate::time::Hertz;
18use crate::Peripheral; 18use crate::Peripheral;
19 19
@@ -120,17 +120,30 @@ impl<'d, M: PeriMode> Spi<'d, M> {
120 rx_dma: Option<ChannelAndRequest<'d>>, 120 rx_dma: Option<ChannelAndRequest<'d>>,
121 config: Config, 121 config: Config,
122 ) -> Self { 122 ) -> Self {
123 let regs = T::info().regs; 123 let mut this = Self {
124 let kernel_clock = T::frequency(); 124 info: T::info(),
125 let br = compute_baud_rate(kernel_clock, config.frequency); 125 kernel_clock: T::frequency(),
126 sck,
127 mosi,
128 miso,
129 tx_dma,
130 rx_dma,
131 current_word_size: <u8 as SealedWord>::CONFIG,
132 _phantom: PhantomData,
133 };
134 this.enable_and_init(config);
135 this
136 }
126 137
138 fn enable_and_init(&mut self, config: Config) {
139 let br = compute_baud_rate(self.kernel_clock, config.frequency);
127 let cpha = config.raw_phase(); 140 let cpha = config.raw_phase();
128 let cpol = config.raw_polarity(); 141 let cpol = config.raw_polarity();
129
130 let lsbfirst = config.raw_byte_order(); 142 let lsbfirst = config.raw_byte_order();
131 143
132 rcc::enable_and_reset::<T>(); 144 self.info.rcc.enable_and_reset();
133 145
146 let regs = self.info.regs;
134 #[cfg(any(spi_v1, spi_f1))] 147 #[cfg(any(spi_v1, spi_f1))]
135 { 148 {
136 regs.cr2().modify(|w| { 149 regs.cr2().modify(|w| {
@@ -209,18 +222,6 @@ impl<'d, M: PeriMode> Spi<'d, M> {
209 w.set_spe(true); 222 w.set_spe(true);
210 }); 223 });
211 } 224 }
212
213 Self {
214 info: T::info(),
215 kernel_clock,
216 sck,
217 mosi,
218 miso,
219 tx_dma,
220 rx_dma,
221 current_word_size: <u8 as SealedWord>::CONFIG,
222 _phantom: PhantomData,
223 }
224 } 225 }
225 226
226 /// Reconfigures it with the supplied config. 227 /// Reconfigures it with the supplied config.
@@ -578,7 +579,7 @@ impl<'d> Spi<'d, Async> {
578 // see RM0453 rev 1 section 7.2.13 page 291 579 // see RM0453 rev 1 section 7.2.13 page 291
579 // The SUBGHZSPI_SCK frequency is obtained by PCLK3 divided by two. 580 // The SUBGHZSPI_SCK frequency is obtained by PCLK3 divided by two.
580 // The SUBGHZSPI_SCK clock maximum speed must not exceed 16 MHz. 581 // The SUBGHZSPI_SCK clock maximum speed must not exceed 16 MHz.
581 let pclk3_freq = <crate::peripherals::SUBGHZSPI as crate::rcc::SealedRccPeripheral>::frequency().0; 582 let pclk3_freq = <crate::peripherals::SUBGHZSPI as SealedRccPeripheral>::frequency().0;
582 let freq = Hertz(core::cmp::min(pclk3_freq / 2, 16_000_000)); 583 let freq = Hertz(core::cmp::min(pclk3_freq / 2, 16_000_000));
583 let mut config = Config::default(); 584 let mut config = Config::default();
584 config.mode = MODE_0; 585 config.mode = MODE_0;