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authorpbert <[email protected]>2023-10-11 21:38:41 +0200
committerpbert <[email protected]>2023-10-12 11:04:44 +0200
commitecdd7c0e2f9dcc07e53e136557140d3ccc6a5ee1 (patch)
tree6db9bf875d3e83d94f6bf8e8a2e7ff03a83c5bb4 /embassy-stm32/src/timer/complementary_pwm.rs
parentd7d79f3068a4a2d883b078b8900ad194f7c98203 (diff)
enable clock first
Diffstat (limited to 'embassy-stm32/src/timer/complementary_pwm.rs')
-rw-r--r--embassy-stm32/src/timer/complementary_pwm.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 3818cc03c..9349a6fad 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -64,7 +64,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
64 fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self { 64 fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
65 into_ref!(tim); 65 into_ref!(tim);
66 66
67 T::reset_and_enable(); 67 T::enable_and_reset();
68 68
69 let mut this = Self { inner: tim }; 69 let mut this = Self { inner: tim };
70 70