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authorxoviat <[email protected]>2025-12-03 09:36:58 -0600
committerxoviat <[email protected]>2025-12-03 09:36:58 -0600
commit077e59a192ca4cb096a9ef939d06ebefebbac42d (patch)
treed77ac51522f10bd3b10e49cf76880d17a1808ddc /embassy-stm32/src/timer/low_level.rs
parent424522b0975b449bc62854c271b196cd9ed192d7 (diff)
timer: restore waveform method
Diffstat (limited to 'embassy-stm32/src/timer/low_level.rs')
-rw-r--r--embassy-stm32/src/timer/low_level.rs25
1 files changed, 21 insertions, 4 deletions
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 6a70d2a40..da1bfac5f 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -13,7 +13,7 @@ use embassy_hal_internal::Peri;
13pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource}; 13pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
14 14
15use super::*; 15use super::*;
16use crate::dma::{Transfer, WritableRingBuffer}; 16use crate::dma::{self, Transfer, WritableRingBuffer};
17use crate::pac::timer::vals; 17use crate::pac::timer::vals;
18use crate::rcc; 18use crate::rcc;
19use crate::time::Hertz; 19use crate::time::Hertz;
@@ -682,9 +682,26 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
682 channel: Channel, 682 channel: Channel,
683 duty: &'a [W], 683 duty: &'a [W],
684 ) -> Transfer<'a> { 684 ) -> Transfer<'a> {
685 #[allow(clippy::let_unit_value)] // eg. stm32f334 685 self.setup_update_dma_inner(dma.request(), dma, channel, duty)
686 let req = dma.request(); 686 }
687 687
688 /// Generate a sequence of PWM waveform
689 pub fn setup_channel_update_dma<'a, C: TimerChannel, W: Word + Into<T::Word>>(
690 &mut self,
691 dma: Peri<'a, impl super::Dma<T, C>>,
692 channel: Channel,
693 duty: &'a [W],
694 ) -> Transfer<'a> {
695 self.setup_update_dma_inner(dma.request(), dma, channel, duty)
696 }
697
698 fn setup_update_dma_inner<'a, W: Word + Into<T::Word>>(
699 &mut self,
700 request: dma::Request,
701 dma: Peri<'a, impl dma::Channel>,
702 channel: Channel,
703 duty: &'a [W],
704 ) -> Transfer<'a> {
688 unsafe { 705 unsafe {
689 #[cfg(not(any(bdma, gpdma)))] 706 #[cfg(not(any(bdma, gpdma)))]
690 use crate::dma::{Burst, FifoThreshold}; 707 use crate::dma::{Burst, FifoThreshold};
@@ -700,7 +717,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
700 717
701 Transfer::new_write( 718 Transfer::new_write(
702 dma, 719 dma,
703 req, 720 request,
704 duty, 721 duty,
705 self.regs_gp16().ccr(channel.index()).as_ptr() as *mut W, 722 self.regs_gp16().ccr(channel.index()).as_ptr() as *mut W,
706 dma_transfer_option, 723 dma_transfer_option,