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authoreZio Pan <[email protected]>2023-12-14 21:33:35 +0800
committereZio Pan <[email protected]>2023-12-14 21:33:35 +0800
commit879c0ad9890e80f2e7c19c715347b86b61eb432a (patch)
tree46d5ce4400a3edaa7cdd9afde1108268ada63914 /embassy-stm32/src/timer/mod.rs
parent2c3d3992200939f71708c8b47d839328dcb12098 (diff)
after stm32-metapac update, TIM CR1 ARPE enum to bool
Diffstat (limited to 'embassy-stm32/src/timer/mod.rs')
-rw-r--r--embassy-stm32/src/timer/mod.rs2
1 files changed, 1 insertions, 1 deletions
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 2313a5b94..9f93c6425 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -77,7 +77,7 @@ pub(crate) mod sealed {
77 Self::regs().dier().write(|r| r.set_uie(enable)); 77 Self::regs().dier().write(|r| r.set_uie(enable));
78 } 78 }
79 79
80 fn set_autoreload_preload(&mut self, enable: vals::Arpe) { 80 fn set_autoreload_preload(&mut self, enable: bool) {
81 Self::regs().cr1().modify(|r| r.set_arpe(enable)); 81 Self::regs().cr1().modify(|r| r.set_arpe(enable));
82 } 82 }
83 83