diff options
| author | Matous Hybl <[email protected]> | 2022-02-28 16:20:42 +0100 |
|---|---|---|
| committer | Matous Hybl <[email protected]> | 2022-02-28 16:20:42 +0100 |
| commit | a88c5e716e7a374e2fc7a602b0c70dea267a2e8a (patch) | |
| tree | e87527f950a1a2092af667a923a6c1b730155cc4 /embassy-stm32/src/timer/mod.rs | |
| parent | 141e007acf5f3c91a9cbd13196c32867bfddd78d (diff) | |
stm32: Register access for timers now doesn't require self
Diffstat (limited to 'embassy-stm32/src/timer/mod.rs')
| -rw-r--r-- | embassy-stm32/src/timer/mod.rs | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs index 4c1eb946b..f9fefdf73 100644 --- a/embassy-stm32/src/timer/mod.rs +++ b/embassy-stm32/src/timer/mod.rs | |||
| @@ -14,7 +14,7 @@ pub(crate) mod sealed { | |||
| 14 | pub trait Basic16bitInstance: RccPeripheral { | 14 | pub trait Basic16bitInstance: RccPeripheral { |
| 15 | type Interrupt: Interrupt; | 15 | type Interrupt: Interrupt; |
| 16 | 16 | ||
| 17 | fn regs(&self) -> crate::pac::timer::TimBasic; | 17 | fn regs() -> crate::pac::timer::TimBasic; |
| 18 | 18 | ||
| 19 | fn start(&mut self); | 19 | fn start(&mut self); |
| 20 | 20 | ||
| @@ -30,17 +30,17 @@ pub(crate) mod sealed { | |||
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | pub trait GeneralPurpose16bitInstance: Basic16bitInstance { | 32 | pub trait GeneralPurpose16bitInstance: Basic16bitInstance { |
| 33 | fn regs_gp16(&self) -> crate::pac::timer::TimGp16; | 33 | fn regs_gp16() -> crate::pac::timer::TimGp16; |
| 34 | } | 34 | } |
| 35 | 35 | ||
| 36 | pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance { | 36 | pub trait GeneralPurpose32bitInstance: GeneralPurpose16bitInstance { |
| 37 | fn regs_gp32(&self) -> crate::pac::timer::TimGp32; | 37 | fn regs_gp32() -> crate::pac::timer::TimGp32; |
| 38 | 38 | ||
| 39 | fn set_frequency<F: Into<Hertz>>(&mut self, frequency: F); | 39 | fn set_frequency<F: Into<Hertz>>(&mut self, frequency: F); |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | pub trait AdvancedControlInstance: Basic16bitInstance { | 42 | pub trait AdvancedControlInstance: Basic16bitInstance { |
| 43 | fn regs_advanced(&self) -> crate::pac::timer::TimAdv; | 43 | fn regs_advanced() -> crate::pac::timer::TimAdv; |
| 44 | } | 44 | } |
| 45 | } | 45 | } |
| 46 | 46 | ||
| @@ -58,26 +58,25 @@ macro_rules! impl_basic_16bit_timer { | |||
| 58 | impl sealed::Basic16bitInstance for crate::peripherals::$inst { | 58 | impl sealed::Basic16bitInstance for crate::peripherals::$inst { |
| 59 | type Interrupt = crate::interrupt::$irq; | 59 | type Interrupt = crate::interrupt::$irq; |
| 60 | 60 | ||
| 61 | fn regs(&self) -> crate::pac::timer::TimBasic { | 61 | fn regs() -> crate::pac::timer::TimBasic { |
| 62 | crate::pac::timer::TimBasic(crate::pac::$inst.0) | 62 | crate::pac::timer::TimBasic(crate::pac::$inst.0) |
| 63 | } | 63 | } |
| 64 | 64 | ||
| 65 | fn start(&mut self) { | 65 | fn start(&mut self) { |
| 66 | unsafe { | 66 | unsafe { |
| 67 | self.regs().cr1().modify(|r| r.set_cen(true)); | 67 | Self::regs().cr1().modify(|r| r.set_cen(true)); |
| 68 | } | 68 | } |
| 69 | } | 69 | } |
| 70 | 70 | ||
| 71 | fn stop(&mut self) { | 71 | fn stop(&mut self) { |
| 72 | let regs = self.regs(); | ||
| 73 | unsafe { | 72 | unsafe { |
| 74 | regs.cr1().modify(|r| r.set_cen(false)); | 73 | Self::regs().cr1().modify(|r| r.set_cen(false)); |
| 75 | } | 74 | } |
| 76 | } | 75 | } |
| 77 | 76 | ||
| 78 | fn reset(&mut self) { | 77 | fn reset(&mut self) { |
| 79 | unsafe { | 78 | unsafe { |
| 80 | self.regs().cnt().write(|r| r.set_cnt(0)); | 79 | Self::regs().cnt().write(|r| r.set_cnt(0)); |
| 81 | } | 80 | } |
| 82 | } | 81 | } |
| 83 | 82 | ||
| @@ -90,7 +89,7 @@ macro_rules! impl_basic_16bit_timer { | |||
| 90 | let arr: u16 = | 89 | let arr: u16 = |
| 91 | unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into()); | 90 | unwrap!((pclk_ticks_per_timer_period / (u32::from(psc) + 1)).try_into()); |
| 92 | 91 | ||
| 93 | let regs = self.regs(); | 92 | let regs = Self::regs(); |
| 94 | unsafe { | 93 | unsafe { |
| 95 | regs.psc().write(|r| r.set_psc(psc)); | 94 | regs.psc().write(|r| r.set_psc(psc)); |
| 96 | regs.arr().write(|r| r.set_arr(arr)); | 95 | regs.arr().write(|r| r.set_arr(arr)); |
| @@ -102,10 +101,11 @@ macro_rules! impl_basic_16bit_timer { | |||
| 102 | } | 101 | } |
| 103 | 102 | ||
| 104 | fn clear_update_interrupt(&mut self) -> bool { | 103 | fn clear_update_interrupt(&mut self) -> bool { |
| 104 | let regs = Self::regs(); | ||
| 105 | unsafe { | 105 | unsafe { |
| 106 | let sr = self.regs().sr().read(); | 106 | let sr = regs.sr().read(); |
| 107 | if sr.uif() { | 107 | if sr.uif() { |
| 108 | self.regs().sr().modify(|r| { | 108 | regs.sr().modify(|r| { |
| 109 | r.set_uif(false); | 109 | r.set_uif(false); |
| 110 | }); | 110 | }); |
| 111 | true | 111 | true |
| @@ -117,7 +117,7 @@ macro_rules! impl_basic_16bit_timer { | |||
| 117 | 117 | ||
| 118 | fn enable_update_interrupt(&mut self, enable: bool) { | 118 | fn enable_update_interrupt(&mut self, enable: bool) { |
| 119 | unsafe { | 119 | unsafe { |
| 120 | self.regs().dier().write(|r| r.set_uie(enable)); | 120 | Self::regs().dier().write(|r| r.set_uie(enable)); |
| 121 | } | 121 | } |
| 122 | } | 122 | } |
| 123 | } | 123 | } |
| @@ -128,7 +128,7 @@ macro_rules! impl_basic_16bit_timer { | |||
| 128 | macro_rules! impl_32bit_timer { | 128 | macro_rules! impl_32bit_timer { |
| 129 | ($inst:ident) => { | 129 | ($inst:ident) => { |
| 130 | impl sealed::GeneralPurpose32bitInstance for crate::peripherals::$inst { | 130 | impl sealed::GeneralPurpose32bitInstance for crate::peripherals::$inst { |
| 131 | fn regs_gp32(&self) -> crate::pac::timer::TimGp32 { | 131 | fn regs_gp32() -> crate::pac::timer::TimGp32 { |
| 132 | crate::pac::$inst | 132 | crate::pac::$inst |
| 133 | } | 133 | } |
| 134 | 134 | ||
| @@ -141,7 +141,7 @@ macro_rules! impl_32bit_timer { | |||
| 141 | let arr: u32 = | 141 | let arr: u32 = |
| 142 | unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into())); | 142 | unwrap!(((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into())); |
| 143 | 143 | ||
| 144 | let regs = self.regs_gp32(); | 144 | let regs = Self::regs_gp32(); |
| 145 | unsafe { | 145 | unsafe { |
| 146 | regs.psc().write(|r| r.set_psc(psc)); | 146 | regs.psc().write(|r| r.set_psc(psc)); |
| 147 | regs.arr().write(|r| r.set_arr(arr)); | 147 | regs.arr().write(|r| r.set_arr(arr)); |
| @@ -169,7 +169,7 @@ foreach_interrupt! { | |||
| 169 | } | 169 | } |
| 170 | 170 | ||
| 171 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { | 171 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { |
| 172 | fn regs_gp16(&self) -> crate::pac::timer::TimGp16 { | 172 | fn regs_gp16() -> crate::pac::timer::TimGp16 { |
| 173 | crate::pac::$inst | 173 | crate::pac::$inst |
| 174 | } | 174 | } |
| 175 | } | 175 | } |
| @@ -185,7 +185,7 @@ foreach_interrupt! { | |||
| 185 | } | 185 | } |
| 186 | 186 | ||
| 187 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { | 187 | impl sealed::GeneralPurpose16bitInstance for crate::peripherals::$inst { |
| 188 | fn regs_gp16(&self) -> crate::pac::timer::TimGp16 { | 188 | fn regs_gp16() -> crate::pac::timer::TimGp16 { |
| 189 | crate::pac::timer::TimGp16(crate::pac::$inst.0) | 189 | crate::pac::timer::TimGp16(crate::pac::$inst.0) |
| 190 | } | 190 | } |
| 191 | } | 191 | } |
| @@ -206,7 +206,7 @@ foreach_interrupt! { | |||
| 206 | } | 206 | } |
| 207 | 207 | ||
| 208 | impl sealed::AdvancedControlInstance for crate::peripherals::$inst { | 208 | impl sealed::AdvancedControlInstance for crate::peripherals::$inst { |
| 209 | fn regs_advanced(&self) -> crate::pac::timer::TimAdv { | 209 | fn regs_advanced() -> crate::pac::timer::TimAdv { |
| 210 | crate::pac::$inst | 210 | crate::pac::$inst |
| 211 | } | 211 | } |
| 212 | } | 212 | } |
