Merge branch 'main' into time

5 files changed, 290 insertions, 149 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 6d4c70dff..77f19a37b 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -220,9 +220,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    #[inline(always)]
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        self.inner.waveform_up(dma, channel, duty).await
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_update_dma(true);
+        self.inner.setup_update_dma(dma, channel, duty).await;
+        self.inner.enable_update_dma(false);
     }
 
     /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
@@ -254,7 +256,6 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    #[inline(always)]
     pub async fn waveform_up_multi_channel(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
@@ -262,15 +263,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         ending_channel: Channel,
         duty: &[u16],
     ) {
+        self.inner.enable_update_dma(true);
         self.inner
-            .waveform_up_multi_channel(dma, starting_channel, ending_channel, duty)
+            .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
             .await;
-    }
-
-    /// Generate a sequence of PWM waveform
-    #[inline(always)]
-    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
-        self.inner.waveform(dma, duty).await;
+        self.inner.enable_update_dma(false);
     }
 }
 
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index f0105ece8..aba08081f 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -13,9 +13,10 @@ use embassy_hal_internal::Peri;
 pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
+use crate::dma::{Transfer, WritableRingBuffer};
 use crate::pac::timer::vals;
+use crate::rcc;
 use crate::time::Hertz;
-use crate::{dma, rcc};
 
 /// Input capture mode.
 #[derive(Clone, Copy)]
@@ -659,29 +660,88 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         }
     }
 
+    /// Setup a ring buffer for the channel
+    pub fn setup_ring_buffer<'a>(
+        &mut self,
+        dma: Peri<'a, impl super::UpDma<T>>,
+        channel: Channel,
+        dma_buf: &'a mut [u16],
+    ) -> WritableRingBuffer<'a, u16> {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        unsafe {
+            use crate::dma::TransferOptions;
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            WritableRingBuffer::new(
+                dma,
+                req,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                dma_buf,
+                dma_transfer_option,
+            )
+        }
+    }
+
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+    pub fn setup_update_dma<'a>(
+        &mut self,
+        dma: Peri<'a, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &'a [u16],
+    ) -> Transfer<'a> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
-        let original_update_dma_state = self.get_update_dma_state();
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
 
-        if !original_update_dma_state {
-            self.enable_update_dma(true);
-        }
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
 
-        self.waveform_helper(dma, req, channel, duty).await;
+            match self.bits() {
+                TimerBits::Bits16 => Transfer::new_write(
+                    dma,
+                    req,
+                    duty,
+                    self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                    dma_transfer_option,
+                ),
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
+                    #[cfg(not(any(bdma, gpdma)))]
+                    panic!("unsupported timer bits");
 
-        // Since DMA is closed before timer update event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_update_dma_state {
-            self.enable_update_dma(false);
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                }
+            }
         }
     }
 
@@ -714,13 +774,13 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub fn setup_update_dma_burst<'a>(
         &mut self,
-        dma: Peri<'_, impl super::UpDma<T>>,
+        dma: Peri<'a, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[u16],
-    ) {
+        duty: &'a [u16],
+    ) -> Transfer<'a> {
         let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
         let start_ch_index = starting_channel.index();
         let end_ch_index = ending_channel.index();
@@ -738,11 +798,6 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
-        let original_update_dma_state = self.get_update_dma_state();
-        if !original_update_dma_state {
-            self.enable_update_dma(true);
-        }
-
         unsafe {
             #[cfg(not(any(bdma, gpdma)))]
             use crate::dma::{Burst, FifoThreshold};
@@ -763,115 +818,9 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 self.regs_gp16().dmar().as_ptr() as *mut u16,
                 dma_transfer_option,
             )
-            .await
-        };
-
-        if !original_update_dma_state {
-            self.enable_update_dma(false);
         }
     }
 
-    /// Generate a sequence of PWM waveform
-    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
-        use crate::pac::timer::vals::Ccds;
-
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let cc_channel = C::CHANNEL;
-
-        let original_cc_dma_on_update = self.get_cc_dma_selection() == Ccds::ON_UPDATE;
-        let original_cc_dma_enabled = self.get_cc_dma_enable_state(cc_channel);
-
-        // redirect CC DMA request onto Update Event
-        if !original_cc_dma_on_update {
-            self.set_cc_dma_selection(Ccds::ON_UPDATE)
-        }
-
-        if !original_cc_dma_enabled {
-            self.set_cc_dma_enable_state(cc_channel, true);
-        }
-
-        self.waveform_helper(dma, req, cc_channel, duty).await;
-
-        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_cc_dma_enabled {
-            self.set_cc_dma_enable_state(cc_channel, false);
-        }
-
-        if !original_cc_dma_on_update {
-            self.set_cc_dma_selection(Ccds::ON_COMPARE)
-        }
-    }
-
-    async fn waveform_helper(
-        &mut self,
-        dma: Peri<'_, impl dma::Channel>,
-        req: dma::Request,
-        channel: Channel,
-        duty: &[u16],
-    ) {
-        let original_duty_state = self.get_compare_value(channel);
-        let original_enable_state = self.get_channel_enable_state(channel);
-
-        if !original_enable_state {
-            self.enable_channel(channel, true);
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            match self.bits() {
-                TimerBits::Bits16 => {
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-            };
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.enable_channel(channel, false);
-        }
-
-        self.set_compare_value(channel, original_duty_state);
-    }
-
     /// Get capture value for a channel.
     pub fn get_capture_value(&self, channel: Channel) -> u32 {
         self.get_compare_value(channel)
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 804d1ef37..3fa363881 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -12,6 +12,7 @@ pub mod low_level;
 pub mod one_pulse;
 pub mod pwm_input;
 pub mod qei;
+pub mod ringbuffered;
 pub mod simple_pwm;
 
 use crate::interrupt;
diff --git a/embassy-stm32/src/timer/ringbuffered.rs b/embassy-stm32/src/timer/ringbuffered.rs
new file mode 100644
index 000000000..e8f97bf59
--- /dev/null
+++ b/embassy-stm32/src/timer/ringbuffered.rs
@@ -0,0 +1,169 @@
+//! RingBuffered PWM driver.
+
+use core::mem::ManuallyDrop;
+use core::task::Waker;
+
+use super::low_level::Timer;
+use super::{Channel, GeneralInstance4Channel};
+use crate::dma::WritableRingBuffer;
+use crate::dma::ringbuffer::Error;
+
+/// A PWM channel that uses a DMA ring buffer for continuous waveform generation.
+///
+/// This allows you to continuously update PWM duty cycles via DMA without blocking the CPU.
+/// The ring buffer enables smooth, uninterrupted waveform generation by automatically cycling
+/// through duty cycle values stored in memory.
+///
+/// You can write new duty cycle values to the ring buffer while it's running, enabling
+/// dynamic waveform generation for applications like motor control, LED dimming, or audio output.
+///
+/// # Example
+/// ```ignore
+/// let mut channel = pwm.ch1().into_ring_buffered_channel(dma_ch, &mut buffer);
+/// channel.start(); // Start DMA transfer
+/// channel.write(&[100, 200, 300]).ok(); // Update duty cycles
+/// ```
+pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel> {
+    timer: ManuallyDrop<Timer<'d, T>>,
+    ring_buf: WritableRingBuffer<'d, u16>,
+    channel: Channel,
+}
+
+impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
+    pub(crate) fn new(
+        timer: ManuallyDrop<Timer<'d, T>>,
+        channel: Channel,
+        ring_buf: WritableRingBuffer<'d, u16>,
+    ) -> Self {
+        Self {
+            timer,
+            ring_buf,
+            channel,
+        }
+    }
+
+    /// Start the ring buffer operation.
+    ///
+    /// You must call this after creating it for it to work.
+    pub fn start(&mut self) {
+        self.ring_buf.start()
+    }
+
+    /// Clear all data in the ring buffer.
+    pub fn clear(&mut self) {
+        self.ring_buf.clear()
+    }
+
+    /// Write elements directly to the raw buffer. This can be used to fill the buffer before starting the DMA transfer.
+    pub fn write_immediate(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+        self.ring_buf.write_immediate(buf)
+    }
+
+    /// Write elements from the ring buffer
+    /// Return a tuple of the length written and the length remaining in the buffer
+    pub fn write(&mut self, buf: &[u16]) -> Result<(usize, usize), Error> {
+        self.ring_buf.write(buf)
+    }
+
+    /// Write an exact number of elements to the ringbuffer.
+    pub async fn write_exact(&mut self, buffer: &[u16]) -> Result<usize, Error> {
+        self.ring_buf.write_exact(buffer).await
+    }
+
+    /// Wait for any ring buffer write error.
+    pub async fn wait_write_error(&mut self) -> Result<usize, Error> {
+        self.ring_buf.wait_write_error().await
+    }
+
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        self.ring_buf.len()
+    }
+
+    /// The capacity of the ringbuffer
+    pub const fn capacity(&self) -> usize {
+        self.ring_buf.capacity()
+    }
+
+    /// Set a waker to be woken when at least one byte is send.
+    pub fn set_waker(&mut self, waker: &Waker) {
+        self.ring_buf.set_waker(waker)
+    }
+
+    /// Request the DMA to reset. The configuration for this channel will not be preserved.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until is_running returns false.
+    pub fn request_reset(&mut self) {
+        self.ring_buf.request_reset()
+    }
+
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until is_running returns false.
+    pub fn request_pause(&mut self) {
+        self.ring_buf.request_pause()
+    }
+
+    /// Return whether DMA is still running.
+    ///
+    /// If this returns false, it can be because either the transfer finished, or it was requested to stop early with request_stop.
+    pub fn is_running(&mut self) -> bool {
+        self.ring_buf.is_running()
+    }
+
+    /// Stop the DMA transfer and await until the buffer is empty.
+    ///
+    /// This disables the DMA transfer's circular mode so that the transfer stops when all available data has been written.
+    ///
+    /// This is designed to be used with streaming output data such as the I2S/SAI or DAC.
+    pub async fn stop(&mut self) {
+        self.ring_buf.stop().await
+    }
+
+    /// Enable the given channel.
+    pub fn enable(&mut self) {
+        self.timer.enable_channel(self.channel, true);
+    }
+
+    /// Disable the given channel.
+    pub fn disable(&mut self) {
+        self.timer.enable_channel(self.channel, false);
+    }
+
+    /// Check whether given channel is enabled
+    pub fn is_enabled(&self) -> bool {
+        self.timer.get_channel_enable_state(self.channel)
+    }
+
+    /// Get max duty value.
+    ///
+    /// This value depends on the configured frequency and the timer's clock rate from RCC.
+    pub fn max_duty_cycle(&self) -> u16 {
+        let max = self.timer.get_max_compare_value();
+        assert!(max < u16::MAX as u32);
+        max as u16 + 1
+    }
+
+    /// Set the output polarity for a given channel.
+    pub fn set_polarity(&mut self, polarity: super::low_level::OutputPolarity) {
+        self.timer.set_output_polarity(self.channel, polarity);
+    }
+
+    /// Set the output compare mode for a given channel.
+    pub fn set_output_compare_mode(&mut self, mode: super::low_level::OutputCompareMode) {
+        self.timer.set_output_compare_mode(self.channel, mode);
+    }
+}
+
+/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
+pub struct RingBufferedPwmChannels<'d, T: GeneralInstance4Channel> {
+    /// Channel 1
+    pub ch1: RingBufferedPwmChannel<'d, T>,
+    /// Channel 2
+    pub ch2: RingBufferedPwmChannel<'d, T>,
+    /// Channel 3
+    pub ch3: RingBufferedPwmChannel<'d, T>,
+    /// Channel 4
+    pub ch4: RingBufferedPwmChannel<'d, T>,
+}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 6c9ef17e0..484e9fd81 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,6 +4,7 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
+use super::ringbuffered::RingBufferedPwmChannel;
 use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
 use crate::Peri;
 #[cfg(gpio_v2)]
@@ -158,6 +159,33 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     pub fn set_output_compare_mode(&mut self, mode: OutputCompareMode) {
         self.timer.set_output_compare_mode(self.channel, mode);
     }
+
+    /// Convert this PWM channel into a ring-buffered PWM channel.
+    ///
+    /// This allows continuous PWM waveform generation using a DMA ring buffer.
+    /// The ring buffer enables dynamic updates to the PWM duty cycle without blocking.
+    ///
+    /// # Arguments
+    /// * `tx_dma` - The DMA channel to use for transferring duty cycle values
+    /// * `dma_buf` - The buffer to use as a ring buffer (must be non-empty and <= 65535 elements)
+    ///
+    /// # Panics
+    /// Panics if `dma_buf` is empty or longer than 65535 elements.
+    pub fn into_ring_buffered_channel(
+        mut self,
+        tx_dma: Peri<'d, impl super::UpDma<T>>,
+        dma_buf: &'d mut [u16],
+    ) -> RingBufferedPwmChannel<'d, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+
+        self.timer.enable_update_dma(true);
+
+        RingBufferedPwmChannel::new(
+            unsafe { self.timer.clone_unchecked() },
+            self.channel,
+            self.timer.setup_ring_buffer(tx_dma, self.channel, dma_buf),
+        )
+    }
 }
 
 /// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
@@ -316,9 +344,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
-    #[inline(always)]
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        self.inner.waveform_up(dma, channel, duty).await;
+        self.inner.enable_channel(channel, true);
+        self.inner.enable_update_dma(true);
+        self.inner.setup_update_dma(dma, channel, duty).await;
+        self.inner.enable_update_dma(false);
     }
 
     /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
@@ -350,7 +380,6 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    #[inline(always)]
     pub async fn waveform_up_multi_channel(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
@@ -358,15 +387,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         ending_channel: Channel,
         duty: &[u16],
     ) {
+        self.inner.enable_update_dma(true);
         self.inner
-            .waveform_up_multi_channel(dma, starting_channel, ending_channel, duty)
+            .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
             .await;
-    }
-
-    /// Generate a sequence of PWM waveform
-    #[inline(always)]
-    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
-        self.inner.waveform(dma, duty).await;
+        self.inner.enable_update_dma(false);
     }
 }