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authorpkj <[email protected]>2025-09-28 21:13:17 +0800
committerpkj <[email protected]>2025-09-28 21:13:17 +0800
commit36d368d70e56181554b690687ef2c88a84704b0c (patch)
tree1abf3c9e64b9b81f82aa18a402f5e32005798005 /embassy-stm32/src/timer
parentb29c7295e406045ec137b78ca5f220bf7909006b (diff)
stm32/timer: Support 32-bit timers in SimplePwm waveform_up method
Add TimerBits matching following waveform method pattern to handle both 16-bit and 32-bit timer DMA transfers with appropriate pointer types.
Diffstat (limited to 'embassy-stm32/src/timer')
-rw-r--r--embassy-stm32/src/timer/simple_pwm.rs35
1 files changed, 27 insertions, 8 deletions
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index e6165e42b..19c1610f7 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -339,14 +339,33 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
339 ..Default::default() 339 ..Default::default()
340 }; 340 };
341 341
342 Transfer::new_write( 342 match self.inner.bits() {
343 dma, 343 TimerBits::Bits16 => {
344 req, 344 Transfer::new_write(
345 duty, 345 dma,
346 self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16, 346 req,
347 dma_transfer_option, 347 duty,
348 ) 348 self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
349 .await 349 dma_transfer_option,
350 )
351 .await
352 }
353 #[cfg(not(any(stm32l0)))]
354 TimerBits::Bits32 => {
355 #[cfg(not(any(bdma, gpdma)))]
356 panic!("unsupported timer bits");
357
358 #[cfg(any(bdma, gpdma))]
359 Transfer::new_write(
360 dma,
361 req,
362 duty,
363 self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
364 dma_transfer_option,
365 )
366 .await
367 }
368 };
350 }; 369 };
351 370
352 // restore output compare state 371 // restore output compare state