Add STM32F1 AFIO remap

7 files changed, 103 insertions, 32 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 68cdec302..08404cdd6 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -17,7 +17,8 @@ use crate::Peri;
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -32,7 +33,7 @@ impl<'d, T: AdvancedInstance4Channel, C: TimerChannel> ComplementaryPwmPin<'d, T
             );
         });
         ComplementaryPwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -54,20 +55,31 @@ pub enum IdlePolarity {
 
 impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Create a new complementary PWM driver.
-    #[allow(clippy::too_many_arguments)]
+    #[allow(clippy::too_many_arguments, unused)]
     pub fn new(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
-        _ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
+        ch1: Option<PwmPin<'d, T, Ch1>>,
+        ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
+        ch2: Option<PwmPin<'d, T, Ch2>>,
+        ch2n: Option<ComplementaryPwmPin<'d, T, Ch2>>,
+        ch3: Option<PwmPin<'d, T, Ch3>>,
+        ch3n: Option<ComplementaryPwmPin<'d, T, Ch3>>,
+        ch4: Option<PwmPin<'d, T, Ch4>>,
+        ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
+        #[cfg(afio)]
+        super::set_afio::<T>(&[
+            ch1.map(|p| p.pin),
+            ch1n.map(|p| p.pin),
+            ch2.map(|p| p.pin),
+            ch2n.map(|p| p.pin),
+            ch3.map(|p| p.pin),
+            ch3n.map(|p| p.pin),
+            ch4.map(|p| p.pin),
+            ch4n.map(|p| p.pin),
+        ]);
         Self::new_inner(tim, freq, counting_mode)
     }
 
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index dda33e7f1..b717e6eac 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -18,7 +18,8 @@ use crate::Peri;
 ///
 /// This wraps a pin to make it usable with capture.
 pub struct CapturePin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 impl<'d, T: GeneralInstance4Channel, C: TimerChannel> CapturePin<'d, T, C> {
@@ -26,7 +27,7 @@ impl<'d, T: GeneralInstance4Channel, C: TimerChannel> CapturePin<'d, T, C> {
     pub fn new(pin: Peri<'d, impl TimerPin<T, C>>, pull: Pull) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
         CapturePin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -39,16 +40,24 @@ pub struct InputCapture<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
     /// Create a new input capture driver.
+    #[allow(unused)]
     pub fn new(
         tim: Peri<'d, T>,
-        _ch1: Option<CapturePin<'d, T, Ch1>>,
-        _ch2: Option<CapturePin<'d, T, Ch2>>,
-        _ch3: Option<CapturePin<'d, T, Ch3>>,
-        _ch4: Option<CapturePin<'d, T, Ch4>>,
+        ch1: Option<CapturePin<'d, T, Ch1>>,
+        ch2: Option<CapturePin<'d, T, Ch2>>,
+        ch3: Option<CapturePin<'d, T, Ch3>>,
+        ch4: Option<CapturePin<'d, T, Ch4>>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
+        #[cfg(afio)]
+        super::set_afio::<T>(&[
+            ch1.map(|p| p.pin),
+            ch2.map(|p| p.pin),
+            ch3.map(|p| p.pin),
+            ch4.map(|p| p.pin),
+        ]);
         Self::new_inner(tim, freq, counting_mode)
     }
 
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 7062f5f4c..38f4a1a51 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -14,6 +14,8 @@ pub mod pwm_input;
 pub mod qei;
 pub mod simple_pwm;
 
+#[cfg(afio)]
+use crate::gpio::SealedPin;
 use crate::interrupt;
 use crate::rcc::RccPeripheral;
 
@@ -155,9 +157,15 @@ trait SealedInstance: RccPeripheral + PeripheralType {
     fn state() -> &'static State;
 }
 
+#[allow(unused)]
+pub(crate) trait Afio {
+    fn afio_mappings() -> &'static [AfioMapping];
+    fn set_afio(value: u8);
+}
+
 /// Core timer instance.
 #[allow(private_bounds)]
-pub trait CoreInstance: SealedInstance + 'static {
+pub trait CoreInstance: SealedInstance + Afio + 'static {
     /// Update Interrupt for this timer.
     type UpdateInterrupt: interrupt::typelevel::Interrupt;
 
@@ -450,3 +458,24 @@ impl<T: GeneralInstance1Channel> interrupt::typelevel::Handler<T::CaptureCompare
         }
     }
 }
+
+#[allow(unused)]
+pub(crate) struct AfioMapping {
+    pub(crate) value: u8,
+    pub(crate) pins: &'static [u8],
+}
+
+#[cfg(afio)]
+fn set_afio<'d, T: Afio>(pins: &[Option<embassy_hal_internal::Peri<'d, crate::gpio::AnyPin>>]) {
+    let mapping = T::afio_mappings()
+        .iter()
+        .find(|m| {
+            pins.iter()
+                .flatten()
+                .map(|p| (*p).pin_port())
+                .all(|p| m.pins.contains(&p))
+        })
+        .expect("Should be called with a combination of timer pins supported by the hardware");
+
+    T::set_afio(mapping.value);
+}
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index 498d9c082..0267749e1 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -42,7 +42,8 @@ impl From<ExternalTriggerPolarity> for Etp {
 ///
 /// This wraps a pin to make it usable as a timer trigger.
 pub struct TriggerPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -113,7 +114,7 @@ impl<'d, T: GeneralInstance4Channel, C: TriggerSource> TriggerPin<'d, T, C> {
     pub fn new(pin: Peri<'d, impl TimerTriggerPin<T, C>>, pull: Pull) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
         TriggerPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -131,14 +132,17 @@ impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
     ///
     /// The pulse is triggered by a channel 1 input pin on both rising and
     /// falling edges. Channel 1 will unusable as an output.
+    #[allow(unused)]
     pub fn new_ch1_edge_detect(
         tim: Peri<'d, T>,
-        _pin: TriggerPin<'d, T, Ch1>,
+        pin: TriggerPin<'d, T, Ch1>,
         _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
         freq: Hertz,
         pulse_end: u32,
         counting_mode: CountingMode,
     ) -> Self {
+        #[cfg(afio)]
+        super::set_afio::<T>(&[Some(pin.pin)]);
         let mut this = Self { inner: Timer::new(tim) };
 
         this.inner.set_trigger_source(Ts::TI1F_ED);
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 1e55f2919..c537e5268 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -20,6 +20,8 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
     pub fn new_ch1(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch1>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
+        #[cfg(afio)]
+        super::set_afio::<T>(&[Some(pin.into())]);
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
@@ -27,6 +29,8 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
     pub fn new_ch2(tim: Peri<'d, T>, pin: Peri<'d, impl TimerPin<T, Ch2>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
+        #[cfg(afio)]
+        super::set_afio::<T>(&[Some(pin.into())]);
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
     }
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index eabe1b22a..4e5a309ac 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -21,19 +21,20 @@ pub enum Direction {
 
 /// Wrapper for using a pin with QEI.
 pub struct QeiPin<'d, T, Channel> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, Channel)>,
 }
 
 impl<'d, T: GeneralInstance4Channel, C: QeiChannel> QeiPin<'d, T, C> {
-    /// Create a new  QEI pin instance.
+    /// Create a new QEI pin instance.
     pub fn new(pin: Peri<'d, impl TimerPin<T, C>>) -> Self {
         critical_section::with(|_| {
             pin.set_low();
             pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
         });
         QeiPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -58,7 +59,10 @@ pub struct Qei<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
     /// Create a new quadrature decoder driver.
-    pub fn new(tim: Peri<'d, T>, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
+    #[allow(unused)]
+    pub fn new(tim: Peri<'d, T>, ch1: QeiPin<'d, T, Ch1>, ch2: QeiPin<'d, T, Ch2>) -> Self {
+        #[cfg(afio)]
+        super::set_afio::<T>(&[Some(ch1.pin), Some(ch2.pin)]);
         Self::new_inner(tim)
     }
 
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index c04b1ab97..df86859fe 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -15,7 +15,8 @@ use crate::Peri;
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct PwmPin<'d, T, C> {
-    _pin: Peri<'d, AnyPin>,
+    #[allow(unused)]
+    pub(crate) pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -42,7 +43,7 @@ impl<'d, T: GeneralInstance4Channel, C: TimerChannel> PwmPin<'d, T, C> {
             pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
         });
         PwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -60,7 +61,7 @@ impl<'d, T: GeneralInstance4Channel, C: TimerChannel> PwmPin<'d, T, C> {
             );
         });
         PwmPin {
-            _pin: pin.into(),
+            pin: pin.into(),
             phantom: PhantomData,
         }
     }
@@ -178,15 +179,23 @@ pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Create a new simple PWM driver.
+    #[allow(unused)]
     pub fn new(
         tim: Peri<'d, T>,
-        _ch1: Option<PwmPin<'d, T, Ch1>>,
-        _ch2: Option<PwmPin<'d, T, Ch2>>,
-        _ch3: Option<PwmPin<'d, T, Ch3>>,
-        _ch4: Option<PwmPin<'d, T, Ch4>>,
+        ch1: Option<PwmPin<'d, T, Ch1>>,
+        ch2: Option<PwmPin<'d, T, Ch2>>,
+        ch3: Option<PwmPin<'d, T, Ch3>>,
+        ch4: Option<PwmPin<'d, T, Ch4>>,
         freq: Hertz,
         counting_mode: CountingMode,
     ) -> Self {
+        #[cfg(afio)]
+        super::set_afio::<T>(&[
+            ch1.map(|p| p.pin),
+            ch2.map(|p| p.pin),
+            ch3.map(|p| p.pin),
+            ch4.map(|p| p.pin),
+        ]);
         Self::new_inner(tim, freq, counting_mode)
     }