timer: allow 16 bit dma buffers for 32 bit timers.

4 files changed, 49 insertions, 40 deletions

diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 996759060..b9434d37b 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -8,6 +8,7 @@ use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
 use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
 use crate::Peri;
+use crate::dma::word::Word;
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
@@ -220,8 +221,14 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[T::Word]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.set_compare_value(channel, 0.into());
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -256,18 +263,21 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[T::Word],
+        duty: &[W],
     ) {
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
             .iter()
             .filter(|ch| ch.index() >= starting_channel.index())
             .filter(|ch| ch.index() <= ending_channel.index())
-            .for_each(|ch| self.inner.enable_channel(*ch, true));
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.set_compare_value(*ch, 0.into());
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 73a81bff1..1af66aec1 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -628,12 +628,12 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     }
 
     /// Setup a ring buffer for the channel
-    pub fn setup_ring_buffer<'a>(
+    pub fn setup_ring_buffer<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        dma_buf: &'a mut [T::Word],
-    ) -> WritableRingBuffer<'a, T::Word> {
+        dma_buf: &'a mut [W],
+    ) -> WritableRingBuffer<'a, W> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
@@ -653,7 +653,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
             WritableRingBuffer::new(
                 dma,
                 req,
-                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut T::Word,
+                self.regs_1ch().ccr(channel.index()).as_ptr() as *mut W,
                 dma_buf,
                 dma_transfer_option,
             )
@@ -664,11 +664,11 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub fn setup_update_dma<'a>(
+    pub fn setup_update_dma<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         channel: Channel,
-        duty: &'a [T::Word],
+        duty: &'a [W],
     ) -> Transfer<'a> {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
@@ -690,7 +690,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 dma,
                 req,
                 duty,
-                self.regs_gp16().ccr(channel.index()).as_ptr() as *mut T::Word,
+                self.regs_gp16().ccr(channel.index()).as_ptr() as *mut W,
                 dma_transfer_option,
             )
         }
@@ -725,12 +725,12 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub fn setup_update_dma_burst<'a>(
+    pub fn setup_update_dma_burst<'a, W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'a, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &'a [T::Word],
+        duty: &'a [W],
     ) -> Transfer<'a> {
         let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
         let start_ch_index = starting_channel.index();
@@ -766,7 +766,7 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
                 dma,
                 req,
                 duty,
-                self.regs_gp16().dmar().as_ptr() as *mut T::Word,
+                self.regs_gp16().dmar().as_ptr() as *mut W,
                 dma_transfer_option,
             )
         }
diff --git a/embassy-stm32/src/timer/ringbuffered.rs b/embassy-stm32/src/timer/ringbuffered.rs
index f5a4328d1..fbb6b19ea 100644
--- a/embassy-stm32/src/timer/ringbuffered.rs
+++ b/embassy-stm32/src/timer/ringbuffered.rs
@@ -7,6 +7,7 @@ use super::low_level::Timer;
 use super::{Channel, GeneralInstance4Channel};
 use crate::dma::WritableRingBuffer;
 use crate::dma::ringbuffer::Error;
+use crate::dma::word::Word;
 
 /// A PWM channel that uses a DMA ring buffer for continuous waveform generation.
 ///
@@ -23,17 +24,17 @@ use crate::dma::ringbuffer::Error;
 /// channel.start(); // Start DMA transfer
 /// channel.write(&[100, 200, 300]).ok(); // Update duty cycles
 /// ```
-pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel> {
+pub struct RingBufferedPwmChannel<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> {
     timer: ManuallyDrop<Timer<'d, T>>,
-    ring_buf: WritableRingBuffer<'d, T::Word>,
+    ring_buf: WritableRingBuffer<'d, W>,
     channel: Channel,
 }
 
-impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
+impl<'d, T: GeneralInstance4Channel, W: Word + Into<T::Word>> RingBufferedPwmChannel<'d, T, W> {
     pub(crate) fn new(
         timer: ManuallyDrop<Timer<'d, T>>,
         channel: Channel,
-        ring_buf: WritableRingBuffer<'d, T::Word>,
+        ring_buf: WritableRingBuffer<'d, W>,
     ) -> Self {
         Self {
             timer,
@@ -55,18 +56,18 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
     }
 
     /// Write elements directly to the raw buffer. This can be used to fill the buffer before starting the DMA transfer.
-    pub fn write_immediate(&mut self, buf: &[T::Word]) -> Result<(usize, usize), Error> {
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write_immediate(buf)
     }
 
     /// Write elements from the ring buffer
     /// Return a tuple of the length written and the length remaining in the buffer
-    pub fn write(&mut self, buf: &[T::Word]) -> Result<(usize, usize), Error> {
+    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
         self.ring_buf.write(buf)
     }
 
     /// Write an exact number of elements to the ringbuffer.
-    pub async fn write_exact(&mut self, buffer: &[T::Word]) -> Result<usize, Error> {
+    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> {
         self.ring_buf.write_exact(buffer).await
     }
 
@@ -155,15 +156,3 @@ impl<'d, T: GeneralInstance4Channel> RingBufferedPwmChannel<'d, T> {
         self.timer.set_output_compare_mode(self.channel, mode);
     }
 }
-
-/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
-pub struct RingBufferedPwmChannels<'d, T: GeneralInstance4Channel> {
-    /// Channel 1
-    pub ch1: RingBufferedPwmChannel<'d, T>,
-    /// Channel 2
-    pub ch2: RingBufferedPwmChannel<'d, T>,
-    /// Channel 3
-    pub ch3: RingBufferedPwmChannel<'d, T>,
-    /// Channel 4
-    pub ch4: RingBufferedPwmChannel<'d, T>,
-}
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 466c56db2..3f37ffcd9 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -7,6 +7,7 @@ use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
 use super::ringbuffered::RingBufferedPwmChannel;
 use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
 use crate::Peri;
+use crate::dma::word::Word;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
@@ -171,11 +172,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
     ///
     /// # Panics
     /// Panics if `dma_buf` is empty or longer than 65535 elements.
-    pub fn into_ring_buffered_channel(
+    pub fn into_ring_buffered_channel<W: Word + Into<T::Word>>(
         mut self,
         tx_dma: Peri<'d, impl super::UpDma<T>>,
-        dma_buf: &'d mut [T::Word],
-    ) -> RingBufferedPwmChannel<'d, T> {
+        dma_buf: &'d mut [W],
+    ) -> RingBufferedPwmChannel<'d, T, W> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
 
         self.timer.enable_update_dma(true);
@@ -344,8 +345,14 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
-    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[T::Word]) {
+    pub async fn waveform_up<W: Word + Into<T::Word>>(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        channel: Channel,
+        duty: &[W],
+    ) {
         self.inner.enable_channel(channel, true);
+        self.inner.set_compare_value(channel, 0.into());
         self.inner.enable_update_dma(true);
         self.inner.setup_update_dma(dma, channel, duty).await;
         self.inner.enable_update_dma(false);
@@ -380,18 +387,21 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Also be aware that embassy timers use one of timers internally. It is possible to
     /// switch this timer by using `time-driver-timX` feature.
     ///
-    pub async fn waveform_up_multi_channel(
+    pub async fn waveform_up_multi_channel<W: Word + Into<T::Word>>(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
         starting_channel: Channel,
         ending_channel: Channel,
-        duty: &[T::Word],
+        duty: &[W],
     ) {
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
             .iter()
             .filter(|ch| ch.index() >= starting_channel.index())
             .filter(|ch| ch.index() <= ending_channel.index())
-            .for_each(|ch| self.inner.enable_channel(*ch, true));
+            .for_each(|ch| {
+                self.inner.enable_channel(*ch, true);
+                self.inner.set_compare_value(*ch, 0.into());
+            });
         self.inner.enable_update_dma(true);
         self.inner
             .setup_update_dma_burst(dma, starting_channel, ending_channel, duty)