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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-02-25 14:28:44 +0000 |
|---|---|---|
| committer | GitHub <[email protected]> | 2022-02-25 14:28:44 +0000 |
| commit | d381b8e2b613dac5a8b6c80033e81fabc4a8632d (patch) | |
| tree | 8dca0824c0c25e19fd48d3c15466b207da588ea3 /embassy-stm32/src/timer | |
| parent | 6da4b6636435b350b21f0b30e7175a2a6899acdc (diff) | |
| parent | 48f700b35c5371f1df374a615a5d68adff02597a (diff) | |
Merge #645
645: stm32 usart: Fix RX interrupt flag handling r=lulf a=timokroeger
* On v1 interrupts cannot be cleared individually.
Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
Handle them all in one go intstead of re-entering the ISR for each one so that
we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
from the buffer before receiving the next byte.
Tested on v1 hardware, lets see if v2 still succeeds on CI.
Co-authored-by: Timo Kröger <[email protected]>
Diffstat (limited to 'embassy-stm32/src/timer')
0 files changed, 0 insertions, 0 deletions
