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authorPriit Laes <[email protected]>2025-11-03 23:08:15 +0200
committerPriit Laes <[email protected]>2025-11-04 09:26:47 +0200
commitf440a3e19584aa8c1c5df742b964ae417cf705a1 (patch)
tree5f0f25bf1fbe49a769a70ef2c621d0be48edb4be /embassy-stm32/src/timer
parenta967d77a0f0eedcc65778528cceee07edbba2813 (diff)
stm32/timer/simplepwm: Fix docs formatting and clarify timer usage
Diffstat (limited to 'embassy-stm32/src/timer')
-rw-r--r--embassy-stm32/src/timer/simple_pwm.rs13
1 files changed, 10 insertions, 3 deletions
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index 06315d7f3..7597c0eee 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -309,7 +309,9 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
309 /// Generate a sequence of PWM waveform 309 /// Generate a sequence of PWM waveform
310 /// 310 ///
311 /// Note: 311 /// Note:
312 /// you will need to provide corresponding TIMx_UP DMA channel to use this method. 312 /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
313 /// Also be aware that embassy timers use one of timers internally. It is possible to
314 /// switch this timer by using `time-driver-timX` feature.
313 pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) { 315 pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
314 #[allow(clippy::let_unit_value)] // eg. stm32f334 316 #[allow(clippy::let_unit_value)] // eg. stm32f334
315 let req = dma.request(); 317 let req = dma.request();
@@ -378,18 +380,23 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
378 /// 380 ///
379 /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like: 381 /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
380 /// 382 ///
383 /// ```rust,ignore
381 /// let dma_buf: [u16; 16] = [ 384 /// let dma_buf: [u16; 16] = [
382 /// ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1 385 /// ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
383 /// ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2 386 /// ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
384 /// ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3 387 /// ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
385 /// ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4 388 /// ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
386 /// ]; 389 /// ];
390 /// ```
387 /// 391 ///
388 /// Each group of N values (where N = number of channels) is transferred on one update event, 392 /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
389 /// updating the duty cycles of all selected channels simultaneously. 393 /// updating the duty cycles of all selected channels simultaneously.
390 /// 394 ///
391 /// Note: 395 /// Note:
392 /// you will need to provide corresponding TIMx_UP DMA channel to use this method. 396 /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
397 /// Also be aware that embassy timers use one of timers internally. It is possible to
398 /// switch this timer by using `time-driver-timX` feature.
399 ///
393 pub async fn waveform_up_multi_channel( 400 pub async fn waveform_up_multi_channel(
394 &mut self, 401 &mut self,
395 dma: Peri<'_, impl super::UpDma<T>>, 402 dma: Peri<'_, impl super::UpDma<T>>,