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authorMatt Johnston <[email protected]>2025-04-02 21:00:08 +0800
committerMatt Johnston <[email protected]>2025-04-04 17:41:53 +0800
commite22fe7cbcfbbb68e4ad6ef7914bf8ed952fca8f4 (patch)
tree59d1be5212a6b87cdc3b2b77ae35361a6de20bd9 /embassy-stm32/src/xspi
parent65f849a589be78f8f5dce2311614982ee96bbae5 (diff)
stm32: xspi wait for prescaler change
This is documented as being required (and is done by stm32cube), hasn't been observed as a problem though.
Diffstat (limited to 'embassy-stm32/src/xspi')
-rw-r--r--embassy-stm32/src/xspi/mod.rs17
1 files changed, 9 insertions, 8 deletions
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index c024b2ed6..c315e2320 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -335,8 +335,17 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
335 w.set_prescaler(config.clock_prescaler); 335 w.set_prescaler(config.clock_prescaler);
336 }); 336 });
337 337
338 // Wait for busy flag to clear after changing prescaler, during calibration
339 while T::REGS.sr().read().busy() {}
340
338 T::REGS.cr().modify(|w| { 341 T::REGS.cr().modify(|w| {
339 w.set_dmm(dual_quad); 342 w.set_dmm(dual_quad);
343
344 // TODO: at the moment only ncs1 seems to get passed in?
345 // Only one must be selected
346 assert!(!(ncs1.is_some() && ncs2.is_some()));
347 assert!(!(ncs1.is_none() && ncs2.is_none()));
348 w.set_cssel(if ncs1.is_some() { Cssel::B_0X0 } else { Cssel::B_0X1 });
340 }); 349 });
341 350
342 T::REGS.tcr().modify(|w| { 351 T::REGS.tcr().modify(|w| {
@@ -344,14 +353,6 @@ impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
344 w.set_dhqc(config.delay_hold_quarter_cycle); 353 w.set_dhqc(config.delay_hold_quarter_cycle);
345 }); 354 });
346 355
347 // TODO: at the moment only ncs1 seems to get passed in?
348 // Only one must be selected
349 assert!(!(ncs1.is_some() && ncs2.is_some()));
350 assert!(!(ncs1.is_none() && ncs2.is_none()));
351 T::REGS.cr().modify(|w| {
352 w.set_cssel(if ncs1.is_some() { Cssel::B_0X0 } else { Cssel::B_0X1 });
353 });
354
355 // Enable peripheral 356 // Enable peripheral
356 T::REGS.cr().modify(|w| { 357 T::REGS.cr().modify(|w| {
357 w.set_en(true); 358 w.set_en(true);