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authorJakob <[email protected]>2025-08-06 15:04:48 +0200
committerJakob <[email protected]>2025-08-10 08:57:15 +0200
commit0941a76be60a3c95aed9a3e1835ec1de6f03ac12 (patch)
treedbe05ebdfaa34941ae31ec6531c27df3cc84533d /embassy-stm32/src
parent7dad187ff740a0a1940d2d503fbc373218f4bd01 (diff)
Add get methods for meo, ossi and ossr
Diffstat (limited to 'embassy-stm32/src')
-rw-r--r--embassy-stm32/src/timer/complementary_pwm.rs15
-rw-r--r--embassy-stm32/src/timer/low_level.rs15
2 files changed, 30 insertions, 0 deletions
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 1178e7d83..bf76155dd 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -100,11 +100,21 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
100 self.inner.set_ossi(val); 100 self.inner.set_ossi(val);
101 } 101 }
102 102
103 /// Get state of OSSR-bit in BDTR register
104 pub fn get_off_state_selection_idle(&self) -> Ossi {
105 self.inner.get_ossi()
106 }
107
103 /// Set state of OSSR-bit in BDTR register 108 /// Set state of OSSR-bit in BDTR register
104 pub fn set_off_state_selection_run(&self, val: Ossr) { 109 pub fn set_off_state_selection_run(&self, val: Ossr) {
105 self.inner.set_ossr(val); 110 self.inner.set_ossr(val);
106 } 111 }
107 112
113 /// Get state of OSSR-bit in BDTR register
114 pub fn get_off_state_selection_run(&self) -> Ossr {
115 self.inner.get_ossr()
116 }
117
108 /// Trigger break input from software 118 /// Trigger break input from software
109 pub fn trigger_software_break(&self, n: usize) { 119 pub fn trigger_software_break(&self, n: usize) {
110 self.inner.trigger_software_break(n); 120 self.inner.trigger_software_break(n);
@@ -115,6 +125,11 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
115 self.inner.set_moe(enable); 125 self.inner.set_moe(enable);
116 } 126 }
117 127
128 /// Get Master Output Enable
129 pub fn get_master_output_enable(&mut self) -> bool {
130 self.inner.get_moe()
131 }
132
118 /// Set Master Slave Mode 2 133 /// Set Master Slave Mode 2
119 pub fn set_mms2(&mut self, mms2: Mms2) { 134 pub fn set_mms2(&mut self, mms2: Mms2) {
120 self.inner.set_mms2_selection(mms2); 135 self.inner.set_mms2_selection(mms2);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 01bf60869..ac039bb0d 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -691,15 +691,30 @@ impl<'d, T: AdvancedInstance1Channel> Timer<'d, T> {
691 self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossi(val)); 691 self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossi(val));
692 } 692 }
693 693
694 /// Get state of OSSI-bit in BDTR register
695 pub fn get_ossi(&self) -> vals::Ossi {
696 self.regs_1ch_cmp().bdtr().read().ossi()
697 }
698
694 /// Set state of OSSR-bit in BDTR register 699 /// Set state of OSSR-bit in BDTR register
695 pub fn set_ossr(&self, val: vals::Ossr) { 700 pub fn set_ossr(&self, val: vals::Ossr) {
696 self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossr(val)); 701 self.regs_1ch_cmp().bdtr().modify(|w| w.set_ossr(val));
697 } 702 }
698 703
704 /// Get state of OSSR-bit in BDTR register
705 pub fn get_ossr(&self) -> vals::Ossr {
706 self.regs_1ch_cmp().bdtr().read().ossr()
707 }
708
699 /// Set state of MOE-bit in BDTR register to en-/disable output 709 /// Set state of MOE-bit in BDTR register to en-/disable output
700 pub fn set_moe(&self, enable: bool) { 710 pub fn set_moe(&self, enable: bool) {
701 self.regs_1ch_cmp().bdtr().modify(|w| w.set_moe(enable)); 711 self.regs_1ch_cmp().bdtr().modify(|w| w.set_moe(enable));
702 } 712 }
713
714 /// Get state of MOE-bit in BDTR register
715 pub fn get_moe(&self) -> bool {
716 self.regs_1ch_cmp().bdtr().read().moe()
717 }
703} 718}
704 719
705#[cfg(not(stm32l0))] 720#[cfg(not(stm32l0))]