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authorDario Nieuwenhuis <[email protected]>2025-03-25 11:03:53 +0000
committerGitHub <[email protected]>2025-03-25 11:03:53 +0000
commit17cce79807ff978270b96ba081a4ee2ed5604dcd (patch)
tree0eaf8440069324b110be690ff99bafafad50dc6e /embassy-stm32/src
parent9d009e59e559f7a43dfd0938f88ef9518d8bf73a (diff)
parent15394ae5fa9b8e3490fa7a600382ef549bff8f02 (diff)
Merge pull request #3992 from elagil/usb_fixes
Small USB-related fixes
Diffstat (limited to 'embassy-stm32/src')
-rw-r--r--embassy-stm32/src/usb/usb.rs10
1 files changed, 10 insertions, 0 deletions
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 24983cf3c..6682374d3 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -887,6 +887,16 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
887 }) 887 })
888 .await; 888 .await;
889 889
890 // Errata for STM32H5, 2.20.1:
891 // During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
892 // have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
893 //
894 // Workaround:
895 // Software should ensure that a small delay is included before accessing the SRAM contents. This delay should be
896 // 800 ns in Full Speed mode and 6.4 μs in Low Speed mode.
897 #[cfg(stm32h5)]
898 embassy_time::block_for(embassy_time::Duration::from_nanos(800));
899
890 RX_COMPLETE[index].store(false, Ordering::Relaxed); 900 RX_COMPLETE[index].store(false, Ordering::Relaxed);
891 901
892 if stat == Stat::DISABLED { 902 if stat == Stat::DISABLED {