Add USBPHYC clock configuration for H7RS series

3 files changed, 42 insertions, 2 deletions

diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 27fc2b8d7..cd1c10407 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -35,7 +35,10 @@ pub enum VoltageScale {
     Scale3,
 }
 #[cfg(any(stm32h7rs))]
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
+pub use crate::pac::{
+    pwr::vals::Vos as VoltageScale,
+    rcc::vals::{Usbphycsel, Usbrefcksel},
+};
 
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
@@ -557,6 +560,27 @@ pub(crate) unsafe fn init(config: Config) {
 
     let rtc = config.ls.init();
 
+    #[cfg(stm32h7rs)]
+    let usb_refck = match config.mux.usbphycsel {
+        Usbphycsel::HSE => hse,
+        Usbphycsel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
+        Usbphycsel::PLL3_Q => pll3.q,
+        _ => None,
+    };
+    #[cfg(stm32h7rs)]
+    let usb_refck_sel = match usb_refck {
+        Some(clk_val) => match clk_val {
+            Hertz(16_000_000) => Usbrefcksel::MHZ16,
+            Hertz(19_200_000) => Usbrefcksel::MHZ19_2,
+            Hertz(20_000_000) => Usbrefcksel::MHZ20,
+            Hertz(24_000_000) => Usbrefcksel::MHZ24,
+            Hertz(26_000_000) => Usbrefcksel::MHZ26,
+            Hertz(32_000_000) => Usbrefcksel::MHZ32,
+            _ => panic!("cannot select USBPHYC reference clock with source frequency of {} Hz, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+        },
+        None => Usbrefcksel::MHZ24,
+    };
+
     #[cfg(stm32h7)]
     {
         RCC.d1cfgr().modify(|w| {
@@ -593,6 +617,10 @@ pub(crate) unsafe fn init(config: Config) {
             w.set_ppre4(config.apb4_pre);
             w.set_ppre5(config.apb5_pre);
         });
+
+        RCC.ahbperckselr().modify(|w| {
+            w.set_usbrefcksel(usb_refck_sel);
+        });
     }
     #[cfg(stm32h5)]
     {
@@ -698,6 +726,8 @@ pub(crate) unsafe fn init(config: Config) {
         #[cfg(stm32h7rs)]
         clk48mohci: None, // TODO
         #[cfg(stm32h7rs)]
+        hse_div_2: hse.map(|clk| clk / 2u32),
+        #[cfg(stm32h7rs)]
         usb: Some(Hertz(48_000_000)),
     );
 }
diff --git a/embassy-stm32/src/usb/mod.rs b/embassy-stm32/src/usb/mod.rs
index 7d8c79618..a473285bf 100644
--- a/embassy-stm32/src/usb/mod.rs
+++ b/embassy-stm32/src/usb/mod.rs
@@ -13,9 +13,19 @@ fn common_init<T: Instance>() {
     // Check the USB clock is enabled and running at exactly 48 MHz.
     // frequency() will panic if not enabled
     let freq = T::frequency();
+
+    // On the H7RS, the USBPHYC embeds a PLL accepting one of the input frequencies listed below and providing 48MHz to OTG_FS and 60MHz to OTG_HS internally
+    #[cfg(stm32h7rs)]
+    if ![16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000].contains(&freq.0) {
+        panic!(
+            "USB clock should be one of 16, 19.2, 20, 24, 26, 32Mhz but is {} Hz. Please double-check your RCC settings.",
+            freq.0
+        )
+    }
     // Check frequency is within the 0.25% tolerance allowed by the spec.
     // Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
     // has tight clock restrictions due to something else (like audio).
+    #[cfg(not(stm32h7rs))]
     if freq.0.abs_diff(48_000_000) > 120_000 {
         panic!(
             "USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 59b5401cc..00cafe6e4 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -554,7 +554,7 @@ fn calculate_trdt<T: Instance>(speed: Dspd) -> u8 {
     match speed {
         Dspd::HIGH_SPEED => {
             // From RM0431 (F72xx), RM0090 (F429), RM0390 (F446)
-            if ahb_freq >= 30_000_000 {
+            if ahb_freq >= 30_000_000 || cfg!(stm32h7rs) {
                 0x9
             } else {
                 panic!("AHB frequency is too low")