stm32: update metapac. Adds U5 LPDMA, fixes ADC_COMMONs.

5 files changed, 59 insertions, 51 deletions

diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 1dda28cf2..f17522076 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -9,7 +9,7 @@ use stm32_metapac::adc::vals::Ckmode;
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcPin, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
-use crate::peripherals::ADC;
+use crate::peripherals::ADC1;
 use crate::{interrupt, Peripheral};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
@@ -36,26 +36,26 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 pub struct Vbat;
 
 #[cfg(not(adc_l0))]
-impl AdcPin<ADC> for Vbat {}
+impl AdcPin<ADC1> for Vbat {}
 
 #[cfg(not(adc_l0))]
-impl super::SealedAdcPin<ADC> for Vbat {
+impl super::SealedAdcPin<ADC1> for Vbat {
     fn channel(&self) -> u8 {
         18
     }
 }
 
 pub struct Vref;
-impl AdcPin<ADC> for Vref {}
-impl super::SealedAdcPin<ADC> for Vref {
+impl AdcPin<ADC1> for Vref {}
+impl super::SealedAdcPin<ADC1> for Vref {
     fn channel(&self) -> u8 {
         17
     }
 }
 
 pub struct Temperature;
-impl AdcPin<ADC> for Temperature {}
-impl super::SealedAdcPin<ADC> for Temperature {
+impl AdcPin<ADC1> for Temperature {}
+impl super::SealedAdcPin<ADC1> for Temperature {
     fn channel(&self) -> u8 {
         16
     }
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 26298a08b..8a748ad72 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -368,7 +368,7 @@ impl<'d, T: Instance, const N: u8, DMA> Drop for DacChannel<'d, T, N, DMA> {
 ///
 /// ```ignore
 /// // Pins may need to be changed for your specific device.
-/// let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC, NoDma, NoDma, p.PA4, p.PA5).split();
+/// let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, NoDma, NoDma, p.PA4, p.PA5).split();
 /// ```
 pub struct Dac<'d, T: Instance, DMACh1 = NoDma, DMACh2 = NoDma> {
     ch1: DacChannel<'d, T, 1, DMACh1>,
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index ef03970ef..a3717e67b 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -32,7 +32,7 @@ impl Default for TransferOptions {
     }
 }
 
-impl From<WordSize> for vals::ChTr1Dw {
+impl From<WordSize> for vals::Dw {
     fn from(raw: WordSize) -> Self {
         match raw {
             WordSize::OneByte => Self::BYTE,
@@ -235,8 +235,8 @@ impl<'a> Transfer<'a> {
         });
         ch.tr2().write(|w| {
             w.set_dreq(match dir {
-                Dir::MemoryToPeripheral => vals::ChTr2Dreq::DESTINATIONPERIPHERAL,
-                Dir::PeripheralToMemory => vals::ChTr2Dreq::SOURCEPERIPHERAL,
+                Dir::MemoryToPeripheral => vals::Dreq::DESTINATIONPERIPHERAL,
+                Dir::PeripheralToMemory => vals::Dreq::SOURCEPERIPHERAL,
             });
             w.set_reqsel(request);
         });
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index c6e015022..37f460574 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -94,8 +94,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 
         #[cfg(rcc_h5)]
         critical_section::with(|_| {
-            crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
-
             crate::pac::RCC.ahb1enr().modify(|w| {
                 w.set_ethen(true);
                 w.set_ethtxen(true);
@@ -161,8 +159,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
 
         #[cfg(rcc_h5)]
         critical_section::with(|_| {
-            crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
-
             crate::pac::RCC.ahb1enr().modify(|w| {
                 w.set_ethen(true);
                 w.set_ethtxen(true);
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 215f8a3d2..f33351e74 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -299,54 +299,66 @@ pub(crate) unsafe fn init(config: Config) {
 
     let rtc = config.ls.init();
 
+    // TODO: all this ADC stuff should probably go into the ADC module, not here.
+    // Most STM32s manage ADC clocks in a similar way with ADCx_COMMON.
     #[cfg(all(stm32f3, not(rcc_f37)))]
     use crate::pac::adccommon::vals::Ckmode;
 
     #[cfg(all(stm32f3, not(rcc_f37)))]
-    let adc = match config.adc {
-        AdcClockSource::Pll(adcpres) => {
-            RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
-            crate::pac::ADC_COMMON
-                .ccr()
-                .modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
-
-            unwrap!(pll) / adcpres
-        }
-        AdcClockSource::Hclk(adcpres) => {
-            assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
+    let adc = {
+        #[cfg(peri_adc1_common)]
+        let common = crate::pac::ADC1_COMMON;
+        #[cfg(peri_adc12_common)]
+        let common = crate::pac::ADC12_COMMON;
+
+        match config.adc {
+            AdcClockSource::Pll(adcpres) => {
+                RCC.cfgr2().modify(|w| w.set_adc12pres(adcpres));
+                common.ccr().modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
+
+                unwrap!(pll) / adcpres
+            }
+            AdcClockSource::Hclk(adcpres) => {
+                assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
 
-            let (div, ckmode) = match adcpres {
-                AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
-                AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
-                AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
-            };
-            crate::pac::ADC_COMMON.ccr().modify(|w| w.set_ckmode(ckmode));
+                let (div, ckmode) = match adcpres {
+                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+                };
+                common.ccr().modify(|w| w.set_ckmode(ckmode));
 
-            hclk / div
+                hclk / div
+            }
         }
     };
 
     #[cfg(all(stm32f3, not(rcc_f37), adc3_common))]
-    let adc34 = match config.adc34 {
-        AdcClockSource::Pll(adcpres) => {
-            RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
-            crate::pac::ADC3_COMMON
-                .ccr()
-                .modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
-
-            unwrap!(pll) / adcpres
-        }
-        AdcClockSource::Hclk(adcpres) => {
-            assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
+    let adc34 = {
+        #[cfg(peri_adc3_common)]
+        let common = crate::pac::ADC3_COMMON;
+        #[cfg(peri_adc34_common)]
+        let common = crate::pac::ADC34_COMMON;
+
+        match config.adc34 {
+            AdcClockSource::Pll(adcpres) => {
+                RCC.cfgr2().modify(|w| w.set_adc34pres(adcpres));
+                common.ccr().modify(|w| w.set_ckmode(Ckmode::ASYNCHRONOUS));
+
+                unwrap!(pll) / adcpres
+            }
+            AdcClockSource::Hclk(adcpres) => {
+                assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
 
-            let (div, ckmode) = match adcpres {
-                AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
-                AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
-                AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
-            };
-            crate::pac::ADC3_COMMON.ccr().modify(|w| w.set_ckmode(ckmode));
+                let (div, ckmode) = match adcpres {
+                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+                };
+                common.ccr().modify(|w| w.set_ckmode(ckmode));
 
-            hclk / div
+                hclk / div
+            }
         }
     };