stm32: can: fd: implement bus-off recovery

as per RM0492 and other relevant RMs, bus-off recovery is not automatic.
CCCR.INIT is set by the device upon bus-off; the CPU must reset
CCCR.INIT to initiate the recovery.

2 files changed, 9 insertions, 0 deletions

diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index e32f19d91..e5cfee528 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -368,6 +368,7 @@ impl Registers {
             w.set_rfne(0, true); // Rx Fifo 0 New Msg
             w.set_rfne(1, true); // Rx Fifo 1 New Msg
             w.set_tce(true); //  Tx Complete
+            w.set_boe(true); // Bus-Off Status Changed
         });
         self.regs.ile().modify(|w| {
             w.set_eint0(true); // Interrupt Line 0
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 23a35168b..563f542d4 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -81,6 +81,14 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
         if ir.rfn(1) {
             T::state().rx_mode.on_interrupt::<T>(1);
         }
+
+        if ir.bo() {
+            regs.ir().write(|w| w.set_bo(true));
+            if regs.psr().read().bo() {
+                // Initiate bus-off recovery sequence by resetting CCCR.INIT
+                regs.cccr().modify(|w| w.set_init(false));
+            }
+        }
     }
 }