diff options
| author | Matt Rodgers <[email protected]> | 2025-01-08 10:11:25 +0000 |
|---|---|---|
| committer | Matt Rodgers <[email protected]> | 2025-01-08 10:11:25 +0000 |
| commit | 844d3b38de8160149ec9bb34359f69973a3dec99 (patch) | |
| tree | 6c6da469586d7518a93a6b707578c003f3cc1213 /embassy-stm32/src | |
| parent | 06869e2e85695f4528d1148dfd81700c905771c5 (diff) | |
stm32: flash: fix flash erase on stm32f3xx series
STM32F3xx series also needs a wait of at least one clock cycle before
reading the BSY bit during a flash erase - previously this was only
applied to STM32F1xx series.
Diffstat (limited to 'embassy-stm32/src')
| -rw-r--r-- | embassy-stm32/src/flash/f1f3.rs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/embassy-stm32/src/flash/f1f3.rs b/embassy-stm32/src/flash/f1f3.rs index ff7f810ea..ec237b9ff 100644 --- a/embassy-stm32/src/flash/f1f3.rs +++ b/embassy-stm32/src/flash/f1f3.rs | |||
| @@ -64,8 +64,8 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E | |||
| 64 | // BSY bit, because there is a one-cycle delay between | 64 | // BSY bit, because there is a one-cycle delay between |
| 65 | // setting the STRT bit and the BSY bit being asserted | 65 | // setting the STRT bit and the BSY bit being asserted |
| 66 | // by hardware. See STM32F105xx, STM32F107xx device errata, | 66 | // by hardware. See STM32F105xx, STM32F107xx device errata, |
| 67 | // section 2.2.8 | 67 | // section 2.2.8, and also RM0316 Rev 10 section 4.2.3 for |
| 68 | #[cfg(stm32f1)] | 68 | // STM32F3xx series. |
| 69 | pac::FLASH.cr().read(); | 69 | pac::FLASH.cr().read(); |
| 70 | 70 | ||
| 71 | let mut ret: Result<(), Error> = wait_ready_blocking(); | 71 | let mut ret: Result<(), Error> = wait_ready_blocking(); |