Merge branch 'embassy-rs:main' into fix/simple-pwm-32bit-timer-support

100 files changed, 549 insertions, 319 deletions

diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 255dc7956..2608160a3 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -4,7 +4,7 @@ use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingR
 #[cfg(stm32wba)]
 use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
-use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
+use super::{AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel, blocking_delay_us};
 use crate::dma::Transfer;
 #[cfg(stm32u5)]
 pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
@@ -15,7 +15,7 @@ pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4S
 #[cfg(stm32wba)]
 pub use crate::pac::adc::vals::{Presc, Res as Resolution, SampleTime};
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
@@ -208,7 +208,10 @@ impl<'d, T: Instance> Adc4<'d, T> {
         info!("ADC4 frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
         let mut s = Self { adc };
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index f2837a8f1..fc28df346 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -4,11 +4,11 @@ use pac::adc::vals::{Adstp, Align, Ckmode, Dmacfg, Exten, Ovrmod, Ovsr};
 use pac::adccommon::vals::Presc;
 
 use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
+    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
 };
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -168,7 +168,10 @@ impl<'d, T: Instance> Adc<'d, T> {
         debug!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
         let mut s = Self {
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index 3cdc9d8fb..f9c23d72b 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -7,7 +7,7 @@ use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
 use crate::time::Hertz;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 3aeb6f2c7..73ceb087a 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -6,7 +6,7 @@ use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 84613078c..cd5de54f5 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -9,7 +9,7 @@ use super::Resolution;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 const ADC_FREQ: Hertz = crate::rcc::HSI_FREQ;
 
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 43498966f..5098aadd8 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -7,11 +7,11 @@ use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
 use pac::adccommon::vals::Presc;
 use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
 
-use super::{blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime};
+use super::{Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, blocking_delay_us};
 use crate::adc::SealedAdcChannel;
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -133,7 +133,10 @@ impl<'d, T: Instance> Adc<'d, T> {
         trace!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
         let mut s = Self {
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index ea986f4cf..22ed8295f 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -22,7 +22,7 @@ use core::marker::PhantomData;
 #[allow(unused)]
 #[cfg(not(any(adc_f3v3, adc_wba)))]
 pub use _version::*;
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
 
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
index 6f69e8486..9b2e5b8fe 100644
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ b/embassy-stm32/src/adc/ringbuffered_v2.rs
@@ -1,13 +1,13 @@
 use core::marker::PhantomData;
 use core::mem;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
 use stm32_metapac::adc::vals::SampleTime;
 
 use crate::adc::{Adc, AdcChannel, Instance, RxDma};
 use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
 use crate::pac::adc::vals;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct OverrunError;
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index d09374876..a5869d110 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -9,7 +9,7 @@ use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::ADC1;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 mod watchdog_v1;
 pub use watchdog_v1::WatchdogChannels;
@@ -66,11 +66,7 @@ pub struct Temperature;
 impl AdcChannel<ADC1> for Temperature {}
 impl super::SealedAdcChannel<ADC1> for Temperature {
     fn channel(&self) -> u8 {
-        if cfg!(adc_l0) {
-            18
-        } else {
-            16
-        }
+        if cfg!(adc_l0) { 18 } else { 16 }
     }
 }
 
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index e94a25b24..93ec78548 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -2,7 +2,7 @@ use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::peripherals::ADC1;
 use crate::time::Hertz;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 mod ringbuffered_v2;
 pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 16063ce4d..47632263b 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -10,10 +10,10 @@ use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 
 use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
+    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
 };
 use crate::dma::Transfer;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index b66437e6e..c7d0103a6 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -5,11 +5,11 @@ use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
 use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
+    Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel, blocking_delay_us,
 };
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -171,7 +171,10 @@ impl<'d, T: Instance> Adc<'d, T> {
         info!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
         #[cfg(stm32h7)]
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 8eb188560..507350c42 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -5,8 +5,8 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -22,7 +22,7 @@ use crate::can::enums::{BusError, RefCountOp, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 /// Interrupt handler.
 pub struct TxInterruptHandler<T: Instance> {
@@ -186,10 +186,10 @@ impl<'d> Can<'d> {
         rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
+        + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
+        + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
+        + 'd,
     ) -> Self {
         let info = T::info();
         let regs = &T::info().regs;
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index c6a66b469..e08349f02 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -1,7 +1,7 @@
 //! Configuration for FDCAN Module
 // Note: This file is copied and modified from fdcan crate by Richard Meadows
 
-use core::num::{NonZeroU16, NonZeroU8};
+use core::num::{NonZeroU8, NonZeroU16};
 
 /// Configures the bit timings.
 ///
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index d8f71e03e..a142a6d63 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -3,8 +3,8 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -13,7 +13,7 @@ use crate::can::fd::peripheral::Registers;
 use crate::gpio::{AfType, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 pub(crate) mod fd;
 
@@ -182,8 +182,8 @@ impl<'d> CanConfigurator<'d> {
         rx: Peri<'d, impl RxPin<T>>,
         tx: Peri<'d, impl TxPin<T>>,
         _irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
+        + 'd,
     ) -> CanConfigurator<'d> {
         set_as_af!(rx, AfType::input(Pull::None));
         set_as_af!(tx, AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -459,7 +459,7 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
     pub async fn write(&mut self, frame: Frame) {
         self.tx_buf.send(frame).await;
         self.info.interrupt0.pend(); // Wake for Tx
-                                     //T::IT0Interrupt::pend(); // Wake for Tx
+        //T::IT0Interrupt::pend(); // Wake for Tx
     }
 
     /// Async read frame from RX buffer.
@@ -548,7 +548,7 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
     pub async fn write(&mut self, frame: FdFrame) {
         self.tx_buf.send(frame).await;
         self.info.interrupt0.pend(); // Wake for Tx
-                                     //T::IT0Interrupt::pend(); // Wake for Tx
+        //T::IT0Interrupt::pend(); // Wake for Tx
     }
 
     /// Async read frame from RX buffer.
diff --git a/embassy-stm32/src/can/util.rs b/embassy-stm32/src/can/util.rs
index fcdbbad62..6d7f0c16a 100644
--- a/embassy-stm32/src/can/util.rs
+++ b/embassy-stm32/src/can/util.rs
@@ -1,6 +1,6 @@
 //! Utility functions shared between CAN controller types.
 
-use core::num::{NonZeroU16, NonZeroU8};
+use core::num::{NonZeroU8, NonZeroU16};
 
 /// Shared struct to represent bit timings used by calc_can_timings.
 #[derive(Clone, Copy, Debug)]
diff --git a/embassy-stm32/src/crc/v1.rs b/embassy-stm32/src/crc/v1.rs
index 13e5263de..836228599 100644
--- a/embassy-stm32/src/crc/v1.rs
+++ b/embassy-stm32/src/crc/v1.rs
@@ -1,6 +1,6 @@
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// CRC driver.
 pub struct Crc<'d> {
diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs
index d834d0971..a566a2e04 100644
--- a/embassy-stm32/src/crc/v2v3.rs
+++ b/embassy-stm32/src/crc/v2v3.rs
@@ -1,7 +1,7 @@
-use crate::pac::crc::vals;
 use crate::pac::CRC as PAC_CRC;
+use crate::pac::crc::vals;
 use crate::peripherals::CRC;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// CRC driver.
 pub struct Crc<'d> {
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 0173b2b5d..4f1115fb7 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1236,7 +1236,10 @@ impl<'d, T: Instance, M: Mode> Cryp<'d, T, M> {
         }
         if C::REQUIRES_PADDING {
             if last_block_remainder != 0 {
-                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
+                panic!(
+                    "Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.",
+                    C::BLOCK_SIZE
+                );
             }
         }
         if last_block {
@@ -1703,7 +1706,10 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         }
         if C::REQUIRES_PADDING {
             if last_block_remainder != 0 {
-                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
+                panic!(
+                    "Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.",
+                    C::BLOCK_SIZE
+                );
             }
         }
         if last_block {
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 08e001337..d74d4a4be 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -8,7 +8,7 @@ use crate::mode::{Async, Blocking, Mode as PeriMode};
 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
 use crate::pac::dac;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 mod tsel;
 use embassy_hal_internal::PeripheralType;
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index bd03f1e00..dcae9f298 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use crate::dma::Transfer;
 use crate::gpio::{AfType, Pull};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 73ecab070..90dbf4f09 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -1,6 +1,6 @@
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicUsize, Ordering, fence};
 use core::task::{Context, Poll, Waker};
 
 use embassy_hal_internal::Peri;
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 4a14c2a8e..3e117c331 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -2,7 +2,7 @@
 
 use core::future::Future;
 use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicUsize, Ordering, fence};
 use core::task::{Context, Poll};
 
 use embassy_hal_internal::Peri;
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
index 9ee52193b..94c597e0d 100644
--- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs
+++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
@@ -3,12 +3,12 @@
 //! FIXME: Add request_pause functionality?
 //! FIXME: Stop the DMA, if a user does not queue new transfers (chain of linked-list items ends automatically).
 use core::future::poll_fn;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 use core::task::Waker;
 
 use embassy_hal_internal::Peri;
 
-use super::{AnyChannel, TransferOptions, STATE};
+use super::{AnyChannel, STATE, TransferOptions};
 use crate::dma::gpdma::linked_list::{RunMode, Table};
 use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use crate::dma::word::Word;
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 5989bfd7c..297fa3674 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -24,7 +24,7 @@ pub(crate) use util::*;
 pub(crate) mod ringbuffer;
 pub mod word;
 
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 
 use crate::interrupt;
 
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
index 661fb1728..eff5b4058 100644
--- a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
+++ b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
@@ -2,7 +2,7 @@ use std::task::Waker;
 
 use proptest::prop_oneof;
 use proptest::strategy::{self, BoxedStrategy, Strategy as _};
-use proptest_state_machine::{prop_state_machine, ReferenceStateMachine, StateMachineTest};
+use proptest_state_machine::{ReferenceStateMachine, StateMachineTest, prop_state_machine};
 
 use super::*;
 
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index deda956af..fd1682d2b 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -7,7 +7,7 @@ use embassy_hal_internal::PeripheralType;
 //use crate::gpio::{AnyPin, SealedPin};
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// Performs a busy-wait delay for a specified number of microseconds.
 pub fn blocking_delay_ms(ms: u32) {
diff --git a/embassy-stm32/src/dts/mod.rs b/embassy-stm32/src/dts/mod.rs
index 1f39c8db5..a75ae0560 100644
--- a/embassy-stm32/src/dts/mod.rs
+++ b/embassy-stm32/src/dts/mod.rs
@@ -1,7 +1,7 @@
 //! Digital Temperature Sensor (DTS)
 
 use core::future::poll_fn;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::Peri;
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 5be1c9739..a77eb8719 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -4,7 +4,7 @@ mod rx_desc;
 mod tx_desc;
 
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
 use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
@@ -190,7 +190,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
             w.set_fes(Fes::FES100); // fast ethernet speed
             w.set_dm(Dm::FULL_DUPLEX); // full duplex
-                                       // TODO: Carrier sense ? ECRSFD
+            // TODO: Carrier sense ? ECRSFD
         });
 
         // Set the mac to pass all multicast packets
@@ -350,7 +350,9 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         }
 
         #[cfg(any(eth_v1b, eth_v1c))]
-        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        config_pins!(
+            rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+        );
 
         let pins = Pins::Mii([
             rx_clk.into(),
diff --git a/embassy-stm32/src/eth/v1/rx_desc.rs b/embassy-stm32/src/eth/v1/rx_desc.rs
index 2a46c1895..6ade1f29c 100644
--- a/embassy-stm32/src/eth/v1/rx_desc.rs
+++ b/embassy-stm32/src/eth/v1/rx_desc.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{compiler_fence, fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence, fence};
 
 use stm32_metapac::eth::vals::{Rpd, Rps};
 use vcell::VolatileCell;
diff --git a/embassy-stm32/src/eth/v1/tx_desc.rs b/embassy-stm32/src/eth/v1/tx_desc.rs
index 1317d20f4..ba99b66cb 100644
--- a/embassy-stm32/src/eth/v1/tx_desc.rs
+++ b/embassy-stm32/src/eth/v1/tx_desc.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{compiler_fence, fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence, fence};
 
 use vcell::VolatileCell;
 
diff --git a/embassy-stm32/src/eth/v2/descriptors.rs b/embassy-stm32/src/eth/v2/descriptors.rs
index 645bfdb14..e335ed8f3 100644
--- a/embassy-stm32/src/eth/v2/descriptors.rs
+++ b/embassy-stm32/src/eth/v2/descriptors.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use vcell::VolatileCell;
 
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index cf7a9901b..39a6e8b0f 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -1,7 +1,7 @@
 mod descriptors;
 
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
 use stm32_metapac::syscfg::vals::EthSelPhy;
@@ -144,7 +144,9 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
                 .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
         });
 
-        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        config_pins!(
+            rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+        );
 
         let pins = Pins::Mii([
             rx_clk.into(),
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 9fce78f95..12600d4eb 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,13 +5,13 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
-use crate::pac::exti::regs::Lines;
 use crate::pac::EXTI;
-use crate::{interrupt, pac, peripherals, Peri};
+use crate::pac::exti::regs::Lines;
+use crate::{Peri, interrupt, pac, peripherals};
 
 const EXTI_COUNT: usize = 16;
 static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
diff --git a/embassy-stm32/src/flash/asynch.rs b/embassy-stm32/src/flash/asynch.rs
index 006dcddeb..a131217b7 100644
--- a/embassy-stm32/src/flash/asynch.rs
+++ b/embassy-stm32/src/flash/asynch.rs
@@ -1,17 +1,17 @@
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::mutex::Mutex;
 
 use super::{
-    blocking_read, ensure_sector_aligned, family, get_flash_regions, get_sector, Async, Error, Flash, FlashLayout,
-    FLASH_BASE, FLASH_SIZE, WRITE_SIZE,
+    Async, Error, FLASH_BASE, FLASH_SIZE, Flash, FlashLayout, WRITE_SIZE, blocking_read, ensure_sector_aligned, family,
+    get_flash_regions, get_sector,
 };
 use crate::interrupt::InterruptExt;
 use crate::peripherals::FLASH;
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 pub(super) static REGION_ACCESS: Mutex<CriticalSectionRawMutex, ()> = Mutex::new(());
 
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index 10023e637..b595938a6 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -1,14 +1,14 @@
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::drop::OnDrop;
 
 use super::{
-    family, get_flash_regions, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE,
-    MAX_ERASE_SIZE, READ_SIZE, WRITE_SIZE,
+    Async, Blocking, Error, FLASH_SIZE, FlashBank, FlashLayout, FlashRegion, FlashSector, MAX_ERASE_SIZE, READ_SIZE,
+    WRITE_SIZE, family, get_flash_regions,
 };
-use crate::Peri;
 use crate::_generated::FLASH_BASE;
+use crate::Peri;
 use crate::peripherals::FLASH;
 
 /// Internal flash memory driver.
diff --git a/embassy-stm32/src/flash/eeprom.rs b/embassy-stm32/src/flash/eeprom.rs
index cc3529eb9..39c497e3f 100644
--- a/embassy-stm32/src/flash/eeprom.rs
+++ b/embassy-stm32/src/flash/eeprom.rs
@@ -1,6 +1,6 @@
 use embassy_hal_internal::drop::OnDrop;
 
-use super::{family, Blocking, Error, Flash, EEPROM_BASE, EEPROM_SIZE};
+use super::{Blocking, EEPROM_BASE, EEPROM_SIZE, Error, Flash, family};
 
 #[cfg(eeprom)]
 impl<'d> Flash<'d, Blocking> {
diff --git a/embassy-stm32/src/flash/f0.rs b/embassy-stm32/src/flash/f0.rs
index 3f9dbe945..5c01fce9c 100644
--- a/embassy-stm32/src/flash/f0.rs
+++ b/embassy-stm32/src/flash/f0.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/f1f3.rs b/embassy-stm32/src/flash/f1f3.rs
index bf9ad2893..9e469ffbc 100644
--- a/embassy-stm32/src/flash/f1f3.rs
+++ b/embassy-stm32/src/flash/f1f3.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/f2.rs b/embassy-stm32/src/flash/f2.rs
index 67e380619..b48ab3b76 100644
--- a/embassy-stm32/src/flash/f2.rs
+++ b/embassy-stm32/src/flash/f2.rs
@@ -1,9 +1,9 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, Ordering, fence};
 
 use pac::flash::regs::Sr;
 
-use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use super::{FlashBank, FlashSector, WRITE_SIZE, get_flash_regions};
 use crate::flash::Error;
 use crate::pac;
 
diff --git a/embassy-stm32/src/flash/f4.rs b/embassy-stm32/src/flash/f4.rs
index 62e0492b5..9c5051492 100644
--- a/embassy-stm32/src/flash/f4.rs
+++ b/embassy-stm32/src/flash/f4.rs
@@ -1,10 +1,10 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, Ordering, fence};
 
 use embassy_sync::waitqueue::AtomicWaker;
 use pac::flash::regs::Sr;
 
-use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use super::{FlashBank, FlashSector, WRITE_SIZE, get_flash_regions};
 use crate::_generated::FLASH_SIZE;
 use crate::flash::Error;
 use crate::pac;
@@ -246,7 +246,9 @@ pub(crate) fn assert_not_corrupted_read(end_address: u32) {
         feature = "stm32f439zi",
     ))]
     if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
-        panic!("Read corruption for stm32f42xxI and stm32f43xxI when PA12 is in use for chips below revision 3, see errata 2.2.11");
+        panic!(
+            "Read corruption for stm32f42xxI and stm32f43xxI when PA12 is in use for chips below revision 3, see errata 2.2.11"
+        );
     }
 
     #[cfg(any(
@@ -270,14 +272,16 @@ pub(crate) fn assert_not_corrupted_read(end_address: u32) {
         feature = "stm32f439zg",
     ))]
     if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
-        panic!("Read corruption for stm32f42xxG and stm32f43xxG in dual bank mode when PA12 is in use for chips below revision 3, see errata 2.2.11");
+        panic!(
+            "Read corruption for stm32f42xxG and stm32f43xxG in dual bank mode when PA12 is in use for chips below revision 3, see errata 2.2.11"
+        );
     }
 }
 
 #[allow(unused)]
 fn pa12_is_output_pull_low() -> bool {
-    use pac::gpio::vals;
     use pac::GPIOA;
+    use pac::gpio::vals;
     const PIN: usize = 12;
     GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
         && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
@@ -287,7 +291,7 @@ fn pa12_is_output_pull_low() -> bool {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use crate::flash::{get_sector, FlashBank};
+    use crate::flash::{FlashBank, get_sector};
 
     #[test]
     #[cfg(stm32f429)]
@@ -370,9 +374,13 @@ mod tests {
 #[cfg(all(bank_setup_configurable))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optcr().read().db1m() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optcr().read().db1m() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/f7.rs b/embassy-stm32/src/flash/f7.rs
index 0547c747a..09389c417 100644
--- a/embassy-stm32/src/flash/f7.rs
+++ b/embassy-stm32/src/flash/f7.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
@@ -99,7 +99,7 @@ unsafe fn blocking_wait_ready() -> Result<(), Error> {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use crate::flash::{get_sector, FlashBank};
+    use crate::flash::{FlashBank, get_sector};
 
     #[test]
     #[cfg(stm32f732)]
@@ -218,9 +218,13 @@ mod tests {
 #[cfg(all(bank_setup_configurable))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && !pac::FLASH.optcr().read().n_dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && pac::FLASH.optcr().read().n_dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index bc1fd360c..d026541a4 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use cortex_m::interrupt;
 
@@ -105,19 +105,27 @@ fn wait_busy() {
 #[cfg(all(bank_setup_configurable, any(flash_g4c2, flash_g4c3, flash_g4c4)))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
 
 #[cfg(all(bank_setup_configurable, flash_g0x1))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dual_bank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dual_bank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/h5.rs b/embassy-stm32/src/flash/h5.rs
index fd9bfcc75..88f247879 100644
--- a/embassy-stm32/src/flash/h5.rs
+++ b/embassy-stm32/src/flash/h5.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/h50.rs b/embassy-stm32/src/flash/h50.rs
index f8e210556..91d5da4d6 100644
--- a/embassy-stm32/src/flash/h50.rs
+++ b/embassy-stm32/src/flash/h50.rs
@@ -1,7 +1,7 @@
 /// STM32H50 series flash impl. See RM0492
 use core::{
     ptr::write_volatile,
-    sync::atomic::{fence, Ordering},
+    sync::atomic::{Ordering, fence},
 };
 
 use cortex_m::interrupt;
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index f1d84101c..8a43cce3f 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -1,7 +1,7 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
-use super::{FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
+use super::{BANK1_REGION, FLASH_REGIONS, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
 
diff --git a/embassy-stm32/src/flash/l.rs b/embassy-stm32/src/flash/l.rs
index 1b82704ec..cd23cda5c 100644
--- a/embassy-stm32/src/flash/l.rs
+++ b/embassy-stm32/src/flash/l.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
@@ -234,19 +234,27 @@ pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
 #[cfg(all(bank_setup_configurable, flash_l5))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
 
 #[cfg(all(bank_setup_configurable, flash_l4))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dualbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dualbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/u0.rs b/embassy-stm32/src/flash/u0.rs
index 68d847eca..a64f6c492 100644
--- a/embassy-stm32/src/flash/u0.rs
+++ b/embassy-stm32/src/flash/u0.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use cortex_m::interrupt;
 
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
index 6c3d4b422..5f1f562c0 100644
--- a/embassy-stm32/src/flash/u5.rs
+++ b/embassy-stm32/src/flash/u5.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashBank, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index ff18a8bee..8ecfbc522 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -4,7 +4,7 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Pull, Speed};
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// FMC driver
 pub struct Fmc<'d, T: Instance> {
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 5a8d23183..b55baffdc 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -4,7 +4,7 @@
 use core::convert::Infallible;
 
 use critical_section::CriticalSection;
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 
 use crate::pac::gpio::{self, vals};
 use crate::peripherals;
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 90c06c0d8..ba573267c 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -19,7 +19,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::mode::Async;
 use crate::mode::{Blocking, Mode};
 use crate::peripherals::HASH;
-use crate::{interrupt, pac, peripherals, rcc, Peri};
+use crate::{Peri, interrupt, pac, peripherals, rcc};
 
 #[cfg(hash_v1)]
 const NUM_CONTEXT_REGS: usize = 51;
@@ -514,11 +514,7 @@ impl<'d, T: Instance> Hash<'d, T, Async> {
             T::regs().imr().modify(|reg| reg.set_dcie(true));
             // Check for completion.
             let bits = T::regs().sr().read();
-            if bits.dcis() {
-                Poll::Ready(())
-            } else {
-                Poll::Pending
-            }
+            if bits.dcis() { Poll::Ready(()) } else { Poll::Pending }
         })
         .await;
 
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 573a1851d..4d3a5d68d 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -2,13 +2,13 @@
 
 use embassy_hal_internal::PeripheralType;
 
-use crate::pac;
-use crate::rcc::{self, RccPeripheral};
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
 // which is not yet supported by this code.
 use crate::Peri;
+use crate::pac;
+use crate::rcc::{self, RccPeripheral};
 
 /// HSEM error.
 #[derive(Debug)]
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
index 95d9e5099..69baa708e 100644
--- a/embassy-stm32/src/hspi/mod.rs
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -16,7 +16,7 @@ use embassy_embedded_hal::{GetConfig, SetConfig};
 use embassy_hal_internal::{Peri, PeripheralType};
 pub use enums::*;
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::hspi::Hspi as Regs;
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 249bac41c..f4bf55d34 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -154,8 +154,8 @@ impl<'d> I2c<'d, Async, Master> {
         scl: Peri<'d, if_afio!(impl SclPin<T, A>)>,
         sda: Peri<'d, if_afio!(impl SdaPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
+        + 'd,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index 081eb1191..e6b6c7c42 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -8,7 +8,7 @@ use core::future::poll_fn;
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_futures::select::{select, Either};
+use embassy_futures::select::{Either, select};
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
 use mode::Master;
@@ -762,11 +762,7 @@ impl Timings {
             mode = Mode::Standard;
             ccr = {
                 let ccr = clock / (frequency * 2);
-                if ccr < 4 {
-                    4
-                } else {
-                    ccr
-                }
+                if ccr < 4 { 4 } else { ccr }
             };
         } else {
             const DUTYCYCLE: u8 = 0;
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 0bfc795ac..01b6b8800 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -2,7 +2,7 @@ use core::cmp;
 use core::future::poll_fn;
 use core::task::Poll;
 
-use config::{Address, OwnAddresses, OA2};
+use config::{Address, OA2, OwnAddresses};
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index b6d3daf54..db22cfa11 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -3,12 +3,12 @@
 use embassy_futures::join::join;
 use stm32_metapac::spi::vals;
 
-use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
+use crate::Peri;
+use crate::dma::{ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer, ringbuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
 use crate::spi::{Config as SpiConfig, RegsExt as _, *};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// I2S mode
 #[derive(Copy, Clone)]
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 670d8332c..e1d8b1c2a 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -1,7 +1,7 @@
 //! Inter-Process Communication Controller (IPCC)
 
 use core::future::poll_fn;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_sync::waitqueue::AtomicWaker;
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 7e0f7884e..dbf0fe620 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -1,5 +1,6 @@
 #![cfg_attr(not(test), no_std)]
 #![allow(async_fn_in_trait)]
+#![allow(unsafe_op_in_unsafe_fn)]
 #![cfg_attr(
     docsrs,
     doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-stm32'>browse the `embassy-stm32` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (stm32h7, stm32h7rs55 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
@@ -194,7 +195,7 @@ macro_rules! bind_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             $(#[cfg($cond_irq)])?
             $(#[doc = $doc])*
             unsafe extern "C" fn $irq() {
@@ -222,7 +223,7 @@ macro_rules! bind_interrupts {
 }
 
 // Reexports
-pub use _generated::{peripherals, Peripherals};
+pub use _generated::{Peripherals, peripherals};
 pub use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(feature = "unstable-pac")]
 pub use stm32_metapac as pac;
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 342f73bc8..1b66ca680 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -56,13 +56,13 @@
 
 use core::arch::asm;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
 use cortex_m::peripheral::SCB;
 use embassy_executor::*;
 
 use crate::interrupt;
-use crate::time_driver::{get_driver, RtcDriver};
+use crate::time_driver::{RtcDriver, get_driver};
 
 const THREAD_PENDER: usize = usize::MAX;
 
diff --git a/embassy-stm32/src/lptim/pwm.rs b/embassy-stm32/src/lptim/pwm.rs
index 96af9f4d9..a69db3caf 100644
--- a/embassy-stm32/src/lptim/pwm.rs
+++ b/embassy-stm32/src/lptim/pwm.rs
@@ -4,12 +4,12 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::Peri;
 
-use super::timer::Timer;
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
 use super::OutputPin;
-#[cfg(any(lptim_v2a, lptim_v2b))]
-use super::{channel::Channel, timer::ChannelDirection, Channel1Pin, Channel2Pin};
+use super::timer::Timer;
 use super::{BasicInstance, Instance};
+#[cfg(any(lptim_v2a, lptim_v2b))]
+use super::{Channel1Pin, Channel2Pin, channel::Channel, timer::ChannelDirection};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
diff --git a/embassy-stm32/src/ltdc.rs b/embassy-stm32/src/ltdc.rs
index 0f6ef569c..de2db9872 100644
--- a/embassy-stm32/src/ltdc.rs
+++ b/embassy-stm32/src/ltdc.rs
@@ -14,7 +14,7 @@ use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
-use crate::{peripherals, rcc, Peri};
+use crate::{Peri, peripherals, rcc};
 
 static LTDC_WAKER: AtomicWaker = AtomicWaker::new();
 
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index e36719ef3..ac8d5de21 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -3,10 +3,10 @@
 
 use embassy_hal_internal::PeripheralType;
 
+use crate::Peri;
 use crate::pac::opamp::vals::*;
 #[cfg(not(any(stm32g4, stm32f3)))]
 use crate::rcc::RccInfo;
-use crate::Peri;
 
 /// Performs a busy-wait delay for a specified number of microseconds.
 #[cfg(opamp_v5)]
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index d93cecb69..592a8594a 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -12,14 +12,14 @@ use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 use stm32_metapac::octospi::vals::{PhaseMode, SizeInBits};
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::octospi::{vals, Octospi as Regs};
+use crate::pac::octospi::{Octospi as Regs, vals};
 #[cfg(octospim_v1)]
 use crate::pac::octospim::Octospim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// OPSI driver config.
 #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index b03cd9009..bb4f4f1d0 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -14,7 +14,7 @@ use crate::gpio::{AfType, AnyPin, OutputType, Pull, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::quadspi::Quadspi as Regs;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// QSPI transfer configuration.
 #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 63fc195dd..3b2a10581 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,6 +1,6 @@
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 
-use crate::pac::common::{Reg, RW};
+use crate::pac::common::{RW, Reg};
 pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
 use crate::time::Hertz;
 
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index 8f2e8db5f..d941054cd 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -1,13 +1,13 @@
 use stm32_metapac::flash::vals::Latency;
 
+#[cfg(any(stm32f4, stm32f7))]
+use crate::pac::PWR;
 #[cfg(any(stm32f413, stm32f423, stm32f412))]
 pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource;
 pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
-#[cfg(any(stm32f4, stm32f7))]
-use crate::pac::PWR;
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 331bab7a0..485edd390 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -597,7 +597,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 81b89046e..2e1cbd702 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -499,9 +499,9 @@ pub use pll::*;
 
 #[cfg(any(stm32l0, stm32l1))]
 mod pll {
-    use super::{pll_enable, PllInstance};
-    pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
+    use super::{PllInstance, pll_enable};
     use crate::pac::RCC;
+    pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
     use crate::time::Hertz;
 
     #[derive(Clone, Copy)]
@@ -563,11 +563,11 @@ mod pll {
 
 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl, stm32u0))]
 mod pll {
-    use super::{pll_enable, PllInstance};
+    use super::{PllInstance, pll_enable};
+    use crate::pac::RCC;
     pub use crate::pac::rcc::vals::{
         Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource,
     };
-    use crate::pac::RCC;
     use crate::time::Hertz;
 
     #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index 59ccc8cb5..3d961df03 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -3,6 +3,7 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Speed};
+use crate::pac::RCC;
 #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
 pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
 #[cfg(not(any(
@@ -31,8 +32,7 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
     rcc_h7rs
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
-use crate::pac::RCC;
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 #[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -91,12 +91,29 @@ pub struct Mco<'d, T: McoInstance> {
 
 impl<'d, T: McoInstance> Mco<'d, T> {
     /// Create a new MCO instance.
-    pub fn new(_peri: Peri<'d, T>, pin: Peri<'d, impl McoPin<T>>, source: T::Source, prescaler: McoPrescaler) -> Self {
+    pub fn new(_peri: Peri<'d, T>, pin: Peri<'d, impl McoPin<T>>, source: T::Source, config: McoConfig) -> Self {
         critical_section::with(|_| unsafe {
-            T::_apply_clock_settings(source, prescaler);
-            set_as_af!(pin, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            T::_apply_clock_settings(source, config.prescaler);
+            set_as_af!(pin, AfType::output(OutputType::PushPull, config.speed));
         });
 
         Self { phantom: PhantomData }
     }
 }
+
+#[non_exhaustive]
+pub struct McoConfig {
+    /// Master Clock Out prescaler
+    pub prescaler: McoPrescaler,
+    /// IO Drive Strength
+    pub speed: Speed,
+}
+
+impl Default for McoConfig {
+    fn default() -> Self {
+        Self {
+            prescaler: McoPrescaler::DIV1,
+            speed: Speed::VeryHigh,
+        }
+    }
+}
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c41f81816..addfca3c3 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -33,7 +33,7 @@ mod _version;
 pub use _version::*;
 use stm32_metapac::RCC;
 
-pub use crate::_generated::{mux, Clocks};
+pub use crate::_generated::{Clocks, mux};
 use crate::time::Hertz;
 
 #[cfg(feature = "low-power")]
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 06895a99a..7b0dcb63f 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -6,9 +6,9 @@ pub use crate::pac::rcc::vals::{
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::rcc::vals::{Hseext, Msipllfast, Msipllsel, Msirgsel, Pllmboost, Pllrge};
-#[cfg(all(peri_usb_otg_hs))]
-pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, PWR, RCC};
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::{SYSCFG, syscfg::vals::Usbrefcksel};
 use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 
@@ -442,7 +442,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 481437939..2528996d5 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -7,9 +7,9 @@ pub use crate::pac::rcc::vals::{
     Hdiv5, Hpre as AHBPrescaler, Hpre5 as AHB5Prescaler, Hsepre as HsePrescaler, Plldiv as PllDiv, Pllm as PllPreDiv,
     Plln as PllMul, Pllsrc as PllSource, Ppre as APBPrescaler, Sai1sel, Sw as Sysclk,
 };
-#[cfg(all(peri_usb_otg_hs))]
-pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, RCC};
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::{SYSCFG, syscfg::vals::Usbrefcksel};
 use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 
@@ -245,7 +245,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index 63654639e..dada9bda1 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -9,7 +9,7 @@ use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, pac, peripherals, rcc, Peri};
+use crate::{Peri, interrupt, pac, peripherals, rcc};
 
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
 
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index a81ac6746..999f24714 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -1,7 +1,7 @@
 #[cfg(feature = "time")]
 use embassy_time::{Duration, TICK_HZ};
 
-use super::{bcd2_to_byte, DateTimeError, Rtc, RtcError};
+use super::{DateTimeError, Rtc, RtcError, bcd2_to_byte};
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::RTC;
 use crate::rtc::SealedInstance;
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 92dec0960..bc6df528b 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -8,12 +8,12 @@ mod low_power;
 use core::cell::Cell;
 
 #[cfg(feature = "low-power")]
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
-#[cfg(feature = "low-power")]
 use embassy_sync::blocking_mutex::Mutex;
+#[cfg(feature = "low-power")]
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 
-use self::datetime::{day_of_week_from_u8, day_of_week_to_u8};
 pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
+use self::datetime::{day_of_week_from_u8, day_of_week_to_u8};
 use crate::pac::rtc::regs::{Dr, Tr};
 use crate::time::Hertz;
 
@@ -25,8 +25,8 @@ mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
 
-use crate::peripherals::RTC;
 use crate::Peri;
+use crate::peripherals::RTC;
 
 /// Errors that can occur on methods on [RtcClock]
 #[non_exhaustive]
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index d0b52049e..01da5d70a 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Key, Osel, Pol, TampalrmType};
+use stm32_metapac::rtc::vals::{Calp, Calw8, Calw16, Fmt, Key, Osel, Pol, TampalrmType};
 
 use super::RtcCalibrationCyclePeriod;
 use crate::pac::rtc::Rtc;
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index fb8b23b79..726d1729a 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -6,12 +6,12 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 pub use crate::dma::word;
-use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
+use crate::dma::{Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer, ringbuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 pub use crate::pac::sai::vals::Mckdiv as MasterClockDivider;
-use crate::pac::sai::{vals, Sai as Regs};
+use crate::pac::sai::{Sai as Regs, vals};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// SAI error
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index ccbd16cbf..408d1b764 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -11,9 +11,9 @@ use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 use sdio_host::common_cmd::{self, Resp, ResponseLen};
-use sdio_host::emmc::{ExtCSD, EMMC};
-use sdio_host::sd::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CIC, CID, CSD, OCR, RCA, SCR, SD};
-use sdio_host::{emmc_cmd, sd_cmd, Cmd};
+use sdio_host::emmc::{EMMC, ExtCSD};
+use sdio_host::sd::{BusWidth, CIC, CID, CSD, CardCapacity, CardStatus, CurrentState, OCR, RCA, SCR, SD, SDStatus};
+use sdio_host::{Cmd, emmc_cmd, sd_cmd};
 
 #[cfg(sdmmc_v1)]
 use crate::dma::ChannelAndRequest;
diff --git a/embassy-stm32/src/spdifrx/mod.rs b/embassy-stm32/src/spdifrx/mod.rs
index b0a32d5d1..6f2d24560 100644
--- a/embassy-stm32/src/spdifrx/mod.rs
+++ b/embassy-stm32/src/spdifrx/mod.rs
@@ -13,7 +13,7 @@ use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::spdifrx::Spdifrx as Regs;
 use crate::rcc::{RccInfo, SealedRccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 /// Possible S/PDIF preamble types.
 #[allow(dead_code)]
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index c5373a54d..c27d09ea7 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -6,15 +6,15 @@ use core::ptr;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_futures::join::join;
-pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use embedded_hal_02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::Peri;
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::spi::{regs, vals, Spi as Regs};
+use crate::pac::spi::{Spi as Regs, regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// SPI error.
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 7db74bdf6..74b10a183 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,14 +1,14 @@
 #![allow(non_snake_case)]
 
 use core::cell::{Cell, RefCell};
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 use critical_section::CriticalSection;
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::blocking_mutex::Mutex;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_time_driver::{Driver, TICK_HZ};
 use embassy_time_queue_utils::Queue;
-use stm32_metapac::timer::{regs, TimGp16};
+use stm32_metapac::timer::{TimGp16, regs};
 
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::timer::vals;
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 484aae1d0..75a83629c 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -7,11 +7,11 @@ pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr};
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
 use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
+use crate::Peri;
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
-use crate::timer::low_level::OutputCompareMode;
 use crate::timer::TimerChannel;
-use crate::Peri;
+use crate::timer::low_level::OutputCompareMode;
 
 /// Complementary PWM pin wrapper.
 ///
@@ -388,7 +388,7 @@ fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
 
 #[cfg(test)]
 mod tests {
-    use super::{compute_dead_time_value, Ckd};
+    use super::{Ckd, compute_dead_time_value};
 
     #[test]
     fn test_compute_dead_time_value() {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 7a25e6c21..2a4ec2db0 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -8,11 +8,11 @@ use core::task::{Context, Poll};
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
 use super::{CaptureCompareInterruptHandler, Channel, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2, Ch3, Ch4};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
-use crate::Peri;
 
 /// Capture pin wrapper.
 ///
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index a75b41bd7..fe8681356 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -11,12 +11,12 @@ use super::low_level::{
 };
 use super::{CaptureCompareInterruptHandler, Channel, ExternalTriggerPin, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::pac::timer::vals::Etp;
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
-use crate::Peri;
 
 /// External input marker type.
 pub enum Ext {}
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 159b5a177..da8a79b09 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -2,9 +2,9 @@
 
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
 use super::{Ch1, Ch2, Channel, GeneralInstance4Channel, TimerPin};
+use crate::Peri;
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// PWM Input driver.
 ///
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index 82b5968b0..a547a2a19 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -1,45 +1,67 @@
 //! Quadrature decoder using a timer.
 
-use core::marker::PhantomData;
-
-use stm32_metapac::timer::vals;
+use stm32_metapac::timer::vals::{self, Sms};
 
 use super::low_level::Timer;
 pub use super::{Ch1, Ch2};
 use super::{GeneralInstance4Channel, TimerPin};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::timer::TimerChannel;
-use crate::Peri;
 
-/// Counting direction
-pub enum Direction {
-    /// Counting up.
-    Upcounting,
-    /// Counting down.
-    Downcounting,
+/// Qei driver config.
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy)]
+pub struct Config {
+    /// Configures the internal pull up/down resistor for Qei's channel 1 pin.
+    pub ch1_pull: Pull,
+    /// Configures the internal pull up/down resistor for Qei's channel 2 pin.
+    pub ch2_pull: Pull,
+    /// Specifies the encoder mode to use for the Qei peripheral.
+    pub mode: QeiMode,
 }
 
-/// Wrapper for using a pin with QEI.
-pub struct QeiPin<'d, T, Channel, #[cfg(afio)] A> {
-    #[allow(unused)]
-    pin: Peri<'d, AnyPin>,
-    phantom: PhantomData<if_afio!((T, Channel, A))>,
+impl Default for Config {
+    /// Arbitrary defaults to preserve backwards compatibility
+    fn default() -> Self {
+        Self {
+            ch1_pull: Pull::None,
+            ch2_pull: Pull::None,
+            mode: QeiMode::Mode3,
+        }
+    }
 }
 
-impl<'d, T: GeneralInstance4Channel, C: QeiChannel, #[cfg(afio)] A> if_afio!(QeiPin<'d, T, C, A>) {
-    /// Create a new QEI pin instance.
-    pub fn new(pin: Peri<'d, if_afio!(impl TimerPin<T, C, A>)>) -> Self {
-        critical_section::with(|_| {
-            pin.set_low();
-            set_as_af!(pin, AfType::input(Pull::None));
-        });
-        QeiPin {
-            pin: pin.into(),
-            phantom: PhantomData,
+/// See STMicro AN4013 for §2.3 for more information
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy)]
+pub enum QeiMode {
+    /// Direct alias for [`Sms::ENCODER_MODE_1`]
+    Mode1,
+    /// Direct alias for [`Sms::ENCODER_MODE_2`]
+    Mode2,
+    /// Direct alias for [`Sms::ENCODER_MODE_3`]
+    Mode3,
+}
+
+impl From<QeiMode> for Sms {
+    fn from(mode: QeiMode) -> Self {
+        match mode {
+            QeiMode::Mode1 => Sms::ENCODER_MODE_1,
+            QeiMode::Mode2 => Sms::ENCODER_MODE_2,
+            QeiMode::Mode3 => Sms::ENCODER_MODE_3,
         }
     }
 }
 
+/// Counting direction
+pub enum Direction {
+    /// Counting up.
+    Upcounting,
+    /// Counting down.
+    Downcounting,
+}
+
 trait SealedQeiChannel: TimerChannel {}
 
 /// Marker trait for a timer channel eligible for use with QEI.
@@ -55,20 +77,28 @@ impl SealedQeiChannel for Ch2 {}
 /// Quadrature decoder driver.
 pub struct Qei<'d, T: GeneralInstance4Channel> {
     inner: Timer<'d, T>,
+    _ch1: Peri<'d, AnyPin>,
+    _ch2: Peri<'d, AnyPin>,
 }
 
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
-    /// Create a new quadrature decoder driver.
+    /// Create a new quadrature decoder driver, with a given [`Config`].
     #[allow(unused)]
-    pub fn new<#[cfg(afio)] A>(
+    pub fn new<CH1: QeiChannel, CH2: QeiChannel, #[cfg(afio)] A>(
         tim: Peri<'d, T>,
-        ch1: if_afio!(QeiPin<'d, T, Ch1, A>),
-        ch2: if_afio!(QeiPin<'d, T, Ch2, A>),
+        ch1: Peri<'d, if_afio!(impl TimerPin<T, CH1, A>)>,
+        ch2: Peri<'d, if_afio!(impl TimerPin<T, CH2, A>)>,
+        config: Config,
     ) -> Self {
-        Self::new_inner(tim)
-    }
+        // Configure the pins to be used for the QEI peripheral.
+        critical_section::with(|_| {
+            ch1.set_low();
+            set_as_af!(ch1, AfType::input(config.ch1_pull));
+
+            ch2.set_low();
+            set_as_af!(ch2, AfType::input(config.ch2_pull));
+        });
 
-    fn new_inner(tim: Peri<'d, T>) -> Self {
         let inner = Timer::new(tim);
         let r = inner.regs_gp16();
 
@@ -88,13 +118,17 @@ impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
         });
 
         r.smcr().modify(|w| {
-            w.set_sms(vals::Sms::ENCODER_MODE_3);
+            w.set_sms(config.mode.into());
         });
 
         r.arr().modify(|w| w.set_arr(u16::MAX));
         r.cr1().modify(|w| w.set_cen(true));
 
-        Self { inner }
+        Self {
+            inner,
+            _ch1: ch1.into(),
+            _ch2: ch2.into(),
+        }
     }
 
     /// Get direction.
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index e60bb5b06..36303aeb4 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -5,11 +5,11 @@ use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
 use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
+use crate::Peri;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// PWM pin wrapper.
 ///
diff --git a/embassy-stm32/src/tsc/acquisition_banks.rs b/embassy-stm32/src/tsc/acquisition_banks.rs
index 7d6442b48..097cf7942 100644
--- a/embassy-stm32/src/tsc/acquisition_banks.rs
+++ b/embassy-stm32/src/tsc/acquisition_banks.rs
@@ -1,11 +1,11 @@
+use super::TSC_NUM_GROUPS;
 use super::io_pin::*;
 #[cfg(any(tsc_v2, tsc_v3))]
 use super::pin_groups::G7;
 #[cfg(tsc_v3)]
 use super::pin_groups::G8;
-use super::pin_groups::{pin_roles, G1, G2, G3, G4, G5, G6};
+use super::pin_groups::{G1, G2, G3, G4, G5, G6, pin_roles};
 use super::types::{Group, GroupStatus};
-use super::TSC_NUM_GROUPS;
 
 /// Represents a collection of TSC (Touch Sensing Controller) pins for an acquisition bank.
 ///
diff --git a/embassy-stm32/src/tsc/pin_groups.rs b/embassy-stm32/src/tsc/pin_groups.rs
index 84421f7ff..9347e6bc0 100644
--- a/embassy-stm32/src/tsc/pin_groups.rs
+++ b/embassy-stm32/src/tsc/pin_groups.rs
@@ -1,11 +1,11 @@
 use core::marker::PhantomData;
 use core::ops::BitOr;
 
+use super::Instance;
 use super::errors::GroupError;
 use super::io_pin::*;
-use super::Instance;
-use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::Peri;
+use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 
 /// Pin type definition to control IO parameters
 #[derive(PartialEq, Clone, Copy)]
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 18aff4fbd..8f259a917 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -19,8 +19,8 @@ use core::marker::PhantomData;
 use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
-use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::{ChannelAndRequest, TransferOptions};
@@ -28,7 +28,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
 pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, Rxordset, TypecVstateCc as CcVState};
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 pub(crate) fn init(
     _cs: critical_section::CriticalSection,
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index c734eed49..69c3a740f 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -1,20 +1,20 @@
 use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::slice;
-use core::sync::atomic::{AtomicBool, AtomicU8, Ordering};
+use core::sync::atomic::{AtomicBool, AtomicU8, AtomicUsize, Ordering};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use embassy_hal_internal::Peri;
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use embassy_sync::waitqueue::AtomicWaker;
 
 #[cfg(not(any(usart_v1, usart_v2)))]
 use super::DePin;
 use super::{
+    Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin, TxPin,
     clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate,
-    sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin,
-    TxPin,
+    sr, tdr,
 };
 use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::{self, InterruptExt};
@@ -68,8 +68,15 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
             // FIXME: Should we disable any further RX interrupts when the buffer becomes full.
         }
 
-        if !state.rx_buf.is_empty() {
-            state.rx_waker.wake();
+        let eager = state.eager_reads.load(Ordering::Relaxed);
+        if eager > 0 {
+            if state.rx_buf.available() >= eager {
+                state.rx_waker.wake();
+            }
+        } else {
+            if state.rx_buf.is_half_full() {
+                state.rx_waker.wake();
+            }
         }
     }
 
@@ -132,6 +139,7 @@ pub(super) struct State {
     tx_done: AtomicBool,
     tx_rx_refcount: AtomicU8,
     half_duplex_readback: AtomicBool,
+    eager_reads: AtomicUsize,
 }
 
 impl State {
@@ -144,6 +152,7 @@ impl State {
             tx_done: AtomicBool::new(true),
             tx_rx_refcount: AtomicU8::new(0),
             half_duplex_readback: AtomicBool::new(false),
+            eager_reads: AtomicUsize::new(0),
         }
     }
 }
@@ -419,6 +428,9 @@ impl<'d> BufferedUart<'d> {
         let state = T::buffered_state();
         let kernel_clock = T::frequency();
 
+        state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
         state.half_duplex_readback.store(
             config.duplex == Duplex::Half(HalfDuplexReadback::Readback),
             Ordering::Relaxed,
@@ -456,6 +468,9 @@ impl<'d> BufferedUart<'d> {
         let info = self.rx.info;
         let state = self.rx.state;
         state.tx_rx_refcount.store(2, Ordering::Relaxed);
+        state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -527,6 +542,11 @@ impl<'d> BufferedUart<'d> {
     pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
         reconfigure(self.rx.info, self.rx.kernel_clock, config)?;
 
+        self.rx
+            .state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
+
         self.rx.info.regs.cr1().modify(|w| {
             w.set_rxneie(true);
             w.set_idleie(true);
@@ -553,24 +573,30 @@ impl<'d> BufferedUartRx<'d> {
         poll_fn(move |cx| {
             let state = self.state;
             let mut rx_reader = unsafe { state.rx_buf.reader() };
-            let data = rx_reader.pop_slice();
+            let mut buf_len = 0;
+            let mut data = rx_reader.pop_slice();
 
-            if !data.is_empty() {
-                let len = data.len().min(buf.len());
-                buf[..len].copy_from_slice(&data[..len]);
+            while !data.is_empty() && buf_len < buf.len() {
+                let data_len = data.len().min(buf.len() - buf_len);
+                buf[buf_len..buf_len + data_len].copy_from_slice(&data[..data_len]);
+                buf_len += data_len;
 
                 let do_pend = state.rx_buf.is_full();
-                rx_reader.pop_done(len);
+                rx_reader.pop_done(data_len);
 
                 if do_pend {
                     self.info.interrupt.pend();
                 }
 
-                return Poll::Ready(Ok(len));
+                data = rx_reader.pop_slice();
             }
 
-            state.rx_waker.register(cx.waker());
-            Poll::Pending
+            if buf_len != 0 {
+                Poll::Ready(Ok(buf_len))
+            } else {
+                state.rx_waker.register(cx.waker());
+                Poll::Pending
+            }
         })
         .await
     }
@@ -579,21 +605,24 @@ impl<'d> BufferedUartRx<'d> {
         loop {
             let state = self.state;
             let mut rx_reader = unsafe { state.rx_buf.reader() };
-            let data = rx_reader.pop_slice();
+            let mut buf_len = 0;
+            let mut data = rx_reader.pop_slice();
 
-            if !data.is_empty() {
-                let len = data.len().min(buf.len());
-                buf[..len].copy_from_slice(&data[..len]);
+            while !data.is_empty() && buf_len < buf.len() {
+                let data_len = data.len().min(buf.len() - buf_len);
+                buf[buf_len..buf_len + data_len].copy_from_slice(&data[..data_len]);
+                buf_len += data_len;
 
                 let do_pend = state.rx_buf.is_full();
-                rx_reader.pop_done(len);
+                rx_reader.pop_done(data_len);
 
                 if do_pend {
                     self.info.interrupt.pend();
                 }
 
-                return Ok(len);
+                data = rx_reader.pop_slice();
             }
+            return Ok(buf_len);
         }
     }
 
@@ -633,6 +662,10 @@ impl<'d> BufferedUartRx<'d> {
     pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
         reconfigure(self.info, self.kernel_clock, config)?;
 
+        self.state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
+
         self.info.regs.cr1().modify(|w| {
             w.set_rxneie(true);
             w.set_idleie(true);
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index ff211e0c9..0e7da634d 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -4,15 +4,16 @@
 
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, AtomicU8, Ordering};
+use core::sync::atomic::{AtomicU8, AtomicUsize, Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::waitqueue::AtomicWaker;
-use futures_util::future::{select, Either};
+use futures_util::future::{Either, select};
 
+use crate::Peri;
 use crate::dma::ChannelAndRequest;
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt as _;
@@ -25,7 +26,6 @@ use crate::pac::usart::Usart as Regs;
 use crate::pac::usart::{regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -185,6 +185,12 @@ pub enum ConfigError {
     RxOrTxNotEnabled,
     /// Data bits and parity combination not supported
     DataParityNotSupported,
+    /// DE assertion time too high
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    DeAssertionTimeTooHigh,
+    /// DE deassertion time too high
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    DeDeassertionTimeTooHigh,
 }
 
 #[non_exhaustive]
@@ -206,6 +212,21 @@ pub struct Config {
     /// If false: the error is ignored and cleared
     pub detect_previous_overrun: bool,
 
+    /// If `None` (the default) then read-like calls on `BufferedUartRx` and `RingBufferedUartRx`
+    /// typically only wake/return after line idle or after the buffer is at least half full
+    /// (for `BufferedUartRx`) or the DMA buffer is written at the half or full positions
+    /// (for `RingBufferedUartRx`), though it may also wake/return earlier in some circumstances.
+    ///
+    /// If `Some(n)` then such reads are also woken/return as soon as at least `n` words are
+    /// available in the buffer, in addition to waking/returning when the conditions described
+    /// above are met. `Some(0)` is treated as `None`. Setting this for `RingBufferedUartRx`
+    /// will trigger an interrupt for every received word to check the buffer level, which may
+    /// impact performance at high data rates.
+    ///
+    /// Has no effect on plain `Uart` or `UartRx` reads, which are specified to either
+    /// return a single word, a full buffer, or after line idle.
+    pub eager_reads: Option<usize>,
+
     /// Set this to true if the line is considered noise free.
     /// This will increase the receiver’s tolerance to clock deviations,
     /// but will effectively disable noise detection.
@@ -239,6 +260,14 @@ pub struct Config {
     /// Set the pin configuration for the DE pin.
     pub de_config: OutputConfig,
 
+    /// Set DE assertion time before the first start bit, 0-31 16ths of a bit period.
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    pub de_assertion_time: u8,
+
+    /// Set DE deassertion time after the last stop bit, 0-31 16ths of a bit period.
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    pub de_deassertion_time: u8,
+
     // private: set by new_half_duplex, not by the user.
     duplex: Duplex,
 }
@@ -270,6 +299,7 @@ impl Default for Config {
             parity: Parity::ParityNone,
             // historical behavior
             detect_previous_overrun: false,
+            eager_reads: None,
             #[cfg(not(usart_v1))]
             assume_noise_free: false,
             #[cfg(any(usart_v3, usart_v4))]
@@ -283,6 +313,10 @@ impl Default for Config {
             tx_config: OutputConfig::PushPull,
             rts_config: OutputConfig::PushPull,
             de_config: OutputConfig::PushPull,
+            #[cfg(not(any(usart_v1, usart_v2)))]
+            de_assertion_time: 0,
+            #[cfg(not(any(usart_v1, usart_v2)))]
+            de_deassertion_time: 0,
             duplex: Duplex::Full,
         }
     }
@@ -966,6 +1000,9 @@ impl<'d, M: Mode> UartRx<'d, M> {
         let info = self.info;
         let state = self.state;
         state.tx_rx_refcount.store(1, Ordering::Relaxed);
+        state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -982,6 +1019,9 @@ impl<'d, M: Mode> UartRx<'d, M> {
 
     /// Reconfigure the driver
     pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        self.state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
         reconfigure(self.info, self.kernel_clock, config)
     }
 
@@ -1462,6 +1502,9 @@ impl<'d, M: Mode> Uart<'d, M> {
         let info = self.rx.info;
         let state = self.rx.state;
         state.tx_rx_refcount.store(2, Ordering::Relaxed);
+        state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
 
         info.rcc.enable_and_reset();
 
@@ -1690,6 +1733,16 @@ fn configure(
         return Err(ConfigError::RxOrTxNotEnabled);
     }
 
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    let dem = r.cr3().read().dem();
+
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    if config.de_assertion_time > 31 {
+        return Err(ConfigError::DeAssertionTimeTooHigh);
+    } else if config.de_deassertion_time > 31 {
+        return Err(ConfigError::DeDeassertionTimeTooHigh);
+    }
+
     // UART must be disabled during configuration.
     r.cr1().modify(|w| {
         w.set_ue(false);
@@ -1738,6 +1791,20 @@ fn configure(
             w.set_re(enable_rx);
         }
 
+        #[cfg(not(any(usart_v1, usart_v2)))]
+        if dem {
+            w.set_deat(if over8 {
+                config.de_assertion_time / 2
+            } else {
+                config.de_assertion_time
+            });
+            w.set_dedt(if over8 {
+                config.de_assertion_time / 2
+            } else {
+                config.de_assertion_time
+            });
+        }
+
         // configure word size and parity, since the parity bit is inserted into the MSB position,
         // it increases the effective word size
         match (config.parity, config.data_bits) {
@@ -2022,6 +2089,7 @@ struct State {
     rx_waker: AtomicWaker,
     tx_waker: AtomicWaker,
     tx_rx_refcount: AtomicU8,
+    eager_reads: AtomicUsize,
 }
 
 impl State {
@@ -2030,6 +2098,7 @@ impl State {
             rx_waker: AtomicWaker::new(),
             tx_waker: AtomicWaker::new(),
             tx_rx_refcount: AtomicU8::new(0),
+            eager_reads: AtomicUsize::new(0),
         }
     }
 }
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 5f4e87834..20bfefd9e 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -1,19 +1,19 @@
 use core::future::poll_fn;
 use core::mem;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embedded_io_async::ReadReady;
-use futures_util::future::{select, Either};
+use futures_util::future::{Either, select};
 
-use super::{rdr, reconfigure, set_baudrate, sr, Config, ConfigError, Error, Info, State, UartRx};
+use super::{Config, ConfigError, Error, Info, State, UartRx, rdr, reconfigure, set_baudrate, sr};
+use crate::Peri;
 use crate::dma::ReadableRingBuffer;
 use crate::gpio::{AnyPin, SealedPin as _};
 use crate::mode::Async;
 use crate::time::Hertz;
 use crate::usart::Regs;
-use crate::Peri;
 
 /// Rx-only Ring-buffered UART Driver
 ///
@@ -26,9 +26,9 @@ use crate::Peri;
 /// contain enough bytes to fill the buffer passed by the caller of
 /// the function, or is empty.
 ///
-/// Waiting for bytes operates in one of two modes, depending on
-/// the behavior of the sender and the size of the buffer passed
-/// to the function:
+/// Waiting for bytes operates in one of three modes, depending on
+/// the behavior of the sender, the size of the buffer passed
+/// to the function, and the configuration:
 ///
 /// - If the sender sends intermittently, the 'idle line'
 /// condition will be detected when the sender stops, and any
@@ -47,7 +47,11 @@ use crate::Peri;
 /// interrupt when those specific buffer addresses have been
 /// written.
 ///
-/// In both cases this will result in variable latency due to the
+/// - If `eager_reads` is enabled in `config`, the UART interrupt
+/// is enabled on all data reception and the call will only wait
+/// for at least one byte to be available before returning.
+///
+/// In the first two cases this will result in variable latency due to the
 /// buffering effect. For example, if the baudrate is 2400 bps, and
 /// the configuration is 8 data bits, no parity bit, and one stop bit,
 /// then a byte will be received every ~4.16ms. If the ring buffer is
@@ -68,15 +72,10 @@ use crate::Peri;
 /// sending, but would be falsely triggered in the worst-case
 /// buffer delay scenario.
 ///
-/// Note: This latency is caused by the limited capabilities of the
-/// STM32 DMA controller; since it cannot generate an interrupt when
-/// it stores a byte into an empty ring buffer, or in any other
-/// configurable conditions, it is not possible to take notice of the
-/// contents of the ring buffer more quickly without introducing
-/// polling. As a result the latency can be reduced by calling the
-/// read functions repeatedly with smaller buffers to receive the
-/// available bytes, as each call to a read function will explicitly
-/// check the ring buffer for available bytes.
+/// Note: Enabling `eager_reads` with `RingBufferedUartRx` will enable
+/// an UART RXNE interrupt, which will cause an interrupt to occur on
+/// every received data byte. The data is still copied using DMA, but
+/// there is nevertheless additional processing overhead for each byte.
 pub struct RingBufferedUartRx<'d> {
     info: &'static Info,
     state: &'static State,
@@ -133,6 +132,9 @@ impl<'d> UartRx<'d, Async> {
 impl<'d> RingBufferedUartRx<'d> {
     /// Reconfigure the driver
     pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
+        self.state
+            .eager_reads
+            .store(config.eager_reads.unwrap_or(0), Ordering::Relaxed);
         reconfigure(self.info, self.kernel_clock, config)
     }
 
@@ -148,8 +150,8 @@ impl<'d> RingBufferedUartRx<'d> {
         let r = self.info.regs;
         // clear all interrupts and DMA Rx Request
         r.cr1().modify(|w| {
-            // disable RXNE interrupt
-            w.set_rxneie(false);
+            // use RXNE only when returning reads early
+            w.set_rxneie(self.state.eager_reads.load(Ordering::Relaxed) > 0);
             // enable parity interrupt if not ParityNone
             w.set_peie(w.pce());
             // enable idle line interrupt
@@ -248,39 +250,67 @@ impl<'d> RingBufferedUartRx<'d> {
     async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> {
         compiler_fence(Ordering::SeqCst);
 
-        // Future which completes when idle line is detected
-        let s = self.state;
-        let uart = poll_fn(|cx| {
-            s.rx_waker.register(cx.waker());
-
-            compiler_fence(Ordering::SeqCst);
-
-            if check_idle_and_errors(self.info.regs)? {
-                // Idle line is detected
-                Poll::Ready(Ok(()))
-            } else {
-                Poll::Pending
-            }
-        });
+        loop {
+            // Future which completes when idle line is detected
+            let s = self.state;
+            let mut uart_init = false;
+            let uart = poll_fn(|cx| {
+                s.rx_waker.register(cx.waker());
+
+                compiler_fence(Ordering::SeqCst);
+
+                // We may have been woken by IDLE or, if eager_reads is set, by RXNE.
+                // However, DMA will clear RXNE, so we can't check directly, and because
+                // the other future borrows `ring_buf`, we can't check `len()` here either.
+                // Instead, return from this future and we'll check the length afterwards.
+                let eager = s.eager_reads.load(Ordering::Relaxed) > 0;
+
+                let idle = check_idle_and_errors(self.info.regs)?;
+                if idle || (eager && uart_init) {
+                    // Idle line is detected, or eager reads is set and some data is available.
+                    Poll::Ready(Ok(idle))
+                } else {
+                    uart_init = true;
+                    Poll::Pending
+                }
+            });
 
-        let mut dma_init = false;
-        // Future which completes when the DMA controller indicates it
-        // has written to the ring buffer's middle byte, or last byte
-        let dma = poll_fn(|cx| {
-            self.ring_buf.set_waker(cx.waker());
+            let mut dma_init = false;
+            // Future which completes when the DMA controller indicates it
+            // has written to the ring buffer's middle byte, or last byte
+            let dma = poll_fn(|cx| {
+                self.ring_buf.set_waker(cx.waker());
 
-            let status = match dma_init {
-                false => Poll::Pending,
-                true => Poll::Ready(()),
-            };
+                let status = match dma_init {
+                    false => Poll::Pending,
+                    true => Poll::Ready(()),
+                };
 
-            dma_init = true;
-            status
-        });
+                dma_init = true;
+                status
+            });
 
-        match select(uart, dma).await {
-            Either::Left((result, _)) => result,
-            Either::Right(((), _)) => Ok(()),
+            match select(uart, dma).await {
+                // UART woke with line idle
+                Either::Left((Ok(true), _)) => {
+                    return Ok(());
+                }
+                // UART woke without idle or error: word received
+                Either::Left((Ok(false), _)) => {
+                    let eager = self.state.eager_reads.load(Ordering::Relaxed);
+                    if eager > 0 && self.ring_buf.len().unwrap_or(0) >= eager {
+                        return Ok(());
+                    } else {
+                        continue;
+                    }
+                }
+                // UART woke with error
+                Either::Left((Err(e), _)) => {
+                    return Err(e);
+                }
+                // DMA woke
+                Either::Right(((), _)) => return Ok(()),
+            }
         }
     }
 
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 5ce81b131..f6b1a81db 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -2,18 +2,18 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::PeripheralType;
 use embassy_usb_driver::{EndpointAddress, EndpointAllocError, EndpointType, Event, Unsupported};
-use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
-use embassy_usb_synopsys_otg::otg_v1::Otg;
 pub use embassy_usb_synopsys_otg::Config;
+use embassy_usb_synopsys_otg::otg_v1::Otg;
+use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
 use embassy_usb_synopsys_otg::{
-    on_interrupt as on_interrupt_impl, Bus as OtgBus, ControlPipe, Driver as OtgDriver, Endpoint, In, OtgInstance, Out,
-    PhyType, State,
+    Bus as OtgBus, ControlPipe, Driver as OtgDriver, Endpoint, In, OtgInstance, Out, PhyType, State,
+    on_interrupt as on_interrupt_impl,
 };
 
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 const MAX_EP_COUNT: usize = 9;
 
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 9e08d99b3..d405e4802 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -12,11 +12,11 @@ use embassy_usb_driver::{
     Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
 };
 
+use crate::pac::USBRAM;
 use crate::pac::usb::regs;
 use crate::pac::usb::vals::{EpType, Stat};
-use crate::pac::USBRAM;
 use crate::rcc::RccPeripheral;
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-stm32/src/vrefbuf/mod.rs b/embassy-stm32/src/vrefbuf/mod.rs
index ccbd748d5..b061306a0 100644
--- a/embassy-stm32/src/vrefbuf/mod.rs
+++ b/embassy-stm32/src/vrefbuf/mod.rs
@@ -62,8 +62,7 @@ impl<'d, T: Instance> VoltageReferenceBuffer<'d, T> {
         }
         trace!(
             "Vrefbuf configured with voltage scale {} and impedance mode {}",
-            voltage_scale as u8,
-            impedance_mode as u8,
+            voltage_scale as u8, impedance_mode as u8,
         );
         VoltageReferenceBuffer { vrefbuf: PhantomData }
     }
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index fb5c3d930..1164739ff 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -4,8 +4,8 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 use stm32_metapac::iwdg::vals::{Key, Pr};
 
-use crate::rcc::LSI_FREQ;
 use crate::Peri;
+use crate::rcc::LSI_FREQ;
 
 /// Independent watchdog (IWDG) driver.
 pub struct IndependentWatchdog<'d, T: Instance> {
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index 901569f64..a80a2692b 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -11,15 +11,15 @@ use embassy_embedded_hal::{GetConfig, SetConfig};
 use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::xspi::vals::*;
 use crate::pac::xspi::Xspi as Regs;
+use crate::pac::xspi::vals::*;
 #[cfg(xspim_v1)]
 use crate::pac::xspim::Xspim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// XPSI driver config.
 #[derive(Clone, Copy)]