diff options
| author | elagil <[email protected]> | 2024-12-22 15:06:42 +0100 |
|---|---|---|
| committer | elagil <[email protected]> | 2024-12-22 15:07:58 +0100 |
| commit | b35b45e151e324d5b64c54f3443bf714ef367551 (patch) | |
| tree | 4e830e72f75869d57c9ac6e8e24aeee0596479d8 /embassy-stm32/src | |
| parent | 6789b5141f9280f1e3d7c6dfcab1a07fe4620b43 (diff) | |
feat: stm32h5 UCPD example
Diffstat (limited to 'embassy-stm32/src')
| -rw-r--r-- | embassy-stm32/src/ucpd.rs | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs index ee0a2c7c1..ac31f46a4 100644 --- a/embassy-stm32/src/ucpd.rs +++ b/embassy-stm32/src/ucpd.rs | |||
| @@ -175,6 +175,21 @@ impl<'d, T: Instance> Ucpd<'d, T> { | |||
| 175 | w.set_ucpden(true); | 175 | w.set_ucpden(true); |
| 176 | }); | 176 | }); |
| 177 | 177 | ||
| 178 | r.cfgr2().write(|w| { | ||
| 179 | w.set_rxafilten(true); | ||
| 180 | }); | ||
| 181 | |||
| 182 | // Software trim according to RM0481, p. 2650 | ||
| 183 | #[cfg(stm32h5)] | ||
| 184 | { | ||
| 185 | let trim_rd_cc1 = unsafe { *(0x4002_242C as *const u32) & 0xF }; | ||
| 186 | let trim_rd_cc2 = unsafe { ((*(0x4002_242C as *const u32)) >> 8) & 0xF }; | ||
| 187 | |||
| 188 | r.cfgr3().write(|w| { | ||
| 189 | w.set_trim_cc1_rd(trim_rd_cc1 as u8); | ||
| 190 | w.set_trim_cc2_rd(trim_rd_cc2 as u8); | ||
| 191 | }); | ||
| 192 | } | ||
| 178 | Self { | 193 | Self { |
| 179 | cc_phy: CcPhy { _lifetime: PhantomData }, | 194 | cc_phy: CcPhy { _lifetime: PhantomData }, |
| 180 | } | 195 | } |
| @@ -278,6 +293,31 @@ impl<'d, T: Instance> CcPhy<'d, T> { | |||
| 278 | }); | 293 | }); |
| 279 | }); | 294 | }); |
| 280 | 295 | ||
| 296 | // Software trim according to RM0481, p. 2668 | ||
| 297 | #[cfg(stm32h5)] | ||
| 298 | T::REGS.cfgr3().modify(|w| match cc_pull { | ||
| 299 | CcPull::Source1_5A => { | ||
| 300 | #[cfg(stm32h5)] | ||
| 301 | { | ||
| 302 | let trim_1a5_cc1 = unsafe { *(0x08FF_F844 as *const u32) & 0xF }; | ||
| 303 | let trim_1a5_cc2 = unsafe { ((*(0x08FF_F844 as *const u32)) >> 16) & 0xF }; | ||
| 304 | |||
| 305 | w.set_trim_cc1_rp(trim_1a5_cc1 as u8); | ||
| 306 | w.set_trim_cc2_rp(trim_1a5_cc2 as u8); | ||
| 307 | }; | ||
| 308 | } | ||
| 309 | _ => { | ||
| 310 | #[cfg(stm32h5)] | ||
| 311 | { | ||
| 312 | let trim_3a0_cc1 = unsafe { (*(0x4002_242C as *const u32) >> 4) & 0xF }; | ||
| 313 | let trim_3a0_cc2 = unsafe { ((*(0x4002_242C as *const u32)) >> 12) & 0xF }; | ||
| 314 | |||
| 315 | w.set_trim_cc1_rp(trim_3a0_cc1 as u8); | ||
| 316 | w.set_trim_cc2_rp(trim_3a0_cc2 as u8); | ||
| 317 | }; | ||
| 318 | } | ||
| 319 | }); | ||
| 320 | |||
| 281 | // Disable dead-battery pull-down resistors which are enabled by default on boot. | 321 | // Disable dead-battery pull-down resistors which are enabled by default on boot. |
| 282 | critical_section::with(|cs| { | 322 | critical_section::with(|cs| { |
| 283 | init( | 323 | init( |
