Merge pull request #2813 from diondokter/u0-dion

More U0 support

8 files changed, 157 insertions, 21 deletions

diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 2ff2ed6a8..8ef68490b 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -10,7 +10,7 @@
 #[cfg_attr(adc_v1, path = "v1.rs")]
 #[cfg_attr(adc_l0, path = "v1.rs")]
 #[cfg_attr(adc_v2, path = "v2.rs")]
-#[cfg_attr(any(adc_v3, adc_g0, adc_h5), path = "v3.rs")]
+#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
 #[cfg_attr(adc_v4, path = "v4.rs")]
 #[cfg_attr(adc_g4, path = "g4.rs")]
 mod _version;
@@ -96,6 +96,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
     adc_f3,
     adc_f3_v1_1,
     adc_g0,
+    adc_u0,
     adc_h5
 )))]
 #[allow(private_bounds)]
@@ -114,6 +115,7 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
     adc_f3,
     adc_f3_v1_1,
     adc_g0,
+    adc_u0,
     adc_h5
 ))]
 #[allow(private_bounds)]
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 4fd8558ba..dc418297e 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -19,6 +19,8 @@ impl<T: Instance> super::SealedAdcPin<T> for VrefInt {
                 let val = 13;
             } else if #[cfg(adc_h5)] {
                 let val = 17;
+            } else if #[cfg(adc_u0)] {
+                let val = 12;
             } else {
                 let val = 0;
             }
@@ -36,6 +38,8 @@ impl<T: Instance> super::SealedAdcPin<T> for Temperature {
                 let val = 12;
             } else if #[cfg(adc_h5)] {
                 let val = 16;
+            } else if #[cfg(adc_u0)] {
+                let val = 11;
             } else {
                 let val = 17;
             }
@@ -53,6 +57,8 @@ impl<T: Instance> super::SealedAdcPin<T> for Vbat {
                 let val = 14;
             } else if #[cfg(adc_h5)] {
                 let val = 2;
+            } else if #[cfg(adc_h5)] {
+                let val = 13;
             } else {
                 let val = 18;
             }
@@ -73,17 +79,29 @@ cfg_if! {
     }
 }
 
+cfg_if! {
+    if #[cfg(adc_u0)] {
+        pub struct DacOut;
+        impl<T: Instance> AdcPin<T> for DacOut {}
+        impl<T: Instance> super::SealedAdcPin<T> for DacOut {
+            fn channel(&self) -> u8 {
+                19
+            }
+        }
+    }
+}
+
 impl<'d, T: Instance> Adc<'d, T> {
     pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
         into_ref!(adc);
         T::enable_and_reset();
         T::regs().cr().modify(|reg| {
-            #[cfg(not(adc_g0))]
+            #[cfg(not(any(adc_g0, adc_u0)))]
             reg.set_deeppwd(false);
             reg.set_advregen(true);
         });
 
-        #[cfg(adc_g0)]
+        #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
             reg.set_chselrmod(false);
         });
@@ -107,11 +125,11 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     pub fn enable_vrefint(&self) -> VrefInt {
-        #[cfg(not(adc_g0))]
+        #[cfg(not(any(adc_g0, adc_u0)))]
         T::common_regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
-        #[cfg(adc_g0)]
+        #[cfg(any(adc_g0, adc_u0))]
         T::regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
@@ -125,7 +143,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     pub fn enable_temperature(&self) -> Temperature {
         cfg_if! {
-            if #[cfg(adc_g0)] {
+            if #[cfg(any(adc_g0, adc_u0))] {
                 T::regs().ccr().modify(|reg| {
                     reg.set_tsen(true);
                 });
@@ -145,7 +163,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     pub fn enable_vbat(&self) -> Vbat {
         cfg_if! {
-            if #[cfg(adc_g0)] {
+            if #[cfg(any(adc_g0, adc_u0))] {
                 T::regs().ccr().modify(|reg| {
                     reg.set_vbaten(true);
                 });
@@ -168,9 +186,9 @@ impl<'d, T: Instance> Adc<'d, T> {
     }
 
     pub fn set_resolution(&mut self, resolution: Resolution) {
-        #[cfg(not(adc_g0))]
+        #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-        #[cfg(adc_g0)]
+        #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
     }
 
@@ -231,9 +249,9 @@ impl<'d, T: Instance> Adc<'d, T> {
         Self::set_channel_sample_time(pin.channel(), self.sample_time);
 
         // Select channel
-        #[cfg(not(adc_g0))]
+        #[cfg(not(any(adc_g0, adc_u0)))]
         T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
-        #[cfg(adc_g0)]
+        #[cfg(any(adc_g0, adc_u0))]
         T::regs().chselr().write(|reg| reg.set_chsel(1 << pin.channel()));
 
         // Some models are affected by an erratum:
@@ -261,7 +279,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
     fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
         cfg_if! {
-            if #[cfg(adc_g0)] {
+            if #[cfg(any(adc_g0, adc_u0))] {
                 T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
             } else if #[cfg(adc_h5)] {
                 match _ch {
diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs
index 13fb6778c..ad7c79f12 100644
--- a/embassy-stm32/src/crc/v2v3.rs
+++ b/embassy-stm32/src/crc/v2v3.rs
@@ -13,6 +13,8 @@ pub struct Crc<'d> {
 }
 
 /// CRC configuration errlr
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum ConfigError {
     /// The selected polynomial is invalid.
     InvalidPolynomial,
diff --git a/embassy-stm32/src/dac/tsel.rs b/embassy-stm32/src/dac/tsel.rs
index 22d8d3dfa..1877954b9 100644
--- a/embassy-stm32/src/dac/tsel.rs
+++ b/embassy-stm32/src/dac/tsel.rs
@@ -235,6 +235,23 @@ pub enum TriggerSel {
     Exti9 = 13,
 }
 
+/// Trigger selection for U0.
+#[cfg(stm32u0)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    Software = 0,
+    Tim1 = 1,
+    Tim2 = 2,
+    Tim3 = 3,
+    Tim6 = 5,
+    Tim7 = 6,
+    Tim15 = 8,
+    Lptim1 = 11,
+    Lptim2 = 12,
+    Exti9 = 14,
+}
+
 /// Trigger selection for G4.
 #[cfg(stm32g4)]
 #[derive(Debug, Copy, Clone, Eq, PartialEq)]
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 9d7861816..8c6ca2471 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -101,10 +101,11 @@ pub enum FlashBank {
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(flash_u5, path = "u5.rs")]
 #[cfg_attr(flash_h50, path = "h50.rs")]
+#[cfg_attr(flash_u0, path = "u0.rs")]
 #[cfg_attr(
     not(any(
         flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
-        flash_g4, flash_h7, flash_h7ab, flash_u5, flash_h50
+        flash_g4, flash_h7, flash_h7ab, flash_u5, flash_h50, flash_u0
     )),
     path = "other.rs"
 )]
diff --git a/embassy-stm32/src/flash/u0.rs b/embassy-stm32/src/flash/u0.rs
new file mode 100644
index 000000000..dfc5a2f76
--- /dev/null
+++ b/embassy-stm32/src/flash/u0.rs
@@ -0,0 +1,96 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{fence, Ordering};
+
+use cortex_m::interrupt;
+
+use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+
+pub(crate) const fn is_default_layout() -> bool {
+    true
+}
+
+pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
+    &FLASH_REGIONS
+}
+
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    // Wait, while the memory interface is busy.
+    while pac::FLASH.sr().read().bsy1() {}
+
+    // Unlock flash
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write(|w| w.set_key(0x4567_0123));
+        pac::FLASH.keyr().write(|w| w.set_key(0xCDEF_89AB));
+    }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    pac::FLASH.cr().write(|w| w.set_pg(true));
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
+        address += val.len() as u32;
+
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+
+    wait_ready_blocking()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+    while pac::FLASH.sr().read().bsy1() {}
+    clear_all_err();
+
+    interrupt::free(|_| {
+        pac::FLASH.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(idx as u8);
+            w.set_strt(true);
+        });
+    });
+
+    let ret: Result<(), Error> = wait_ready_blocking();
+    pac::FLASH.cr().modify(|w| w.set_per(false));
+    ret
+}
+
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+    while pac::FLASH.sr().read().bsy1() {}
+
+    let sr = pac::FLASH.sr().read();
+
+    if sr.progerr() {
+        return Err(Error::Prog);
+    }
+
+    if sr.wrperr() {
+        return Err(Error::Protected);
+    }
+
+    if sr.pgaerr() {
+        return Err(Error::Unaligned);
+    }
+
+    Ok(())
+}
+
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
diff --git a/embassy-stm32/src/usb/mod.rs b/embassy-stm32/src/usb/mod.rs
index 1e3c44167..349438ec5 100644
--- a/embassy-stm32/src/usb/mod.rs
+++ b/embassy-stm32/src/usb/mod.rs
@@ -23,7 +23,7 @@ fn common_init<T: Instance>() {
         )
     }
 
-    #[cfg(any(stm32l4, stm32l5, stm32wb))]
+    #[cfg(any(stm32l4, stm32l5, stm32wb, stm32u0))]
     critical_section::with(|_| crate::pac::PWR.cr2().modify(|w| w.set_usv(true)));
 
     #[cfg(pwr_h5)]
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index f48808cb3..81a2d2623 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -107,14 +107,14 @@ const EP_COUNT: usize = 8;
 
 #[cfg(any(usbram_16x1_512, usbram_16x2_512))]
 const USBRAM_SIZE: usize = 512;
-#[cfg(usbram_16x2_1024)]
+#[cfg(any(usbram_16x2_1024, usbram_32_1024))]
 const USBRAM_SIZE: usize = 1024;
 #[cfg(usbram_32_2048)]
 const USBRAM_SIZE: usize = 2048;
 
-#[cfg(not(usbram_32_2048))]
+#[cfg(not(any(usbram_32_2048, usbram_32_1024)))]
 const USBRAM_ALIGN: usize = 2;
-#[cfg(usbram_32_2048)]
+#[cfg(any(usbram_32_2048, usbram_32_1024))]
 const USBRAM_ALIGN: usize = 4;
 
 const NEW_AW: AtomicWaker = AtomicWaker::new();
@@ -159,7 +159,7 @@ fn calc_out_len(len: u16) -> (u16, u16) {
     }
 }
 
-#[cfg(not(usbram_32_2048))]
+#[cfg(not(any(usbram_32_2048, usbram_32_1024)))]
 mod btable {
     use super::*;
 
@@ -180,7 +180,7 @@ mod btable {
         USBRAM.mem(index * 4 + 3).read()
     }
 }
-#[cfg(usbram_32_2048)]
+#[cfg(any(usbram_32_2048, usbram_32_1024))]
 mod btable {
     use super::*;
 
@@ -224,9 +224,9 @@ impl<T: Instance> EndpointBuffer<T> {
             let n = USBRAM_ALIGN.min(buf.len() - i * USBRAM_ALIGN);
             val[..n].copy_from_slice(&buf[i * USBRAM_ALIGN..][..n]);
 
-            #[cfg(not(usbram_32_2048))]
+            #[cfg(not(any(usbram_32_2048, usbram_32_1024)))]
             let val = u16::from_le_bytes(val);
-            #[cfg(usbram_32_2048)]
+            #[cfg(any(usbram_32_2048, usbram_32_1024))]
             let val = u32::from_le_bytes(val);
             USBRAM.mem(self.addr as usize / USBRAM_ALIGN + i).write_value(val);
         }