Remove Peripheral trait, rename PeripheralRef->Peri.

75 files changed, 1207 insertions, 1455 deletions

diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index 84763ad4f..a9c1d8faf 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -8,7 +8,7 @@ use super::{
 };
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -154,8 +154,7 @@ pub enum Averaging {
 
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd, sample_time: SampleTime, resolution: Resolution) -> Self {
-        embassy_hal_internal::into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>, sample_time: SampleTime, resolution: Resolution) -> Self {
         rcc::enable_and_reset::<T>();
 
         T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
@@ -319,7 +318,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         Self::apply_channel_conf()
     }
 
-    async fn dma_convert(&mut self, rx_dma: &mut impl RxDma<T>, readings: &mut [u16]) {
+    async fn dma_convert(&mut self, rx_dma: Peri<'_, impl RxDma<T>>, readings: &mut [u16]) {
         // Enable overrun control, so no new DMA requests will be generated until
         // previous DR values is read.
         T::regs().isr().modify(|reg| {
@@ -374,7 +373,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// TODO(chudsaviet): externalize generic code and merge with read().
     pub async fn read_in_hw_order(
         &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
         hw_channel_selection: u32,
         scandir: Scandir,
         readings: &mut [u16],
@@ -415,7 +414,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     // For other channels, use `read_in_hw_order()` or blocking read.
     pub async fn read(
         &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
         channel_sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
         readings: &mut [u16],
     ) {
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index b37ec260f..fa6255c23 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -2,12 +2,10 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::into_ref;
-
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -48,8 +46,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
 }
 
 impl<'d, T: Instance> Adc<'d, T> {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
         T::regs().cr2().modify(|reg| reg.set_adon(true));
 
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 0ebeb8a9e..3aeb6f2c7 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -2,13 +2,11 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::into_ref;
-
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -56,13 +54,11 @@ impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
 
 impl<'d, T: Instance> Adc<'d, T> {
     pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         use crate::pac::adc::vals;
 
-        into_ref!(adc);
-
         rcc::enable_and_reset::<T>();
 
         // Enable the adc regulator
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 291a3861e..944e971bb 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -3,14 +3,13 @@ use core::marker::PhantomData;
 use core::task::Poll;
 
 use embassy_futures::yield_now;
-use embassy_hal_internal::into_ref;
 use embassy_time::Instant;
 
 use super::Resolution;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 
 const ADC_FREQ: Hertz = crate::rcc::HSI_FREQ;
 
@@ -138,11 +137,9 @@ impl<T: Instance> Drop for Temperature<T> {
 
 impl<'d, T: Instance> Adc<'d, T> {
     pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
-        into_ref!(adc);
-
         rcc::enable_and_reset::<T>();
 
         //let r = T::regs();
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 0291ef4de..6a00e788e 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -11,7 +11,7 @@ use super::{blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolut
 use crate::adc::SealedAdcChannel;
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -135,8 +135,7 @@ impl Prescaler {
 
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        embassy_hal_internal::into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         let prescaler = Prescaler::from_ker_ck(T::frequency());
@@ -364,8 +363,8 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// use embassy_stm32::adc::{Adc, AdcChannel}
     ///
     /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin1 = p.PA1.degrade_adc();
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin1 = p.PA1.into();
     /// let mut measurements = [0u16; 2];
     ///
     /// adc.read_async(
@@ -382,7 +381,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// ```
     pub async fn read(
         &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
         sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
         readings: &mut [u16],
     ) {
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 31a08b6eb..321db7431 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -22,6 +22,7 @@ use core::marker::PhantomData;
 #[allow(unused)]
 #[cfg(not(any(adc_f3_v2)))]
 pub use _version::*;
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
 
@@ -42,7 +43,7 @@ dma_trait!(RxDma4, adc4::Instance);
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
     #[allow(unused)]
-    adc: crate::PeripheralRef<'d, T>,
+    adc: crate::Peri<'d, T>,
     #[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
     sample_time: SampleTime,
 }
@@ -111,7 +112,7 @@ pub(crate) fn blocking_delay_us(us: u32) {
     adc_c0
 )))]
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
+pub trait Instance: SealedInstance + crate::PeripheralType {
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 /// ADC instance.
@@ -132,7 +133,7 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
     adc_c0
 ))]
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
+pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 
@@ -159,7 +160,7 @@ pub struct AnyAdcChannel<T> {
     channel: u8,
     _phantom: PhantomData<T>,
 }
-
+impl_peripheral!(AnyAdcChannel<T: Instance>);
 impl<T: Instance> AdcChannel<T> for AnyAdcChannel<T> {}
 impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     fn channel(&self) -> u8 {
@@ -233,11 +234,11 @@ foreach_adc!(
 
 macro_rules! impl_adc_pin {
     ($inst:ident, $pin:ident, $ch:expr) => {
-        impl crate::adc::AdcChannel<peripherals::$inst> for crate::peripherals::$pin {}
-        impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::peripherals::$pin {
+        impl crate::adc::AdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {}
+        impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {
             #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
             fn setup(&mut self) {
-                <Self as crate::gpio::SealedPin>::set_as_analog(self);
+                <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(self);
             }
 
             fn channel(&self) -> u8 {
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
index f3d1ca0ab..fabf0284b 100644
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ b/embassy-stm32/src/adc/ringbuffered_v2.rs
@@ -2,13 +2,12 @@ use core::marker::PhantomData;
 use core::mem;
 use core::sync::atomic::{compiler_fence, Ordering};
 
-use embassy_hal_internal::{into_ref, Peripheral};
 use stm32_metapac::adc::vals::SampleTime;
 
 use crate::adc::{Adc, AdcChannel, Instance, RxDma};
 use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
 use crate::pac::adc::vals;
-use crate::rcc;
+use crate::{rcc, Peri};
 
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct OverrunError;
@@ -103,13 +102,8 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// It is critical to call `read` frequently to prevent DMA buffer overrun.
     ///
     /// [`read`]: #method.read
-    pub fn into_ring_buffered(
-        self,
-        dma: impl Peripheral<P = impl RxDma<T>> + 'd,
-        dma_buf: &'d mut [u16],
-    ) -> RingBufferedAdc<'d, T> {
+    pub fn into_ring_buffered(self, dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> RingBufferedAdc<'d, T> {
         assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        into_ref!(dma);
 
         let opts: crate::dma::TransferOptions = TransferOptions {
             half_transfer_ir: true,
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/u5_adc4.rs
index cec88d482..a5cfbfdcf 100644
--- a/embassy-stm32/src/adc/u5_adc4.rs
+++ b/embassy-stm32/src/adc/u5_adc4.rs
@@ -6,7 +6,7 @@ use crate::dma::Transfer;
 pub use crate::pac::adc::regs::Adc4Chselrmod0;
 pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
@@ -169,13 +169,13 @@ pub trait SealedInstance {
     fn regs() -> crate::pac::adc::Adc4;
 }
 
-pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
+pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 
 pub struct Adc4<'d, T: Instance> {
     #[allow(unused)]
-    adc: crate::PeripheralRef<'d, T>,
+    adc: crate::Peri<'d, T>,
 }
 
 #[derive(Debug)]
@@ -186,8 +186,7 @@ pub enum Adc4Error {
 
 impl<'d, T: Instance> Adc4<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        embassy_hal_internal::into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
         let prescaler = Prescaler::from_ker_ck(T::frequency());
 
@@ -379,15 +378,15 @@ impl<'d, T: Instance> Adc4<'d, T> {
     /// let mut adc4 = adc4::Adc4::new(p.ADC4);
     /// let mut adc4_pin1 = p.PC1;
     /// let mut adc4_pin2 = p.PC0;
-    /// let mut degraded41 = adc4_pin1.degrade_adc();
-    /// let mut degraded42 = adc4_pin2.degrade_adc();
+    /// let mut.into()d41 = adc4_pin1.into();
+    /// let mut.into()d42 = adc4_pin2.into();
     /// let mut measurements = [0u16; 2];
     /// // not that the channels must be in ascending order
     /// adc4.read(
     ///     &mut p.GPDMA1_CH1,
     ///    [
-    ///        &mut degraded42,
-    ///        &mut degraded41,
+    ///        &mut.into()d42,
+    ///        &mut.into()d41,
     ///    ]
     ///    .into_iter(),
     ///    &mut measurements,
@@ -395,7 +394,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
     /// ```
     pub async fn read(
         &mut self,
-        rx_dma: &mut impl RxDma4<T>,
+        rx_dma: Peri<'_, impl RxDma4<T>>,
         sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
         readings: &mut [u16],
     ) -> Result<(), Adc4Error> {
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index d5cd14661..fb6f5b7d0 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -2,7 +2,6 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::into_ref;
 #[cfg(adc_l0)]
 use stm32_metapac::adc::vals::Ckmode;
 
@@ -10,7 +9,7 @@ use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::ADC1;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const VREF_INT: u32 = 1230;
@@ -63,10 +62,9 @@ impl super::SealedAdcChannel<ADC1> for Temperature {
 
 impl<'d, T: Instance> Adc<'d, T> {
     pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
-        into_ref!(adc);
         rcc::enable_and_reset::<T>();
 
         // Delay 1μs when using HSI14 as the ADC clock.
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 842a5ee6d..e94a25b24 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,10 +1,8 @@
-use embassy_hal_internal::into_ref;
-
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::peripherals::ADC1;
 use crate::time::Hertz;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 
 mod ringbuffered_v2;
 pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
@@ -97,8 +95,7 @@ impl<'d, T> Adc<'d, T>
 where
     T: Instance,
 {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         let presc = Prescaler::from_pclk2(T::frequency());
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 7a608a44e..2de12d1d6 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,12 +1,11 @@
 use cfg_if::cfg_if;
-use embassy_hal_internal::into_ref;
 use pac::adc::vals::Dmacfg;
 
 use super::{
     blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
 };
 use crate::dma::Transfer;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -95,8 +94,7 @@ cfg_if! {
 }
 
 impl<'d, T: Instance> Adc<'d, T> {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
         T::regs().cr().modify(|reg| {
             #[cfg(not(any(adc_g0, adc_u0)))]
@@ -288,7 +286,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// ```
     pub async fn read(
         &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
         sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
         readings: &mut [u16],
     ) {
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 9860efa8a..5910eef30 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -9,7 +9,7 @@ use super::{
 };
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -158,8 +158,7 @@ pub enum Averaging {
 
 impl<'d, T: Instance> Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
-        embassy_hal_internal::into_ref!(adc);
+    pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         let prescaler = Prescaler::from_ker_ck(T::frequency());
@@ -344,8 +343,8 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// use embassy_stm32::adc::{Adc, AdcChannel}
     ///
     /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin2 = p.PA2.degrade_adc();
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin2 = p.PA2.into();
     /// let mut measurements = [0u16; 2];
     ///
     /// adc.read_async(
@@ -362,7 +361,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// ```
     pub async fn read(
         &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
         sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
         readings: &mut [u16],
     ) {
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index c0b3c730b..305666d5b 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -6,7 +6,7 @@ use core::marker::PhantomData;
 use core::task::Poll;
 
 use embassy_hal_internal::interrupt::InterruptExt;
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -21,7 +21,7 @@ use crate::can::enums::{BusError, InternalOperation, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals, Peri};
 
 /// Interrupt handler.
 pub struct TxInterruptHandler<T: Instance> {
@@ -173,16 +173,15 @@ impl<'d> Can<'d> {
     /// Creates a new Bxcan instance, keeping the peripheral in sleep mode.
     /// You must call [Can::enable_non_blocking] to use the peripheral.
     pub fn new<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        _peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
             + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
             + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
             + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
             + 'd,
     ) -> Self {
-        into_ref!(_peri, rx, tx);
         let info = T::info();
         let regs = &T::info().regs;
 
@@ -1083,7 +1082,7 @@ trait SealedInstance {
 
 /// CAN instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
     /// TX interrupt for this instance.
     type TXInterrupt: crate::interrupt::typelevel::Interrupt;
     /// RX0 interrupt for this instance.
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index f950b6f99..5467a40f1 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -4,7 +4,7 @@ use core::marker::PhantomData;
 use core::task::Poll;
 
 use embassy_hal_internal::interrupt::InterruptExt;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -13,7 +13,7 @@ use crate::can::fd::peripheral::Registers;
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals, Peri};
 
 pub(crate) mod fd;
 
@@ -175,15 +175,13 @@ impl<'d> CanConfigurator<'d> {
     /// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
     /// You must call [Fdcan::enable_non_blocking] to use the peripheral.
     pub fn new<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        _peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
             + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
             + 'd,
     ) -> CanConfigurator<'d> {
-        into_ref!(_peri, rx, tx);
-
         rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
         tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
@@ -957,7 +955,7 @@ trait SealedInstance {
 
 /// Instance trait
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
     /// Interrupt 0
     type IT0Interrupt: crate::interrupt::typelevel::Interrupt;
     /// Interrupt 1
@@ -965,7 +963,7 @@ pub trait Instance: SealedInstance + RccPeripheral + 'static {
 }
 
 /// Fdcan Instance struct
-pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
+pub struct FdcanInstance<'a, T: Instance>(Peri<'a, T>);
 
 macro_rules! impl_fdcan {
     ($inst:ident,
diff --git a/embassy-stm32/src/cordic/mod.rs b/embassy-stm32/src/cordic/mod.rs
index fb342d2e7..320774857 100644
--- a/embassy-stm32/src/cordic/mod.rs
+++ b/embassy-stm32/src/cordic/mod.rs
@@ -1,7 +1,7 @@
 //! coordinate rotation digital computer (CORDIC)
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 
 use crate::pac::cordic::vals;
 use crate::{dma, peripherals, rcc};
@@ -16,7 +16,7 @@ pub mod utils;
 
 /// CORDIC driver
 pub struct Cordic<'d, T: Instance> {
-    peri: PeripheralRef<'d, T>,
+    peri: Peri<'d, T>,
     config: Config,
 }
 
@@ -137,7 +137,7 @@ trait SealedInstance {
 
 /// CORDIC instance trait
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral {}
 
 /// CORDIC configuration
 #[derive(Debug)]
@@ -198,11 +198,9 @@ impl<'d, T: Instance> Cordic<'d, T> {
     /// Note:  
     /// If you need a peripheral -> CORDIC -> peripheral mode,  
     /// you may want to set Cordic into [Mode::ZeroOverhead] mode, and add extra arguments with [Self::extra_config]
-    pub fn new(peri: impl Peripheral<P = T> + 'd, config: Config) -> Self {
+    pub fn new(peri: Peri<'d, T>, config: Config) -> Self {
         rcc::enable_and_reset::<T>();
 
-        into_ref!(peri);
-
         let mut instance = Self { peri, config };
 
         instance.reconfigure();
@@ -378,8 +376,8 @@ impl<'d, T: Instance> Cordic<'d, T> {
     /// If you want to make sure ARG2 is set to +1, consider run [.reconfigure()](Self::reconfigure).
     pub async fn async_calc_32bit(
         &mut self,
-        write_dma: impl Peripheral<P = impl WriteDma<T>>,
-        read_dma: impl Peripheral<P = impl ReadDma<T>>,
+        mut write_dma: Peri<'_, impl WriteDma<T>>,
+        mut read_dma: Peri<'_, impl ReadDma<T>>,
         arg: &[u32],
         res: &mut [u32],
         arg1_only: bool,
@@ -393,8 +391,6 @@ impl<'d, T: Instance> Cordic<'d, T> {
 
         let active_res_buf = &mut res[..res_cnt];
 
-        into_ref!(write_dma, read_dma);
-
         self.peri
             .set_argument_count(if arg1_only { AccessCount::One } else { AccessCount::Two });
 
@@ -416,7 +412,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
 
         unsafe {
             let write_transfer = dma::Transfer::new_write(
-                &mut write_dma,
+                write_dma.reborrow(),
                 write_req,
                 arg,
                 T::regs().wdata().as_ptr() as *mut _,
@@ -424,7 +420,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
             );
 
             let read_transfer = dma::Transfer::new_read(
-                &mut read_dma,
+                read_dma.reborrow(),
                 read_req,
                 T::regs().rdata().as_ptr() as *mut _,
                 active_res_buf,
@@ -519,8 +515,8 @@ impl<'d, T: Instance> Cordic<'d, T> {
     /// User will take respond to merge two u16 arguments into one u32 data, and/or split one u32 data into two u16 results.
     pub async fn async_calc_16bit(
         &mut self,
-        write_dma: impl Peripheral<P = impl WriteDma<T>>,
-        read_dma: impl Peripheral<P = impl ReadDma<T>>,
+        mut write_dma: Peri<'_, impl WriteDma<T>>,
+        mut read_dma: Peri<'_, impl ReadDma<T>>,
         arg: &[u32],
         res: &mut [u32],
     ) -> Result<usize, CordicError> {
@@ -536,8 +532,6 @@ impl<'d, T: Instance> Cordic<'d, T> {
 
         let active_res_buf = &mut res[..res_cnt];
 
-        into_ref!(write_dma, read_dma);
-
         // In q1.15 mode, 1 write/read to access 2 arguments/results
         self.peri.set_argument_count(AccessCount::One);
         self.peri.set_result_count(AccessCount::One);
@@ -557,7 +551,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
 
         unsafe {
             let write_transfer = dma::Transfer::new_write(
-                &mut write_dma,
+                write_dma.reborrow(),
                 write_req,
                 arg,
                 T::regs().wdata().as_ptr() as *mut _,
@@ -565,7 +559,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
             );
 
             let read_transfer = dma::Transfer::new_read(
-                &mut read_dma,
+                read_dma.reborrow(),
                 read_req,
                 T::regs().rdata().as_ptr() as *mut _,
                 active_res_buf,
diff --git a/embassy-stm32/src/crc/v1.rs b/embassy-stm32/src/crc/v1.rs
index f3d13de7c..a78b3c2b7 100644
--- a/embassy-stm32/src/crc/v1.rs
+++ b/embassy-stm32/src/crc/v1.rs
@@ -1,23 +1,18 @@
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 
 /// CRC driver.
 pub struct Crc<'d> {
-    _peri: PeripheralRef<'d, CRC>,
+    _peri: Peri<'d, CRC>,
 }
 
 impl<'d> Crc<'d> {
     /// Instantiates the CRC32 peripheral and initializes it to default values.
-    pub fn new(peripheral: impl Peripheral<P = CRC> + 'd) -> Self {
-        into_ref!(peripheral);
-
+    pub fn new(peripheral: Peri<'d, CRC>) -> Self {
         // Note: enable and reset come from RccPeripheral.
         // enable CRC clock in RCC.
         rcc::enable_and_reset::<CRC>();
-        // Peripheral the peripheral
         let mut instance = Self { _peri: peripheral };
         instance.reset();
         instance
diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs
index ecb507ff4..c94c9f380 100644
--- a/embassy-stm32/src/crc/v2v3.rs
+++ b/embassy-stm32/src/crc/v2v3.rs
@@ -1,13 +1,11 @@
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
 use crate::pac::crc::vals;
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 
 /// CRC driver.
 pub struct Crc<'d> {
-    _peripheral: PeripheralRef<'d, CRC>,
+    _peripheral: Peri<'d, CRC>,
     _config: Config,
 }
 
@@ -80,11 +78,10 @@ pub enum PolySize {
 
 impl<'d> Crc<'d> {
     /// Instantiates the CRC32 peripheral and initializes it to default values.
-    pub fn new(peripheral: impl Peripheral<P = CRC> + 'd, config: Config) -> Self {
+    pub fn new(peripheral: Peri<'d, CRC>, config: Config) -> Self {
         // Note: enable and reset come from RccPeripheral.
         // reset to default values and enable CRC clock in RCC.
         rcc::enable_and_reset::<CRC>();
-        into_ref!(peripheral);
         let mut instance = Self {
             _peripheral: peripheral,
             _config: config,
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 54d2c30e5..fba3c0fd7 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -4,13 +4,13 @@ use core::cmp::min;
 use core::marker::PhantomData;
 use core::ptr;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::{ChannelAndRequest, TransferOptions};
 use crate::interrupt::typelevel::Interrupt;
 use crate::mode::{Async, Blocking, Mode};
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::{interrupt, pac, peripherals, rcc};
 
 const DES_BLOCK_SIZE: usize = 8; // 64 bits
 const AES_BLOCK_SIZE: usize = 16; // 128 bits
@@ -988,7 +988,7 @@ pub enum Direction {
 
 /// Crypto Accelerator Driver
 pub struct Cryp<'d, T: Instance, M: Mode> {
-    _peripheral: PeripheralRef<'d, T>,
+    _peripheral: Peri<'d, T>,
     _phantom: PhantomData<M>,
     indma: Option<ChannelAndRequest<'d>>,
     outdma: Option<ChannelAndRequest<'d>>,
@@ -997,11 +997,10 @@ pub struct Cryp<'d, T: Instance, M: Mode> {
 impl<'d, T: Instance> Cryp<'d, T, Blocking> {
     /// Create a new CRYP driver in blocking mode.
     pub fn new_blocking(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         rcc::enable_and_reset::<T>();
-        into_ref!(peri);
         let instance = Self {
             _peripheral: peri,
             _phantom: PhantomData,
@@ -1461,13 +1460,12 @@ impl<'d, T: Instance, M: Mode> Cryp<'d, T, M> {
 impl<'d, T: Instance> Cryp<'d, T, Async> {
     /// Create a new CRYP driver.
     pub fn new(
-        peri: impl Peripheral<P = T> + 'd,
-        indma: impl Peripheral<P = impl DmaIn<T>> + 'd,
-        outdma: impl Peripheral<P = impl DmaOut<T>> + 'd,
+        peri: Peri<'d, T>,
+        indma: Peri<'d, impl DmaIn<T>>,
+        outdma: Peri<'d, impl DmaOut<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         rcc::enable_and_reset::<T>();
-        into_ref!(peri, indma, outdma);
         let instance = Self {
             _peripheral: peri,
             _phantom: PhantomData,
@@ -1879,7 +1877,7 @@ trait SealedInstance {
 
 /// CRYP instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
     /// Interrupt for this CRYP instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 7a63dc5fc..30046849b 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -3,16 +3,15 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::into_ref;
-
 use crate::dma::ChannelAndRequest;
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
 use crate::pac::dac;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 mod tsel;
+use embassy_hal_internal::PeripheralType;
 pub use tsel::TriggerSel;
 
 /// Operating mode for DAC channel
@@ -121,12 +120,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Async> {
     ///
     /// By default, triggering is disabled, but it can be enabled using
     /// [`DacChannel::set_trigger()`].
-    pub fn new(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = impl Dma<T, C>> + 'd,
-        pin: impl Peripheral<P = impl DacPin<T, C>> + 'd,
-    ) -> Self {
-        into_ref!(dma, pin);
+    pub fn new(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
         pin.set_as_analog();
         Self::new_inner(
             peri,
@@ -147,8 +141,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Async> {
     /// By default, triggering is disabled, but it can be enabled using
     /// [`DacChannel::set_trigger()`].
     #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-    pub fn new_internal(peri: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = impl Dma<T, C>> + 'd) -> Self {
-        into_ref!(dma);
+    pub fn new_internal(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>) -> Self {
         Self::new_inner(peri, new_dma!(dma), Mode::NormalInternalUnbuffered)
     }
 
@@ -204,8 +197,7 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Blocking> {
     ///
     /// By default, triggering is disabled, but it can be enabled using
     /// [`DacChannel::set_trigger()`].
-    pub fn new_blocking(peri: impl Peripheral<P = T> + 'd, pin: impl Peripheral<P = impl DacPin<T, C>> + 'd) -> Self {
-        into_ref!(pin);
+    pub fn new_blocking(peri: Peri<'d, T>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
         pin.set_as_analog();
         Self::new_inner(
             peri,
@@ -226,14 +218,14 @@ impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Blocking> {
     /// By default, triggering is disabled, but it can be enabled using
     /// [`DacChannel::set_trigger()`].
     #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-    pub fn new_internal_blocking(peri: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new_internal_blocking(peri: Peri<'d, T>) -> Self {
         Self::new_inner(peri, None, Mode::NormalInternalUnbuffered)
     }
 }
 
 impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> {
     fn new_inner(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         dma: Option<ChannelAndRequest<'d>>,
         #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
     ) -> Self {
@@ -395,13 +387,12 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
     /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
     /// method on the underlying channels.
     pub fn new(
-        peri: impl Peripheral<P = T> + 'd,
-        dma_ch1: impl Peripheral<P = impl Dma<T, Ch1>> + 'd,
-        dma_ch2: impl Peripheral<P = impl Dma<T, Ch2>> + 'd,
-        pin_ch1: impl Peripheral<P = impl DacPin<T, Ch1> + crate::gpio::Pin> + 'd,
-        pin_ch2: impl Peripheral<P = impl DacPin<T, Ch2> + crate::gpio::Pin> + 'd,
+        peri: Peri<'d, T>,
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
     ) -> Self {
-        into_ref!(dma_ch1, dma_ch2, pin_ch1, pin_ch2);
         pin_ch1.set_as_analog();
         pin_ch2.set_as_analog();
         Self::new_inner(
@@ -429,11 +420,10 @@ impl<'d, T: Instance> Dac<'d, T, Async> {
     /// method on the underlying channels.
     #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
     pub fn new_internal(
-        peri: impl Peripheral<P = T> + 'd,
-        dma_ch1: impl Peripheral<P = impl Dma<T, Ch1>> + 'd,
-        dma_ch2: impl Peripheral<P = impl Dma<T, Ch2>> + 'd,
+        peri: Peri<'d, T>,
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
     ) -> Self {
-        into_ref!(dma_ch1, dma_ch2);
         Self::new_inner(
             peri,
             new_dma!(dma_ch1),
@@ -457,11 +447,10 @@ impl<'d, T: Instance> Dac<'d, T, Blocking> {
     /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
     /// method on the underlying channels.
     pub fn new_blocking(
-        peri: impl Peripheral<P = T> + 'd,
-        pin_ch1: impl Peripheral<P = impl DacPin<T, Ch1> + crate::gpio::Pin> + 'd,
-        pin_ch2: impl Peripheral<P = impl DacPin<T, Ch2> + crate::gpio::Pin> + 'd,
+        peri: Peri<'d, T>,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
     ) -> Self {
-        into_ref!(pin_ch1, pin_ch2);
         pin_ch1.set_as_analog();
         pin_ch2.set_as_analog();
         Self::new_inner(
@@ -488,14 +477,14 @@ impl<'d, T: Instance> Dac<'d, T, Blocking> {
     /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
     /// method on the underlying channels.
     #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-    pub fn new_internal(peri: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new_internal(peri: Peri<'d, T>) -> Self {
         Self::new_inner(peri, None, None, Mode::NormalInternalUnbuffered)
     }
 }
 
 impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> {
     fn new_inner(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         dma_ch1: Option<ChannelAndRequest<'d>>,
         dma_ch2: Option<ChannelAndRequest<'d>>,
         #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
@@ -572,7 +561,7 @@ trait SealedInstance {
 
 /// DAC instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {}
 
 /// Channel 1 marker type.
 pub enum Ch1 {}
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index 4ba4e824e..d05faee21 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -3,13 +3,13 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::Transfer;
 use crate::gpio::{AfType, Pull};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -106,8 +106,7 @@ impl Default for Config {
 
 macro_rules! config_pins {
     ($($pin:ident),*) => {
-        into_ref!($($pin),*);
-        critical_section::with(|_| {
+                critical_section::with(|_| {
             $(
                 $pin.set_as_af($pin.af_num(), AfType::input(Pull::None));
             )*
@@ -117,8 +116,8 @@ macro_rules! config_pins {
 
 /// DCMI driver.
 pub struct Dcmi<'d, T: Instance, Dma: FrameDma<T>> {
-    inner: PeripheralRef<'d, T>,
-    dma: PeripheralRef<'d, Dma>,
+    inner: Peri<'d, T>,
+    dma: Peri<'d, Dma>,
 }
 
 impl<'d, T, Dma> Dcmi<'d, T, Dma>
@@ -128,23 +127,22 @@ where
 {
     /// Create a new DCMI driver with 8 data bits.
     pub fn new_8bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
         config_pins!(v_sync, h_sync, pixclk);
 
@@ -153,25 +151,24 @@ where
 
     /// Create a new DCMI driver with 10 data bits.
     pub fn new_10bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
         config_pins!(v_sync, h_sync, pixclk);
 
@@ -180,27 +177,26 @@ where
 
     /// Create a new DCMI driver with 12 data bits.
     pub fn new_12bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        d10: Peri<'d, impl D10Pin<T>>,
+        d11: Peri<'d, impl D11Pin<T>>,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
         config_pins!(v_sync, h_sync, pixclk);
 
@@ -209,29 +205,28 @@ where
 
     /// Create a new DCMI driver with 14 data bits.
     pub fn new_14bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
-        d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
-        d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        d10: Peri<'d, impl D10Pin<T>>,
+        d11: Peri<'d, impl D11Pin<T>>,
+        d12: Peri<'d, impl D12Pin<T>>,
+        d13: Peri<'d, impl D13Pin<T>>,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
         config_pins!(v_sync, h_sync, pixclk);
 
@@ -240,21 +235,20 @@ where
 
     /// Create a new DCMI driver with 8 data bits, with embedded synchronization.
     pub fn new_es_8bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
         config_pins!(pixclk);
 
@@ -263,23 +257,22 @@ where
 
     /// Create a new DCMI driver with 10 data bits, with embedded synchronization.
     pub fn new_es_10bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
         config_pins!(pixclk);
 
@@ -288,25 +281,24 @@ where
 
     /// Create a new DCMI driver with 12 data bits, with embedded synchronization.
     pub fn new_es_12bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        d10: Peri<'d, impl D10Pin<T>>,
+        d11: Peri<'d, impl D11Pin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
         config_pins!(pixclk);
 
@@ -315,27 +307,26 @@ where
 
     /// Create a new DCMI driver with 14 data bits, with embedded synchronization.
     pub fn new_es_14bit(
-        peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
-        d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
-        d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        d8: Peri<'d, impl D8Pin<T>>,
+        d9: Peri<'d, impl D9Pin<T>>,
+        d10: Peri<'d, impl D10Pin<T>>,
+        d11: Peri<'d, impl D11Pin<T>>,
+        d12: Peri<'d, impl D12Pin<T>>,
+        d13: Peri<'d, impl D13Pin<T>>,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(peri, dma);
         config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
         config_pins!(pixclk);
 
@@ -343,8 +334,8 @@ where
     }
 
     fn new_inner(
-        peri: PeripheralRef<'d, T>,
-        dma: PeripheralRef<'d, Dma>,
+        peri: Peri<'d, T>,
+        dma: Peri<'d, Dma>,
         config: Config,
         use_embedded_synchronization: bool,
         edm: u8,
@@ -396,7 +387,7 @@ where
         let r = self.inner.regs();
         let src = r.dr().as_ptr() as *mut u32;
         let request = self.dma.request();
-        let dma_read = unsafe { Transfer::new_read(&mut self.dma, request, src, buffer, Default::default()) };
+        let dma_read = unsafe { Transfer::new_read(self.dma.reborrow(), request, src, buffer, Default::default()) };
 
         Self::clear_interrupt_flags();
         Self::enable_irqs();
@@ -435,7 +426,7 @@ trait SealedInstance: crate::rcc::RccPeripheral {
 
 /// DCMI instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {
+pub trait Instance: SealedInstance + PeripheralType + 'static {
     /// Interrupt for this instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index d31f4d01a..7dbbe7b72 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -3,7 +3,7 @@ use core::pin::Pin;
 use core::sync::atomic::{fence, AtomicUsize, Ordering};
 use core::task::{Context, Poll, Waker};
 
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use super::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
@@ -571,13 +571,13 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
 }
 
 impl<'a> Transfer<'a> {
     /// Create a new read DMA transfer (peripheral to memory).
     pub unsafe fn new_read<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         peri_addr: *mut W,
         buf: &'a mut [W],
@@ -588,16 +588,14 @@ impl<'a> Transfer<'a> {
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
     pub unsafe fn new_read_raw<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         peri_addr: *mut W,
         buf: *mut [W],
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
@@ -612,7 +610,7 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral).
     pub unsafe fn new_write<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         buf: &'a [MW],
         peri_addr: *mut PW,
@@ -623,16 +621,14 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
     pub unsafe fn new_write_raw<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         buf: *const [MW],
         peri_addr: *mut PW,
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::MemoryToPeripheral,
             peri_addr as *const u32,
@@ -647,17 +643,15 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
     pub unsafe fn new_write_repeated<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         repeated: &'a W,
         count: usize,
         peri_addr: *mut W,
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::MemoryToPeripheral,
             peri_addr as *const u32,
@@ -671,7 +665,7 @@ impl<'a> Transfer<'a> {
     }
 
     unsafe fn new_inner(
-        channel: PeripheralRef<'a, AnyChannel>,
+        channel: Peri<'a, AnyChannel>,
         _request: Request,
         dir: Dir,
         peri_addr: *const u32,
@@ -769,7 +763,7 @@ impl<'a> Future for Transfer<'a> {
 
 // ==============================
 
-struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>);
+struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
 
 impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
     fn get_remaining_transfers(&self) -> usize {
@@ -795,21 +789,20 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 
 /// Ringbuffer for receiving data using DMA circular mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
     ringbuf: ReadableDmaRingBuffer<'a, W>,
 }
 
 impl<'a, W: Word> ReadableRingBuffer<'a, W> {
     /// Create a new ring buffer.
     pub unsafe fn new(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         _request: Request,
         peri_addr: *mut W,
         buffer: &'a mut [W],
         mut options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-        let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
+        let channel: Peri<'a, AnyChannel> = channel.into();
 
         let buffer_ptr = buffer.as_mut_ptr();
         let len = buffer.len();
@@ -948,21 +941,20 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 
 /// Ringbuffer for writing data using DMA circular mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
     ringbuf: WritableDmaRingBuffer<'a, W>,
 }
 
 impl<'a, W: Word> WritableRingBuffer<'a, W> {
     /// Create a new ring buffer.
     pub unsafe fn new(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         _request: Request,
         peri_addr: *mut W,
         buffer: &'a mut [W],
         mut options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-        let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
+        let channel: Peri<'a, AnyChannel> = channel.into();
 
         let len = buffer.len();
         let dir = Dir::MemoryToPeripheral;
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 799b8b355..ade70fb55 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -5,7 +5,7 @@ use core::pin::Pin;
 use core::sync::atomic::{fence, Ordering};
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use super::word::{Word, WordSize};
@@ -109,13 +109,13 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
 }
 
 impl<'a> Transfer<'a> {
     /// Create a new read DMA transfer (peripheral to memory).
     pub unsafe fn new_read<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         peri_addr: *mut W,
         buf: &'a mut [W],
@@ -126,16 +126,14 @@ impl<'a> Transfer<'a> {
 
     /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
     pub unsafe fn new_read_raw<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         peri_addr: *mut W,
         buf: *mut [W],
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::PeripheralToMemory,
             peri_addr as *const u32,
@@ -150,7 +148,7 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral).
     pub unsafe fn new_write<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         buf: &'a [MW],
         peri_addr: *mut PW,
@@ -161,16 +159,14 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
     pub unsafe fn new_write_raw<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         buf: *const [MW],
         peri_addr: *mut PW,
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::MemoryToPeripheral,
             peri_addr as *const u32,
@@ -185,17 +181,15 @@ impl<'a> Transfer<'a> {
 
     /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
     pub unsafe fn new_write_repeated<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
         request: Request,
         repeated: &'a MW,
         count: usize,
         peri_addr: *mut PW,
         options: TransferOptions,
     ) -> Self {
-        into_ref!(channel);
-
         Self::new_inner(
-            channel.map_into(),
+            channel.into(),
             request,
             Dir::MemoryToPeripheral,
             peri_addr as *const u32,
@@ -209,7 +203,7 @@ impl<'a> Transfer<'a> {
     }
 
     unsafe fn new_inner(
-        channel: PeripheralRef<'a, AnyChannel>,
+        channel: Peri<'a, AnyChannel>,
         request: Request,
         dir: Dir,
         peri_addr: *const u32,
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index ac4a0f98e..d3b070a6d 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -22,7 +22,7 @@ pub(crate) use util::*;
 pub(crate) mod ringbuffer;
 pub mod word;
 
-use embassy_hal_internal::{impl_peripheral, Peripheral};
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 
 use crate::interrupt;
 
@@ -51,17 +51,7 @@ pub(crate) trait ChannelInterrupt {
 
 /// DMA channel.
 #[allow(private_bounds)]
-pub trait Channel: SealedChannel + Peripheral<P = Self> + Into<AnyChannel> + 'static {
-    /// Type-erase (degrade) this pin into an `AnyChannel`.
-    ///
-    /// This converts DMA channel singletons (`DMA1_CH3`, `DMA2_CH1`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of channels, or avoiding generics.
-    #[inline]
-    fn degrade(self) -> AnyChannel {
-        AnyChannel { id: self.id() }
-    }
-}
+pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
 
 macro_rules! dma_channel_impl {
     ($channel_peri:ident, $index:expr) => {
@@ -79,8 +69,10 @@ macro_rules! dma_channel_impl {
         impl crate::dma::Channel for crate::peripherals::$channel_peri {}
 
         impl From<crate::peripherals::$channel_peri> for crate::dma::AnyChannel {
-            fn from(x: crate::peripherals::$channel_peri) -> Self {
-                crate::dma::Channel::degrade(x)
+            fn from(val: crate::peripherals::$channel_peri) -> Self {
+                Self {
+                    id: crate::dma::SealedChannel::id(&val),
+                }
             }
         }
     };
diff --git a/embassy-stm32/src/dma/util.rs b/embassy-stm32/src/dma/util.rs
index 5e1158182..8bf89e2fe 100644
--- a/embassy-stm32/src/dma/util.rs
+++ b/embassy-stm32/src/dma/util.rs
@@ -1,13 +1,12 @@
-use embassy_hal_internal::PeripheralRef;
-
 use super::word::Word;
 use super::{AnyChannel, Request, Transfer, TransferOptions};
+use crate::Peri;
 
 /// Convenience wrapper, contains a channel and a request number.
 ///
 /// Commonly used in peripheral drivers that own DMA channels.
 pub(crate) struct ChannelAndRequest<'d> {
-    pub channel: PeripheralRef<'d, AnyChannel>,
+    pub channel: Peri<'d, AnyChannel>,
     pub request: Request,
 }
 
@@ -18,7 +17,7 @@ impl<'d> ChannelAndRequest<'d> {
         buf: &'a mut [W],
         options: TransferOptions,
     ) -> Transfer<'a> {
-        Transfer::new_read(&mut self.channel, self.request, peri_addr, buf, options)
+        Transfer::new_read(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
     pub unsafe fn read_raw<'a, W: Word>(
@@ -27,7 +26,7 @@ impl<'d> ChannelAndRequest<'d> {
         buf: *mut [W],
         options: TransferOptions,
     ) -> Transfer<'a> {
-        Transfer::new_read_raw(&mut self.channel, self.request, peri_addr, buf, options)
+        Transfer::new_read_raw(self.channel.reborrow(), self.request, peri_addr, buf, options)
     }
 
     pub unsafe fn write<'a, W: Word>(
@@ -36,7 +35,7 @@ impl<'d> ChannelAndRequest<'d> {
         peri_addr: *mut W,
         options: TransferOptions,
     ) -> Transfer<'a> {
-        Transfer::new_write(&mut self.channel, self.request, buf, peri_addr, options)
+        Transfer::new_write(self.channel.reborrow(), self.request, buf, peri_addr, options)
     }
 
     pub unsafe fn write_raw<'a, MW: Word, PW: Word>(
@@ -45,7 +44,7 @@ impl<'d> ChannelAndRequest<'d> {
         peri_addr: *mut PW,
         options: TransferOptions,
     ) -> Transfer<'a> {
-        Transfer::new_write_raw(&mut self.channel, self.request, buf, peri_addr, options)
+        Transfer::new_write_raw(self.channel.reborrow(), self.request, buf, peri_addr, options)
     }
 
     #[allow(dead_code)]
@@ -56,6 +55,13 @@ impl<'d> ChannelAndRequest<'d> {
         peri_addr: *mut W,
         options: TransferOptions,
     ) -> Transfer<'a> {
-        Transfer::new_write_repeated(&mut self.channel, self.request, repeated, count, peri_addr, options)
+        Transfer::new_write_repeated(
+            self.channel.reborrow(),
+            self.request,
+            repeated,
+            count,
+            peri_addr,
+            options,
+        )
     }
 }
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index 77c3d95c3..e97ccd9d0 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -2,12 +2,12 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 
 //use crate::gpio::{AnyPin, SealedPin};
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 /// Performs a busy-wait delay for a specified number of microseconds.
 pub fn blocking_delay_ms(ms: u32) {
@@ -69,14 +69,12 @@ impl From<PacketType> for u8 {
 /// DSIHOST driver.
 pub struct DsiHost<'d, T: Instance> {
     _peri: PhantomData<&'d mut T>,
-    _te: PeripheralRef<'d, AnyPin>,
+    _te: Peri<'d, AnyPin>,
 }
 
 impl<'d, T: Instance> DsiHost<'d, T> {
     /// Note: Full-Duplex modes are not supported at this time
-    pub fn new(_peri: impl Peripheral<P = T> + 'd, te: impl Peripheral<P = impl TePin<T>> + 'd) -> Self {
-        into_ref!(te);
-
+    pub fn new(_peri: Peri<'d, T>, te: Peri<'d, impl TePin<T>>) -> Self {
         rcc::enable_and_reset::<T>();
 
         // Set Tearing Enable pin according to CubeMx example
@@ -88,7 +86,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
         */
         Self {
             _peri: PhantomData,
-            _te: te.map_into(),
+            _te: te.into(),
         }
     }
 
@@ -412,7 +410,7 @@ trait SealedInstance: crate::rcc::SealedRccPeripheral {
 
 /// DSI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {}
 
 pin_trait!(TePin, Instance);
 
diff --git a/embassy-stm32/src/dts/mod.rs b/embassy-stm32/src/dts/mod.rs
index 58d7cf841..1f39c8db5 100644
--- a/embassy-stm32/src/dts/mod.rs
+++ b/embassy-stm32/src/dts/mod.rs
@@ -4,13 +4,13 @@ use core::future::poll_fn;
 use core::sync::atomic::{compiler_fence, Ordering};
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::InterruptExt;
 use crate::peripherals::DTS;
 use crate::time::Hertz;
-use crate::{interrupt, pac, rcc, Peripheral};
+use crate::{interrupt, pac, rcc};
 
 mod tsel;
 pub use tsel::TriggerSel;
@@ -72,7 +72,7 @@ const MAX_DTS_CLK_FREQ: Hertz = Hertz::mhz(1);
 
 /// Digital temperature sensor driver.
 pub struct Dts<'d> {
-    _peri: PeripheralRef<'d, DTS>,
+    _peri: Peri<'d, DTS>,
 }
 
 static WAKER: AtomicWaker = AtomicWaker::new();
@@ -80,11 +80,10 @@ static WAKER: AtomicWaker = AtomicWaker::new();
 impl<'d> Dts<'d> {
     /// Create a new temperature sensor driver.
     pub fn new(
-        _peri: impl Peripheral<P = DTS> + 'd,
+        _peri: Peri<'d, DTS>,
         _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::DTS, InterruptHandler> + 'd,
         config: Config,
     ) -> Self {
-        into_ref!(_peri);
         rcc::enable_and_reset::<DTS>();
 
         let prescaler = rcc::frequency::<DTS>() / MAX_DTS_CLK_FREQ;
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index 109ceeeb3..97d7b4347 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -9,6 +9,7 @@ mod generic_phy;
 use core::mem::MaybeUninit;
 use core::task::Context;
 
+use embassy_hal_internal::PeripheralType;
 use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
 use embassy_sync::waitqueue::AtomicWaker;
 
@@ -199,7 +200,7 @@ trait SealedInstance {
 
 /// Ethernet instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
 
 impl SealedInstance for crate::peripherals::ETH {
     fn regs() -> crate::pac::eth::Eth {
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index e12ac2fef..640191d69 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -6,7 +6,7 @@ mod tx_desc;
 use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
 
 pub(crate) use self::rx_desc::{RDes, RDesRing};
@@ -15,6 +15,7 @@ use super::*;
 #[cfg(eth_v1a)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+use crate::interrupt;
 use crate::interrupt::InterruptExt;
 #[cfg(eth_v1a)]
 use crate::pac::AFIO;
@@ -22,7 +23,6 @@ use crate::pac::AFIO;
 use crate::pac::SYSCFG;
 use crate::pac::{ETH, RCC};
 use crate::rcc::SealedRccPeripheral;
-use crate::{interrupt, Peripheral};
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -47,11 +47,11 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandl
 
 /// Ethernet driver.
 pub struct Ethernet<'d, T: Instance, P: Phy> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
     pub(crate) tx: TDesRing<'d>,
     pub(crate) rx: RDesRing<'d>,
 
-    pins: [PeripheralRef<'d, AnyPin>; 9],
+    pins: [Peri<'d, AnyPin>; 9],
     pub(crate) phy: P,
     pub(crate) station_management: EthernetStationManagement<T>,
     pub(crate) mac_addr: [u8; 6],
@@ -95,22 +95,20 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     /// safety: the returned instance is not leak-safe
     pub fn new<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
-        crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
+        mdio: Peri<'d, impl MDIOPin<T>>,
+        mdc: Peri<'d, impl MDCPin<T>>,
+        crs: Peri<'d, impl CRSPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
-        into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
-
         // Enable the necessary Clocks
         #[cfg(eth_v1a)]
         critical_section::with(|_| {
@@ -213,15 +211,15 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         };
 
         let pins = [
-            ref_clk.map_into(),
-            mdio.map_into(),
-            mdc.map_into(),
-            crs.map_into(),
-            rx_d0.map_into(),
-            rx_d1.map_into(),
-            tx_d0.map_into(),
-            tx_d1.map_into(),
-            tx_en.map_into(),
+            ref_clk.into(),
+            mdio.into(),
+            mdc.into(),
+            crs.into(),
+            rx_d0.into(),
+            rx_d1.into(),
+            tx_d0.into(),
+            tx_d1.into(),
+            tx_en.into(),
         ];
 
         let mut this = Self {
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 26e4eeb63..034c5dd88 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -3,16 +3,16 @@ mod descriptors;
 use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 use stm32_metapac::syscfg::vals::EthSelPhy;
 
 pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
 use super::*;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
+use crate::interrupt;
 use crate::interrupt::InterruptExt;
 use crate::pac::ETH;
 use crate::rcc::SealedRccPeripheral;
-use crate::{interrupt, Peripheral};
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -37,7 +37,7 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandl
 
 /// Ethernet driver.
 pub struct Ethernet<'d, T: Instance, P: Phy> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
     pub(crate) tx: TDesRing<'d>,
     pub(crate) rx: RDesRing<'d>,
     pins: Pins<'d>,
@@ -48,8 +48,8 @@ pub struct Ethernet<'d, T: Instance, P: Phy> {
 
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([PeripheralRef<'d, AnyPin>; 9]),
-    Mii([PeripheralRef<'d, AnyPin>; 14]),
+    Rmii([Peri<'d, AnyPin>; 9]),
+    Mii([Peri<'d, AnyPin>; 14]),
 }
 
 macro_rules! config_pins {
@@ -67,17 +67,17 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     /// Create a new RMII ethernet driver using 9 pins.
     pub fn new<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
-        crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
+        mdio: Peri<'d, impl MDIOPin<T>>,
+        mdc: Peri<'d, impl MDCPin<T>>,
+        crs: Peri<'d, impl CRSPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
@@ -92,19 +92,18 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
         });
 
-        into_ref!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
         config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
         let pins = Pins::Rmii([
-            ref_clk.map_into(),
-            mdio.map_into(),
-            mdc.map_into(),
-            crs.map_into(),
-            rx_d0.map_into(),
-            rx_d1.map_into(),
-            tx_d0.map_into(),
-            tx_d1.map_into(),
-            tx_en.map_into(),
+            ref_clk.into(),
+            mdio.into(),
+            mdc.into(),
+            crs.into(),
+            rx_d0.into(),
+            rx_d1.into(),
+            tx_d0.into(),
+            tx_d1.into(),
+            tx_en.into(),
         ]);
 
         Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
@@ -113,22 +112,22 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     /// Create a new MII ethernet driver using 14 pins.
     pub fn new_mii<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        rx_clk: impl Peripheral<P = impl RXClkPin<T>> + 'd,
-        tx_clk: impl Peripheral<P = impl TXClkPin<T>> + 'd,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
-        rxdv: impl Peripheral<P = impl RXDVPin<T>> + 'd,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
-        rx_d2: impl Peripheral<P = impl RXD2Pin<T>> + 'd,
-        rx_d3: impl Peripheral<P = impl RXD3Pin<T>> + 'd,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
-        tx_d2: impl Peripheral<P = impl TXD2Pin<T>> + 'd,
-        tx_d3: impl Peripheral<P = impl TXD3Pin<T>> + 'd,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        rx_clk: Peri<'d, impl RXClkPin<T>>,
+        tx_clk: Peri<'d, impl TXClkPin<T>>,
+        mdio: Peri<'d, impl MDIOPin<T>>,
+        mdc: Peri<'d, impl MDCPin<T>>,
+        rxdv: Peri<'d, impl RXDVPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        rx_d2: Peri<'d, impl RXD2Pin<T>>,
+        rx_d3: Peri<'d, impl RXD3Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_d2: Peri<'d, impl TXD2Pin<T>>,
+        tx_d3: Peri<'d, impl TXD3Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
@@ -145,24 +144,23 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
                 .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
         });
 
-        into_ref!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
         config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
 
         let pins = Pins::Mii([
-            rx_clk.map_into(),
-            tx_clk.map_into(),
-            mdio.map_into(),
-            mdc.map_into(),
-            rxdv.map_into(),
-            rx_d0.map_into(),
-            rx_d1.map_into(),
-            rx_d2.map_into(),
-            rx_d3.map_into(),
-            tx_d0.map_into(),
-            tx_d1.map_into(),
-            tx_d2.map_into(),
-            tx_d3.map_into(),
-            tx_en.map_into(),
+            rx_clk.into(),
+            tx_clk.into(),
+            mdio.into(),
+            mdc.into(),
+            rxdv.into(),
+            rx_d0.into(),
+            rx_d1.into(),
+            rx_d2.into(),
+            rx_d3.into(),
+            tx_d0.into(),
+            tx_d1.into(),
+            tx_d2.into(),
+            tx_d3.into(),
+            tx_en.into(),
         ]);
 
         Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
@@ -170,7 +168,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
     fn new_inner<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         pins: Pins<'d>,
         phy: P,
@@ -254,7 +252,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         };
 
         let mut this = Self {
-            _peri: peri.into_ref(),
+            _peri: peri,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
             rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
             pins,
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 9604c5149..9fce78f95 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,13 +5,13 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, into_ref};
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
 use crate::pac::exti::regs::Lines;
 use crate::pac::EXTI;
-use crate::{interrupt, pac, peripherals, Peripheral};
+use crate::{interrupt, pac, peripherals, Peri};
 
 const EXTI_COUNT: usize = 16;
 static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
@@ -105,13 +105,7 @@ impl<'d> Unpin for ExtiInput<'d> {}
 
 impl<'d> ExtiInput<'d> {
     /// Create an EXTI input.
-    pub fn new<T: GpioPin>(
-        pin: impl Peripheral<P = T> + 'd,
-        ch: impl Peripheral<P = T::ExtiChannel> + 'd,
-        pull: Pull,
-    ) -> Self {
-        into_ref!(pin, ch);
-
+    pub fn new<T: GpioPin>(pin: Peri<'d, T>, ch: Peri<'d, T::ExtiChannel>, pull: Pull) -> Self {
         // Needed if using AnyPin+AnyChannel.
         assert_eq!(pin.pin(), ch.number());
 
@@ -338,23 +332,12 @@ trait SealedChannel {}
 
 /// EXTI channel trait.
 #[allow(private_bounds)]
-pub trait Channel: SealedChannel + Sized {
+pub trait Channel: PeripheralType + SealedChannel + Sized {
     /// Get the EXTI channel number.
     fn number(&self) -> u8;
-
-    /// Type-erase (degrade) this channel into an `AnyChannel`.
-    ///
-    /// This converts EXTI channel singletons (`EXTI0`, `EXTI1`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of channels, or avoiding generics.
-    fn degrade(self) -> AnyChannel {
-        AnyChannel {
-            number: self.number() as u8,
-        }
-    }
 }
 
-/// Type-erased (degraded) EXTI channel.
+/// Type-erased EXTI channel.
 ///
 /// This represents ownership over any EXTI channel, known at runtime.
 pub struct AnyChannel {
@@ -377,6 +360,14 @@ macro_rules! impl_exti {
                 $number
             }
         }
+
+        impl From<peripherals::$type> for AnyChannel {
+            fn from(val: peripherals::$type) -> Self {
+                Self {
+                    number: val.number() as u8,
+                }
+            }
+        }
     };
 }
 
diff --git a/embassy-stm32/src/flash/asynch.rs b/embassy-stm32/src/flash/asynch.rs
index 9468ac632..599b7bb4e 100644
--- a/embassy-stm32/src/flash/asynch.rs
+++ b/embassy-stm32/src/flash/asynch.rs
@@ -2,7 +2,6 @@ use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::into_ref;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::mutex::Mutex;
 
@@ -12,18 +11,16 @@ use super::{
 };
 use crate::interrupt::InterruptExt;
 use crate::peripherals::FLASH;
-use crate::{interrupt, Peripheral};
+use crate::{interrupt, Peri};
 
 pub(super) static REGION_ACCESS: Mutex<CriticalSectionRawMutex, ()> = Mutex::new(());
 
 impl<'d> Flash<'d, Async> {
     /// Create a new flash driver with async capabilities.
     pub fn new(
-        p: impl Peripheral<P = FLASH> + 'd,
+        p: Peri<'d, FLASH>,
         _irq: impl interrupt::typelevel::Binding<crate::interrupt::typelevel::FLASH, InterruptHandler> + 'd,
     ) -> Self {
-        into_ref!(p);
-
         crate::interrupt::FLASH.unpend();
         unsafe { crate::interrupt::FLASH.enable() };
 
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index 0004a7488..1376ca4b4 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -2,27 +2,24 @@ use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, PeripheralRef};
 
 use super::{
     family, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE, MAX_ERASE_SIZE,
     READ_SIZE, WRITE_SIZE,
 };
+use crate::Peri;
 use crate::_generated::FLASH_BASE;
 use crate::peripherals::FLASH;
-use crate::Peripheral;
 
 /// Internal flash memory driver.
 pub struct Flash<'d, MODE = Async> {
-    pub(crate) inner: PeripheralRef<'d, FLASH>,
+    pub(crate) inner: Peri<'d, FLASH>,
     pub(crate) _mode: PhantomData<MODE>,
 }
 
 impl<'d> Flash<'d, Blocking> {
     /// Create a new flash driver, usable in blocking mode.
-    pub fn new_blocking(p: impl Peripheral<P = FLASH> + 'd) -> Self {
-        into_ref!(p);
-
+    pub fn new_blocking(p: Peri<'d, FLASH>) -> Self {
         Self {
             inner: p,
             _mode: PhantomData,
diff --git a/embassy-stm32/src/flash/f4.rs b/embassy-stm32/src/flash/f4.rs
index 86afdce8a..687eabaeb 100644
--- a/embassy-stm32/src/flash/f4.rs
+++ b/embassy-stm32/src/flash/f4.rs
@@ -13,8 +13,7 @@ use crate::pac;
 mod alt_regions {
     use core::marker::PhantomData;
 
-    use embassy_hal_internal::PeripheralRef;
-
+    use crate::Peri;
     use crate::_generated::flash_regions::{OTPRegion, BANK1_REGION1, BANK1_REGION2, BANK1_REGION3, OTP_REGION};
     use crate::_generated::FLASH_SIZE;
     use crate::flash::{asynch, Async, Bank1Region1, Bank1Region2, Blocking, Error, Flash, FlashBank, FlashRegion};
@@ -50,10 +49,10 @@ mod alt_regions {
         &ALT_BANK2_REGION3,
     ];
 
-    pub struct AltBank1Region3<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region1<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region2<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region3<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
+    pub struct AltBank1Region3<'d, MODE = Async>(pub &'static FlashRegion, Peri<'d, FLASH>, PhantomData<MODE>);
+    pub struct AltBank2Region1<'d, MODE = Async>(pub &'static FlashRegion, Peri<'d, FLASH>, PhantomData<MODE>);
+    pub struct AltBank2Region2<'d, MODE = Async>(pub &'static FlashRegion, Peri<'d, FLASH>, PhantomData<MODE>);
+    pub struct AltBank2Region3<'d, MODE = Async>(pub &'static FlashRegion, Peri<'d, FLASH>, PhantomData<MODE>);
 
     pub struct AltFlashLayout<'d, MODE = Async> {
         pub bank1_region1: Bank1Region1<'d, MODE>,
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index 83b49a3dd..71ca775cb 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -1,10 +1,10 @@
 //! Flexible Memory Controller (FMC) / Flexible Static Memory Controller (FSMC)
 use core::marker::PhantomData;
 
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Pull, Speed};
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 
 /// FMC driver
 pub struct Fmc<'d, T: Instance> {
@@ -21,7 +21,7 @@ where
     ///
     /// **Note:** This is currently used to provide access to some basic FMC functions
     /// for manual configuration for memory types that stm32-fmc does not support.
-    pub fn new_raw(_instance: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new_raw(_instance: Peri<'d, T>) -> Self {
         Self { peri: PhantomData }
     }
 
@@ -74,8 +74,7 @@ where
 
 macro_rules! config_pins {
     ($($pin:ident),*) => {
-        into_ref!($($pin),*);
-        $(
+                $(
             $pin.set_as_af($pin.af_num(), AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up));
         )*
     };
@@ -92,12 +91,12 @@ macro_rules! fmc_sdram_constructor {
     )) => {
         /// Create a new FMC instance.
         pub fn $name<CHIP: stm32_fmc::SdramChip>(
-            _instance: impl Peripheral<P = T> + 'd,
-            $($addr_pin_name: impl Peripheral<P = impl $addr_signal<T>> + 'd),*,
-            $($ba_pin_name: impl Peripheral<P = impl $ba_signal<T>> + 'd),*,
-            $($d_pin_name: impl Peripheral<P = impl $d_signal<T>> + 'd),*,
-            $($nbl_pin_name: impl Peripheral<P = impl $nbl_signal<T>> + 'd),*,
-            $($ctrl_pin_name: impl Peripheral<P = impl $ctrl_signal<T>> + 'd),*,
+            _instance: Peri<'d, T>,
+            $($addr_pin_name: Peri<'d, impl $addr_signal<T>>),*,
+            $($ba_pin_name: Peri<'d, impl $ba_signal<T>>),*,
+            $($d_pin_name: Peri<'d, impl $d_signal<T>>),*,
+            $($nbl_pin_name: Peri<'d, impl $nbl_signal<T>>),*,
+            $($ctrl_pin_name: Peri<'d, impl $ctrl_signal<T>>),*,
             chip: CHIP
         ) -> stm32_fmc::Sdram<Fmc<'d, T>, CHIP> {
 
@@ -245,7 +244,7 @@ trait SealedInstance: crate::rcc::RccPeripheral {
 
 /// FMC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 
 foreach_peripheral!(
     (fmc, $inst:ident) => {
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 65e1bfb8c..bb37c4194 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -4,10 +4,10 @@
 use core::convert::Infallible;
 
 use critical_section::CriticalSection;
-use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
+use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
 
 use crate::pac::gpio::{self, vals};
-use crate::{peripherals, Peripheral};
+use crate::peripherals;
 
 /// GPIO flexible pin.
 ///
@@ -15,7 +15,7 @@ use crate::{peripherals, Peripheral};
 /// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
 /// mode.
 pub struct Flex<'d> {
-    pub(crate) pin: PeripheralRef<'d, AnyPin>,
+    pub(crate) pin: Peri<'d, AnyPin>,
 }
 
 impl<'d> Flex<'d> {
@@ -25,10 +25,9 @@ impl<'d> Flex<'d> {
     /// before the pin is put into output mode.
     ///
     #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd) -> Self {
-        into_ref!(pin);
+    pub fn new(pin: Peri<'d, impl Pin>) -> Self {
         // Pin will be in disconnected state.
-        Self { pin: pin.map_into() }
+        Self { pin: pin.into() }
     }
 
     /// Put the pin into input mode.
@@ -310,7 +309,7 @@ pub struct Input<'d> {
 impl<'d> Input<'d> {
     /// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
     #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, pull: Pull) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, pull: Pull) -> Self {
         let mut pin = Flex::new(pin);
         pin.set_as_input(pull);
         Self { pin }
@@ -375,7 +374,7 @@ pub struct Output<'d> {
 impl<'d> Output<'d> {
     /// Create GPIO output driver for a [Pin] with the provided [Level] and [Speed] configuration.
     #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed) -> Self {
         let mut pin = Flex::new(pin);
         match initial_output {
             Level::High => pin.set_high(),
@@ -440,7 +439,7 @@ pub struct OutputOpenDrain<'d> {
 impl<'d> OutputOpenDrain<'d> {
     /// Create a new GPIO open drain output driver for a [Pin] with the provided [Level] and [Speed].
     #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed) -> Self {
         let mut pin = Flex::new(pin);
         match initial_output {
             Level::High => pin.set_high(),
@@ -454,7 +453,7 @@ impl<'d> OutputOpenDrain<'d> {
     /// and [Pull].
     #[inline]
     #[cfg(gpio_v2)]
-    pub fn new_pull(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
+    pub fn new_pull(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed, pull: Pull) -> Self {
         let mut pin = Flex::new(pin);
         match initial_output {
             Level::High => pin.set_high(),
@@ -780,7 +779,7 @@ pub(crate) trait SealedPin {
 
 /// GPIO pin trait.
 #[allow(private_bounds)]
-pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + SealedPin + Sized + 'static {
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
     /// EXTI channel assigned to this pin.
     ///
     /// For example, PC4 uses EXTI4.
@@ -798,18 +797,6 @@ pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + SealedPin + Sized + 'static
     fn port(&self) -> u8 {
         self._port()
     }
-
-    /// Type-erase (degrade) this pin into an `AnyPin`.
-    ///
-    /// This converts pin singletons (`PA5`, `PB6`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of pins, or avoiding generics.
-    #[inline]
-    fn degrade(self) -> AnyPin {
-        AnyPin {
-            pin_port: self.pin_port(),
-        }
-    }
 }
 
 /// Type-erased GPIO pin
@@ -822,8 +809,8 @@ impl AnyPin {
     ///
     /// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
     #[inline]
-    pub unsafe fn steal(pin_port: u8) -> Self {
-        Self { pin_port }
+    pub unsafe fn steal(pin_port: u8) -> Peri<'static, Self> {
+        Peri::new_unchecked(Self { pin_port })
     }
 
     #[inline]
@@ -867,8 +854,10 @@ foreach_pin!(
         }
 
         impl From<peripherals::$pin_name> for AnyPin {
-            fn from(x: peripherals::$pin_name) -> Self {
-                x.degrade()
+            fn from(val: peripherals::$pin_name) -> Self {
+                Self {
+                    pin_port: val.pin_port(),
+                }
             }
         }
     };
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 3951e9d63..1258e8923 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -8,7 +8,7 @@ use core::ptr;
 #[cfg(hash_v2)]
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use stm32_metapac::hash::regs::*;
 
@@ -19,7 +19,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::mode::Async;
 use crate::mode::{Blocking, Mode};
 use crate::peripherals::HASH;
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::{interrupt, pac, peripherals, rcc, Peri};
 
 #[cfg(hash_v1)]
 const NUM_CONTEXT_REGS: usize = 51;
@@ -119,7 +119,7 @@ type HmacKey<'k> = Option<&'k [u8]>;
 
 /// HASH driver.
 pub struct Hash<'d, T: Instance, M: Mode> {
-    _peripheral: PeripheralRef<'d, T>,
+    _peripheral: Peri<'d, T>,
     _phantom: PhantomData<M>,
     #[cfg(hash_v2)]
     dma: Option<ChannelAndRequest<'d>>,
@@ -128,11 +128,10 @@ pub struct Hash<'d, T: Instance, M: Mode> {
 impl<'d, T: Instance> Hash<'d, T, Blocking> {
     /// Instantiates, resets, and enables the HASH peripheral.
     pub fn new_blocking(
-        peripheral: impl Peripheral<P = T> + 'd,
+        peripheral: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         rcc::enable_and_reset::<HASH>();
-        into_ref!(peripheral);
         let instance = Self {
             _peripheral: peripheral,
             _phantom: PhantomData,
@@ -396,12 +395,11 @@ impl<'d, T: Instance, M: Mode> Hash<'d, T, M> {
 impl<'d, T: Instance> Hash<'d, T, Async> {
     /// Instantiates, resets, and enables the HASH peripheral.
     pub fn new(
-        peripheral: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = impl Dma<T>> + 'd,
+        peripheral: Peri<'d, T>,
+        dma: Peri<'d, impl Dma<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         rcc::enable_and_reset::<HASH>();
-        into_ref!(peripheral, dma);
         let instance = Self {
             _peripheral: peripheral,
             _phantom: PhantomData,
@@ -583,7 +581,7 @@ trait SealedInstance {
 
 /// HASH instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
     /// Interrupt for this HASH instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index d9b7c16fb..1d0594125 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -4,12 +4,12 @@ mod traits;
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 pub use traits::Instance;
 
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::rcc;
 use crate::time::Hertz;
-use crate::{rcc, Peripheral};
 
 /// HRTIM burst controller instance.
 pub struct BurstController<T: Instance> {
@@ -62,13 +62,13 @@ pub trait AdvancedChannel<T: Instance>: SealedAdvancedChannel<T> {}
 
 /// HRTIM PWM pin.
 pub struct PwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
 /// HRTIM complementary PWM pin.
 pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -76,8 +76,7 @@ macro_rules! advanced_channel_impl {
     ($new_chx:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
         impl<'d, T: Instance> PwmPin<'d, T, $channel<T>> {
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -86,7 +85,7 @@ macro_rules! advanced_channel_impl {
                     );
                 });
                 PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -94,8 +93,7 @@ macro_rules! advanced_channel_impl {
 
         impl<'d, T: Instance> ComplementaryPwmPin<'d, T, $channel<T>> {
             #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $complementary_pin_trait<T>> + 'd) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $complementary_pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -104,7 +102,7 @@ macro_rules! advanced_channel_impl {
                     );
                 });
                 ComplementaryPwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -129,7 +127,7 @@ advanced_channel_impl!(new_chf, ChF, 5, ChannelFPin, ChannelFComplementaryPin);
 
 /// Struct used to divide a high resolution timer into multiple channels
 pub struct AdvancedPwm<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
     /// Master instance.
     pub master: Master<T>,
     /// Burst controller.
@@ -154,7 +152,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
     ///
     /// This splits the HRTIM into its constituent parts, which you can then use individually.
     pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
         _cha: Option<PwmPin<'d, T, ChA<T>>>,
         _chan: Option<ComplementaryPwmPin<'d, T, ChA<T>>>,
         _chb: Option<PwmPin<'d, T, ChB<T>>>,
@@ -171,9 +169,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
         Self::new_inner(tim)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(tim);
-
+    fn new_inner(tim: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         #[cfg(stm32f334)]
diff --git a/embassy-stm32/src/hrtim/traits.rs b/embassy-stm32/src/hrtim/traits.rs
index 75f9971e2..6c0661146 100644
--- a/embassy-stm32/src/hrtim/traits.rs
+++ b/embassy-stm32/src/hrtim/traits.rs
@@ -1,3 +1,5 @@
+use embassy_hal_internal::PeripheralType;
+
 use crate::rcc::RccPeripheral;
 use crate::time::Hertz;
 
@@ -153,7 +155,7 @@ pub(crate) trait SealedInstance: RccPeripheral {
 
 /// HRTIM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 
 foreach_interrupt! {
     ($inst:ident, hrtim, HRTIM, MASTER, $irq:ident) => {
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 06ab7a9bc..31527bcdb 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -1,13 +1,14 @@
 //! Hardware Semaphore (HSEM)
 
+use embassy_hal_internal::PeripheralType;
+
+use crate::pac;
+use crate::rcc::RccPeripheral;
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
 // which is not yet supported by this code.
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
-use crate::rcc::RccPeripheral;
-use crate::{pac, Peripheral};
+use crate::Peri;
 
 /// HSEM error.
 #[derive(Debug)]
@@ -73,13 +74,12 @@ fn core_id_to_index(core: CoreId) -> usize {
 
 /// HSEM driver
 pub struct HardwareSemaphore<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
 }
 
 impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Creates a new HardwareSemaphore instance.
-    pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(peripheral);
+    pub fn new(peripheral: Peri<'d, T>) -> Self {
         HardwareSemaphore { _peri: peripheral }
     }
 
@@ -177,7 +177,7 @@ trait SealedInstance {
 
 /// HSEM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
 
 impl SealedInstance for crate::peripherals::HSEM {
     fn regs() -> crate::pac::hsem::Hsem {
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
index 54b442481..62bc0e979 100644
--- a/embassy-stm32/src/hspi/mod.rs
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -13,15 +13,15 @@ pub mod enums;
 use core::marker::PhantomData;
 
 use embassy_embedded_hal::{GetConfig, SetConfig};
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 pub use enums::*;
 
 use crate::dma::{word, ChannelAndRequest};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::hspi::Hspi as Regs;
+use crate::peripherals;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
 
 /// HSPI driver config.
 #[derive(Clone, Copy)]
@@ -163,27 +163,27 @@ pub enum HspiError {
 
 /// HSPI driver.
 pub struct Hspi<'d, T: Instance, M: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
-    d0: Option<PeripheralRef<'d, AnyPin>>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
-    d4: Option<PeripheralRef<'d, AnyPin>>,
-    d5: Option<PeripheralRef<'d, AnyPin>>,
-    d6: Option<PeripheralRef<'d, AnyPin>>,
-    d7: Option<PeripheralRef<'d, AnyPin>>,
-    d8: Option<PeripheralRef<'d, AnyPin>>,
-    d9: Option<PeripheralRef<'d, AnyPin>>,
-    d10: Option<PeripheralRef<'d, AnyPin>>,
-    d11: Option<PeripheralRef<'d, AnyPin>>,
-    d12: Option<PeripheralRef<'d, AnyPin>>,
-    d13: Option<PeripheralRef<'d, AnyPin>>,
-    d14: Option<PeripheralRef<'d, AnyPin>>,
-    d15: Option<PeripheralRef<'d, AnyPin>>,
-    nss: Option<PeripheralRef<'d, AnyPin>>,
-    dqs0: Option<PeripheralRef<'d, AnyPin>>,
-    dqs1: Option<PeripheralRef<'d, AnyPin>>,
+    _peri: Peri<'d, T>,
+    sck: Option<Peri<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
+    d8: Option<Peri<'d, AnyPin>>,
+    d9: Option<Peri<'d, AnyPin>>,
+    d10: Option<Peri<'d, AnyPin>>,
+    d11: Option<Peri<'d, AnyPin>>,
+    d12: Option<Peri<'d, AnyPin>>,
+    d13: Option<Peri<'d, AnyPin>>,
+    d14: Option<Peri<'d, AnyPin>>,
+    d15: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
+    dqs0: Option<Peri<'d, AnyPin>>,
+    dqs1: Option<Peri<'d, AnyPin>>,
     dma: Option<ChannelAndRequest<'d>>,
     _phantom: PhantomData<M>,
     config: Config,
@@ -247,34 +247,32 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
     }
 
     fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: Option<PeripheralRef<'d, AnyPin>>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
-        d4: Option<PeripheralRef<'d, AnyPin>>,
-        d5: Option<PeripheralRef<'d, AnyPin>>,
-        d6: Option<PeripheralRef<'d, AnyPin>>,
-        d7: Option<PeripheralRef<'d, AnyPin>>,
-        d8: Option<PeripheralRef<'d, AnyPin>>,
-        d9: Option<PeripheralRef<'d, AnyPin>>,
-        d10: Option<PeripheralRef<'d, AnyPin>>,
-        d11: Option<PeripheralRef<'d, AnyPin>>,
-        d12: Option<PeripheralRef<'d, AnyPin>>,
-        d13: Option<PeripheralRef<'d, AnyPin>>,
-        d14: Option<PeripheralRef<'d, AnyPin>>,
-        d15: Option<PeripheralRef<'d, AnyPin>>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
-        nss: Option<PeripheralRef<'d, AnyPin>>,
-        dqs0: Option<PeripheralRef<'d, AnyPin>>,
-        dqs1: Option<PeripheralRef<'d, AnyPin>>,
+        peri: Peri<'d, T>,
+        d0: Option<Peri<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
+        d8: Option<Peri<'d, AnyPin>>,
+        d9: Option<Peri<'d, AnyPin>>,
+        d10: Option<Peri<'d, AnyPin>>,
+        d11: Option<Peri<'d, AnyPin>>,
+        d12: Option<Peri<'d, AnyPin>>,
+        d13: Option<Peri<'d, AnyPin>>,
+        d14: Option<Peri<'d, AnyPin>>,
+        d15: Option<Peri<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
+        dqs0: Option<Peri<'d, AnyPin>>,
+        dqs1: Option<Peri<'d, AnyPin>>,
         dma: Option<ChannelAndRequest<'d>>,
         config: Config,
         width: HspiWidth,
         dual_memory_mode: bool,
     ) -> Self {
-        into_ref!(peri);
-
         // System configuration
         rcc::enable_and_reset::<T>();
 
@@ -579,11 +577,11 @@ impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
 impl<'d, T: Instance> Hspi<'d, T, Blocking> {
     /// Create new blocking HSPI driver for single spi external chip
     pub fn new_blocking_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -620,18 +618,18 @@ impl<'d, T: Instance> Hspi<'d, T, Blocking> {
 
     /// Create new blocking HSPI driver for octospi external chip
     pub fn new_blocking_octospi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dqs0: impl Peripheral<P = impl DQS0Pin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs0: Peri<'d, impl DQS0Pin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -670,12 +668,12 @@ impl<'d, T: Instance> Hspi<'d, T, Blocking> {
 impl<'d, T: Instance> Hspi<'d, T, Async> {
     /// Create new HSPI driver for a single spi external chip
     pub fn new_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl HspiDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl HspiDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -712,19 +710,19 @@ impl<'d, T: Instance> Hspi<'d, T, Async> {
 
     /// Create new HSPI driver for octospi external chip
     pub fn new_octospi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dqs0: impl Peripheral<P = impl DQS0Pin<T>> + 'd,
-        dma: impl Peripheral<P = impl HspiDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs0: Peri<'d, impl DQS0Pin<T>>,
+        dma: Peri<'d, impl HspiDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -943,7 +941,7 @@ pub(crate) trait SealedInstance {
 
 /// HSPI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 
 pin_trait!(SckPin, Instance);
 pin_trait!(NckPin, Instance);
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 3a9954663..1689fdb84 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -9,7 +9,7 @@ use core::future::Future;
 use core::iter;
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(feature = "time")]
 use embassy_time::{Duration, Instant};
@@ -131,8 +131,8 @@ pub struct I2c<'d, M: Mode> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    scl: Option<PeripheralRef<'d, AnyPin>>,
-    sda: Option<PeripheralRef<'d, AnyPin>>,
+    scl: Option<Peri<'d, AnyPin>>,
+    sda: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
     #[cfg(feature = "time")]
@@ -143,14 +143,14 @@ pub struct I2c<'d, M: Mode> {
 impl<'d> I2c<'d, Async> {
     /// Create a new I2C driver.
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        scl: impl Peripheral<P = impl SclPin<T>> + 'd,
-        sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
             + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
             + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         freq: Hertz,
         config: Config,
     ) -> Self {
@@ -169,9 +169,9 @@ impl<'d> I2c<'d, Async> {
 impl<'d> I2c<'d, Blocking> {
     /// Create a new blocking I2C driver.
     pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        scl: impl Peripheral<P = impl SclPin<T>> + 'd,
-        sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        scl: Peri<'d, impl SclPin<T>>,
+        sda: Peri<'d, impl SdaPin<T>>,
         freq: Hertz,
         config: Config,
     ) -> Self {
@@ -190,9 +190,9 @@ impl<'d> I2c<'d, Blocking> {
 impl<'d, M: Mode> I2c<'d, M> {
     /// Create a new I2C driver.
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        scl: Option<PeripheralRef<'d, AnyPin>>,
-        sda: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        scl: Option<Peri<'d, AnyPin>>,
+        sda: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         freq: Hertz,
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index ce166d718..5005a5cdb 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -1,7 +1,6 @@
 //! Inter-IC Sound (I2S)
 
 use embassy_futures::join::join;
-use embassy_hal_internal::into_ref;
 use stm32_metapac::spi::vals;
 
 use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
@@ -9,7 +8,7 @@ use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
 use crate::spi::{Config as SpiConfig, RegsExt as _, *};
 use crate::time::Hertz;
-use crate::{Peripheral, PeripheralRef};
+use crate::Peri;
 
 /// I2S mode
 #[derive(Copy, Clone)]
@@ -225,11 +224,11 @@ pub struct I2S<'d, W: Word> {
     #[allow(dead_code)]
     mode: Mode,
     spi: Spi<'d, Async>,
-    txsd: Option<PeripheralRef<'d, AnyPin>>,
-    rxsd: Option<PeripheralRef<'d, AnyPin>>,
-    ws: Option<PeripheralRef<'d, AnyPin>>,
-    ck: Option<PeripheralRef<'d, AnyPin>>,
-    mck: Option<PeripheralRef<'d, AnyPin>>,
+    txsd: Option<Peri<'d, AnyPin>>,
+    rxsd: Option<Peri<'d, AnyPin>>,
+    ws: Option<Peri<'d, AnyPin>>,
+    ck: Option<Peri<'d, AnyPin>>,
+    mck: Option<Peri<'d, AnyPin>>,
     tx_ring_buffer: Option<WritableRingBuffer<'d, W>>,
     rx_ring_buffer: Option<ReadableRingBuffer<'d, W>>,
 }
@@ -237,12 +236,12 @@ pub struct I2S<'d, W: Word> {
 impl<'d, W: Word> I2S<'d, W> {
     /// Create a transmitter driver.
     pub fn new_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
-        txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sd: Peri<'d, impl MosiPin<T>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        mck: Peri<'d, impl MckPin<T>>,
+        txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
         freq: Hertz,
         config: Config,
@@ -264,11 +263,11 @@ impl<'d, W: Word> I2S<'d, W> {
 
     /// Create a transmitter driver without a master clock pin.
     pub fn new_txonly_nomck<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
-        txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sd: Peri<'d, impl MosiPin<T>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
         freq: Hertz,
         config: Config,
@@ -290,12 +289,12 @@ impl<'d, W: Word> I2S<'d, W> {
 
     /// Create a receiver driver.
     pub fn new_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sd: impl Peripheral<P = impl MisoPin<T>> + 'd,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
-        rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sd: Peri<'d, impl MisoPin<T>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        mck: Peri<'d, impl MckPin<T>>,
+        rxdma: Peri<'d, impl RxDma<T>>,
         rxdma_buf: &'d mut [W],
         freq: Hertz,
         config: Config,
@@ -318,15 +317,15 @@ impl<'d, W: Word> I2S<'d, W> {
     #[cfg(spi_v3)]
     /// Create a full duplex driver.
     pub fn new_full_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        txsd: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        rxsd: impl Peripheral<P = impl MisoPin<T>> + 'd,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
-        txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        txsd: Peri<'d, impl MosiPin<T>>,
+        rxsd: Peri<'d, impl MisoPin<T>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        mck: Peri<'d, impl MckPin<T>>,
+        txdma: Peri<'d, impl TxDma<T>>,
         txdma_buf: &'d mut [W],
-        rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rxdma: Peri<'d, impl RxDma<T>>,
         rxdma_buf: &'d mut [W],
         freq: Hertz,
         config: Config,
@@ -466,20 +465,18 @@ impl<'d, W: Word> I2S<'d, W> {
     }
 
     fn new_inner<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        txsd: Option<PeripheralRef<'d, AnyPin>>,
-        rxsd: Option<PeripheralRef<'d, AnyPin>>,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
-        mck: Option<PeripheralRef<'d, AnyPin>>,
+        peri: Peri<'d, T>,
+        txsd: Option<Peri<'d, AnyPin>>,
+        rxsd: Option<Peri<'d, AnyPin>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        mck: Option<Peri<'d, AnyPin>>,
         txdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
         rxdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
         freq: Hertz,
         config: Config,
         function: Function,
     ) -> Self {
-        into_ref!(ws, ck);
-
         ws.set_as_af(ws.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
         ck.set_as_af(ck.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
@@ -583,11 +580,11 @@ impl<'d, W: Word> I2S<'d, W> {
             Self {
                 mode: config.mode,
                 spi,
-                txsd: txsd.map(|w| w.map_into()),
-                rxsd: rxsd.map(|w| w.map_into()),
-                ws: Some(ws.map_into()),
-                ck: Some(ck.map_into()),
-                mck: mck.map(|w| w.map_into()),
+                txsd: txsd.map(|w| w.into()),
+                rxsd: rxsd.map(|w| w.into()),
+                ws: Some(ws.into()),
+                ck: Some(ck.into()),
+                mck: mck.map(|w| w.into()),
                 tx_ring_buffer: txdma.map(|(ch, buf)| unsafe {
                     WritableRingBuffer::new(ch.channel, ch.request, regs.tx_ptr(), buf, opts)
                 }),
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index c37908dbc..4d7aac81f 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -211,7 +211,7 @@ macro_rules! bind_interrupts {
 
 // Reexports
 pub use _generated::{peripherals, Peripherals};
-pub use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+pub use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(feature = "unstable-pac")]
 pub use stm32_metapac as pac;
 #[cfg(not(feature = "unstable-pac"))]
diff --git a/embassy-stm32/src/lptim/mod.rs b/embassy-stm32/src/lptim/mod.rs
index 1649cc5b4..e0ddba1c7 100644
--- a/embassy-stm32/src/lptim/mod.rs
+++ b/embassy-stm32/src/lptim/mod.rs
@@ -10,6 +10,7 @@ use crate::rcc::RccPeripheral;
 mod channel;
 #[cfg(any(lptim_v2a, lptim_v2b))]
 pub use channel::Channel;
+use embassy_hal_internal::PeripheralType;
 
 pin_trait!(OutputPin, BasicInstance);
 pin_trait!(Channel1Pin, BasicInstance);
@@ -22,7 +23,7 @@ pub(crate) trait SealedBasicInstance: RccPeripheral {}
 
 /// LPTIM basic instance trait.
 #[allow(private_bounds)]
-pub trait BasicInstance: SealedBasicInstance + 'static {}
+pub trait BasicInstance: PeripheralType + SealedBasicInstance + 'static {}
 
 /// LPTIM instance trait.
 #[allow(private_bounds)]
diff --git a/embassy-stm32/src/lptim/pwm.rs b/embassy-stm32/src/lptim/pwm.rs
index 132f5815e..2f2d7ba01 100644
--- a/embassy-stm32/src/lptim/pwm.rs
+++ b/embassy-stm32/src/lptim/pwm.rs
@@ -2,7 +2,7 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 
 use super::timer::Timer;
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
@@ -14,7 +14,6 @@ use super::{BasicInstance, Instance};
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
-use crate::Peripheral;
 
 /// Output marker type.
 pub enum Output {}
@@ -27,7 +26,7 @@ pub enum Ch2 {}
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct PwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -48,8 +47,7 @@ macro_rules! channel_impl {
     ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
         impl<'d, T: BasicInstance> PwmPin<'d, T, $channel> {
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -58,16 +56,12 @@ macro_rules! channel_impl {
                     );
                 });
                 PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
-            pub fn $new_chx_with_config(
-                pin: impl Peripheral<P = impl $pin_trait<T>> + 'd,
-                pin_config: PwmPinConfig,
-            ) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -79,7 +73,7 @@ macro_rules! channel_impl {
                     );
                 });
                 PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -102,7 +96,7 @@ pub struct Pwm<'d, T: Instance> {
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
 impl<'d, T: Instance> Pwm<'d, T> {
     /// Create a new PWM driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd, _output_pin: PwmPin<'d, T, Output>, freq: Hertz) -> Self {
+    pub fn new(tim: Peri<'d, T>, _output_pin: PwmPin<'d, T, Output>, freq: Hertz) -> Self {
         Self::new_inner(tim, freq)
     }
 
@@ -128,7 +122,7 @@ impl<'d, T: Instance> Pwm<'d, T> {
 impl<'d, T: Instance> Pwm<'d, T> {
     /// Create a new PWM driver.
     pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
         _ch1_pin: Option<PwmPin<'d, T, Ch1>>,
         _ch2_pin: Option<PwmPin<'d, T, Ch2>>,
         freq: Hertz,
@@ -174,7 +168,7 @@ impl<'d, T: Instance> Pwm<'d, T> {
 }
 
 impl<'d, T: Instance> Pwm<'d, T> {
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
         this.inner.enable();
diff --git a/embassy-stm32/src/lptim/timer/mod.rs b/embassy-stm32/src/lptim/timer/mod.rs
index e62fcab49..a629be62b 100644
--- a/embassy-stm32/src/lptim/timer/mod.rs
+++ b/embassy-stm32/src/lptim/timer/mod.rs
@@ -1,7 +1,7 @@
 //! Low-level timer driver.
 mod prescaler;
 
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 
 #[cfg(any(lptim_v2a, lptim_v2b))]
 use super::channel::Channel;
@@ -17,14 +17,12 @@ use crate::time::Hertz;
 
 /// Low-level timer driver.
 pub struct Timer<'d, T: Instance> {
-    _tim: PeripheralRef<'d, T>,
+    _tim: Peri<'d, T>,
 }
 
 impl<'d, T: Instance> Timer<'d, T> {
     /// Create a new timer driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(tim);
-
+    pub fn new(tim: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         Self { _tim: tim }
diff --git a/embassy-stm32/src/ltdc.rs b/embassy-stm32/src/ltdc.rs
index 16210b7dc..0f6ef569c 100644
--- a/embassy-stm32/src/ltdc.rs
+++ b/embassy-stm32/src/ltdc.rs
@@ -6,7 +6,7 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use stm32_metapac::ltdc::regs::Dccr;
 use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
@@ -14,7 +14,7 @@ use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
-use crate::{peripherals, rcc, Peripheral};
+use crate::{peripherals, rcc, Peri};
 
 static LTDC_WAKER: AtomicWaker = AtomicWaker::new();
 
@@ -83,7 +83,7 @@ pub enum PolarityActive {
 
 /// LTDC driver.
 pub struct Ltdc<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
 }
 
 /// LTDC interrupt handler.
@@ -178,47 +178,45 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 impl<'d, T: Instance> Ltdc<'d, T> {
     // Create a new LTDC driver without specifying color and control pins. This is typically used if you want to drive a display though a DsiHost
     /// Note: Full-Duplex modes are not supported at this time
-    pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(peri: Peri<'d, T>) -> Self {
         Self::setup_clocks();
-        into_ref!(peri);
         Self { _peri: peri }
     }
 
     /// Create a new LTDC driver. 8 pins per color channel for blue, green and red
     #[allow(clippy::too_many_arguments)]
     pub fn new_with_pins(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl ClkPin<T>> + 'd,
-        hsync: impl Peripheral<P = impl HsyncPin<T>> + 'd,
-        vsync: impl Peripheral<P = impl VsyncPin<T>> + 'd,
-        b0: impl Peripheral<P = impl B0Pin<T>> + 'd,
-        b1: impl Peripheral<P = impl B1Pin<T>> + 'd,
-        b2: impl Peripheral<P = impl B2Pin<T>> + 'd,
-        b3: impl Peripheral<P = impl B3Pin<T>> + 'd,
-        b4: impl Peripheral<P = impl B4Pin<T>> + 'd,
-        b5: impl Peripheral<P = impl B5Pin<T>> + 'd,
-        b6: impl Peripheral<P = impl B6Pin<T>> + 'd,
-        b7: impl Peripheral<P = impl B7Pin<T>> + 'd,
-        g0: impl Peripheral<P = impl G0Pin<T>> + 'd,
-        g1: impl Peripheral<P = impl G1Pin<T>> + 'd,
-        g2: impl Peripheral<P = impl G2Pin<T>> + 'd,
-        g3: impl Peripheral<P = impl G3Pin<T>> + 'd,
-        g4: impl Peripheral<P = impl G4Pin<T>> + 'd,
-        g5: impl Peripheral<P = impl G5Pin<T>> + 'd,
-        g6: impl Peripheral<P = impl G6Pin<T>> + 'd,
-        g7: impl Peripheral<P = impl G7Pin<T>> + 'd,
-        r0: impl Peripheral<P = impl R0Pin<T>> + 'd,
-        r1: impl Peripheral<P = impl R1Pin<T>> + 'd,
-        r2: impl Peripheral<P = impl R2Pin<T>> + 'd,
-        r3: impl Peripheral<P = impl R3Pin<T>> + 'd,
-        r4: impl Peripheral<P = impl R4Pin<T>> + 'd,
-        r5: impl Peripheral<P = impl R5Pin<T>> + 'd,
-        r6: impl Peripheral<P = impl R6Pin<T>> + 'd,
-        r7: impl Peripheral<P = impl R7Pin<T>> + 'd,
+        clk: Peri<'d, impl ClkPin<T>>,
+        hsync: Peri<'d, impl HsyncPin<T>>,
+        vsync: Peri<'d, impl VsyncPin<T>>,
+        b0: Peri<'d, impl B0Pin<T>>,
+        b1: Peri<'d, impl B1Pin<T>>,
+        b2: Peri<'d, impl B2Pin<T>>,
+        b3: Peri<'d, impl B3Pin<T>>,
+        b4: Peri<'d, impl B4Pin<T>>,
+        b5: Peri<'d, impl B5Pin<T>>,
+        b6: Peri<'d, impl B6Pin<T>>,
+        b7: Peri<'d, impl B7Pin<T>>,
+        g0: Peri<'d, impl G0Pin<T>>,
+        g1: Peri<'d, impl G1Pin<T>>,
+        g2: Peri<'d, impl G2Pin<T>>,
+        g3: Peri<'d, impl G3Pin<T>>,
+        g4: Peri<'d, impl G4Pin<T>>,
+        g5: Peri<'d, impl G5Pin<T>>,
+        g6: Peri<'d, impl G6Pin<T>>,
+        g7: Peri<'d, impl G7Pin<T>>,
+        r0: Peri<'d, impl R0Pin<T>>,
+        r1: Peri<'d, impl R1Pin<T>>,
+        r2: Peri<'d, impl R2Pin<T>>,
+        r3: Peri<'d, impl R3Pin<T>>,
+        r4: Peri<'d, impl R4Pin<T>>,
+        r5: Peri<'d, impl R5Pin<T>>,
+        r6: Peri<'d, impl R6Pin<T>>,
+        r7: Peri<'d, impl R7Pin<T>>,
     ) -> Self {
         Self::setup_clocks();
-        into_ref!(peri);
         new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         new_pin!(hsync, AfType::output(OutputType::PushPull, Speed::VeryHigh));
         new_pin!(vsync, AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -529,7 +527,7 @@ trait SealedInstance: crate::rcc::SealedRccPeripheral {
 
 /// LTDC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
     /// Interrupt for this LTDC instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/macros.rs b/embassy-stm32/src/macros.rs
index 000773e2d..2c181a254 100644
--- a/embassy-stm32/src/macros.rs
+++ b/embassy-stm32/src/macros.rs
@@ -14,7 +14,7 @@ macro_rules! peri_trait {
 
         /// Peripheral instance trait.
         #[allow(private_bounds)]
-        pub trait Instance: crate::Peripheral<P = Self> + SealedInstance + crate::rcc::RccPeripheral {
+        pub trait Instance: SealedInstance + crate::PeripheralType  + crate::rcc::RccPeripheral {
             $($(
                 /// Interrupt for this peripheral.
                 type $irq: crate::interrupt::typelevel::Interrupt;
@@ -88,10 +88,10 @@ macro_rules! dma_trait_impl {
 #[allow(unused)]
 macro_rules! new_dma_nonopt {
     ($name:ident) => {{
-        let dma = $name.into_ref();
+        let dma = $name;
         let request = dma.request();
         crate::dma::ChannelAndRequest {
-            channel: dma.map_into(),
+            channel: dma.into(),
             request,
         }
     }};
@@ -99,10 +99,10 @@ macro_rules! new_dma_nonopt {
 
 macro_rules! new_dma {
     ($name:ident) => {{
-        let dma = $name.into_ref();
+        let dma = $name;
         let request = dma.request();
         Some(crate::dma::ChannelAndRequest {
-            channel: dma.map_into(),
+            channel: dma.into(),
             request,
         })
     }};
@@ -110,8 +110,8 @@ macro_rules! new_dma {
 
 macro_rules! new_pin {
     ($name:ident, $af_type:expr) => {{
-        let pin = $name.into_ref();
+        let pin = $name;
         pin.set_as_af(pin.af_num(), $af_type);
-        Some(pin.map_into())
+        Some(pin.into())
     }};
 }
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index c7610f4b5..a81493c1b 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -1,10 +1,10 @@
 //! Operational Amplifier (OPAMP)
 #![macro_use]
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 
 use crate::pac::opamp::vals::*;
-use crate::Peripheral;
+use crate::Peri;
 
 /// Gain
 #[allow(missing_docs)]
@@ -52,16 +52,14 @@ pub struct OpAmpInternalOutput<'d, T: Instance> {
 
 /// OpAmp driver.
 pub struct OpAmp<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
 }
 
 impl<'d, T: Instance> OpAmp<'d, T> {
     /// Create a new driver instance.
     ///
     /// Does not enable the opamp, but does set the speed mode on some families.
-    pub fn new(opamp: impl Peripheral<P = T> + 'd, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
-        into_ref!(opamp);
-
+    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
         #[cfg(opamp_g4)]
         T::regs().csr().modify(|w| {
             w.set_opahsm(speed.into());
@@ -82,12 +80,10 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// [`OpAmpOutput`] is dropped.
     pub fn buffer_ext(
         &mut self,
-        in_pin: impl Peripheral<P = impl NonInvertingPin<T> + crate::gpio::Pin>,
-        out_pin: impl Peripheral<P = impl OutputPin<T> + crate::gpio::Pin>,
+        in_pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
+        out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>,
         gain: OpAmpGain,
     ) -> OpAmpOutput<'_, T> {
-        into_ref!(in_pin);
-        into_ref!(out_pin);
         in_pin.set_as_analog();
         out_pin.set_as_analog();
 
@@ -119,11 +115,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     /// directly used as an ADC input. The opamp will be disabled when the
     /// [`OpAmpOutput`] is dropped.
     #[cfg(opamp_g4)]
-    pub fn buffer_dac(
-        &mut self,
-        out_pin: impl Peripheral<P = impl OutputPin<T> + crate::gpio::Pin>,
-    ) -> OpAmpOutput<'_, T> {
-        into_ref!(out_pin);
+    pub fn buffer_dac(&mut self, out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>) -> OpAmpOutput<'_, T> {
         out_pin.set_as_analog();
 
         T::regs().csr().modify(|w| {
@@ -149,10 +141,9 @@ impl<'d, T: Instance> OpAmp<'d, T> {
     #[cfg(opamp_g4)]
     pub fn buffer_int(
         &mut self,
-        pin: impl Peripheral<P = impl NonInvertingPin<T> + crate::gpio::Pin>,
+        pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
         gain: OpAmpGain,
     ) -> OpAmpInternalOutput<'_, T> {
-        into_ref!(pin);
         pin.set_as_analog();
 
         // PGA_GAIN value may have different meaning in different MCU serials, use with caution.
@@ -211,7 +202,7 @@ pub(crate) trait SealedOutputPin<T: Instance> {}
 
 /// Opamp instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 /// Non-inverting pin trait.
 #[allow(private_bounds)]
 pub trait NonInvertingPin<T: Instance>: SealedNonInvertingPin<T> {}
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index 5dff3c4c3..74edfd5e4 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -8,7 +8,7 @@ pub mod enums;
 use core::marker::PhantomData;
 
 use embassy_embedded_hal::{GetConfig, SetConfig};
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 use stm32_metapac::octospi::vals::{PhaseMode, SizeInBits};
 
@@ -19,7 +19,7 @@ use crate::pac::octospi::{vals, Octospi as Regs};
 #[cfg(octospim_v1)]
 use crate::pac::octospim::Octospim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 /// OPSI driver config.
 #[derive(Clone, Copy)]
@@ -160,18 +160,18 @@ pub enum OspiError {
 
 /// OSPI driver.
 pub struct Ospi<'d, T: Instance, M: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
-    d0: Option<PeripheralRef<'d, AnyPin>>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
-    d4: Option<PeripheralRef<'d, AnyPin>>,
-    d5: Option<PeripheralRef<'d, AnyPin>>,
-    d6: Option<PeripheralRef<'d, AnyPin>>,
-    d7: Option<PeripheralRef<'d, AnyPin>>,
-    nss: Option<PeripheralRef<'d, AnyPin>>,
-    dqs: Option<PeripheralRef<'d, AnyPin>>,
+    _peri: Peri<'d, T>,
+    sck: Option<Peri<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
+    dqs: Option<Peri<'d, AnyPin>>,
     dma: Option<ChannelAndRequest<'d>>,
     _phantom: PhantomData<M>,
     config: Config,
@@ -245,25 +245,23 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
     }
 
     fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: Option<PeripheralRef<'d, AnyPin>>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
-        d4: Option<PeripheralRef<'d, AnyPin>>,
-        d5: Option<PeripheralRef<'d, AnyPin>>,
-        d6: Option<PeripheralRef<'d, AnyPin>>,
-        d7: Option<PeripheralRef<'d, AnyPin>>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
-        nss: Option<PeripheralRef<'d, AnyPin>>,
-        dqs: Option<PeripheralRef<'d, AnyPin>>,
+        peri: Peri<'d, T>,
+        d0: Option<Peri<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
+        dqs: Option<Peri<'d, AnyPin>>,
         dma: Option<ChannelAndRequest<'d>>,
         config: Config,
         width: OspiWidth,
         dual_quad: bool,
     ) -> Self {
-        into_ref!(peri);
-
         #[cfg(octospim_v1)]
         {
             // RCC for octospim should be enabled before writing register
@@ -685,11 +683,11 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
 impl<'d, T: Instance> Ospi<'d, T, Blocking> {
     /// Create new blocking OSPI driver for a single spi external chip
     pub fn new_blocking_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -717,11 +715,11 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 
     /// Create new blocking OSPI driver for a dualspi external chip
     pub fn new_blocking_dualspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -749,13 +747,13 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 
     /// Create new blocking OSPI driver for a quadspi external chip
     pub fn new_blocking_quadspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -783,17 +781,17 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 
     /// Create new blocking OSPI driver for two quadspi external chips
     pub fn new_blocking_dualquadspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -821,17 +819,17 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 
     /// Create new blocking OSPI driver for octospi external chips
     pub fn new_blocking_octospi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -861,12 +859,12 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 impl<'d, T: Instance> Ospi<'d, T, Async> {
     /// Create new blocking OSPI driver for a single spi external chip
     pub fn new_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -894,12 +892,12 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
 
     /// Create new blocking OSPI driver for a dualspi external chip
     pub fn new_dualspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -927,14 +925,14 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
 
     /// Create new blocking OSPI driver for a quadspi external chip
     pub fn new_quadspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -962,18 +960,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
 
     /// Create new blocking OSPI driver for two quadspi external chips
     pub fn new_dualquadspi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -1001,18 +999,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
 
     /// Create new blocking OSPI driver for octospi external chips
     pub fn new_octospi(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl OctoDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -1221,12 +1219,12 @@ pub(crate) trait SealedInstance {
 /// OSPI instance trait.
 #[cfg(octospim_v1)]
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral + SealedOctospimInstance {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + SealedOctospimInstance {}
 
 /// OSPI instance trait.
 #[cfg(not(octospim_v1))]
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 
 pin_trait!(SckPin, Instance);
 pin_trait!(NckPin, Instance);
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 411e533c9..0df057c53 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -6,7 +6,7 @@ pub mod enums;
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use enums::*;
 
 use crate::dma::ChannelAndRequest;
@@ -14,7 +14,7 @@ use crate::gpio::{AfType, AnyPin, OutputType, Pull, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::quadspi::Quadspi as Regs;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 /// QSPI transfer configuration.
 pub struct TransferConfig {
@@ -75,13 +75,13 @@ impl Default for Config {
 /// QSPI driver.
 #[allow(dead_code)]
 pub struct Qspi<'d, T: Instance, M: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
-    d0: Option<PeripheralRef<'d, AnyPin>>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
-    nss: Option<PeripheralRef<'d, AnyPin>>,
+    _peri: Peri<'d, T>,
+    sck: Option<Peri<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
     dma: Option<ChannelAndRequest<'d>>,
     _phantom: PhantomData<M>,
     config: Config,
@@ -89,19 +89,17 @@ pub struct Qspi<'d, T: Instance, M: PeriMode> {
 
 impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
     fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: Option<PeripheralRef<'d, AnyPin>>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
-        nss: Option<PeripheralRef<'d, AnyPin>>,
+        peri: Peri<'d, T>,
+        d0: Option<Peri<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
         dma: Option<ChannelAndRequest<'d>>,
         config: Config,
         fsel: FlashSelection,
     ) -> Self {
-        into_ref!(peri);
-
         rcc::enable_and_reset::<T>();
 
         while T::REGS.sr().read().busy() {}
@@ -272,13 +270,13 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
 impl<'d, T: Instance> Qspi<'d, T, Blocking> {
     /// Create a new QSPI driver for bank 1, in blocking mode.
     pub fn new_blocking_bank1(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        d0: Peri<'d, impl BK1D0Pin<T>>,
+        d1: Peri<'d, impl BK1D1Pin<T>>,
+        d2: Peri<'d, impl BK1D2Pin<T>>,
+        d3: Peri<'d, impl BK1D3Pin<T>>,
+        sck: Peri<'d, impl SckPin<T>>,
+        nss: Peri<'d, impl BK1NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -300,13 +298,13 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
 
     /// Create a new QSPI driver for bank 2, in blocking mode.
     pub fn new_blocking_bank2(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        d0: Peri<'d, impl BK2D0Pin<T>>,
+        d1: Peri<'d, impl BK2D1Pin<T>>,
+        d2: Peri<'d, impl BK2D2Pin<T>>,
+        d3: Peri<'d, impl BK2D3Pin<T>>,
+        sck: Peri<'d, impl SckPin<T>>,
+        nss: Peri<'d, impl BK2NSSPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -330,14 +328,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
 impl<'d, T: Instance> Qspi<'d, T, Async> {
     /// Create a new QSPI driver for bank 1.
     pub fn new_bank1(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        d0: Peri<'d, impl BK1D0Pin<T>>,
+        d1: Peri<'d, impl BK1D1Pin<T>>,
+        d2: Peri<'d, impl BK1D2Pin<T>>,
+        d3: Peri<'d, impl BK1D3Pin<T>>,
+        sck: Peri<'d, impl SckPin<T>>,
+        nss: Peri<'d, impl BK1NSSPin<T>>,
+        dma: Peri<'d, impl QuadDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -359,14 +357,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
 
     /// Create a new QSPI driver for bank 2.
     pub fn new_bank2(
-        peri: impl Peripheral<P = T> + 'd,
-        d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
-        dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        d0: Peri<'d, impl BK2D0Pin<T>>,
+        d1: Peri<'d, impl BK2D1Pin<T>>,
+        d2: Peri<'d, impl BK2D2Pin<T>>,
+        d3: Peri<'d, impl BK2D3Pin<T>>,
+        sck: Peri<'d, impl SckPin<T>>,
+        nss: Peri<'d, impl BK2NSSPin<T>>,
+        dma: Peri<'d, impl QuadDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -465,7 +463,7 @@ trait SealedInstance {
 
 /// QSPI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 
 pin_trait!(SckPin, Instance);
 pin_trait!(BK1D0Pin, Instance);
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index d1ce14c86..c50e071fb 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -1,6 +1,6 @@
 use core::marker::PhantomData;
 
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Speed};
 #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
@@ -32,7 +32,7 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::pac::RCC;
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 #[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -43,7 +43,7 @@ pub enum McoPrescaler {
 pub(crate) trait SealedMcoInstance {}
 
 #[allow(private_bounds)]
-pub trait McoInstance: SealedMcoInstance + 'static {
+pub trait McoInstance: PeripheralType + SealedMcoInstance + 'static {
     type Source;
 
     #[doc(hidden)]
@@ -91,14 +91,7 @@ pub struct Mco<'d, T: McoInstance> {
 
 impl<'d, T: McoInstance> Mco<'d, T> {
     /// Create a new MCO instance.
-    pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl McoPin<T>> + 'd,
-        source: T::Source,
-        prescaler: McoPrescaler,
-    ) -> Self {
-        into_ref!(pin);
-
+    pub fn new(_peri: Peri<'d, T>, pin: Peri<'d, impl McoPin<T>>, source: T::Source, prescaler: McoPrescaler) -> Self {
         critical_section::with(|_| unsafe {
             T::_apply_clock_settings(source, prescaler);
             pin.set_as_af(pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index b96200e5e..250a08a39 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -5,12 +5,12 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use rand_core::{CryptoRng, RngCore};
 
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::{interrupt, pac, peripherals, rcc, Peri};
 
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
 
@@ -43,17 +43,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 
 /// RNG driver.
 pub struct Rng<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
 }
 
 impl<'d, T: Instance> Rng<'d, T> {
     /// Create a new RNG driver.
     pub fn new(
-        inner: impl Peripheral<P = T> + 'd,
+        inner: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
     ) -> Self {
         rcc::enable_and_reset::<T>();
-        into_ref!(inner);
         let mut random = Self { _inner: inner };
         random.reset();
 
@@ -228,7 +227,7 @@ trait SealedInstance {
 
 /// RNG instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
     /// Interrupt for this RNG instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index c2919e2bd..b16c6fdca 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -29,9 +29,9 @@ use crate::time::Hertz;
 mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
-use embassy_hal_internal::Peripheral;
 
 use crate::peripherals::RTC;
+use crate::Peri;
 
 /// Errors that can occur on methods on [RtcClock]
 #[non_exhaustive]
@@ -151,7 +151,7 @@ pub enum RtcCalibrationCyclePeriod {
 
 impl Rtc {
     /// Create a new RTC instance.
-    pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
+    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> Self {
         #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
         crate::rcc::enable_and_reset::<RTC>();
 
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index 39ed44712..0c9c27797 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -4,7 +4,7 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 
 pub use crate::dma::word;
 #[cfg(not(gpdma))]
@@ -12,7 +12,7 @@ use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptio
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::pac::sai::{vals, Sai as Regs};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 
 /// SAI error
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -679,7 +679,7 @@ fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AfType, AfType) {
 
 #[cfg(not(gpdma))]
 fn get_ring_buffer<'d, T: Instance, W: word::Word>(
-    dma: impl Peripheral<P = impl Channel> + 'd,
+    dma: Peri<'d, impl Channel>,
     dma_buf: &'d mut [W],
     request: Request,
     sub_block: WhichSubBlock,
@@ -718,16 +718,15 @@ fn update_synchronous_config(config: &mut Config) {
 }
 
 /// SAI subblock instance.
-pub struct SubBlock<'d, T, S: SubBlockInstance> {
-    peri: PeripheralRef<'d, T>,
+pub struct SubBlock<'d, T: Instance, S: SubBlockInstance> {
+    peri: Peri<'d, T>,
     _phantom: PhantomData<S>,
 }
 
 /// Split the main SAIx peripheral into the two subblocks.
 ///
 /// You can then create a [`Sai`] driver for each each half.
-pub fn split_subblocks<'d, T: Instance>(peri: impl Peripheral<P = T> + 'd) -> (SubBlock<'d, T, A>, SubBlock<'d, T, B>) {
-    into_ref!(peri);
+pub fn split_subblocks<'d, T: Instance>(peri: Peri<'d, T>) -> (SubBlock<'d, T, A>, SubBlock<'d, T, B>) {
     rcc::enable_and_reset::<T>();
 
     (
@@ -744,11 +743,11 @@ pub fn split_subblocks<'d, T: Instance>(peri: impl Peripheral<P = T> + 'd) -> (S
 
 /// SAI sub-block driver.
 pub struct Sai<'d, T: Instance, W: word::Word> {
-    _peri: PeripheralRef<'d, T>,
-    sd: Option<PeripheralRef<'d, AnyPin>>,
-    fs: Option<PeripheralRef<'d, AnyPin>>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
-    mclk: Option<PeripheralRef<'d, AnyPin>>,
+    _peri: Peri<'d, T>,
+    sd: Option<Peri<'d, AnyPin>>,
+    fs: Option<Peri<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
+    mclk: Option<Peri<'d, AnyPin>>,
     #[cfg(gpdma)]
     ring_buffer: PhantomData<W>,
     #[cfg(not(gpdma))]
@@ -763,16 +762,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     /// You can obtain the [`SubBlock`] with [`split_subblocks`].
     pub fn new_asynchronous_with_mclk<S: SubBlockInstance>(
         peri: SubBlock<'d, T, S>,
-        sck: impl Peripheral<P = impl SckPin<T, S>> + 'd,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
-        fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
-        mclk: impl Peripheral<P = impl MclkPin<T, S>> + 'd,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        sck: Peri<'d, impl SckPin<T, S>>,
+        sd: Peri<'d, impl SdPin<T, S>>,
+        fs: Peri<'d, impl FsPin<T, S>>,
+        mclk: Peri<'d, impl MclkPin<T, S>>,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
         dma_buf: &'d mut [W],
         mut config: Config,
     ) -> Self {
-        into_ref!(mclk);
-
         let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
         mclk.set_as_af(mclk.af_num(), ck_af_type);
 
@@ -788,15 +785,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     /// You can obtain the [`SubBlock`] with [`split_subblocks`].
     pub fn new_asynchronous<S: SubBlockInstance>(
         peri: SubBlock<'d, T, S>,
-        sck: impl Peripheral<P = impl SckPin<T, S>> + 'd,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
-        fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        sck: Peri<'d, impl SckPin<T, S>>,
+        sd: Peri<'d, impl SdPin<T, S>>,
+        fs: Peri<'d, impl FsPin<T, S>>,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
         dma_buf: &'d mut [W],
         config: Config,
     ) -> Self {
         let peri = peri.peri;
-        into_ref!(peri, dma, sck, sd, fs);
 
         let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
         sd.set_as_af(sd.af_num(), sd_af_type);
@@ -809,10 +805,10 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
         Self::new_inner(
             peri,
             sub_block,
-            Some(sck.map_into()),
+            Some(sck.into()),
             None,
-            Some(sd.map_into()),
-            Some(fs.map_into()),
+            Some(sd.into()),
+            Some(fs.into()),
             get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
             config,
         )
@@ -823,15 +819,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     /// You can obtain the [`SubBlock`] with [`split_subblocks`].
     pub fn new_synchronous<S: SubBlockInstance>(
         peri: SubBlock<'d, T, S>,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        sd: Peri<'d, impl SdPin<T, S>>,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
         dma_buf: &'d mut [W],
         mut config: Config,
     ) -> Self {
         update_synchronous_config(&mut config);
 
         let peri = peri.peri;
-        into_ref!(dma, peri, sd);
 
         let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
         sd.set_as_af(sd.af_num(), sd_af_type);
@@ -844,7 +839,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             sub_block,
             None,
             None,
-            Some(sd.map_into()),
+            Some(sd.into()),
             None,
             get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
             config,
@@ -852,12 +847,12 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
     }
 
     fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         sub_block: WhichSubBlock,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
-        mclk: Option<PeripheralRef<'d, AnyPin>>,
-        sd: Option<PeripheralRef<'d, AnyPin>>,
-        fs: Option<PeripheralRef<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
+        mclk: Option<Peri<'d, AnyPin>>,
+        sd: Option<Peri<'d, AnyPin>>,
+        fs: Option<Peri<'d, AnyPin>>,
         ring_buffer: RingBuffer<'d, W>,
         config: Config,
     ) -> Self {
@@ -947,7 +942,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
         }
 
         Self {
-            _peri: peri.into_ref(),
+            _peri: peri,
             sub_block,
             sck,
             mclk,
@@ -1106,7 +1101,7 @@ impl SubBlockInstance for B {}
 
 /// SAI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 
 pin_trait!(SckPin, Instance, SubBlockInstance);
 pin_trait!(FsPin, Instance, SubBlockInstance);
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index d8671caf7..8f3c45f50 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -8,7 +8,7 @@ use core::ops::{Deref, DerefMut};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID, CSD, OCR, SCR};
 
@@ -21,7 +21,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::pac::sdmmc::Sdmmc as RegBlock;
 use crate::rcc::{self, RccPeripheral};
 use crate::time::Hertz;
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -303,16 +303,16 @@ impl Default for Config {
 
 /// Sdmmc device
 pub struct Sdmmc<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
     #[cfg(sdmmc_v1)]
     dma: ChannelAndRequest<'d>,
 
-    clk: PeripheralRef<'d, AnyPin>,
-    cmd: PeripheralRef<'d, AnyPin>,
-    d0: PeripheralRef<'d, AnyPin>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
+    clk: Peri<'d, AnyPin>,
+    cmd: Peri<'d, AnyPin>,
+    d0: Peri<'d, AnyPin>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
 
     config: Config,
     /// Current clock to card
@@ -338,16 +338,14 @@ const DATA_AF: AfType = CMD_AF;
 impl<'d, T: Instance> Sdmmc<'d, T> {
     /// Create a new SDMMC driver, with 1 data lane.
     pub fn new_1bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dma: impl Peripheral<P = impl SdmmcDma<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        dma: Peri<'d, impl SdmmcDma<T>>,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(dma, clk, cmd, d0);
-
         critical_section::with(|_| {
             clk.set_as_af(clk.af_num(), CLK_AF);
             cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -357,9 +355,9 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::new_inner(
             sdmmc,
             new_dma_nonopt!(dma),
-            clk.map_into(),
-            cmd.map_into(),
-            d0.map_into(),
+            clk.into(),
+            cmd.into(),
+            d0.into(),
             None,
             None,
             None,
@@ -369,19 +367,17 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Create a new SDMMC driver, with 4 data lanes.
     pub fn new_4bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dma: impl Peripheral<P = impl SdmmcDma<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        dma: Peri<'d, impl SdmmcDma<T>>,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(clk, cmd, d0, d1, d2, d3);
-
         critical_section::with(|_| {
             clk.set_as_af(clk.af_num(), CLK_AF);
             cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -394,12 +390,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
         Self::new_inner(
             sdmmc,
             new_dma_nonopt!(dma),
-            clk.map_into(),
-            cmd.map_into(),
-            d0.map_into(),
-            Some(d1.map_into()),
-            Some(d2.map_into()),
-            Some(d3.map_into()),
+            clk.into(),
+            cmd.into(),
+            d0.into(),
+            Some(d1.into()),
+            Some(d2.into()),
+            Some(d3.into()),
             config,
         )
     }
@@ -409,47 +405,34 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 impl<'d, T: Instance> Sdmmc<'d, T> {
     /// Create a new SDMMC driver, with 1 data lane.
     pub fn new_1bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(clk, cmd, d0);
-
         critical_section::with(|_| {
             clk.set_as_af(clk.af_num(), CLK_AF);
             cmd.set_as_af(cmd.af_num(), CMD_AF);
             d0.set_as_af(d0.af_num(), DATA_AF);
         });
 
-        Self::new_inner(
-            sdmmc,
-            clk.map_into(),
-            cmd.map_into(),
-            d0.map_into(),
-            None,
-            None,
-            None,
-            config,
-        )
+        Self::new_inner(sdmmc, clk.into(), cmd.into(), d0.into(), None, None, None, config)
     }
 
     /// Create a new SDMMC driver, with 4 data lanes.
     pub fn new_4bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(clk, cmd, d0, d1, d2, d3);
-
         critical_section::with(|_| {
             clk.set_as_af(clk.af_num(), CLK_AF);
             cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -461,12 +444,12 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
         Self::new_inner(
             sdmmc,
-            clk.map_into(),
-            cmd.map_into(),
-            d0.map_into(),
-            Some(d1.map_into()),
-            Some(d2.map_into()),
-            Some(d3.map_into()),
+            clk.into(),
+            cmd.into(),
+            d0.into(),
+            Some(d1.into()),
+            Some(d2.into()),
+            Some(d3.into()),
             config,
         )
     }
@@ -474,18 +457,16 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
 impl<'d, T: Instance> Sdmmc<'d, T> {
     fn new_inner(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
         #[cfg(sdmmc_v1)] dma: ChannelAndRequest<'d>,
-        clk: PeripheralRef<'d, AnyPin>,
-        cmd: PeripheralRef<'d, AnyPin>,
-        d0: PeripheralRef<'d, AnyPin>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
+        clk: Peri<'d, AnyPin>,
+        cmd: Peri<'d, AnyPin>,
+        d0: Peri<'d, AnyPin>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
         config: Config,
     ) -> Self {
-        into_ref!(sdmmc);
-
         rcc::enable_and_reset::<T>();
 
         T::Interrupt::unpend();
@@ -1478,7 +1459,7 @@ trait SealedInstance {
 
 /// SDMMC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
     /// Interrupt for this instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/spdifrx/mod.rs b/embassy-stm32/src/spdifrx/mod.rs
index a205780ad..08dba04fe 100644
--- a/embassy-stm32/src/spdifrx/mod.rs
+++ b/embassy-stm32/src/spdifrx/mod.rs
@@ -4,7 +4,6 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::ringbuffer::Error as RingbufferError;
@@ -16,7 +15,7 @@ use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::spdifrx::Spdifrx as Regs;
 use crate::rcc::{RccInfo, SealedRccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals, Peri};
 
 /// Possible S/PDIF preamble types.
 #[allow(dead_code)]
@@ -36,10 +35,10 @@ enum PreambleType {
 
 macro_rules! new_spdifrx_pin {
     ($name:ident, $af_type:expr) => {{
-        let pin = $name.into_ref();
+        let pin = $name;
         let input_sel = pin.input_sel();
         pin.set_as_af(pin.af_num(), $af_type);
-        (Some(pin.map_into()), input_sel)
+        (Some(pin.into()), input_sel)
     }};
 }
 
@@ -61,8 +60,8 @@ macro_rules! impl_spdifrx_pin {
 /// Data is read by DMAs and stored in a ring buffer.
 #[cfg(not(gpdma))]
 pub struct Spdifrx<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
-    spdifrx_in: Option<PeripheralRef<'d, AnyPin>>,
+    _peri: Peri<'d, T>,
+    spdifrx_in: Option<Peri<'d, AnyPin>>,
     data_ring_buffer: ReadableRingBuffer<'d, u32>,
 }
 
@@ -131,18 +130,16 @@ impl<'d, T: Instance> Spdifrx<'d, T> {
 
     /// Create a new `Spdifrx` instance.
     pub fn new(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::GlobalInterrupt, GlobalInterruptHandler<T>> + 'd,
         config: Config,
-        spdifrx_in: impl Peripheral<P = impl InPin<T>> + 'd,
-        data_dma: impl Peripheral<P = impl Channel + Dma<T>> + 'd,
+        spdifrx_in: Peri<'d, impl InPin<T>>,
+        data_dma: Peri<'d, impl Channel + Dma<T>>,
         data_dma_buf: &'d mut [u32],
     ) -> Self {
         let (spdifrx_in, input_sel) = new_spdifrx_pin!(spdifrx_in, AfType::input(Pull::None));
         Self::setup(config, input_sel);
 
-        into_ref!(peri, data_dma);
-
         let regs = T::info().regs;
         let dr_request = data_dma.request();
         let dr_ring_buffer =
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index a43da1b5a..6578aa1aa 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -6,7 +6,6 @@ use core::ptr;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_futures::join::join;
-use embassy_hal_internal::PeripheralRef;
 pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 
 use crate::dma::{word, ChannelAndRequest};
@@ -15,7 +14,7 @@ use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::spi::{regs, vals, Spi as Regs};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 
 /// SPI error.
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -130,9 +129,9 @@ impl Config {
 pub struct Spi<'d, M: PeriMode> {
     pub(crate) info: &'static Info,
     kernel_clock: Hertz,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
-    mosi: Option<PeripheralRef<'d, AnyPin>>,
-    miso: Option<PeripheralRef<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
+    mosi: Option<Peri<'d, AnyPin>>,
+    miso: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
     _phantom: PhantomData<M>,
@@ -142,10 +141,10 @@ pub struct Spi<'d, M: PeriMode> {
 
 impl<'d, M: PeriMode> Spi<'d, M> {
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
-        mosi: Option<PeripheralRef<'d, AnyPin>>,
-        miso: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        sck: Option<Peri<'d, AnyPin>>,
+        mosi: Option<Peri<'d, AnyPin>>,
+        miso: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
@@ -465,10 +464,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {
 impl<'d> Spi<'d, Blocking> {
     /// Create a new blocking SPI driver.
     pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        mosi: Peri<'d, impl MosiPin<T>>,
+        miso: Peri<'d, impl MisoPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -484,9 +483,9 @@ impl<'d> Spi<'d, Blocking> {
 
     /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).
     pub fn new_blocking_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        miso: Peri<'d, impl MisoPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -502,9 +501,9 @@ impl<'d> Spi<'d, Blocking> {
 
     /// Create a new blocking SPI driver, in TX-only mode (only MOSI pin, no MISO).
     pub fn new_blocking_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        mosi: Peri<'d, impl MosiPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -522,8 +521,8 @@ impl<'d> Spi<'d, Blocking> {
     ///
     /// This can be useful for bit-banging non-SPI protocols.
     pub fn new_blocking_txonly_nosck<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        mosi: Peri<'d, impl MosiPin<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -541,12 +540,12 @@ impl<'d> Spi<'d, Blocking> {
 impl<'d> Spi<'d, Async> {
     /// Create a new SPI driver.
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        mosi: Peri<'d, impl MosiPin<T>>,
+        miso: Peri<'d, impl MisoPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -562,11 +561,11 @@ impl<'d> Spi<'d, Async> {
 
     /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).
     pub fn new_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
-        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        miso: Peri<'d, impl MisoPin<T>>,
+        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -585,10 +584,10 @@ impl<'d> Spi<'d, Async> {
 
     /// Create a new SPI driver, in TX-only mode (only MOSI pin, no MISO).
     pub fn new_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        mosi: Peri<'d, impl MosiPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -606,9 +605,9 @@ impl<'d> Spi<'d, Async> {
     ///
     /// This can be useful for bit-banging non-SPI protocols.
     pub fn new_txonly_nosck<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        mosi: Peri<'d, impl MosiPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Self {
         Self::new_inner(
@@ -625,9 +624,9 @@ impl<'d> Spi<'d, Async> {
     #[cfg(stm32wl)]
     /// Useful for on chip peripherals like SUBGHZ which are hardwired.
     pub fn new_subghz<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
     ) -> Self {
         // see RM0453 rev 1 section 7.2.13 page 291
         // The SUBGHZSPI_SCK frequency is obtained by PCLK3 divided by two.
@@ -644,7 +643,7 @@ impl<'d> Spi<'d, Async> {
 
     #[allow(dead_code)]
     pub(crate) fn new_internal<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 02c01e900..f543bafab 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,7 +2,6 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use stm32_metapac::timer::vals::Ckd;
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
@@ -14,13 +13,13 @@ use super::{
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::low_level::OutputCompareMode;
-use crate::Peripheral;
+use crate::Peri;
 
 /// Complementary PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -28,8 +27,7 @@ macro_rules! complementary_channel_impl {
     ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
         impl<'d, T: AdvancedInstance4Channel> ComplementaryPwmPin<'d, T, $channel> {
             #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -38,7 +36,7 @@ macro_rules! complementary_channel_impl {
                     );
                 });
                 ComplementaryPwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -60,7 +58,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     /// Create a new complementary PWM driver.
     #[allow(clippy::too_many_arguments)]
     pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
         _ch1: Option<PwmPin<'d, T, Ch1>>,
         _ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
         _ch2: Option<PwmPin<'d, T, Ch2>>,
@@ -75,7 +73,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         Self::new_inner(tim, freq, counting_mode)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
         this.inner.set_counting_mode(counting_mode);
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index b7c13343c..0450f14fa 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -5,8 +5,6 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
 use super::{
     CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin,
@@ -15,7 +13,7 @@ use super::{
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 
 /// Channel 1 marker type.
 pub enum Ch1 {}
@@ -30,7 +28,7 @@ pub enum Ch4 {}
 ///
 /// This wraps a pin to make it usable with capture.
 pub struct CapturePin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -38,11 +36,10 @@ macro_rules! channel_impl {
     ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
         impl<'d, T: GeneralInstance4Channel> CapturePin<'d, T, $channel> {
             #[doc = concat!("Create a new ", stringify!($channel), " capture pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, pull: Pull) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
                 pin.set_as_af(pin.af_num(), AfType::input(pull));
                 CapturePin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -63,7 +60,7 @@ pub struct InputCapture<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
     /// Create a new input capture driver.
     pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
         _ch1: Option<CapturePin<'d, T, Ch1>>,
         _ch2: Option<CapturePin<'d, T, Ch2>>,
         _ch3: Option<CapturePin<'d, T, Ch3>>,
@@ -75,7 +72,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
         Self::new_inner(tim, freq, counting_mode)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
         this.inner.set_counting_mode(counting_mode);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index 5b0c95109..8fc32c1f3 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -8,7 +8,7 @@
 
 use core::mem::ManuallyDrop;
 
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 // Re-export useful enums
 pub use stm32_metapac::timer::vals::{FilterValue, Sms as SlaveMode, Ts as TriggerSource};
 
@@ -181,7 +181,7 @@ impl From<OutputPolarity> for bool {
 
 /// Low-level timer driver.
 pub struct Timer<'d, T: CoreInstance> {
-    tim: PeripheralRef<'d, T>,
+    tim: Peri<'d, T>,
 }
 
 impl<'d, T: CoreInstance> Drop for Timer<'d, T> {
@@ -192,9 +192,7 @@ impl<'d, T: CoreInstance> Drop for Timer<'d, T> {
 
 impl<'d, T: CoreInstance> Timer<'d, T> {
     /// Create a new timer driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd) -> Self {
-        into_ref!(tim);
-
+    pub fn new(tim: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
         Self { tim }
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 97740c2ed..765a3d9fa 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -2,7 +2,7 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::Peripheral;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 
 #[cfg(not(stm32l0))]
@@ -66,7 +66,7 @@ impl State {
     }
 }
 
-trait SealedInstance: RccPeripheral + Peripheral<P = Self> {
+trait SealedInstance: RccPeripheral + PeripheralType {
     /// Async state for this timer
     fn state() -> &'static State;
 }
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index e3eb6042a..98b798634 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -1,12 +1,10 @@
 //! PWM Input driver.
 
-use embassy_hal_internal::into_ref;
-
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
 use super::{Channel, Channel1Pin, Channel2Pin, GeneralInstance4Channel};
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 
 /// PWM Input driver.
 pub struct PwmInput<'d, T: GeneralInstance4Channel> {
@@ -16,34 +14,20 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
     /// Create a new PWM input driver.
-    pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl Channel1Pin<T>> + 'd,
-        pull: Pull,
-        freq: Hertz,
-    ) -> Self {
-        into_ref!(pin);
-
+    pub fn new(tim: Peri<'d, T>, pin: Peri<'d, impl Channel1Pin<T>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
     }
 
     /// Create a new PWM input driver.
-    pub fn new_alt(
-        tim: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl Channel2Pin<T>> + 'd,
-        pull: Pull,
-        freq: Hertz,
-    ) -> Self {
-        into_ref!(pin);
-
+    pub fn new_alt(tim: Peri<'d, T>, pin: Peri<'d, impl Channel2Pin<T>>, pull: Pull, freq: Hertz) -> Self {
         pin.set_as_af(pin.af_num(), AfType::input(pull));
 
         Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, ch1: Channel, ch2: Channel) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, ch1: Channel, ch2: Channel) -> Self {
         let mut inner = Timer::new(tim);
 
         inner.set_counting_mode(CountingMode::EdgeAlignedUp);
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index fc5835414..bac290f28 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -2,13 +2,12 @@
 
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use stm32_metapac::timer::vals;
 
 use super::low_level::Timer;
 use super::{Channel1Pin, Channel2Pin, GeneralInstance4Channel};
 use crate::gpio::{AfType, AnyPin, Pull};
-use crate::Peripheral;
+use crate::Peri;
 
 /// Counting direction
 pub enum Direction {
@@ -25,7 +24,7 @@ pub enum Ch2 {}
 
 /// Wrapper for using a pin with QEI.
 pub struct QeiPin<'d, T, Channel> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, Channel)>,
 }
 
@@ -33,14 +32,13 @@ macro_rules! channel_impl {
     ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
         impl<'d, T: GeneralInstance4Channel> QeiPin<'d, T, $channel> {
             #[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
                 });
                 QeiPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -58,11 +56,11 @@ pub struct Qei<'d, T: GeneralInstance4Channel> {
 
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
     /// Create a new quadrature decoder driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
+    pub fn new(tim: Peri<'d, T>, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
         Self::new_inner(tim)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
+    fn new_inner(tim: Peri<'d, T>) -> Self {
         let inner = Timer::new(tim);
         let r = inner.regs_gp16();
 
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index c5a366cd5..54ab7d0d5 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -3,15 +3,13 @@
 use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
 use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 
 /// Channel 1 marker type.
 pub enum Ch1 {}
@@ -26,7 +24,7 @@ pub enum Ch4 {}
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct PwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     phantom: PhantomData<(T, C)>,
 }
 
@@ -47,24 +45,19 @@ macro_rules! channel_impl {
     ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
         impl<'d, T: GeneralInstance4Channel> PwmPin<'d, T, $channel> {
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
                 });
                 PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
 
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
-            pub fn $new_chx_with_config(
-                pin: impl Peripheral<P = impl $pin_trait<T>> + 'd,
-                pin_config: PwmPinConfig,
-            ) -> Self {
-                into_ref!(pin);
+            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
                 critical_section::with(|_| {
                     pin.set_low();
                     pin.set_as_af(
@@ -76,7 +69,7 @@ macro_rules! channel_impl {
                     );
                 });
                 PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     phantom: PhantomData,
                 }
             }
@@ -202,7 +195,7 @@ pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Create a new simple PWM driver.
     pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
         _ch1: Option<PwmPin<'d, T, Ch1>>,
         _ch2: Option<PwmPin<'d, T, Ch2>>,
         _ch3: Option<PwmPin<'d, T, Ch3>>,
@@ -213,7 +206,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         Self::new_inner(tim, freq, counting_mode)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
         let mut this = Self { inner: Timer::new(tim) };
 
         this.inner.set_counting_mode(counting_mode);
@@ -331,14 +324,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(
-        &mut self,
-        dma: impl Peripheral<P = impl super::UpDma<T>>,
-        channel: Channel,
-        duty: &[u16],
-    ) {
-        into_ref!(dma);
-
+    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
         #[allow(clippy::let_unit_value)] // eg. stm32f334
         let req = dma.request();
 
@@ -368,7 +354,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
             };
 
             Transfer::new_write(
-                &mut dma,
+                dma,
                 req,
                 duty,
                 self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
@@ -399,11 +385,9 @@ macro_rules! impl_waveform_chx {
     ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
         impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
             /// Generate a sequence of PWM waveform
-            pub async fn $fn_name(&mut self, dma: impl Peripheral<P = impl super::$dma_ch<T>>, duty: &[u16]) {
+            pub async fn $fn_name(&mut self, dma: Peri<'_, impl super::$dma_ch<T>>, duty: &[u16]) {
                 use crate::pac::timer::vals::Ccds;
 
-                into_ref!(dma);
-
                 #[allow(clippy::let_unit_value)] // eg. stm32f334
                 let req = dma.request();
 
@@ -443,7 +427,7 @@ macro_rules! impl_waveform_chx {
                     match self.inner.bits() {
                         TimerBits::Bits16 => {
                             Transfer::new_write(
-                                &mut dma,
+                                dma,
                                 req,
                                 duty,
                                 self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
@@ -458,7 +442,7 @@ macro_rules! impl_waveform_chx {
 
                             #[cfg(any(bdma, gpdma))]
                             Transfer::new_write(
-                                &mut dma,
+                                dma,
                                 req,
                                 duty,
                                 self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
diff --git a/embassy-stm32/src/tsc/mod.rs b/embassy-stm32/src/tsc/mod.rs
index 0d5c27465..9359d83e9 100644
--- a/embassy-stm32/src/tsc/mod.rs
+++ b/embassy-stm32/src/tsc/mod.rs
@@ -98,6 +98,7 @@ use core::marker::PhantomData;
 
 pub use acquisition_banks::*;
 pub use config::*;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 pub use errors::*;
 pub use io_pin::*;
@@ -106,7 +107,7 @@ pub use tsc::*;
 pub use types::*;
 
 use crate::rcc::RccPeripheral;
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals};
 
 #[cfg(tsc_v1)]
 const TSC_NUM_GROUPS: usize = 6;
@@ -142,7 +143,7 @@ pub(crate) trait SealedInstance {
 
 /// TSC instance trait
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {
     /// Interrupt for this TSC instance
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/tsc/pin_groups.rs b/embassy-stm32/src/tsc/pin_groups.rs
index 1f3aafa35..6f914a94e 100644
--- a/embassy-stm32/src/tsc/pin_groups.rs
+++ b/embassy-stm32/src/tsc/pin_groups.rs
@@ -1,13 +1,11 @@
 use core::marker::PhantomData;
 use core::ops::BitOr;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
-
 use super::errors::GroupError;
 use super::io_pin::*;
 use super::Instance;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
-use crate::Peripheral;
+use crate::Peri;
 
 /// Pin type definition to control IO parameters
 #[derive(PartialEq, Clone, Copy)]
@@ -23,7 +21,7 @@ pub enum PinType {
 /// Pin struct that maintains usage
 #[allow(missing_docs)]
 pub struct Pin<'d, T, Group> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
     role: PinType,
     tsc_io_pin: IOPin,
     phantom: PhantomData<(T, Group)>,
@@ -426,17 +424,13 @@ macro_rules! trait_to_io_pin {
 macro_rules! impl_set_io {
     ($method:ident, $group:ident, $trait:ident, $index:expr) => {
         #[doc = concat!("Create a new pin1 for ", stringify!($group), " TSC group instance.")]
-        pub fn $method<Role: pin_roles::Role>(
-            &mut self,
-            pin: impl Peripheral<P = impl $trait<T>> + 'd,
-        ) -> IOPinWithRole<$group, Role> {
-            into_ref!(pin);
+        pub fn $method<Role: pin_roles::Role>(&mut self, pin: Peri<'d, impl $trait<T>>) -> IOPinWithRole<$group, Role> {
             critical_section::with(|_| {
                 pin.set_low();
                 pin.set_as_af(pin.af_num(), AfType::output(Role::output_type(), Speed::VeryHigh));
                 let tsc_io_pin = trait_to_io_pin!($trait);
                 let new_pin = Pin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                     role: Role::pin_type(),
                     tsc_io_pin,
                     phantom: PhantomData,
diff --git a/embassy-stm32/src/tsc/tsc.rs b/embassy-stm32/src/tsc/tsc.rs
index 17d2da82f..e92479c26 100644
--- a/embassy-stm32/src/tsc/tsc.rs
+++ b/embassy-stm32/src/tsc/tsc.rs
@@ -3,7 +3,7 @@ use core::marker::PhantomData;
 use core::ops::BitOr;
 use core::task::Poll;
 
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 
 use super::acquisition_banks::*;
 use super::config::*;
@@ -14,7 +14,7 @@ use super::types::*;
 use super::{Instance, InterruptHandler, TSC_NUM_GROUPS};
 use crate::interrupt::typelevel::Interrupt;
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc};
 
 /// Internal structure holding masks for different types of TSC IOs.
 ///
@@ -31,7 +31,7 @@ struct IOMasks {
 
 /// TSC driver
 pub struct Tsc<'d, T: Instance, K: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
     _pin_groups: PinGroups<'d, T>,
     state: State,
     config: Config,
@@ -218,13 +218,7 @@ impl<'d, T: Instance, K: PeriMode> Tsc<'d, T, K> {
         groups
     }
 
-    fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
-        pin_groups: PinGroups<'d, T>,
-        config: Config,
-    ) -> Result<Self, GroupError> {
-        into_ref!(peri);
-
+    fn new_inner(peri: Peri<'d, T>, pin_groups: PinGroups<'d, T>, config: Config) -> Result<Self, GroupError> {
         pin_groups.check()?;
 
         let masks = IOMasks {
@@ -410,7 +404,7 @@ impl<'d, T: Instance, K: PeriMode> Drop for Tsc<'d, T, K> {
 impl<'d, T: Instance> Tsc<'d, T, Async> {
     /// Create a Tsc instance that can be awaited for completion
     pub fn new_async(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         pin_groups: PinGroups<'d, T>,
         config: Config,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
@@ -441,11 +435,7 @@ impl<'d, T: Instance> Tsc<'d, T, Async> {
 
 impl<'d, T: Instance> Tsc<'d, T, Blocking> {
     /// Create a Tsc instance that must be polled for completion
-    pub fn new_blocking(
-        peri: impl Peripheral<P = T> + 'd,
-        pin_groups: PinGroups<'d, T>,
-        config: Config,
-    ) -> Result<Self, GroupError> {
+    pub fn new_blocking(peri: Peri<'d, T>, pin_groups: PinGroups<'d, T>, config: Config) -> Result<Self, GroupError> {
         Self::new_inner(peri, pin_groups, config)
     }
 
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index c40ee8ad0..87693f148 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -20,15 +20,15 @@ use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::{ChannelAndRequest, TransferOptions};
-use crate::interrupt;
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
 pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, Rxordset, TypecVstateCc as CcVState};
 use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, Peri};
 
 pub(crate) fn init(
     _cs: critical_section::CriticalSection,
@@ -122,13 +122,12 @@ pub struct Ucpd<'d, T: Instance> {
 impl<'d, T: Instance> Ucpd<'d, T> {
     /// Creates a new UCPD driver instance.
     pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        cc1: impl Peripheral<P = impl Cc1Pin<T>> + 'd,
-        cc2: impl Peripheral<P = impl Cc2Pin<T>> + 'd,
+        cc1: Peri<'d, impl Cc1Pin<T>>,
+        cc2: Peri<'d, impl Cc2Pin<T>>,
         config: Config,
     ) -> Self {
-        into_ref!(cc1, cc2);
         cc1.set_as_analog();
         cc2.set_as_analog();
 
@@ -208,8 +207,8 @@ impl<'d, T: Instance> Ucpd<'d, T> {
     /// and a Power Delivery (PD) PHY with receiver and transmitter.
     pub fn split_pd_phy(
         self,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
         cc_sel: CcSel,
     ) -> (CcPhy<'d, T>, PdPhy<'d, T>) {
         let r = T::REGS;
@@ -229,7 +228,6 @@ impl<'d, T: Instance> Ucpd<'d, T> {
         // Both parts must be dropped before the peripheral can be disabled.
         T::state().drop_not_ready.store(true, Ordering::Relaxed);
 
-        into_ref!(rx_dma, tx_dma);
         let rx_dma_req = rx_dma.request();
         let tx_dma_req = tx_dma.request();
         (
@@ -237,11 +235,11 @@ impl<'d, T: Instance> Ucpd<'d, T> {
             PdPhy {
                 _lifetime: PhantomData,
                 rx_dma: ChannelAndRequest {
-                    channel: rx_dma.map_into(),
+                    channel: rx_dma.into(),
                     request: rx_dma_req,
                 },
                 tx_dma: ChannelAndRequest {
-                    channel: tx_dma.map_into(),
+                    channel: tx_dma.into(),
                     request: tx_dma_req,
                 },
             },
@@ -689,7 +687,7 @@ trait SealedInstance {
 
 /// UCPD instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {
     /// Interrupt for this instance.
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 7fa9ee08e..b1640b6dc 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -6,7 +6,7 @@ use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
-use embassy_hal_internal::{Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 #[cfg(not(any(usart_v1, usart_v2)))]
@@ -159,9 +159,9 @@ pub struct BufferedUartTx<'d> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    tx: Option<PeripheralRef<'d, AnyPin>>,
-    cts: Option<PeripheralRef<'d, AnyPin>>,
-    de: Option<PeripheralRef<'d, AnyPin>>,
+    tx: Option<Peri<'d, AnyPin>>,
+    cts: Option<Peri<'d, AnyPin>>,
+    de: Option<Peri<'d, AnyPin>>,
     is_borrowed: bool,
 }
 
@@ -172,8 +172,8 @@ pub struct BufferedUartRx<'d> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
     is_borrowed: bool,
 }
 
@@ -207,10 +207,10 @@ impl<'d> SetConfig for BufferedUartTx<'d> {
 impl<'d> BufferedUart<'d> {
     /// Create a new bidirectional buffered UART driver
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -230,12 +230,12 @@ impl<'d> BufferedUart<'d> {
 
     /// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
     pub fn new_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -255,11 +255,11 @@ impl<'d> BufferedUart<'d> {
 
     /// Create a new bidirectional buffered UART driver with only the RTS pin as the DE pin
     pub fn new_with_rts_as_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -279,11 +279,11 @@ impl<'d> BufferedUart<'d> {
 
     /// Create a new bidirectional buffered UART driver with only the request-to-send pin
     pub fn new_with_rts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -304,11 +304,11 @@ impl<'d> BufferedUart<'d> {
     /// Create a new bidirectional buffered UART driver with a driver-enable pin
     #[cfg(not(any(usart_v1, usart_v2)))]
     pub fn new_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        de: Peri<'d, impl DePin<T>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -339,8 +339,8 @@ impl<'d> BufferedUart<'d> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
     pub fn new_half_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -379,8 +379,8 @@ impl<'d> BufferedUart<'d> {
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
     pub fn new_half_duplex_on_rx<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
@@ -405,12 +405,12 @@ impl<'d> BufferedUart<'d> {
     }
 
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
-        de: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        rx: Option<Peri<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
+        de: Option<Peri<'d, AnyPin>>,
         tx_buffer: &'d mut [u8],
         rx_buffer: &'d mut [u8],
         config: Config,
@@ -505,17 +505,17 @@ impl<'d> BufferedUart<'d> {
                 info: self.tx.info,
                 state: self.tx.state,
                 kernel_clock: self.tx.kernel_clock,
-                tx: self.tx.tx.as_mut().map(PeripheralRef::reborrow),
-                cts: self.tx.cts.as_mut().map(PeripheralRef::reborrow),
-                de: self.tx.de.as_mut().map(PeripheralRef::reborrow),
+                tx: self.tx.tx.as_mut().map(Peri::reborrow),
+                cts: self.tx.cts.as_mut().map(Peri::reborrow),
+                de: self.tx.de.as_mut().map(Peri::reborrow),
                 is_borrowed: true,
             },
             BufferedUartRx {
                 info: self.rx.info,
                 state: self.rx.state,
                 kernel_clock: self.rx.kernel_clock,
-                rx: self.rx.rx.as_mut().map(PeripheralRef::reborrow),
-                rts: self.rx.rts.as_mut().map(PeripheralRef::reborrow),
+                rx: self.rx.rx.as_mut().map(Peri::reborrow),
+                rts: self.rx.rts.as_mut().map(Peri::reborrow),
                 is_borrowed: true,
             },
         )
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 568067360..675e90c7f 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -9,7 +9,7 @@ use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::PeripheralRef;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use futures_util::future::{select, Either};
 
@@ -30,7 +30,7 @@ use crate::pac::usart::Usart as Regs;
 use crate::pac::usart::{regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -348,9 +348,9 @@ pub struct UartTx<'d, M: Mode> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    tx: Option<PeripheralRef<'d, AnyPin>>,
-    cts: Option<PeripheralRef<'d, AnyPin>>,
-    de: Option<PeripheralRef<'d, AnyPin>>,
+    tx: Option<Peri<'d, AnyPin>>,
+    cts: Option<Peri<'d, AnyPin>>,
+    de: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     duplex: Duplex,
     _phantom: PhantomData<M>,
@@ -398,8 +398,8 @@ pub struct UartRx<'d, M: Mode> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
     detect_previous_overrun: bool,
     #[cfg(any(usart_v1, usart_v2))]
@@ -419,9 +419,9 @@ impl<'d, M: Mode> SetConfig for UartRx<'d, M> {
 impl<'d> UartTx<'d, Async> {
     /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -435,10 +435,10 @@ impl<'d> UartTx<'d, Async> {
 
     /// Create a new tx-only UART with a clear-to-send pin
     pub fn new_with_cts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -478,8 +478,8 @@ impl<'d> UartTx<'d, Blocking> {
     ///
     /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
     pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -493,9 +493,9 @@ impl<'d> UartTx<'d, Blocking> {
 
     /// Create a new blocking tx-only UART with a clear-to-send pin
     pub fn new_blocking_with_cts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -510,9 +510,9 @@ impl<'d> UartTx<'d, Blocking> {
 
 impl<'d, M: Mode> UartTx<'d, M> {
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        tx: Option<Peri<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -650,10 +650,10 @@ impl<'d> UartRx<'d, Async> {
     ///
     /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -667,11 +667,11 @@ impl<'d> UartRx<'d, Async> {
 
     /// Create a new rx-only UART with a request-to-send pin
     pub fn new_with_rts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -908,8 +908,8 @@ impl<'d> UartRx<'d, Blocking> {
     ///
     /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
     pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(peri, new_pin!(rx, AfType::input(config.rx_pull)), None, None, config)
@@ -917,9 +917,9 @@ impl<'d> UartRx<'d, Blocking> {
 
     /// Create a new rx-only UART with a request-to-send pin
     pub fn new_blocking_with_rts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -934,9 +934,9 @@ impl<'d> UartRx<'d, Blocking> {
 
 impl<'d, M: Mode> UartRx<'d, M> {
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        rx: Option<Peri<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
@@ -1104,12 +1104,12 @@ fn drop_tx_rx(info: &Info, state: &State) {
 impl<'d> Uart<'d, Async> {
     /// Create a new bidirectional UART
     pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1127,14 +1127,14 @@ impl<'d> Uart<'d, Async> {
 
     /// Create a new bidirectional UART with request-to-send and clear-to-send pins
     pub fn new_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rts: Peri<'d, impl RtsPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1153,13 +1153,13 @@ impl<'d> Uart<'d, Async> {
     #[cfg(not(any(usart_v1, usart_v2)))]
     /// Create a new bidirectional UART with a driver-enable pin
     pub fn new_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        de: Peri<'d, impl DePin<T>>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1188,11 +1188,11 @@ impl<'d> Uart<'d, Async> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
     pub fn new_half_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         mut config: Config,
         readback: HalfDuplexReadback,
         half_duplex: HalfDuplexConfig,
@@ -1228,11 +1228,11 @@ impl<'d> Uart<'d, Async> {
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
     pub fn new_half_duplex_on_rx<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
         mut config: Config,
         readback: HalfDuplexReadback,
         half_duplex: HalfDuplexConfig,
@@ -1277,9 +1277,9 @@ impl<'d> Uart<'d, Async> {
 impl<'d> Uart<'d, Blocking> {
     /// Create a new blocking bidirectional UART.
     pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1297,11 +1297,11 @@ impl<'d> Uart<'d, Blocking> {
 
     /// Create a new bidirectional UART with request-to-send and clear-to-send pins
     pub fn new_blocking_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1320,10 +1320,10 @@ impl<'d> Uart<'d, Blocking> {
     #[cfg(not(any(usart_v1, usart_v2)))]
     /// Create a new bidirectional UART with a driver-enable pin
     pub fn new_blocking_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        de: Peri<'d, impl DePin<T>>,
         config: Config,
     ) -> Result<Self, ConfigError> {
         Self::new_inner(
@@ -1351,8 +1351,8 @@ impl<'d> Uart<'d, Blocking> {
     /// on the line must be managed by software (for instance by using a centralized arbiter).
     #[doc(alias("HDSEL"))]
     pub fn new_blocking_half_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
         mut config: Config,
         readback: HalfDuplexReadback,
         half_duplex: HalfDuplexConfig,
@@ -1388,8 +1388,8 @@ impl<'d> Uart<'d, Blocking> {
     #[cfg(not(any(usart_v1, usart_v2)))]
     #[doc(alias("HDSEL"))]
     pub fn new_blocking_half_duplex_on_rx<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
         mut config: Config,
         readback: HalfDuplexReadback,
         half_duplex: HalfDuplexConfig,
@@ -1413,12 +1413,12 @@ impl<'d> Uart<'d, Blocking> {
 
 impl<'d, M: Mode> Uart<'d, M> {
     fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
-        de: Option<PeripheralRef<'d, AnyPin>>,
+        _peri: Peri<'d, T>,
+        rx: Option<Peri<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
+        de: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
@@ -2050,7 +2050,7 @@ pub(crate) trait SealedInstance: crate::rcc::RccPeripheral {
 
 /// USART peripheral instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send {
     /// Interrupt for this peripheral.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index ffd4ee544..600e72582 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -4,7 +4,6 @@ use core::sync::atomic::{compiler_fence, Ordering};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::PeripheralRef;
 use embedded_io_async::ReadReady;
 use futures_util::future::{select, Either};
 
@@ -18,6 +17,7 @@ use crate::mode::Async;
 use crate::pac::usart::regs;
 use crate::time::Hertz;
 use crate::usart::{Regs, Sr};
+use crate::Peri;
 
 /// Rx-only Ring-buffered UART Driver
 ///
@@ -26,8 +26,8 @@ pub struct RingBufferedUartRx<'d> {
     info: &'static Info,
     state: &'static State,
     kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
     ring_buf: ReadableRingBuffer<'d, u8>,
 }
 
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index d3c7978e4..51429b8cc 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -1,6 +1,6 @@
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use embassy_usb_driver::{EndpointAddress, EndpointAllocError, EndpointType, Event, Unsupported};
 use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
 use embassy_usb_synopsys_otg::otg_v1::Otg;
@@ -11,9 +11,9 @@ use embassy_usb_synopsys_otg::{
 };
 
 use crate::gpio::{AfType, OutputType, Speed};
-use crate::interrupt;
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, Peri};
 
 const MAX_EP_COUNT: usize = 9;
 
@@ -32,8 +32,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 
 macro_rules! config_ulpi_pins {
     ($($pin:ident),*) => {
-        into_ref!($($pin),*);
-        critical_section::with(|_| {
+                critical_section::with(|_| {
             $(
                 $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
             )*
@@ -62,15 +61,13 @@ impl<'d, T: Instance> Driver<'d, T> {
     /// Must be large enough to fit all OUT endpoint max packet sizes.
     /// Endpoint allocation will fail if it is too small.
     pub fn new_fs(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dp: impl Peripheral<P = impl DpPin<T>> + 'd,
-        dm: impl Peripheral<P = impl DmPin<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
+        dm: Peri<'d, impl DmPin<T>>,
         ep_out_buffer: &'d mut [u8],
         config: Config,
     ) -> Self {
-        into_ref!(dp, dm);
-
         dp.set_as_af(dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
         dm.set_as_af(dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
 
@@ -100,17 +97,16 @@ impl<'d, T: Instance> Driver<'d, T> {
     /// Must be large enough to fit all OUT endpoint max packet sizes.
     /// Endpoint allocation will fail if it is too small.
     pub fn new_hs(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        _dp: impl Peripheral<P = impl DpPin<T>> + 'd,
-        _dm: impl Peripheral<P = impl DmPin<T>> + 'd,
+        _dp: Peri<'d, impl DpPin<T>>,
+        _dm: Peri<'d, impl DmPin<T>>,
         ep_out_buffer: &'d mut [u8],
         config: Config,
     ) -> Self {
         // For STM32U5 High speed pins need to be left in analog mode
         #[cfg(not(all(stm32u5, peri_usb_otg_hs)))]
         {
-            into_ref!(_dp, _dm);
             _dp.set_as_af(_dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
             _dm.set_as_af(_dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
         }
@@ -139,20 +135,20 @@ impl<'d, T: Instance> Driver<'d, T> {
     /// Must be large enough to fit all OUT endpoint max packet sizes.
     /// Endpoint allocation will fail if it is too small.
     pub fn new_fs_ulpi(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
-        ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
-        ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,
-        ulpi_stp: impl Peripheral<P = impl UlpiStpPin<T>> + 'd,
-        ulpi_d0: impl Peripheral<P = impl UlpiD0Pin<T>> + 'd,
-        ulpi_d1: impl Peripheral<P = impl UlpiD1Pin<T>> + 'd,
-        ulpi_d2: impl Peripheral<P = impl UlpiD2Pin<T>> + 'd,
-        ulpi_d3: impl Peripheral<P = impl UlpiD3Pin<T>> + 'd,
-        ulpi_d4: impl Peripheral<P = impl UlpiD4Pin<T>> + 'd,
-        ulpi_d5: impl Peripheral<P = impl UlpiD5Pin<T>> + 'd,
-        ulpi_d6: impl Peripheral<P = impl UlpiD6Pin<T>> + 'd,
-        ulpi_d7: impl Peripheral<P = impl UlpiD7Pin<T>> + 'd,
+        ulpi_clk: Peri<'d, impl UlpiClkPin<T>>,
+        ulpi_dir: Peri<'d, impl UlpiDirPin<T>>,
+        ulpi_nxt: Peri<'d, impl UlpiNxtPin<T>>,
+        ulpi_stp: Peri<'d, impl UlpiStpPin<T>>,
+        ulpi_d0: Peri<'d, impl UlpiD0Pin<T>>,
+        ulpi_d1: Peri<'d, impl UlpiD1Pin<T>>,
+        ulpi_d2: Peri<'d, impl UlpiD2Pin<T>>,
+        ulpi_d3: Peri<'d, impl UlpiD3Pin<T>>,
+        ulpi_d4: Peri<'d, impl UlpiD4Pin<T>>,
+        ulpi_d5: Peri<'d, impl UlpiD5Pin<T>>,
+        ulpi_d6: Peri<'d, impl UlpiD6Pin<T>>,
+        ulpi_d7: Peri<'d, impl UlpiD7Pin<T>>,
         ep_out_buffer: &'d mut [u8],
         config: Config,
     ) -> Self {
@@ -185,20 +181,20 @@ impl<'d, T: Instance> Driver<'d, T> {
     /// Must be large enough to fit all OUT endpoint max packet sizes.
     /// Endpoint allocation will fail if it is too small.
     pub fn new_hs_ulpi(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
-        ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
-        ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,
-        ulpi_stp: impl Peripheral<P = impl UlpiStpPin<T>> + 'd,
-        ulpi_d0: impl Peripheral<P = impl UlpiD0Pin<T>> + 'd,
-        ulpi_d1: impl Peripheral<P = impl UlpiD1Pin<T>> + 'd,
-        ulpi_d2: impl Peripheral<P = impl UlpiD2Pin<T>> + 'd,
-        ulpi_d3: impl Peripheral<P = impl UlpiD3Pin<T>> + 'd,
-        ulpi_d4: impl Peripheral<P = impl UlpiD4Pin<T>> + 'd,
-        ulpi_d5: impl Peripheral<P = impl UlpiD5Pin<T>> + 'd,
-        ulpi_d6: impl Peripheral<P = impl UlpiD6Pin<T>> + 'd,
-        ulpi_d7: impl Peripheral<P = impl UlpiD7Pin<T>> + 'd,
+        ulpi_clk: Peri<'d, impl UlpiClkPin<T>>,
+        ulpi_dir: Peri<'d, impl UlpiDirPin<T>>,
+        ulpi_nxt: Peri<'d, impl UlpiNxtPin<T>>,
+        ulpi_stp: Peri<'d, impl UlpiStpPin<T>>,
+        ulpi_d0: Peri<'d, impl UlpiD0Pin<T>>,
+        ulpi_d1: Peri<'d, impl UlpiD1Pin<T>>,
+        ulpi_d2: Peri<'d, impl UlpiD2Pin<T>>,
+        ulpi_d3: Peri<'d, impl UlpiD3Pin<T>>,
+        ulpi_d4: Peri<'d, impl UlpiD4Pin<T>>,
+        ulpi_d5: Peri<'d, impl UlpiD5Pin<T>>,
+        ulpi_d6: Peri<'d, impl UlpiD6Pin<T>>,
+        ulpi_d7: Peri<'d, impl UlpiD7Pin<T>>,
         ep_out_buffer: &'d mut [u8],
         config: Config,
     ) -> Self {
@@ -411,7 +407,7 @@ trait SealedInstance {
 
 /// USB instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
     /// Interrupt for this USB instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 6682374d3..0b878915a 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -5,7 +5,7 @@ use core::marker::PhantomData;
 use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use embassy_usb_driver as driver;
 use embassy_usb_driver::{
@@ -16,7 +16,7 @@ use crate::pac::usb::regs;
 use crate::pac::usb::vals::{EpType, Stat};
 use crate::pac::USBRAM;
 use crate::rcc::RccPeripheral;
-use crate::{interrupt, Peripheral};
+use crate::{interrupt, Peri};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -290,13 +290,12 @@ impl<'d, T: Instance> Driver<'d, T> {
     /// Create a new USB driver with start-of-frame (SOF) output.
     #[cfg(not(stm32l1))]
     pub fn new_with_sof(
-        _usb: impl Peripheral<P = T> + 'd,
+        _usb: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dp: impl Peripheral<P = impl DpPin<T>> + 'd,
-        dm: impl Peripheral<P = impl DmPin<T>> + 'd,
-        sof: impl Peripheral<P = impl SofPin<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
+        dm: Peri<'d, impl DmPin<T>>,
+        sof: Peri<'d, impl SofPin<T>>,
     ) -> Self {
-        into_ref!(sof);
         {
             use crate::gpio::{AfType, OutputType, Speed};
             sof.set_as_af(sof.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -307,13 +306,11 @@ impl<'d, T: Instance> Driver<'d, T> {
 
     /// Create a new USB driver.
     pub fn new(
-        _usb: impl Peripheral<P = T> + 'd,
+        _usb: Peri<'d, T>,
         _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dp: impl Peripheral<P = impl DpPin<T>> + 'd,
-        dm: impl Peripheral<P = impl DmPin<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
+        dm: Peri<'d, impl DmPin<T>>,
     ) -> Self {
-        into_ref!(dp, dm);
-
         super::common_init::<T>();
 
         let regs = T::regs();
@@ -1236,7 +1233,7 @@ trait SealedInstance {
 
 /// USB instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
     /// Interrupt for this USB instance.
     type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index ab21c4b6b..fb5c3d930 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -1,10 +1,11 @@
 //! Watchdog Timer (IWDG, WWDG)
 use core::marker::PhantomData;
 
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use stm32_metapac::iwdg::vals::{Key, Pr};
 
 use crate::rcc::LSI_FREQ;
+use crate::Peri;
 
 /// Independent watchdog (IWDG) driver.
 pub struct IndependentWatchdog<'d, T: Instance> {
@@ -29,9 +30,7 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> {
     ///
     /// [Self] has to be started with [Self::unleash()].
     /// Once timer expires, MCU will be reset. To prevent this, timer must be reloaded by repeatedly calling [Self::pet()] within timeout interval.
-    pub fn new(_instance: impl Peripheral<P = T> + 'd, timeout_us: u32) -> Self {
-        into_ref!(_instance);
-
+    pub fn new(_instance: Peri<'d, T>, timeout_us: u32) -> Self {
         // Find lowest prescaler value, which makes watchdog period longer or equal to timeout.
         // This iterates from 4 (2^2) to 256 (2^8).
         let psc_power = unwrap!((2..=8).find(|psc_power| {
@@ -86,7 +85,7 @@ trait SealedInstance {
 
 /// IWDG instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance {}
+pub trait Instance: SealedInstance + PeripheralType {}
 
 foreach_peripheral!(
     (iwdg, $inst:ident) => {