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authorelagil <[email protected]>2025-01-26 17:33:26 +0100
committerelagil <[email protected]>2025-01-26 17:33:26 +0100
commitd9026f06fea80fcb85fca00aede1bc911fb9de1b (patch)
tree2602f53af208b968b50d8dcae9d5447789aa6bc7 /embassy-stm32/src
parent7db46771b8ad14467f759c98d604bfaf9e3b5e01 (diff)
fix: STM32H5 UCPD reception
Diffstat (limited to 'embassy-stm32/src')
-rw-r--r--embassy-stm32/src/ucpd.rs20
1 files changed, 14 insertions, 6 deletions
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 2d44bf8ff..133a1c827 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -137,6 +137,13 @@ impl<'d, T: Instance> Ucpd<'d, T> {
137 unsafe { T::Interrupt::enable() }; 137 unsafe { T::Interrupt::enable() };
138 138
139 let r = T::REGS; 139 let r = T::REGS;
140
141 #[cfg(stm32h5)]
142 r.cfgr2().write(|w| {
143 // Only takes effect, when UCPDEN=0.
144 w.set_rxafilten(true);
145 });
146
140 r.cfgr1().write(|w| { 147 r.cfgr1().write(|w| {
141 // "The receiver is designed to work in the clock frequency range from 6 to 18 MHz. 148 // "The receiver is designed to work in the clock frequency range from 6 to 18 MHz.
142 // However, the optimum performance is ensured in the range from 6 to 12 MHz" 149 // However, the optimum performance is ensured in the range from 6 to 12 MHz"
@@ -175,11 +182,6 @@ impl<'d, T: Instance> Ucpd<'d, T> {
175 w.set_ucpden(true); 182 w.set_ucpden(true);
176 }); 183 });
177 184
178 #[cfg(stm32h5)]
179 r.cfgr2().write(|w| {
180 w.set_rxafilten(true);
181 });
182
183 // Software trim according to RM0481, p. 2650/2668 185 // Software trim according to RM0481, p. 2650/2668
184 #[cfg(stm32h5)] 186 #[cfg(stm32h5)]
185 { 187 {
@@ -436,7 +438,7 @@ impl<'d, T: Instance> PdPhy<'d, T> {
436 pub async fn receive_with_sop(&mut self, buf: &mut [u8]) -> Result<(Sop, usize), RxError> { 438 pub async fn receive_with_sop(&mut self, buf: &mut [u8]) -> Result<(Sop, usize), RxError> {
437 let r = T::REGS; 439 let r = T::REGS;
438 440
439 let dma = unsafe { 441 let mut dma = unsafe {
440 self.rx_dma 442 self.rx_dma
441 .read(r.rxdr().as_ptr() as *mut u8, buf, TransferOptions::default()) 443 .read(r.rxdr().as_ptr() as *mut u8, buf, TransferOptions::default())
442 }; 444 };
@@ -451,14 +453,20 @@ impl<'d, T: Instance> PdPhy<'d, T> {
451 }); 453 });
452 }); 454 });
453 455
456 // Stop DMA reception immediately after receiving a packet, to prevent storing multiple packets in the same buffer.
454 poll_fn(|cx| { 457 poll_fn(|cx| {
455 let sr = r.sr().read(); 458 let sr = r.sr().read();
459
456 if sr.rxhrstdet() { 460 if sr.rxhrstdet() {
461 dma.request_stop();
462
457 // Clean and re-enable hard reset receive interrupt. 463 // Clean and re-enable hard reset receive interrupt.
458 r.icr().write(|w| w.set_rxhrstdetcf(true)); 464 r.icr().write(|w| w.set_rxhrstdetcf(true));
459 r.imr().modify(|w| w.set_rxhrstdetie(true)); 465 r.imr().modify(|w| w.set_rxhrstdetie(true));
460 Poll::Ready(Err(RxError::HardReset)) 466 Poll::Ready(Err(RxError::HardReset))
461 } else if sr.rxmsgend() { 467 } else if sr.rxmsgend() {
468 dma.request_stop();
469
462 let ret = if sr.rxovr() { 470 let ret = if sr.rxovr() {
463 Err(RxError::Overrun) 471 Err(RxError::Overrun)
464 } else if sr.rxerr() { 472 } else if sr.rxerr() {