diff options
| author | ftk <[email protected]> | 2024-04-27 15:49:30 +0300 |
|---|---|---|
| committer | ftk <[email protected]> | 2024-04-27 15:49:30 +0300 |
| commit | e7bfd7bac90d254ea6dee408564d5e0f8a80ca19 (patch) | |
| tree | 6228725a617b64e96d040653f9be710acc022c71 /embassy-stm32/src | |
| parent | 34074e6eb0741e084653b3ef71163393741f558b (diff) | |
stm32 timer: fix 32bit timer off by 1 ARR error
Diffstat (limited to 'embassy-stm32/src')
| -rw-r--r-- | embassy-stm32/src/timer/low_level.rs | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs index a5d942314..294dff7ea 100644 --- a/embassy-stm32/src/timer/low_level.rs +++ b/embassy-stm32/src/timer/low_level.rs | |||
| @@ -257,7 +257,10 @@ impl<'d, T: CoreInstance> Timer<'d, T> { | |||
| 257 | TimerBits::Bits32 => { | 257 | TimerBits::Bits32 => { |
| 258 | let pclk_ticks_per_timer_period = (timer_f / f) as u64; | 258 | let pclk_ticks_per_timer_period = (timer_f / f) as u64; |
| 259 | let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into()); | 259 | let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into()); |
| 260 | let arr: u32 = unwrap!((pclk_ticks_per_timer_period / (psc as u64 + 1)).try_into()); | 260 | let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1); |
| 261 | |||
| 262 | // the timer counts `0..=arr`, we want it to count `0..divide_by` | ||
| 263 | let arr: u32 = unwrap!(u32::try_from(divide_by - 1)); | ||
| 261 | 264 | ||
| 262 | let regs = self.regs_gp32_unchecked(); | 265 | let regs = self.regs_gp32_unchecked(); |
| 263 | regs.psc().write_value(psc); | 266 | regs.psc().write_value(psc); |
