Merge branch 'main' of https://github.com/embassy-rs/embassy into xspi

120 files changed, 8490 insertions, 4246 deletions

diff --git a/embassy-stm32/src/adc/adc4.rs b/embassy-stm32/src/adc/adc4.rs
index 255dc7956..453513309 100644
--- a/embassy-stm32/src/adc/adc4.rs
+++ b/embassy-stm32/src/adc/adc4.rs
@@ -4,8 +4,8 @@ use pac::adc::vals::{Adc4Dmacfg as Dmacfg, Adc4Exten as Exten, Adc4OversamplingR
 #[cfg(stm32wba)]
 use pac::adc::vals::{Chselrmod, Cont, Dmacfg, Exten, OversamplingRatio, Ovss, Smpsel};
 
-use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
-use crate::dma::Transfer;
+use super::blocking_delay_us;
+use crate::adc::ConversionMode;
 #[cfg(stm32u5)]
 pub use crate::pac::adc::regs::Adc4Chselrmod0 as Chselr;
 #[cfg(stm32wba)]
@@ -15,7 +15,7 @@ pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4S
 #[cfg(stm32wba)]
 pub use crate::pac::adc::vals::{Presc, Res as Resolution, SampleTime};
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
@@ -24,56 +24,24 @@ pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
-const VREF_CHANNEL: u8 = 0;
-const VCORE_CHANNEL: u8 = 12;
-const TEMP_CHANNEL: u8 = 13;
-const VBAT_CHANNEL: u8 = 14;
-const DAC_CHANNEL: u8 = 21;
-
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::VrefInt> for Adc4<'d, T> {
+    const CHANNEL: u8 = 0;
 }
 
-/// Internal temperature channel.
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Temperature> for Adc4<'d, T> {
+    const CHANNEL: u8 = 13;
 }
 
-/// Internal battery voltage channel.
-pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        VBAT_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vcore> for Adc4<'d, T> {
+    const CHANNEL: u8 = 12;
 }
 
-/// Internal DAC channel.
-pub struct Dac;
-impl<T: Instance> AdcChannel<T> for Dac {}
-impl<T: Instance> SealedAdcChannel<T> for Dac {
-    fn channel(&self) -> u8 {
-        DAC_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Vbat> for Adc4<'d, T> {
+    const CHANNEL: u8 = 14;
 }
 
-/// Internal Vcore channel.
-pub struct Vcore;
-impl<T: Instance> AdcChannel<T> for Vcore {}
-impl<T: Instance> SealedAdcChannel<T> for Vcore {
-    fn channel(&self) -> u8 {
-        VCORE_CHANNEL
-    }
+impl<'d, T: Instance> super::SealedSpecialConverter<super::Dac> for Adc4<'d, T> {
+    const CHANNEL: u8 = 21;
 }
 
 #[derive(Copy, Clone)]
@@ -108,71 +76,17 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
     }
 }
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
-
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
-    }
-
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
-    }
-
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
-        }
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
     }
 }
 
@@ -185,6 +99,127 @@ pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeri
     type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        use crate::peripherals::ADC4;
+
+        impl super::BasicAnyInstance for ADC4 {
+            type SampleTime = SampleTime;
+        }
+
+        impl super::SealedAnyInstance for ADC4 {
+            fn dr() -> *mut u16 {
+                ADC4::regs().dr().as_ptr() as *mut u16
+            }
+
+            fn enable() {
+                if !ADC4::regs().cr().read().aden()  || !ADC4::regs().isr().read().adrdy() {
+                    ADC4::regs().isr().write(|w| w.set_adrdy(true));
+                    ADC4::regs().cr().modify(|w| w.set_aden(true));
+                    while !ADC4::regs().isr().read().adrdy() {}
+                }
+            }
+
+            fn start() {
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+            }
+
+            fn stop() {
+                let cr = ADC4::regs().cr().read();
+                if cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_adstp(true));
+                    while ADC4::regs().cr().read().adstart() {}
+                }
+
+                if cr.aden() || cr.adstart() {
+                    ADC4::regs().cr().modify(|w| w.set_addis(true));
+                    while ADC4::regs().cr().read().aden() {}
+                }
+
+                // Reset configuration.
+                ADC4::regs().cfgr1().modify(|reg| {
+                    reg.set_dmaen(false);
+                });
+            }
+
+            fn configure_dma(conversion_mode: ConversionMode) {
+                match conversion_mode {
+                    ConversionMode::Singular => {
+                        ADC4::regs().isr().modify(|reg| {
+                            reg.set_ovr(true);
+                            reg.set_eos(true);
+                            reg.set_eoc(true);
+                        });
+
+                        ADC4::regs().cfgr1().modify(|reg| {
+                            reg.set_dmaen(true);
+                            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+                            #[cfg(stm32u5)]
+                            reg.set_chselrmod(false);
+                            #[cfg(stm32wba)]
+                            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
+                        });
+                    }
+                    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                    _ => unreachable!(),
+                }
+            }
+
+            fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+                let mut prev_channel: i16 = -1;
+                #[cfg(stm32wba)]
+                ADC4::regs().chselr().write_value(Chselr(0_u32));
+                #[cfg(stm32u5)]
+                ADC4::regs().chselrmod0().write_value(Chselr(0_u32));
+                for (_i, ((channel, _), sample_time)) in sequence.enumerate() {
+                    ADC4::regs().smpr().modify(|w| {
+                        w.set_smp(_i, sample_time);
+                    });
+
+                    let channel_num = channel;
+                    if channel_num as i16 <= prev_channel {
+                        return;
+                    };
+                    prev_channel = channel_num as i16;
+
+                    #[cfg(stm32wba)]
+                    ADC4::regs().chselr().modify(|w| {
+                        w.set_chsel0(channel as usize, true);
+                    });
+                    #[cfg(stm32u5)]
+                    ADC4::regs().chselrmod0().modify(|w| {
+                        w.set_chsel(channel as usize, true);
+                    });
+                }
+            }
+
+            fn convert() -> u16 {
+                // Reset interrupts
+                ADC4::regs().isr().modify(|reg| {
+                    reg.set_eos(true);
+                    reg.set_eoc(true);
+                });
+
+                // Start conversion
+                ADC4::regs().cr().modify(|reg| {
+                    reg.set_adstart(true);
+                });
+
+                while !ADC4::regs().isr().read().eos() {
+                    // spin
+                }
+
+                ADC4::regs().dr().read().0 as u16
+            }
+        }
+
+        impl super::AnyInstance for ADC4 {}
+    };
+);
+
 pub struct Adc4<'d, T: Instance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
@@ -196,35 +231,24 @@ pub enum Adc4Error {
     DMAError,
 }
 
-impl<'d, T: Instance> Adc4<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> super::Adc<'d, T> {
     /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
+    pub fn new_adc4(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
 
-        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         info!("ADC4 frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
-        let mut s = Self { adc };
-
-        s.power_up();
-
-        s.calibrate();
-        blocking_delay_us(1);
-
-        s.enable();
-        s.configure();
-
-        s
-    }
-
-    fn power_up(&mut self) {
         T::regs().isr().modify(|w| {
             w.set_ldordy(true);
         });
@@ -236,22 +260,15 @@ impl<'d, T: Instance> Adc4<'d, T> {
         T::regs().isr().modify(|w| {
             w.set_ldordy(true);
         });
-    }
 
-    fn calibrate(&mut self) {
         T::regs().cr().modify(|w| w.set_adcal(true));
         while T::regs().cr().read().adcal() {}
         T::regs().isr().modify(|w| w.set_eocal(true));
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
+        blocking_delay_us(1);
+
+        T::enable();
 
-    fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
             #[cfg(stm32u5)]
@@ -277,73 +294,63 @@ impl<'d, T: Instance> Adc4<'d, T> {
                 w.set_smpsel(i, Smpsel::SMP1);
             }
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint_adc4(&self) -> super::VrefInt {
         T::regs().ccr().modify(|w| {
             w.set_vrefen(true);
         });
 
-        VrefInt {}
+        super::VrefInt {}
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature_adc4(&self) -> super::Temperature {
         T::regs().ccr().modify(|w| {
             w.set_vsensesel(true);
         });
 
-        Temperature {}
+        super::Temperature {}
     }
 
     /// Enable reading the vbat internal channel.
     #[cfg(stm32u5)]
-    pub fn enable_vbat(&self) -> Vbat {
+    pub fn enable_vbat_adc4(&self) -> super::Vbat {
         T::regs().ccr().modify(|w| {
             w.set_vbaten(true);
         });
 
-        Vbat {}
+        super::Vbat {}
     }
 
     /// Enable reading the vbat internal channel.
-    pub fn enable_vcore(&self) -> Vcore {
-        Vcore {}
+    pub fn enable_vcore_adc4(&self) -> super::Vcore {
+        super::Vcore {}
     }
 
     /// Enable reading the vbat internal channel.
     #[cfg(stm32u5)]
-    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+    pub fn enable_dac_channel_adc4(&self, dac: DacChannel) -> super::Dac {
         let mux;
         match dac {
             DacChannel::OUT1 => mux = false,
             DacChannel::OUT2 => mux = true,
         }
         T::regs().or().modify(|w| w.set_chn21sel(mux));
-        Dac {}
-    }
-
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        T::regs().smpr().modify(|w| {
-            w.set_smp(0, sample_time);
-        });
-    }
-
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        T::regs().smpr().read().smp(0)
+        super::Dac {}
     }
 
     /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
+    pub fn set_resolution_adc4(&mut self, resolution: Resolution) {
         T::regs().cfgr1().modify(|w| w.set_res(resolution.into()));
     }
 
     /// Set hardware averaging.
     #[cfg(stm32u5)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
             Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, 0),
             Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, 1),
@@ -363,7 +370,7 @@ impl<'d, T: Instance> Adc4<'d, T> {
         })
     }
     #[cfg(stm32wba)]
-    pub fn set_averaging(&mut self, averaging: Averaging) {
+    pub fn set_averaging_adc4(&mut self, averaging: Averaging) {
         let (enable, samples, right_shift) = match averaging {
             Averaging::Disabled => (false, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT0),
             Averaging::Samples2 => (true, OversamplingRatio::OVERSAMPLE2X, Ovss::SHIFT1),
@@ -382,164 +389,4 @@ impl<'d, T: Instance> Adc4<'d, T> {
             w.set_ovse(enable)
         })
     }
-
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        channel.setup();
-
-        // Select channel
-        #[cfg(stm32wba)]
-        {
-            T::regs().chselr().write_value(Chselr(0_u32));
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel() as usize, true);
-            });
-        }
-        #[cfg(stm32u5)]
-        {
-            T::regs().chselrmod0().write_value(Chselr(0_u32));
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel() as usize, true);
-            });
-        }
-
-        // Reset interrupts
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    /// The channels in `sequence` must be in ascending order.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::adc4;
-    /// use embassy_stm32::adc::AdcChannel;
-    ///
-    /// let mut adc4 = adc4::Adc4::new(p.ADC4);
-    /// let mut adc4_pin1 = p.PC1;
-    /// let mut adc4_pin2 = p.PC0;
-    /// let mut.into()d41 = adc4_pin1.into();
-    /// let mut.into()d42 = adc4_pin2.into();
-    /// let mut measurements = [0u16; 2];
-    /// // not that the channels must be in ascending order
-    /// adc4.read(
-    ///     &mut p.GPDMA1_CH1,
-    ///    [
-    ///        &mut.into()d42,
-    ///        &mut.into()d41,
-    ///    ]
-    ///    .into_iter(),
-    ///    &mut measurements,
-    /// ).await.unwrap();
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma4<T>>,
-        sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) -> Result<(), Adc4Error> {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            #[cfg(stm32u5)]
-            reg.set_chselrmod(false);
-            #[cfg(stm32wba)]
-            reg.set_chselrmod(Chselrmod::ENABLE_INPUT)
-        });
-
-        // Verify and activate sequence
-        let mut prev_channel: i16 = -1;
-        #[cfg(stm32wba)]
-        T::regs().chselr().write_value(Chselr(0_u32));
-        #[cfg(stm32u5)]
-        T::regs().chselrmod0().write_value(Chselr(0_u32));
-        for channel in sequence {
-            let channel_num = channel.channel;
-            if channel_num as i16 <= prev_channel {
-                return Err(Adc4Error::InvalidSequence);
-            };
-            prev_channel = channel_num as i16;
-
-            #[cfg(stm32wba)]
-            T::regs().chselr().modify(|w| {
-                w.set_chsel0(channel.channel as usize, true);
-            });
-            #[cfg(stm32u5)]
-            T::regs().chselrmod0().modify(|w| {
-                w.set_chsel(channel.channel as usize, true);
-            });
-        }
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_dmaen(false);
-        });
-
-        if T::regs().isr().read().ovr() {
-            Err(Adc4Error::DMAError)
-        } else {
-            Ok(())
-        }
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
index f2837a8f1..3e109e429 100644
--- a/embassy-stm32/src/adc/c0.rs
+++ b/embassy-stm32/src/adc/c0.rs
@@ -1,14 +1,12 @@
-use pac::adc::vals::Scandir;
 #[allow(unused)]
 use pac::adc::vals::{Adstp, Align, Ckmode, Dmacfg, Exten, Ovrmod, Ovsr};
 use pac::adccommon::vals::Presc;
+use stm32_metapac::adc::vals::{SampleTime, Scandir};
 
-use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
-};
-use crate::dma::Transfer;
+use super::{Adc, Instance, Resolution, blocking_delay_us};
+use crate::adc::{AnyInstance, ConversionMode};
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -19,189 +17,200 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(25);
 
 const TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US: u32 = 20;
 
-const TEMP_CHANNEL: u8 = 9;
-const VREF_CHANNEL: u8 = 10;
-
-const NUM_HW_CHANNELS: u8 = 22;
 const CHSELR_SQ_SIZE: usize = 8;
 const CHSELR_SQ_MAX_CHANNEL: u8 = 14;
 const CHSELR_SQ_SEQUENCE_END_MARKER: u8 = 0b1111;
 
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs,
-// this currently cannot be modeled with stm32-data,
-// so these are available from the software on all ADCs.
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 10;
 }
 
-/// Internal temperature channel.
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
-    }
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 9;
 }
 
-#[derive(Copy, Clone, Debug)]
-pub enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
+    }
 }
 
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
-        }
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
     }
 
-    #[allow(unused)]
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
-        }
+    fn enable() {
+        T::regs().isr().modify(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        // ADRDY is "ADC ready". Wait until it will be True.
+        while !T::regs().isr().read().adrdy() {}
     }
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
+    fn start() {
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
         }
+
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmacfg(Dmacfg::from_bits(0));
+            reg.set_dmaen(false);
+        });
     }
-}
 
-#[cfg(feature = "defmt")]
-impl<'a> defmt::Format for Prescaler {
-    fn format(&self, fmt: defmt::Formatter) {
-        match self {
-            Prescaler::NotDivided => defmt::write!(fmt, "Prescaler::NotDivided"),
-            Prescaler::DividedBy2 => defmt::write!(fmt, "Prescaler::DividedBy2"),
-            Prescaler::DividedBy4 => defmt::write!(fmt, "Prescaler::DividedBy4"),
-            Prescaler::DividedBy6 => defmt::write!(fmt, "Prescaler::DividedBy6"),
-            Prescaler::DividedBy8 => defmt::write!(fmt, "Prescaler::DividedBy8"),
-            Prescaler::DividedBy10 => defmt::write!(fmt, "Prescaler::DividedBy10"),
-            Prescaler::DividedBy12 => defmt::write!(fmt, "Prescaler::DividedBy12"),
-            Prescaler::DividedBy16 => defmt::write!(fmt, "Prescaler::DividedBy16"),
-            Prescaler::DividedBy32 => defmt::write!(fmt, "Prescaler::DividedBy32"),
-            Prescaler::DividedBy64 => defmt::write!(fmt, "Prescaler::DividedBy64"),
-            Prescaler::DividedBy128 => defmt::write!(fmt, "Prescaler::DividedBy128"),
-            Prescaler::DividedBy256 => defmt::write!(fmt, "Prescaler::DividedBy256"),
+    fn configure_dma(conversion_mode: super::ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Singular => {
+                // Enable overrun control, so no new DMA requests will be generated until
+                // previous DR values is read.
+                T::regs().isr().modify(|reg| {
+                    reg.set_ovr(true);
+                });
+
+                // Set continuous mode with oneshot dma.
+                T::regs().cfgr1().modify(|reg| {
+                    reg.set_discen(false);
+                    reg.set_cont(true);
+                    reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
+                    reg.set_dmaen(true);
+                    reg.set_ovrmod(Ovrmod::PRESERVE);
+                });
+            }
         }
     }
-}
 
-/// Number of samples used for averaging.
-/// TODO: Implement hardware averaging setting.
-#[allow(unused)]
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-    Samples512,
-    Samples1024,
-}
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>) {
+        let mut needs_hw = sequence.len() == 1 || sequence.len() > CHSELR_SQ_SIZE;
+        let mut is_ordered_up = true;
+        let mut is_ordered_down = true;
 
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>, sample_time: SampleTime, resolution: Resolution) -> Self {
-        rcc::enable_and_reset::<T>();
+        let sequence_len = sequence.len();
+        let mut hw_channel_selection: u32 = 0;
+        let mut last_channel: u8 = 0;
+        let mut sample_time: Self::SampleTime = SampleTime::CYCLES2_5;
 
-        T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
+        T::regs().chselr_sq().write(|w| {
+            for (i, ((channel, _), _sample_time)) in sequence.enumerate() {
+                assert!(
+                    sample_time == _sample_time || i == 0,
+                    "C0 only supports one sample time for the sequence."
+                );
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+                sample_time = _sample_time;
+                needs_hw = needs_hw || channel > CHSELR_SQ_MAX_CHANNEL;
+                is_ordered_up = is_ordered_up && (channel > last_channel || i == 0);
+                is_ordered_down = is_ordered_down && (channel < last_channel || i == 0);
+                hw_channel_selection += 1 << channel;
+                last_channel = channel;
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
-        debug!("ADC frequency set to {}", frequency);
+                if !needs_hw {
+                    w.set_sq(i, channel);
+                }
+            }
 
-        if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
-        }
+            for i in sequence_len..CHSELR_SQ_SIZE {
+                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
+            }
+        });
 
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
+        if needs_hw {
+            assert!(
+                sequence_len <= CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but read set cannot be more than {} in size.",
+                CHSELR_SQ_SIZE
+            );
+            assert!(
+                sequence_len > CHSELR_SQ_SIZE || is_ordered_up || is_ordered_down,
+                "Sequencer is required because of unordered channels, but only support HW channels smaller than {}.",
+                CHSELR_SQ_MAX_CHANNEL
+            );
+
+            // Set required channels for multi-convert.
+            unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
+        }
 
-        s.power_up();
+        T::regs().smpr().modify(|w| {
+            w.smpsel(0);
+            w.set_smp1(sample_time);
+        });
 
-        s.set_resolution(resolution);
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_chselrmod(!needs_hw);
+            reg.set_align(Align::RIGHT);
+            reg.set_scandir(if is_ordered_up { Scandir::UP } else { Scandir::BACK });
+        });
 
-        s.calibrate();
+        // Trigger and wait for the channel selection procedure to complete.
+        T::regs().isr().modify(|w| w.set_ccrdy(false));
+        while !T::regs().isr().read().ccrdy() {}
+    }
 
-        s.enable();
+    fn convert() -> u16 {
+        // Set single conversion mode.
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
 
-        s.configure_default();
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
 
-        s.set_sample_time_all_channels(sample_time);
+        // Waiting for End Of Conversion (EOC).
+        while !T::regs().isr().read().eoc() {}
 
-        s
+        T::regs().dr().read().data() as u16
     }
+}
+
+impl<'d, T: AnyInstance> Adc<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: Peri<'d, T>, resolution: Resolution) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
+
+        let prescaler = from_ker_ck(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
+
+        let frequency = T::frequency() / prescaler;
+        debug!("ADC frequency set to {}", frequency);
+
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
+        }
 
-    fn power_up(&mut self) {
         T::regs().cr().modify(|reg| {
             reg.set_advregen(true);
         });
 
         // "The software must wait for the ADC voltage regulator startup time."
         // See datasheet for the value.
-        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US + 1);
-    }
+        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US as u64 + 1);
+
+        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
 
-    fn calibrate(&mut self) {
         // We have to make sure AUTOFF is OFF, but keep its value after calibration.
         let autoff_value = T::regs().cfgr1().read().autoff();
         T::regs().cfgr1().modify(|w| w.set_autoff(false));
@@ -215,255 +224,35 @@ impl<'d, T: Instance> Adc<'d, T> {
         debug!("ADC calibration value: {}.", T::regs().dr().read().data());
 
         T::regs().cfgr1().modify(|w| w.set_autoff(autoff_value));
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().modify(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        // ADRDY is "ADC ready". Wait until it will be True.
-        while !T::regs().isr().read().adrdy() {}
-    }
+        T::enable();
 
-    fn configure_default(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr1().modify(|w| {
             w.set_cont(false);
             w.set_exten(Exten::DISABLED);
             w.set_align(Align::RIGHT);
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt {
+    pub fn enable_vrefint(&self) -> super::VrefInt {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
 
-        VrefInt {}
+        super::VrefInt {}
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
         debug!("Ensure that sample time is set to more than temperature sensor T_start from the datasheet!");
         T::common_regs().ccr().modify(|reg| {
             reg.set_tsen(true);
         });
 
-        Temperature {}
-    }
-
-    /// Set the ADC sample time.
-    /// Shall only be called when ADC is not converting.
-    pub fn set_sample_time_all_channels(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-
-        // Set all channels to use SMP1 field as source.
-        T::regs().smpr().modify(|w| {
-            w.smpsel(0);
-            w.set_smp1(sample_time);
-        });
-    }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        // Set single conversion mode.
-        T::regs().cfgr1().modify(|w| w.set_cont(false));
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Waiting for End Of Conversion (EOC).
-        while !T::regs().isr().read().eoc() {}
-
-        T::regs().dr().read().data() as u16
-    }
-
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel);
-        T::regs().cfgr1().write(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_align(Align::RIGHT);
-        });
-        self.convert()
-    }
-
-    fn setup_channel_sequencer<'a>(channel_sequence: impl ExactSizeIterator<Item = &'a mut AnyAdcChannel<T>>) {
-        assert!(
-            channel_sequence.len() <= CHSELR_SQ_SIZE,
-            "Seqenced read set cannot be more than {} in size.",
-            CHSELR_SQ_SIZE
-        );
-        let mut last_sq_set: usize = 0;
-        T::regs().chselr_sq().write(|w| {
-            for (i, channel) in channel_sequence.enumerate() {
-                assert!(
-                    channel.channel() <= CHSELR_SQ_MAX_CHANNEL,
-                    "Sequencer only support HW channels smaller than {}.",
-                    CHSELR_SQ_MAX_CHANNEL
-                );
-                w.set_sq(i, channel.channel());
-                last_sq_set = i;
-            }
-
-            for i in (last_sq_set + 1)..CHSELR_SQ_SIZE {
-                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
-            }
-        });
-
-        Self::apply_channel_conf()
-    }
-
-    async fn dma_convert(&mut self, rx_dma: Peri<'_, impl RxDma<T>>, readings: &mut [u16]) {
-        // Enable overrun control, so no new DMA requests will be generated until
-        // previous DR values is read.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-
-        // Set continuous mode with oneshot dma.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
-            reg.set_dmaen(true);
-            reg.set_ovrmod(Ovrmod::PRESERVE);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion.
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmacfg(Dmacfg::from_bits(0));
-            reg.set_dmaen(false);
-        });
-    }
-
-    /// Read one or multiple ADC channels using DMA in hardware order.
-    /// Readings will be ordered based on **hardware** ADC channel number and `scandir` setting.
-    /// Readings won't be in the same order as in the `set`!
-    ///
-    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
-    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
-    /// TODO(chudsaviet): externalize generic code and merge with read().
-    pub async fn read_in_hw_order(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        hw_channel_selection: u32,
-        scandir: Scandir,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            hw_channel_selection != 0,
-            "Some bits in `hw_channel_selection` shall be set."
-        );
-        assert!(
-            (hw_channel_selection >> NUM_HW_CHANNELS) == 0,
-            "STM32C0 only have {} ADC channels. `hw_channel_selection` cannot have bits higher than this number set.",
-            NUM_HW_CHANNELS
-        );
-        // To check for correct readings slice size, we shall solve Hamming weight problem,
-        // which is either slow or memory consuming.
-        // Since we have limited resources, we don't do it here.
-        // Not doing this have a great potential for a bug through.
-
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-            reg.set_scandir(scandir);
-            reg.set_align(Align::RIGHT);
-        });
-
-        // Set required channels for multi-convert.
-        unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
-
-        Self::apply_channel_conf();
-
-        self.dma_convert(rx_dma, readings).await
-    }
-
-    // Read ADC channels in specified order using DMA (CHSELRMOD = 1).
-    // In STM32C0, only lower 14 ADC channels can be read this way.
-    // For other channels, use `read_in_hw_order()` or blocking read.
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        channel_sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
-        readings: &mut [u16],
-    ) {
-        assert!(
-            channel_sequence.len() != 0,
-            "Asynchronous read channel sequence cannot be empty."
-        );
-        assert!(
-            channel_sequence.len() == readings.len(),
-            "Channel sequence length must be equal to readings length."
-        );
-
-        // Ensure no conversions are ongoing.
-        Self::cancel_conversions();
-
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(true);
-            reg.set_align(Align::RIGHT);
-        });
-
-        Self::setup_channel_sequencer(channel_sequence);
-
-        self.dma_convert(rx_dma, readings).await
-    }
-
-    fn configure_channel(channel: &mut impl AdcChannel<T>) {
-        channel.setup();
-        // write() because we want all other bits to be set to 0.
-        T::regs()
-            .chselr()
-            .write(|w| w.set_chsel(channel.channel().into(), true));
-
-        Self::apply_channel_conf();
-    }
-
-    fn apply_channel_conf() {
-        // Trigger and wait for the channel selection procedure to complete.
-        T::regs().isr().modify(|w| w.set_ccrdy(false));
-        while !T::regs().isr().read().ccrdy() {}
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
+        super::Temperature {}
     }
 }
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index 3cdc9d8fb..d6c6f480b 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -3,11 +3,11 @@ use core::marker::PhantomData;
 use core::task::Poll;
 
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::adc::{Adc, AdcChannel, Instance, SampleTime, VrefInt};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
 use crate::time::Hertz;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -28,20 +28,12 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
-pub struct Vref;
-impl<T: Instance> AdcChannel<T> for Vref {}
-impl<T: Instance> super::SealedAdcChannel<T> for Vref {
-    fn channel(&self) -> u8 {
-        17
-    }
+impl<T: Instance> super::SealedSpecialConverter<VrefInt> for T {
+    const CHANNEL: u8 = 17;
 }
 
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        16
-    }
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
 }
 
 impl<'d, T: Instance> Adc<'d, T> {
@@ -51,7 +43,7 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         // 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)
         // for at least two ADC clock cycles.
-        blocking_delay_us((1_000_000 * 2) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 2) / Self::freq().0 as u64 + 1);
 
         // Reset calibration
         T::regs().cr2().modify(|reg| reg.set_rstcal(true));
@@ -66,15 +58,12 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
 
         // One cycle after calibration
-        blocking_delay_us((1_000_000 * 1) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 1) / Self::freq().0 as u64 + 1);
 
         T::Interrupt::unpend();
         unsafe { T::Interrupt::enable() };
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
+        Self { adc }
     }
 
     fn freq() -> Hertz {
@@ -94,22 +83,18 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> super::VrefInt {
         T::regs().cr2().modify(|reg| {
             reg.set_tsvrefe(true);
         });
-        Vref {}
+        super::VrefInt {}
     }
 
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
         T::regs().cr2().modify(|reg| {
             reg.set_tsvrefe(true);
         });
-        Temperature {}
-    }
-
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
+        super::Temperature {}
     }
 
     /// Perform a single conversion.
@@ -134,8 +119,8 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().dr().read().0 as u16
     }
 
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::set_channel_sample_time(channel.channel(), self.sample_time);
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
+        Self::set_channel_sample_time(channel.channel(), sample_time);
         T::regs().cr1().modify(|reg| {
             reg.set_scan(false);
             reg.set_discen(false);
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index 3aeb6f2c7..29bfdac97 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -3,10 +3,10 @@ use core::marker::PhantomData;
 use core::task::Poll;
 
 use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::adc::{Adc, AdcChannel, Instance, SampleTime, VrefInt};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -29,27 +29,12 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
     }
 }
 
-pub struct Vref;
-impl<T: Instance> AdcChannel<T> for Vref {}
-impl<T: Instance> super::SealedAdcChannel<T> for Vref {
-    fn channel(&self) -> u8 {
-        18
-    }
-}
-
-impl Vref {
-    /// The value that vref would be if vdda was at 3300mv
-    pub fn value(&self) -> u16 {
-        crate::pac::VREFINTCAL.data().read()
-    }
+impl<T: Instance> super::SealedSpecialConverter<VrefInt> for T {
+    const CHANNEL: u8 = 18;
 }
 
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        16
-    }
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
 }
 
 impl<'d, T: Instance> Adc<'d, T> {
@@ -77,7 +62,7 @@ impl<'d, T: Instance> Adc<'d, T> {
         while T::regs().cr().read().adcal() {}
 
         // Wait more than 4 clock cycles after adcal is cleared (RM0364 p. 223).
-        blocking_delay_us((1_000_000 * 4) / Self::freq().0 + 1);
+        blocking_delay_us((1_000_000 * 4) / Self::freq().0 as u64 + 1);
 
         // Enable the adc
         T::regs().cr().modify(|w| w.set_aden(true));
@@ -90,10 +75,7 @@ impl<'d, T: Instance> Adc<'d, T> {
             T::Interrupt::enable();
         }
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
+        Self { adc }
     }
 
     fn freq() -> Hertz {
@@ -112,20 +94,16 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> super::VrefInt {
         T::common_regs().ccr().modify(|w| w.set_vrefen(true));
 
-        Vref {}
+        super::VrefInt {}
     }
 
-    pub fn enable_temperature(&self) -> Temperature {
+    pub fn enable_temperature(&self) -> super::Temperature {
         T::common_regs().ccr().modify(|w| w.set_tsen(true));
 
-        Temperature {}
-    }
-
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
+        super::Temperature {}
     }
 
     /// Perform a single conversion.
@@ -150,8 +128,8 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().dr().read().rdata()
     }
 
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::set_channel_sample_time(channel.channel(), self.sample_time);
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
+        Self::set_channel_sample_time(channel.channel(), sample_time);
 
         // Configure the channel to sample
         T::regs().sqr1().write(|w| w.set_sq(0, channel.channel()));
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 84613078c..919ac3cc0 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -9,7 +9,7 @@ use super::Resolution;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 const ADC_FREQ: Hertz = crate::rcc::HSI_FREQ;
 
@@ -79,7 +79,7 @@ impl<T: Instance> Vref<T> {
     }
 
     pub async fn calibrate(&mut self, adc: &mut Adc<'_, T>) -> Calibration {
-        let vref_val = adc.read(self).await;
+        let vref_val = adc.read(self, SampleTime::from(0)).await;
         Calibration {
             vref_cal: self.calibrated_value(),
             vref_val,
@@ -270,7 +270,8 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
+        self.set_sample_time(channel, sample_time).await;
         self.set_sample_sequence(&[channel.channel()]).await;
         self.convert().await
     }
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index 43498966f..1767a3bb3 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,175 +1,278 @@
+#[cfg(stm32g4)]
+use pac::adc::regs::Difsel as DifselReg;
+#[allow(unused)]
+#[cfg(stm32g4)]
+pub use pac::adc::vals::{Adcaldif, Adstp, Difsel, Dmacfg, Dmaen, Exten, Rovsm, Trovs};
 #[allow(unused)]
 #[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
-#[allow(unused)]
-#[cfg(stm32g4)]
-use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
-use pac::adccommon::vals::Presc;
-use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
+pub use pac::adccommon::vals::{Dual, Presc};
 
-use super::{blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime};
-use crate::adc::SealedAdcChannel;
-use crate::dma::Transfer;
+use super::{
+    Adc, AnyAdcChannel, ConversionMode, Instance, RegularConversionMode, Resolution, RxDma, SampleTime,
+    blocking_delay_us,
+};
+use crate::adc::{AnyInstance, SealedAdcChannel};
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
+
+mod injected;
+pub use injected::InjectedAdc;
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
+const NR_INJECTED_RANKS: usize = 4;
+
 /// Max single ADC operation clock frequency
 #[cfg(stm32g4)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance + VrefChannel> AdcChannel<T> for VrefInt {}
-impl<T: Instance + VrefChannel> super::SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        T::CHANNEL
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
     }
 }
 
-/// Internal temperature channel.
-pub struct Temperature;
-impl<T: Instance + TemperatureChannel> AdcChannel<T> for Temperature {}
-impl<T: Instance + TemperatureChannel> super::SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        T::CHANNEL
-    }
+/// ADC configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    pub dual_mode: Option<Dual>,
+    pub resolution: Option<Resolution>,
+    #[cfg(stm32g4)]
+    pub oversampling_shift: Option<u8>,
+    #[cfg(stm32g4)]
+    pub oversampling_ratio: Option<u8>,
+    #[cfg(stm32g4)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
 }
 
-/// Internal battery voltage channel.
-pub struct Vbat;
-impl<T: Instance + VBatChannel> AdcChannel<T> for Vbat {}
-impl<T: Instance + VBatChannel> super::SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        T::CHANNEL
-    }
+// Trigger source for ADC conversions¨
+#[derive(Copy, Clone)]
+pub struct ConversionTrigger {
+    // See Table 166 and 167 in RM0440 Rev 9 for ADC1/2 External triggers
+    // Note that Injected and Regular channels uses different mappings
+    pub channel: u8,
+    pub edge: Exten,
 }
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        // Make sure bits are off
+        while T::regs().cr().read().addis() {
+            // spin
+        }
+
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
 
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
         }
     }
 
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
+    fn start() {
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            // The software must poll ADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
+            while T::regs().cr().read().adstart() {}
         }
+
+        // Disable dma control and continuous conversion, if enabled
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(Dmaen::DISABLE);
+        });
     }
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
+    fn convert() -> u16 {
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
         }
+
+        T::regs().dr().read().0 as u16
     }
-}
 
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Create a new ADC driver.
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
+    fn configure_dma(conversion_mode: ConversionMode) {
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false); // Convert all channels for each trigger
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(Dmaen::ENABLE);
+        });
 
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        if let ConversionMode::Repeated(mode) = conversion_mode {
+            match mode {
+                RegularConversionMode::Continuous => {
+                    T::regs().cfgr().modify(|reg| {
+                        reg.set_cont(true);
+                    });
+                }
+                RegularConversionMode::Triggered(trigger) => {
+                    T::regs().cfgr().modify(|r| {
+                        r.set_cont(false); // New trigger is neede for each sample to be read
+                    });
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
-        trace!("ADC frequency set to {}", frequency);
+                    T::regs().cfgr().modify(|r| {
+                        r.set_extsel(trigger.channel);
+                        r.set_exten(trigger.edge);
+                    });
 
-        if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+                    // Regular conversions uses DMA so no need to generate interrupt
+                    T::regs().ier().modify(|r| r.set_eosie(false));
+                }
+            }
         }
+    }
+
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        T::regs().cr().modify(|w| w.set_aden(false));
 
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
-        s.power_up();
-        s.configure_differential_inputs();
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
 
-        s.calibrate();
-        blocking_delay_us(1);
+        #[cfg(stm32g4)]
+        let mut difsel = DifselReg::default();
+        let mut smpr = T::regs().smpr().read();
+        let mut smpr2 = T::regs().smpr2().read();
+        let mut sqr1 = T::regs().sqr1().read();
+        let mut sqr2 = T::regs().sqr2().read();
+        let mut sqr3 = T::regs().sqr3().read();
+        let mut sqr4 = T::regs().sqr4().read();
 
-        s.enable();
-        s.configure();
+        // Configure channels and ranks
+        for (_i, ((ch, is_differential), sample_time)) in sequence.enumerate() {
+            let sample_time = sample_time.into();
+            if ch <= 9 {
+                smpr.set_smp(ch as _, sample_time);
+            } else {
+                smpr2.set_smp((ch - 10) as _, sample_time);
+            }
 
-        s
+            match _i {
+                0..=3 => {
+                    sqr1.set_sq(_i, ch);
+                }
+                4..=8 => {
+                    sqr2.set_sq(_i - 4, ch);
+                }
+                9..=13 => {
+                    sqr3.set_sq(_i - 9, ch);
+                }
+                14..=15 => {
+                    sqr4.set_sq(_i - 14, ch);
+                }
+                _ => unreachable!(),
+            }
+
+            #[cfg(stm32g4)]
+            {
+                if ch < 18 {
+                    difsel.set_difsel(
+                        ch.into(),
+                        if is_differential {
+                            Difsel::DIFFERENTIAL
+                        } else {
+                            Difsel::SINGLE_ENDED
+                        },
+                    );
+                }
+            }
+        }
+
+        T::regs().smpr().write_value(smpr);
+        T::regs().smpr2().write_value(smpr2);
+        T::regs().sqr1().write_value(sqr1);
+        T::regs().sqr2().write_value(sqr2);
+        T::regs().sqr3().write_value(sqr3);
+        T::regs().sqr4().write_value(sqr4);
+        #[cfg(stm32g4)]
+        T::regs().difsel().write_value(difsel);
     }
+}
+
+impl<'d, T: Instance + AnyInstance> Adc<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        let prescaler = from_ker_ck(T::frequency());
+
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
+
+        let frequency = T::frequency() / prescaler;
+        trace!("ADC frequency set to {}", frequency);
+
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
+        }
 
-    fn power_up(&mut self) {
         T::regs().cr().modify(|reg| {
             reg.set_deeppwd(false);
             reg.set_advregen(true);
         });
 
         blocking_delay_us(20);
-    }
 
-    fn configure_differential_inputs(&mut self) {
         T::regs().difsel().modify(|w| {
             for n in 0..18 {
                 w.set_difsel(n, Difsel::SINGLE_ENDED);
             }
         });
-    }
 
-    fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
             w.set_adcaldif(Adcaldif::SINGLE_ENDED);
         });
@@ -189,120 +292,79 @@ impl<'d, T: Instance> Adc<'d, T> {
         while T::regs().cr().read().adcal() {}
 
         blocking_delay_us(20);
-    }
-
-    fn enable(&mut self) {
-        // Make sure bits are off
-        while T::regs().cr().read().addis() {
-            // spin
-        }
-
-        if !T::regs().cr().read().aden() {
-            // Enable ADC
-            T::regs().isr().modify(|reg| {
-                reg.set_adrdy(true);
-            });
-            T::regs().cr().modify(|reg| {
-                reg.set_aden(true);
-            });
 
-            while !T::regs().isr().read().adrdy() {
-                // spin
-            }
-        }
-    }
+        T::enable();
 
-    fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
             w.set_cont(false);
             w.set_exten(Exten::DISABLED);
         });
+
+        if let Some(dual) = config.dual_mode {
+            T::common_regs().ccr().modify(|reg| {
+                reg.set_dual(dual);
+            })
+        }
+
+        if let Some(resolution) = config.resolution {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+        }
+
+        #[cfg(stm32g4)]
+        if let Some(shift) = config.oversampling_shift {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        }
+
+        #[cfg(stm32g4)]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
+
+        #[cfg(stm32g4)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
-    pub fn enable_vrefint(&self) -> VrefInt
+    pub fn enable_vrefint(&self) -> super::VrefInt
     where
-        T: VrefChannel,
+        T: super::SpecialConverter<super::VrefInt>,
     {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vrefen(true);
         });
 
-        VrefInt {}
+        super::VrefInt {}
     }
 
     /// Enable reading the temperature internal channel.
-    pub fn enable_temperature(&self) -> Temperature
+    pub fn enable_temperature(&self) -> super::Temperature
     where
-        T: TemperatureChannel,
+        T: super::SpecialConverter<super::Temperature>,
     {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vsenseen(true);
         });
 
-        Temperature {}
+        super::Temperature {}
     }
 
     /// Enable reading the vbat internal channel.
-    pub fn enable_vbat(&self) -> Vbat
+    pub fn enable_vbat(&self) -> super::Vbat
     where
-        T: VBatChannel,
+        T: super::SpecialConverter<super::Vbat>,
     {
         T::common_regs().ccr().modify(|reg| {
             reg.set_vbaten(true);
         });
 
-        Vbat {}
-    }
-
-    /// Enable differential channel.
-    /// Caution:
-    /// : When configuring the channel “i” in differential input mode, its negative input voltage VINN[i]
-    /// is connected to another channel. As a consequence, this channel is no longer usable in
-    /// single-ended mode or in differential mode and must never be configured to be converted.
-    /// Some channels are shared between ADC1/ADC2/ADC3/ADC4/ADC5: this can make the
-    /// channel on the other ADC unusable. The only exception is when ADC master and the slave
-    /// operate in interleaved mode.
-    #[cfg(stm32g4)]
-    pub fn set_differential_channel(&mut self, ch: usize, enable: bool) {
-        T::regs().cr().modify(|w| w.set_aden(false)); // disable adc
-        T::regs().difsel().modify(|w| {
-            w.set_difsel(
-                ch,
-                if enable {
-                    Difsel::DIFFERENTIAL
-                } else {
-                    Difsel::SINGLE_ENDED
-                },
-            );
-        });
-        T::regs().cr().modify(|w| w.set_aden(true));
-    }
-
-    #[cfg(stm32g4)]
-    pub fn set_differential(&mut self, channel: &mut impl AdcChannel<T>, enable: bool) {
-        self.set_differential_channel(channel.channel() as usize, enable);
-    }
-
-    /// Set oversampling shift.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-
-    /// Set oversampling ratio.
-    #[cfg(stm32g4)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-
-    /// Enable oversampling in regular mode.
-    #[cfg(stm32g4)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        super::Vbat {}
     }
 
     // Reads that are not implemented as INJECTED in "blocking_read"
@@ -318,260 +380,215 @@ impl<'d, T: Instance> Adc<'d, T> {
     //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
     // }
 
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read an ADC pin.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        channel.setup();
-
-        self.read_channel(channel)
-    }
-
-    /// Read one or multiple ADC channels using DMA.
+    /// Configures the ADC for injected conversions.
     ///
-    /// `sequence` iterator and `readings` must have the same length.
+    /// Injected conversions are separate from the regular conversion sequence and are typically
+    /// triggered by software or an external event. This method sets up a fixed-length sequence of
+    /// injected channels with specified sample times, the trigger source, and whether the end-of-sequence
+    /// interrupt should be enabled.
     ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    /// # Parameters
+    /// - `sequence`: An array of tuples containing the ADC channels and their sample times. The length
+    ///   `N` determines the number of injected ranks to configure (maximum 4 for STM32).
+    /// - `trigger`: The trigger source that starts the injected conversion sequence.
+    /// - `interrupt`: If `true`, enables the end-of-sequence (JEOS) interrupt for injected conversions.
     ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin1 = p.PA1.into();
-    /// let mut measurements = [0u16; 2];
+    /// # Returns
+    /// An `InjectedAdc<T, N>` instance that represents the configured injected sequence. The returned
+    /// type encodes the sequence length `N` in its type, ensuring that reads return exactly `N` samples.
     ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
+    /// # Panics
+    /// This function will panic if:
+    /// - `sequence` is empty.
+    /// - `sequence` length exceeds the maximum number of injected ranks (`NR_INJECTED_RANKS`).
+    ///
+    /// # Notes
+    /// - Injected conversions can run independently of regular ADC conversions.
+    /// - The order of channels in `sequence` determines the rank order in the injected sequence.
+    /// - Accessing samples beyond `N` will result in a panic; use the returned type
+    ///   `InjectedAdc<T, N>` to enforce bounds at compile time.
+    pub fn setup_injected_conversions<'a, const N: usize>(
+        self,
+        sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        trigger: ConversionTrigger,
+        interrupt: bool,
+    ) -> InjectedAdc<T, N> {
+        assert!(N != 0, "Read sequence cannot be empty");
         assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
+            N <= NR_INJECTED_RANKS,
+            "Read sequence cannot be more than {} in length",
+            NR_INJECTED_RANKS
         );
 
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
-        self.enable();
-
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
+        T::enable();
 
-        // Configure channels and ranks
-        for (_i, (channel, sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
+        T::regs().jsqr().modify(|w| w.set_jl(N as u8 - 1));
 
-            match _i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(_i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(_i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(_i - 9, channel.channel());
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(_i - 14, channel.channel());
-                    });
-                }
-                _ => unreachable!(),
+        for (n, (channel, sample_time)) in sequence.into_iter().enumerate() {
+            let sample_time = sample_time.into();
+            if channel.channel() <= 9 {
+                T::regs()
+                    .smpr()
+                    .modify(|reg| reg.set_smp(channel.channel() as _, sample_time));
+            } else {
+                T::regs()
+                    .smpr2()
+                    .modify(|reg| reg.set_smp((channel.channel() - 10) as _, sample_time));
             }
-        }
-
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(Dmaen::ENABLE);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
 
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
+            let idx = match n {
+                0..=3 => n,
+                4..=8 => n - 4,
+                9..=13 => n - 9,
+                14..=15 => n - 14,
+                _ => unreachable!(),
+            };
 
-        // Wait for conversion sequence to finish.
-        transfer.await;
+            T::regs().jsqr().modify(|w| w.set_jsq(idx, channel.channel()));
+        }
 
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
+        T::regs().cfgr().modify(|reg| reg.set_jdiscen(false));
 
-        // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
+        // Set external trigger for injected conversion sequence
+        // Possible trigger values are seen in Table 167 in RM0440 Rev 9
+        T::regs().jsqr().modify(|r| {
+            r.set_jextsel(trigger.channel);
+            r.set_jexten(trigger.edge);
         });
-    }
-
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        // Configure channel
-        Self::set_channel_sample_time(channel.channel(), sample_time);
-    }
 
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel, self.sample_time);
-        #[cfg(stm32h7)]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
-        }
+        // Enable end of injected sequence interrupt
+        T::regs().ier().modify(|r| r.set_jeosie(interrupt));
 
-        T::regs().sqr1().write(|reg| {
-            reg.set_sq(0, channel.channel());
-            reg.set_l(0);
-        });
+        Self::start_injected_conversions();
 
-        self.convert()
+        InjectedAdc::new(sequence) // InjectedAdc<'a, T, N> now borrows the channels
     }
 
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+    /// Configures ADC for both regular conversions with a ring-buffered DMA and injected conversions.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral to use for the ring-buffered ADC transfers.
+    /// - `dma_buf`: The buffer to store DMA-transferred samples for regular conversions.
+    /// - `regular_sequence`: The sequence of channels and their sample times for regular conversions.
+    /// - `regular_conversion_mode`: The mode for regular conversions (e.g., continuous or triggered).
+    /// - `injected_sequence`: An array of channels and sample times for injected conversions (length `N`).
+    /// - `injected_trigger`: The trigger source for injected conversions.
+    /// - `injected_interrupt`: Whether to enable the end-of-sequence interrupt for injected conversions.
+    ///
+    /// Injected conversions are typically used with interrupts. If ADC1 and ADC2 are used in dual mode,
+    /// it is recommended to enable interrupts only for the ADC whose sequence takes the longest to complete.
+    ///
+    /// # Returns
+    /// A tuple containing:
+    /// 1. `RingBufferedAdc<'a, T>` — the configured ADC for regular conversions using DMA.
+    /// 2. `InjectedAdc<T, N>` — the configured ADC for injected conversions.
+    ///
+    /// # Safety
+    /// This function is `unsafe` because it clones the ADC peripheral handle unchecked. Both the
+    /// `RingBufferedAdc` and `InjectedAdc` take ownership of the handle and drop it independently.
+    /// Ensure no other code concurrently accesses the same ADC instance in a conflicting way.
+    pub fn into_ring_buffered_and_injected<'a, const N: usize>(
+        self,
+        dma: Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        regular_sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        regular_conversion_mode: RegularConversionMode,
+        injected_sequence: [(AnyAdcChannel<T>, SampleTime); N],
+        injected_trigger: ConversionTrigger,
+        injected_interrupt: bool,
+    ) -> (super::RingBufferedAdc<'a, T>, InjectedAdc<T, N>) {
+        unsafe {
+            (
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                }
+                .into_ring_buffered(dma, dma_buf, regular_sequence, regular_conversion_mode),
+                Self {
+                    adc: self.adc.clone_unchecked(),
+                }
+                .setup_injected_conversions(injected_sequence, injected_trigger, injected_interrupt),
+            )
         }
     }
 
-    fn cancel_conversions() {
+    /// Stop injected conversions
+    pub(super) fn stop_injected_conversions() {
         if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
             T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
+                reg.set_jadstp(Adstp::STOP);
             });
-            while T::regs().cr().read().adstart() {}
+            // The software must poll JADSTART until the bit is reset before assuming the
+            // ADC is completely stopped
+            while T::regs().cr().read().jadstart() {}
         }
     }
-}
 
-/// Implemented for ADCs that have a Temperature channel
-pub trait TemperatureChannel {
-    const CHANNEL: u8;
-}
-/// Implemented for ADCs that have a Vref channel
-pub trait VrefChannel {
-    const CHANNEL: u8;
+    /// Start injected ADC conversion
+    pub(super) fn start_injected_conversions() {
+        T::regs().cr().modify(|reg| {
+            reg.set_jadstart(true);
+        });
+    }
 }
-/// Implemented for ADCs that have a VBat channel
-pub trait VBatChannel {
-    const CHANNEL: u8;
+
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    /// Read sampled data from all injected ADC injected ranks
+    /// Clear the JEOS flag to allow a new injected sequence
+    pub(super) fn read_injected_data() -> [u16; N] {
+        let mut data = [0u16; N];
+        for i in 0..N {
+            data[i] = T::regs().jdr(i).read().jdata();
+        }
+
+        // Clear JEOS by writing 1
+        T::regs().isr().modify(|r| r.set_jeos(true));
+        data
+    }
 }
 
 #[cfg(stm32g4)]
 mod g4 {
-    pub use super::*;
+    use crate::adc::{SealedSpecialConverter, Temperature, Vbat, VrefInt};
 
-    impl TemperatureChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<Temperature> for crate::peripherals::ADC1 {
         const CHANNEL: u8 = 16;
     }
 
-    impl VrefChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC1 {
         const CHANNEL: u8 = 18;
     }
 
-    impl VBatChannel for crate::peripherals::ADC1 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC1 {
         const CHANNEL: u8 = 17;
     }
 
     #[cfg(peri_adc3_common)]
-    impl VrefChannel for crate::peripherals::ADC3 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC3 {
         const CHANNEL: u8 = 18;
     }
 
     #[cfg(peri_adc3_common)]
-    impl VBatChannel for crate::peripherals::ADC3 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC3 {
         const CHANNEL: u8 = 17;
     }
 
     #[cfg(not(stm32g4x1))]
-    impl VrefChannel for crate::peripherals::ADC4 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC4 {
         const CHANNEL: u8 = 18;
     }
 
     #[cfg(not(stm32g4x1))]
-    impl TemperatureChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<Temperature> for crate::peripherals::ADC5 {
         const CHANNEL: u8 = 4;
     }
 
     #[cfg(not(stm32g4x1))]
-    impl VrefChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<VrefInt> for crate::peripherals::ADC5 {
         const CHANNEL: u8 = 18;
     }
 
     #[cfg(not(stm32g4x1))]
-    impl VBatChannel for crate::peripherals::ADC5 {
+    impl SealedSpecialConverter<Vbat> for crate::peripherals::ADC5 {
         const CHANNEL: u8 = 17;
     }
 }
@@ -579,13 +596,13 @@ mod g4 {
 // TODO this should look at each ADC individually and impl the correct channels
 #[cfg(stm32h7)]
 mod h7 {
-    impl<T: Instance> TemperatureChannel for T {
+    impl<T: Instance> SealedSpecialConverter<Temperature> for T {
         const CHANNEL: u8 = 18;
     }
-    impl<T: Instance> VrefChannel for T {
+    impl<T: Instance> SealedSpecialConverter<VrefInt> for T {
         const CHANNEL: u8 = 19;
     }
-    impl<T: Instance> VBatChannel for T {
+    impl<T: Instance> SealedSpecialConverter<Vbat> for T {
         // TODO this should be 14 for H7a/b/35
         const CHANNEL: u8 = 17;
     }
diff --git a/embassy-stm32/src/adc/injected.rs b/embassy-stm32/src/adc/injected.rs
new file mode 100644
index 000000000..ccaa5d1b2
--- /dev/null
+++ b/embassy-stm32/src/adc/injected.rs
@@ -0,0 +1,44 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use super::{AnyAdcChannel, SampleTime};
+#[allow(unused_imports)]
+use crate::adc::Instance;
+use crate::adc::{Adc, AnyInstance};
+
+/// Injected ADC sequence with owned channels.
+pub struct InjectedAdc<T: Instance, const N: usize> {
+    _channels: [(AnyAdcChannel<T>, SampleTime); N],
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance, const N: usize> InjectedAdc<T, N> {
+    pub(crate) fn new(channels: [(AnyAdcChannel<T>, SampleTime); N]) -> Self {
+        Self {
+            _channels: channels,
+            _phantom: PhantomData,
+        }
+    }
+
+    pub fn stop_injected_conversions(&mut self) {
+        Adc::<T>::stop_injected_conversions()
+    }
+
+    pub fn start_injected_conversions(&mut self) {
+        Adc::<T>::start_injected_conversions()
+    }
+
+    pub fn read_injected_samples(&mut self) -> [u16; N] {
+        InjectedAdc::<T, N>::read_injected_data()
+    }
+}
+
+impl<T: Instance + AnyInstance, const N: usize> Drop for InjectedAdc<T, N> {
+    fn drop(&mut self) {
+        T::stop();
+        compiler_fence(Ordering::SeqCst);
+    }
+}
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index ea986f4cf..6d53d9b91 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -17,38 +17,38 @@
 #[cfg_attr(adc_c0, path = "c0.rs")]
 mod _version;
 
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+mod ringbuffered;
+
 use core::marker::PhantomData;
 
 #[allow(unused)]
 #[cfg(not(any(adc_f3v3, adc_wba)))]
 pub use _version::*;
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
 use embassy_sync::waitqueue::AtomicWaker;
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+pub use ringbuffered::RingBufferedAdc;
 
 #[cfg(any(adc_u5, adc_wba))]
 #[path = "adc4.rs"]
 pub mod adc4;
 
+#[allow(unused)]
+pub(self) use crate::block_for_us as blocking_delay_us;
 pub use crate::pac::adc::vals;
 #[cfg(not(any(adc_f1, adc_f3v3)))]
 pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 
-#[cfg(not(adc_wba))]
-dma_trait!(RxDma, Instance);
-#[cfg(adc_u5)]
-dma_trait!(RxDma4, adc4::Instance);
-#[cfg(adc_wba)]
-dma_trait!(RxDma4, adc4::Instance);
+dma_trait!(RxDma, AnyInstance);
 
 /// Analog to Digital driver.
-pub struct Adc<'d, T: Instance> {
+pub struct Adc<'d, T: AnyInstance> {
     #[allow(unused)]
     adc: crate::Peri<'d, T>,
-    #[cfg(not(any(adc_f3v3, adc_f3v2, adc_wba)))]
-    sample_time: SampleTime,
 }
 
 #[cfg(any(adc_f1, adc_f3v1, adc_v1, adc_l0, adc_f3v2))]
@@ -82,22 +82,318 @@ pub(crate) trait SealedAdcChannel<T> {
 
     #[allow(unused)]
     fn channel(&self) -> u8;
+
+    #[allow(unused)]
+    fn is_differential(&self) -> bool {
+        false
+    }
 }
 
-/// Performs a busy-wait delay for a specified number of microseconds.
-#[allow(unused)]
-pub(crate) fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
+// Temporary patch for ADCs that have not implemented the standard iface yet
+#[cfg(any(adc_v1, adc_l0, adc_f1, adc_f3v1, adc_f3v2, adc_f3v3, adc_v1))]
+trait_set::trait_set! {
+    pub trait AnyInstance = Instance;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+pub trait BasicAnyInstance {
+    type SampleTime;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+pub(self) trait SealedAnyInstance: BasicAnyInstance {
+    fn enable();
+    fn start();
+    fn stop();
+    fn convert() -> u16;
+    fn configure_dma(conversion_mode: ConversionMode);
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), Self::SampleTime)>);
+    #[allow(dead_code)]
+    fn dr() -> *mut u16;
+}
+
+// On chips without ADC4, AnyInstance is an Instance
+#[cfg(any(adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_g4, adc_c0))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + Instance {}
+
+// On chips with ADC4, AnyInstance is an Instance or adc4::Instance
+#[cfg(any(adc_v4, adc_u5, adc_wba))]
+#[allow(private_bounds)]
+pub trait AnyInstance: SealedAnyInstance + crate::PeripheralType + crate::rcc::RccPeripheral {}
+
+// Implement AnyInstance automatically for SealedAnyInstance
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> BasicAnyInstance for T {
+    type SampleTime = SampleTime;
+}
+
+#[cfg(any(
+    adc_v2, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_g4, adc_c0
+))]
+impl<T: SealedAnyInstance + Instance> AnyInstance for T {}
+
+#[cfg(any(adc_c0, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5))]
+/// Number of samples used for averaging.
+#[derive(Copy, Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples512,
+    #[cfg(any(adc_c0, adc_v4, adc_u5))]
+    Samples1024,
+}
+
+#[cfg(any(
+    adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0
+))]
+pub(crate) enum ConversionMode {
+    // Should match the cfg on "read" below
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    Singular,
+    // Should match the cfg on "into_ring_buffered" below
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    Repeated(RegularConversionMode),
+}
+
+// Should match the cfg on "into_ring_buffered" below
+#[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+// Conversion mode for regular ADC channels
+#[derive(Copy, Clone)]
+pub enum RegularConversionMode {
+    // Samples as fast as possible
+    Continuous,
+    #[cfg(adc_g4)]
+    // Sample at rate determined by external trigger
+    Triggered(ConversionTrigger),
+}
+
+impl<'d, T: AnyInstance> Adc<'d, T> {
+    #[cfg(any(
+        adc_v2, adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_u5, adc_v4, adc_wba, adc_c0
+    ))]
+    /// Read an ADC pin.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: T::SampleTime) -> u16 {
+        #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+        channel.setup();
+
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_v2, adc_v3, adc_g0, adc_h7rs, adc_u0, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+        T::configure_sequence([((channel.channel(), channel.is_differential()), sample_time)].into_iter());
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+
+        T::convert()
+    }
+
+    #[cfg(any(adc_g4, adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+    /// Read one or multiple ADC regular channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin1 = p.PA1.into();
+    /// let mut measurements = [0u16; 2];
+    ///
+    /// adc.read(
+    ///     p.DMA1_CH2.reborrow(),
+    ///     [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ]
+    ///     .into_iter(),
+    ///     &mut measurements,
+    /// )
+    /// .await;
+    /// defmt::info!("measurements: {}", measurements);
+    /// ```
+    ///
+    /// Note: This is not very efficient as the ADC needs to be reconfigured for each read. Use
+    /// `into_ring_buffered`, `into_ring_buffered_and_injected`
+    ///
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
+    pub async fn read(
+        &mut self,
+        rx_dma: embassy_hal_internal::Peri<'_, impl RxDma<T>>,
+        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, T::SampleTime)>,
+        readings: &mut [u16],
+    ) {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+        T::configure_dma(ConversionMode::Singular);
+
+        let request = rx_dma.request();
+        let transfer =
+            unsafe { crate::dma::Transfer::new_read(rx_dma, request, T::dr(), readings, Default::default()) };
+
+        T::start();
+
+        // Wait for conversion sequence to finish.
+        transfer.await;
+
+        // Ensure conversions are finished.
+        T::stop();
+    }
+
+    #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
+    ///
+    /// Use the [`read`] method to retrieve measurements from the DMA ring buffer. The read buffer
+    /// should be exactly half the size of `dma_buf`. When using triggered mode, it is recommended
+    /// to configure `dma_buf` as a double buffer so that one half can be read while the other half
+    /// is being filled by the DMA, preventing data loss. The trigger period of the ADC effectively
+    /// defines the period at which the buffer should be read.
+    ///
+    /// If continous conversion mode is selected, the provided `dma_buf` must be large enough to prevent
+    /// DMA buffer overruns. Its length should be a multiple of the number of ADC channels being measured.
+    /// For example, if 3 channels are measured and you want to store 40 samples per channel,
+    /// the buffer length should be `3 * 40 = 120`.
+    ///
+    /// # Parameters
+    /// - `dma`: The DMA peripheral used to transfer ADC data into the buffer.
+    /// - `dma_buf`: The buffer where DMA stores ADC samples.
+    /// - `regular_sequence`: Sequence of channels and sample times for regular ADC conversions.
+    /// - `regular_conversion_mode`: Mode for regular conversions (continuous or triggered).
+    ///
+    /// # Returns
+    /// A `RingBufferedAdc<'a, T>` instance configured for continuous DMA-based sampling.
+    ///
+    /// Note: Depending on hardware limitations, this method may require channels to be passed
+    /// in order or require the sequence to have the same sample time for all channnels, depending
+    /// on the number and properties of the channels in the sequence. This method will panic if
+    /// the hardware cannot deliver the requested configuration.
+    pub fn into_ring_buffered<'a>(
+        self,
+        dma: embassy_hal_internal::Peri<'a, impl RxDma<T>>,
+        dma_buf: &'a mut [u16],
+        sequence: impl ExactSizeIterator<Item = (AnyAdcChannel<T>, T::SampleTime)>,
+        mode: RegularConversionMode,
+    ) -> RingBufferedAdc<'a, T> {
+        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // Ensure no conversions are ongoing
+        T::stop();
+        #[cfg(any(adc_g0, adc_v3, adc_h7rs, adc_u0, adc_v4, adc_u5, adc_wba, adc_c0))]
+        T::enable();
+
+        T::configure_sequence(
+            sequence.map(|(channel, sample_time)| ((channel.channel, channel.is_differential), sample_time)),
+        );
+
+        // On chips with differential channels, enable after configure_sequence to allow setting differential channels
+        //
+        // TODO: If hardware allows, enable after configure_sequence on all chips
+        #[cfg(any(adc_g4, adc_h5))]
+        T::enable();
+        T::configure_dma(ConversionMode::Repeated(mode));
+
+        core::mem::forget(self);
+
+        RingBufferedAdc::new(dma, dma_buf)
     }
 }
 
+pub(self) trait SpecialChannel {}
+
+/// Implemented for ADCs that have a special channel
+trait SealedSpecialConverter<T: SpecialChannel + Sized> {
+    const CHANNEL: u8;
+}
+
+#[allow(private_bounds)]
+pub trait SpecialConverter<T: SpecialChannel + Sized>: SealedSpecialConverter<T> {}
+
+impl<C: SpecialChannel + Sized, T: SealedSpecialConverter<C>> SpecialConverter<C> for T {}
+
+impl<C: SpecialChannel, T: Instance + SealedSpecialConverter<C>> AdcChannel<T> for C {}
+impl<C: SpecialChannel, T: Instance + SealedSpecialConverter<C>> SealedAdcChannel<T> for C {
+    fn channel(&self) -> u8 {
+        T::CHANNEL
+    }
+}
+
+pub struct VrefInt;
+impl SpecialChannel for VrefInt {}
+
+impl VrefInt {
+    #[cfg(any(adc_f3v1, adc_f3v2))]
+    /// The value that vref would be if vdda was at 3300mv
+    pub fn calibrated_value(&self) -> u16 {
+        crate::pac::VREFINTCAL.data().read()
+    }
+}
+
+/// Internal temperature channel.
+pub struct Temperature;
+impl SpecialChannel for Temperature {}
+
+/// Internal battery voltage channel.
+pub struct Vbat;
+impl SpecialChannel for Vbat {}
+
+/// Vcore channel.
+pub struct Vcore;
+impl SpecialChannel for Vcore {}
+
+/// Internal dac channel.
+pub struct Dac;
+impl SpecialChannel for Dac {}
+
 /// ADC instance.
 #[cfg(not(any(
     adc_f1, adc_v1, adc_l0, adc_v2, adc_v3, adc_v4, adc_g4, adc_f3v1, adc_f3v2, adc_g0, adc_u0, adc_h5, adc_h7rs,
@@ -127,6 +423,7 @@ pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
 
         AnyAdcChannel {
             channel: self.channel(),
+            is_differential: self.is_differential(),
             _phantom: PhantomData,
         }
     }
@@ -138,14 +435,19 @@ pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
 /// storing them in an array.
 pub struct AnyAdcChannel<T> {
     channel: u8,
+    is_differential: bool,
     _phantom: PhantomData<T>,
 }
-impl_peripheral!(AnyAdcChannel<T: Instance>);
-impl<T: Instance> AdcChannel<T> for AnyAdcChannel<T> {}
-impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
+impl_peripheral!(AnyAdcChannel<T: AnyInstance>);
+impl<T: AnyInstance> AdcChannel<T> for AnyAdcChannel<T> {}
+impl<T: AnyInstance> SealedAdcChannel<T> for AnyAdcChannel<T> {
     fn channel(&self) -> u8 {
         self.channel
     }
+
+    fn is_differential(&self) -> bool {
+        self.is_differential
+    }
 }
 
 impl<T> AnyAdcChannel<T> {
@@ -264,6 +566,39 @@ macro_rules! impl_adc_pin {
     };
 }
 
+#[allow(unused_macros)]
+macro_rules! impl_adc_pair {
+    ($inst:ident, $pin:ident, $npin:ident, $ch:expr) => {
+        impl crate::adc::AdcChannel<peripherals::$inst>
+            for (
+                crate::Peri<'_, crate::peripherals::$pin>,
+                crate::Peri<'_, crate::peripherals::$npin>,
+            )
+        {
+        }
+        impl crate::adc::SealedAdcChannel<peripherals::$inst>
+            for (
+                crate::Peri<'_, crate::peripherals::$pin>,
+                crate::Peri<'_, crate::peripherals::$npin>,
+            )
+        {
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5, adc_wba))]
+            fn setup(&mut self) {
+                <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(&mut self.0);
+                <crate::peripherals::$npin as crate::gpio::SealedPin>::set_as_analog(&mut self.1);
+            }
+
+            fn channel(&self) -> u8 {
+                $ch
+            }
+
+            fn is_differential(&self) -> bool {
+                true
+            }
+        }
+    };
+}
+
 /// Get the maximum reading value for this resolution.
 ///
 /// This is `2**n - 1`.
diff --git a/embassy-stm32/src/adc/ringbuffered.rs b/embassy-stm32/src/adc/ringbuffered.rs
new file mode 100644
index 000000000..5437866d3
--- /dev/null
+++ b/embassy-stm32/src/adc/ringbuffered.rs
@@ -0,0 +1,180 @@
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+#[allow(unused_imports)]
+use embassy_hal_internal::Peri;
+
+use crate::adc::AnyInstance;
+#[allow(unused_imports)]
+use crate::adc::{Instance, RxDma};
+#[allow(unused_imports)]
+use crate::dma::{ReadableRingBuffer, TransferOptions};
+use crate::rcc;
+
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct OverrunError;
+
+pub struct RingBufferedAdc<'d, T: Instance> {
+    _phantom: PhantomData<T>,
+    ring_buf: ReadableRingBuffer<'d, u16>,
+}
+
+impl<'d, T: Instance + AnyInstance> RingBufferedAdc<'d, T> {
+    pub(crate) fn new(dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> Self {
+        //dma side setup
+        let opts = TransferOptions {
+            half_transfer_ir: true,
+            circular: true,
+            ..Default::default()
+        };
+
+        // Safety: we forget the struct before this function returns.
+        let request = dma.request();
+
+        let ring_buf =
+            unsafe { ReadableRingBuffer::new(dma, request, T::regs().dr().as_ptr() as *mut u16, dma_buf, opts) };
+
+        Self {
+            _phantom: PhantomData,
+            ring_buf,
+        }
+    }
+
+    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
+    pub fn start(&mut self) {
+        compiler_fence(Ordering::SeqCst);
+        self.ring_buf.start();
+
+        T::start();
+    }
+
+    pub fn stop(&mut self) {
+        self.ring_buf.request_pause();
+
+        compiler_fence(Ordering::SeqCst);
+    }
+
+    pub fn clear(&mut self) {
+        self.ring_buf.clear();
+    }
+
+    /// Reads measurements from the DMA ring buffer.
+    ///
+    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
+    /// The length of the `measurements` array should be exactly half of the DMA buffer length.
+    /// Because interrupts are only generated if half or full DMA transfer completes.
+    ///
+    /// Each call to `read` will populate the `measurements` array in the same order as the channels
+    /// defined with `sequence`. There will be many sequences worth of measurements in this array
+    /// because it only returns if at least half of the DMA buffer is filled. For example if 2
+    /// channels are sampled `measurements` contain: `[sq0 sq1 sq0 sq1 sq0 sq1 ..]`.
+    ///
+    /// Note that the ADC Datarate can be very fast, it is suggested to use DMA mode inside tightly
+    /// running tasks. Otherwise, you'll see constant Overrun errors occurring, this means that
+    /// you're sampling too quickly for the task to handle, and you may need to increase the buffer size.
+    /// Example:
+    /// ```rust,ignore
+    /// const DMA_BUF_LEN: usize = 120;
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.degrade_adc();
+    /// let mut adc_pin1 = p.PA1.degrade_adc();
+    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
+    ///
+    /// let mut ring_buffered_adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(
+    ///     p.DMA2_CH0,
+    ///      adc_dma_buf, [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ].into_iter());
+    ///
+    ///
+    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
+    /// loop {
+    ///     match ring_buffered_adc.read(&mut measurements).await {
+    ///         Ok(_) => {
+    ///             defmt::info!("adc1: {}", measurements);
+    ///         }
+    ///         Err(e) => {
+    ///             defmt::warn!("Error: {:?}", e);
+    ///         }
+    ///     }
+    /// }
+    /// ```
+    ///
+    ///
+    /// [`teardown_adc`]: #method.teardown_adc
+    /// [`start_continuous_sampling`]: #method.start_continuous_sampling
+    pub async fn read(&mut self, measurements: &mut [u16]) -> Result<usize, OverrunError> {
+        assert_eq!(
+            self.ring_buf.capacity() / 2,
+            measurements.len(),
+            "Buffer size must be half the size of the ring buffer"
+        );
+
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+
+        self.ring_buf.read_exact(measurements).await.map_err(|_| OverrunError)
+    }
+
+    /// Read bytes that are readily available in the ring buffer.
+    /// If no bytes are currently available in the buffer the call waits until the some
+    /// bytes are available (at least one byte and at most half the buffer size)
+    ///
+    /// Background receive is started if `start_continuous_sampling()` has not been previously called.
+    ///
+    /// Receive in the background is terminated if an error is returned.
+    /// It must then manually be started again by calling `start_continuous_sampling()` or by re-calling `blocking_read()`.
+    pub fn blocking_read(&mut self, buf: &mut [u16]) -> Result<usize, OverrunError> {
+        if !self.ring_buf.is_running() {
+            self.start();
+        }
+
+        #[cfg(adc_v2)]
+        {
+            // Clear overrun flag if set.
+            if T::regs().sr().read().ovr() {
+                self.stop();
+
+                return Err(OverrunError);
+            }
+        }
+        loop {
+            match self.ring_buf.read(buf) {
+                Ok((0, _)) => {}
+                Ok((len, _)) => {
+                    return Ok(len);
+                }
+                Err(_) => {
+                    self.ring_buf.request_pause();
+
+                    return Err(OverrunError);
+                }
+            }
+        }
+    }
+}
+
+impl<T: Instance + AnyInstance> Drop for RingBufferedAdc<'_, T> {
+    fn drop(&mut self) {
+        T::stop();
+
+        compiler_fence(Ordering::SeqCst);
+
+        self.ring_buf.request_pause();
+        rcc::disable::<T>();
+    }
+}
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
deleted file mode 100644
index 6f69e8486..000000000
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ /dev/null
@@ -1,432 +0,0 @@
-use core::marker::PhantomData;
-use core::mem;
-use core::sync::atomic::{compiler_fence, Ordering};
-
-use stm32_metapac::adc::vals::SampleTime;
-
-use crate::adc::{Adc, AdcChannel, Instance, RxDma};
-use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
-use crate::pac::adc::vals;
-use crate::{rcc, Peri};
-
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct OverrunError;
-
-fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
-    r.sr().modify(|regs| {
-        regs.set_eoc(false);
-        regs.set_ovr(false);
-    });
-}
-
-#[derive(PartialOrd, PartialEq, Debug, Clone, Copy)]
-pub enum Sequence {
-    One,
-    Two,
-    Three,
-    Four,
-    Five,
-    Six,
-    Seven,
-    Eight,
-    Nine,
-    Ten,
-    Eleven,
-    Twelve,
-    Thirteen,
-    Fourteen,
-    Fifteen,
-    Sixteen,
-}
-
-impl From<Sequence> for u8 {
-    fn from(s: Sequence) -> u8 {
-        match s {
-            Sequence::One => 0,
-            Sequence::Two => 1,
-            Sequence::Three => 2,
-            Sequence::Four => 3,
-            Sequence::Five => 4,
-            Sequence::Six => 5,
-            Sequence::Seven => 6,
-            Sequence::Eight => 7,
-            Sequence::Nine => 8,
-            Sequence::Ten => 9,
-            Sequence::Eleven => 10,
-            Sequence::Twelve => 11,
-            Sequence::Thirteen => 12,
-            Sequence::Fourteen => 13,
-            Sequence::Fifteen => 14,
-            Sequence::Sixteen => 15,
-        }
-    }
-}
-
-impl From<u8> for Sequence {
-    fn from(val: u8) -> Self {
-        match val {
-            0 => Sequence::One,
-            1 => Sequence::Two,
-            2 => Sequence::Three,
-            3 => Sequence::Four,
-            4 => Sequence::Five,
-            5 => Sequence::Six,
-            6 => Sequence::Seven,
-            7 => Sequence::Eight,
-            8 => Sequence::Nine,
-            9 => Sequence::Ten,
-            10 => Sequence::Eleven,
-            11 => Sequence::Twelve,
-            12 => Sequence::Thirteen,
-            13 => Sequence::Fourteen,
-            14 => Sequence::Fifteen,
-            15 => Sequence::Sixteen,
-            _ => panic!("Invalid sequence number"),
-        }
-    }
-}
-
-pub struct RingBufferedAdc<'d, T: Instance> {
-    _phantom: PhantomData<T>,
-    ring_buf: ReadableRingBuffer<'d, u16>,
-}
-
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Configures the ADC to use a DMA ring buffer for continuous data acquisition.
-    ///
-    /// The `dma_buf` should be large enough to prevent DMA buffer overrun.
-    /// The length of the `dma_buf` should be a multiple of the ADC channel count.
-    /// For example, if 3 channels are measured, its length can be 3 * 40 = 120 measurements.
-    ///
-    /// `read` method is used to read out measurements from the DMA ring buffer, and its buffer should be exactly half of the `dma_buf` length.
-    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
-    ///
-    /// [`read`]: #method.read
-    pub fn into_ring_buffered(self, dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> RingBufferedAdc<'d, T> {
-        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-
-        let opts: crate::dma::TransferOptions = TransferOptions {
-            half_transfer_ir: true,
-            priority: Priority::VeryHigh,
-            ..Default::default()
-        };
-
-        // Safety: we forget the struct before this function returns.
-        let rx_src = T::regs().dr().as_ptr() as *mut u16;
-        let request = dma.request();
-
-        let ring_buf = unsafe { ReadableRingBuffer::new(dma, request, rx_src, dma_buf, opts) };
-
-        // Don't disable the clock
-        mem::forget(self);
-
-        RingBufferedAdc {
-            _phantom: PhantomData,
-            ring_buf,
-        }
-    }
-}
-
-impl<'d, T: Instance> RingBufferedAdc<'d, T> {
-    fn is_on() -> bool {
-        T::regs().cr2().read().adon()
-    }
-
-    fn stop_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(false);
-        });
-    }
-
-    fn start_adc() {
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-        });
-    }
-
-    /// Sets the channel sample time
-    ///
-    /// ## SAFETY:
-    /// - ADON == 0 i.e ADC must not be enabled when this is called.
-    unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        if ch <= 9 {
-            T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-
-    fn set_channels_sample_time(&mut self, ch: &[u8], sample_time: SampleTime) {
-        let ch_iter = ch.iter();
-        for idx in ch_iter {
-            unsafe {
-                Self::set_channel_sample_time(*idx, sample_time);
-            }
-        }
-    }
-
-    pub fn set_sample_sequence(
-        &mut self,
-        sequence: Sequence,
-        channel: &mut impl AdcChannel<T>,
-        sample_time: SampleTime,
-    ) {
-        let was_on = Self::is_on();
-        if !was_on {
-            Self::start_adc();
-        }
-
-        // Check the sequence is long enough
-        T::regs().sqr1().modify(|r| {
-            let prev: Sequence = r.l().into();
-            if prev < sequence {
-                let new_l: Sequence = sequence;
-                trace!("Setting sequence length from {:?} to {:?}", prev as u8, new_l as u8);
-                r.set_l(sequence.into())
-            } else {
-                r.set_l(prev.into())
-            }
-        });
-
-        // Set this GPIO as an analog input.
-        channel.setup();
-
-        // Set the channel in the right sequence field.
-        match sequence {
-            Sequence::One => T::regs().sqr3().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Two => T::regs().sqr3().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Three => T::regs().sqr3().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Four => T::regs().sqr3().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Five => T::regs().sqr3().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Six => T::regs().sqr3().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Seven => T::regs().sqr2().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Eight => T::regs().sqr2().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Nine => T::regs().sqr2().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Ten => T::regs().sqr2().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Eleven => T::regs().sqr2().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Twelve => T::regs().sqr2().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Thirteen => T::regs().sqr1().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Fourteen => T::regs().sqr1().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Fifteen => T::regs().sqr1().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Sixteen => T::regs().sqr1().modify(|w| w.set_sq(3, channel.channel())),
-        };
-
-        if !was_on {
-            Self::stop_adc();
-        }
-
-        self.set_channels_sample_time(&[channel.channel()], sample_time);
-
-        Self::start_adc();
-    }
-
-    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
-    pub fn start(&mut self) -> Result<(), OverrunError> {
-        self.setup_adc();
-        self.ring_buf.clear();
-
-        Ok(())
-    }
-
-    fn stop(&mut self, err: OverrunError) -> Result<usize, OverrunError> {
-        self.teardown_adc();
-        Err(err)
-    }
-
-    /// Stops DMA transfer.
-    /// It does not turn off ADC.
-    /// Calling `start` restarts continuous DMA transfer.
-    ///
-    /// [`start`]: #method.start
-    pub fn teardown_adc(&mut self) {
-        // Stop the DMA transfer
-        self.ring_buf.request_pause();
-
-        let r = T::regs();
-
-        // Stop ADC
-        r.cr2().modify(|reg| {
-            // Stop ADC
-            reg.set_swstart(false);
-            // Stop DMA
-            reg.set_dma(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Disable interrupt for end of conversion
-            w.set_eocie(false);
-            // Disable interrupt for overrun
-            w.set_ovrie(false);
-        });
-
-        clear_interrupt_flags(r);
-
-        compiler_fence(Ordering::SeqCst);
-    }
-
-    fn setup_adc(&mut self) {
-        compiler_fence(Ordering::SeqCst);
-
-        self.ring_buf.start();
-
-        let r = T::regs();
-
-        // Enable ADC
-        let was_on = Self::is_on();
-        if !was_on {
-            r.cr2().modify(|reg| {
-                reg.set_adon(false);
-                reg.set_swstart(false);
-            });
-        }
-
-        // Clear all interrupts
-        r.sr().modify(|regs| {
-            regs.set_eoc(false);
-            regs.set_ovr(false);
-            regs.set_strt(false);
-        });
-
-        r.cr1().modify(|w| {
-            // Enable interrupt for end of conversion
-            w.set_eocie(true);
-            // Enable interrupt for overrun
-            w.set_ovrie(true);
-            // Scanning converisons of multiple channels
-            w.set_scan(true);
-            // Continuous conversion mode
-            w.set_discen(false);
-        });
-
-        r.cr2().modify(|w| {
-            // Enable DMA mode
-            w.set_dma(true);
-            // Enable continuous conversions
-            w.set_cont(true);
-            // DMA requests are issues as long as DMA=1 and data are converted.
-            w.set_dds(vals::Dds::CONTINUOUS);
-            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACH_CONVERSION);
-        });
-
-        // Begin ADC conversions
-        T::regs().cr2().modify(|reg| {
-            reg.set_adon(true);
-            reg.set_swstart(true);
-        });
-
-        super::blocking_delay_us(3);
-    }
-
-    /// Read bytes that are readily available in the ring buffer.
-    /// If no bytes are currently available in the buffer the call waits until the some
-    /// bytes are available (at least one byte and at most half the buffer size)
-    ///
-    /// Background receive is started if `start()` has not been previously called.
-    ///
-    /// Receive in the background is terminated if an error is returned.
-    /// It must then manually be started again by calling `start()` or by re-calling `read()`.
-    pub fn blocking_read<const N: usize>(&mut self, buf: &mut [u16; N]) -> Result<usize, OverrunError> {
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-
-        loop {
-            match self.ring_buf.read(buf) {
-                Ok((0, _)) => {}
-                Ok((len, _)) => {
-                    return Ok(len);
-                }
-                Err(_) => {
-                    return self.stop(OverrunError);
-                }
-            }
-        }
-    }
-
-    /// Reads measurements from the DMA ring buffer.
-    ///
-    /// This method fills the provided `measurements` array with ADC readings from the DMA buffer.
-    /// The length of the `measurements` array should be exactly half of the DMA buffer length. Because interrupts are only generated if half or full DMA transfer completes.
-    ///
-    /// Each call to `read` will populate the `measurements` array in the same order as the channels defined with `set_sample_sequence`.
-    /// There will be many sequences worth of measurements in this array because it only returns if at least half of the DMA buffer is filled.
-    /// For example if 3 channels are sampled `measurements` contain: `[sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3 sq0 sq1 sq3..]`.
-    ///
-    /// If an error is returned, it indicates a DMA overrun, and the process must be restarted by calling `start` or `read` again.
-    ///
-    /// By default, the ADC fills the DMA buffer as quickly as possible. To control the sample rate, call `teardown_adc` after each readout, and then start the DMA again at the desired interval.
-    /// Note that even if using `teardown_adc` to control the sample rate, with each call to `read`, measurements equivalent to half the size of the DMA buffer are still collected.
-    ///
-    /// Example:
-    /// ```rust,ignore
-    /// const DMA_BUF_LEN: usize = 120;
-    /// let adc_dma_buf = [0u16; DMA_BUF_LEN];
-    /// let mut adc: RingBufferedAdc<embassy_stm32::peripherals::ADC1> = adc.into_ring_buffered(p.DMA2_CH0, adc_dma_buf);
-    ///
-    /// adc.set_sample_sequence(Sequence::One, &mut p.PA0, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Two, &mut p.PA1, SampleTime::CYCLES112);
-    /// adc.set_sample_sequence(Sequence::Three, &mut p.PA2, SampleTime::CYCLES112);
-    ///
-    /// let mut measurements = [0u16; DMA_BUF_LEN / 2];
-    /// loop {
-    ///     match adc.read(&mut measurements).await {
-    ///         Ok(_) => {
-    ///             defmt::info!("adc1: {}", measurements);
-    ///             // Only needed to manually control sample rate.
-    ///             adc.teardown_adc();
-    ///         }
-    ///         Err(e) => {
-    ///             defmt::warn!("Error: {:?}", e);
-    ///             // DMA overrun, next call to `read` restarts ADC.
-    ///         }
-    ///     }
-    ///
-    ///     // Manually control sample rate.
-    ///     Timer::after_millis(100).await;
-    /// }
-    /// ```
-    ///
-    ///
-    /// [`set_sample_sequence`]: #method.set_sample_sequence
-    /// [`teardown_adc`]: #method.teardown_adc
-    /// [`start`]: #method.start
-    pub async fn read<const N: usize>(&mut self, measurements: &mut [u16; N]) -> Result<usize, OverrunError> {
-        assert_eq!(
-            self.ring_buf.capacity() / 2,
-            N,
-            "Buffer size must be half the size of the ring buffer"
-        );
-
-        let r = T::regs();
-
-        // Start background receive if it was not already started
-        if !r.cr2().read().dma() {
-            self.start()?;
-        }
-
-        // Clear overrun flag if set.
-        if r.sr().read().ovr() {
-            return self.stop(OverrunError);
-        }
-        match self.ring_buf.read_exact(measurements).await {
-            Ok(len) => Ok(len),
-            Err(_) => self.stop(OverrunError),
-        }
-    }
-}
-
-impl<T: Instance> Drop for RingBufferedAdc<'_, T> {
-    fn drop(&mut self) {
-        self.teardown_adc();
-        rcc::disable::<T>();
-    }
-}
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index d09374876..58c30935f 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -5,11 +5,12 @@ use core::task::Poll;
 #[cfg(adc_l0)]
 use stm32_metapac::adc::vals::Ckmode;
 
-use super::blocking_delay_us;
+#[cfg(not(adc_l0))]
+use super::Vbat;
+use super::{Temperature, VrefInt, blocking_delay_us};
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
-use crate::peripherals::ADC1;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 mod watchdog_v1;
 pub use watchdog_v1::WatchdogChannels;
@@ -42,36 +43,23 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 }
 
 #[cfg(not(adc_l0))]
-pub struct Vbat;
-
-#[cfg(not(adc_l0))]
-impl AdcChannel<ADC1> for Vbat {}
+impl super::SealedSpecialConverter<super::Vbat> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
+}
 
 #[cfg(not(adc_l0))]
-impl super::SealedAdcChannel<ADC1> for Vbat {
-    fn channel(&self) -> u8 {
-        18
-    }
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 17;
 }
 
-pub struct Vref;
-impl AdcChannel<ADC1> for Vref {}
-impl super::SealedAdcChannel<ADC1> for Vref {
-    fn channel(&self) -> u8 {
-        17
-    }
+#[cfg(adc_l0)]
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
 }
 
-pub struct Temperature;
-impl AdcChannel<ADC1> for Temperature {}
-impl super::SealedAdcChannel<ADC1> for Temperature {
-    fn channel(&self) -> u8 {
-        if cfg!(adc_l0) {
-            18
-        } else {
-            16
-        }
-    }
+#[cfg(not(adc_l0))]
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 16;
 }
 
 impl<'d, T: Instance> Adc<'d, T> {
@@ -118,10 +106,7 @@ impl<'d, T: Instance> Adc<'d, T> {
             T::Interrupt::enable();
         }
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
+        Self { adc }
     }
 
     #[cfg(not(adc_l0))]
@@ -134,12 +119,12 @@ impl<'d, T: Instance> Adc<'d, T> {
         Vbat
     }
 
-    pub fn enable_vref(&self) -> Vref {
+    pub fn enable_vref(&self) -> VrefInt {
         // Table 28. Embedded internal reference voltage
         // tstart = 10μs
         T::regs().ccr().modify(|reg| reg.set_vrefen(true));
         blocking_delay_us(10);
-        Vref
+        VrefInt
     }
 
     pub fn enable_temperature(&self) -> Temperature {
@@ -153,10 +138,6 @@ impl<'d, T: Instance> Adc<'d, T> {
         Temperature
     }
 
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-
     pub fn set_resolution(&mut self, resolution: Resolution) {
         T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
     }
@@ -167,12 +148,13 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode));
     }
 
-    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+    pub async fn read(&mut self, channel: &mut impl AdcChannel<T>, sample_time: SampleTime) -> u16 {
         let ch_num = channel.channel();
         channel.setup();
 
         // A.7.5 Single conversion sequence code example - Software trigger
         T::regs().chselr().write(|reg| reg.set_chsel_x(ch_num as usize, true));
+        T::regs().smpr().modify(|reg| reg.set_smp(sample_time.into()));
 
         self.convert().await
     }
@@ -183,7 +165,6 @@ impl<'d, T: Instance> Adc<'d, T> {
             reg.set_eosmp(true);
         });
 
-        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
         T::regs().ier().modify(|w| w.set_eocie(true));
         T::regs().cr().modify(|reg| reg.set_adstart(true));
 
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index e94a25b24..3c4431ae0 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,23 +1,40 @@
-use super::blocking_delay_us;
-use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
-use crate::peripherals::ADC1;
+use core::sync::atomic::{Ordering, compiler_fence};
+
+use super::{ConversionMode, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::{Adc, Instance, Resolution, SampleTime};
+use crate::pac::adc::vals;
+pub use crate::pac::adccommon::vals::Adcpre;
 use crate::time::Hertz;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
-mod ringbuffered_v2;
-pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
+fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
+    r.sr().modify(|regs| {
+        regs.set_eoc(false);
+        regs.set_ovr(false);
+    });
+}
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
 /// VREF voltage used for factory calibration of VREFINTCAL register.
 pub const VREF_CALIB_MV: u32 = 3300;
 
-pub struct VrefInt;
-impl AdcChannel<ADC1> for VrefInt {}
-impl super::SealedAdcChannel<ADC1> for VrefInt {
-    fn channel(&self) -> u8 {
-        17
-    }
+impl super::SealedSpecialConverter<super::VrefInt> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 17;
+}
+
+#[cfg(any(stm32f2, stm32f40x, stm32f41x))]
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 16;
+}
+
+#[cfg(not(any(stm32f2, stm32f40x, stm32f41x)))]
+impl super::SealedSpecialConverter<super::Temperature> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
+}
+
+impl super::SealedSpecialConverter<super::Vbat> for crate::peripherals::ADC1 {
+    const CHANNEL: u8 = 18;
 }
 
 impl VrefInt {
@@ -27,20 +44,6 @@ impl VrefInt {
     }
 }
 
-pub struct Temperature;
-impl AdcChannel<ADC1> for Temperature {}
-impl super::SealedAdcChannel<ADC1> for Temperature {
-    fn channel(&self) -> u8 {
-        cfg_if::cfg_if! {
-            if #[cfg(any(stm32f2, stm32f40x, stm32f41x))] {
-                16
-            } else {
-                18
-            }
-        }
-    }
-}
-
 impl Temperature {
     /// Time needed for temperature sensor readings to stabilize
     pub fn start_time_us() -> u32 {
@@ -48,76 +51,176 @@ impl Temperature {
     }
 }
 
-pub struct Vbat;
-impl AdcChannel<ADC1> for Vbat {}
-impl super::SealedAdcChannel<ADC1> for Vbat {
-    fn channel(&self) -> u8 {
-        18
+fn from_pclk2(freq: Hertz) -> Adcpre {
+    // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
+    #[cfg(stm32f2)]
+    const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
+    // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
+    #[cfg(not(stm32f2))]
+    const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
+    let raw_div = rcc::raw_prescaler(freq.0, MAX_FREQUENCY.0);
+    match raw_div {
+        0..=1 => Adcpre::DIV2,
+        2..=3 => Adcpre::DIV4,
+        4..=5 => Adcpre::DIV6,
+        6..=7 => Adcpre::DIV8,
+        _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
     }
 }
 
-enum Prescaler {
-    Div2,
-    Div4,
-    Div6,
-    Div8,
+/// ADC configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    resolution: Option<Resolution>,
 }
 
-impl Prescaler {
-    fn from_pclk2(freq: Hertz) -> Self {
-        // Datasheet for F2 specifies min frequency 0.6 MHz, and max 30 MHz (with VDDA 2.4-3.6V).
-        #[cfg(stm32f2)]
-        const MAX_FREQUENCY: Hertz = Hertz(30_000_000);
-        // Datasheet for both F4 and F7 specifies min frequency 0.6 MHz, typ freq. 30 MHz and max 36 MHz.
-        #[cfg(not(stm32f2))]
-        const MAX_FREQUENCY: Hertz = Hertz(36_000_000);
-        let raw_div = freq.0 / MAX_FREQUENCY.0;
-        match raw_div {
-            0..=1 => Self::Div2,
-            2..=3 => Self::Div4,
-            4..=5 => Self::Div6,
-            6..=7 => Self::Div8,
-            _ => panic!("Selected PCLK2 frequency is too high for ADC with largest possible prescaler."),
-        }
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        T::regs().cr2().modify(|reg| {
+            reg.set_adon(true);
+        });
+
+        blocking_delay_us(3);
+    }
+
+    fn start() {
+        // Begin ADC conversions
+        T::regs().cr2().modify(|reg| {
+            reg.set_swstart(true);
+        });
+    }
+
+    fn stop() {
+        let r = T::regs();
+
+        // Stop ADC
+        r.cr2().modify(|reg| {
+            // Stop ADC
+            reg.set_swstart(false);
+            // Stop ADC
+            reg.set_adon(false);
+            // Stop DMA
+            reg.set_dma(false);
+        });
+
+        r.cr1().modify(|w| {
+            // Disable interrupt for end of conversion
+            w.set_eocie(false);
+            // Disable interrupt for overrun
+            w.set_ovrie(false);
+        });
+
+        clear_interrupt_flags(r);
+
+        compiler_fence(Ordering::SeqCst);
     }
 
-    fn adcpre(&self) -> crate::pac::adccommon::vals::Adcpre {
-        match self {
-            Prescaler::Div2 => crate::pac::adccommon::vals::Adcpre::DIV2,
-            Prescaler::Div4 => crate::pac::adccommon::vals::Adcpre::DIV4,
-            Prescaler::Div6 => crate::pac::adccommon::vals::Adcpre::DIV6,
-            Prescaler::Div8 => crate::pac::adccommon::vals::Adcpre::DIV8,
+    fn convert() -> u16 {
+        // clear end of conversion flag
+        T::regs().sr().modify(|reg| {
+            reg.set_eoc(false);
+        });
+
+        // Start conversion
+        T::regs().cr2().modify(|reg| {
+            reg.set_swstart(true);
+        });
+
+        while T::regs().sr().read().strt() == false {
+            // spin //wait for actual start
+        }
+        while T::regs().sr().read().eoc() == false {
+            // spin //wait for finish
         }
+
+        T::regs().dr().read().0 as u16
     }
-}
 
-impl<'d, T> Adc<'d, T>
-where
-    T: Instance,
-{
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
+    fn configure_dma(conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Repeated(_) => {
+                let r = T::regs();
+
+                // Clear all interrupts
+                r.sr().modify(|regs| {
+                    regs.set_eoc(false);
+                    regs.set_ovr(false);
+                    regs.set_strt(false);
+                });
+
+                r.cr1().modify(|w| {
+                    // Enable interrupt for end of conversion
+                    w.set_eocie(true);
+                    // Enable interrupt for overrun
+                    w.set_ovrie(true);
+                    // Scanning converisons of multiple channels
+                    w.set_scan(true);
+                    // Continuous conversion mode
+                    w.set_discen(false);
+                });
+
+                r.cr2().modify(|w| {
+                    // Enable DMA mode
+                    w.set_dma(true);
+                    // Enable continuous conversions
+                    w.set_cont(true);
+                    // DMA requests are issues as long as DMA=1 and data are converted.
+                    w.set_dds(vals::Dds::CONTINUOUS);
+                    // EOC flag is set at the end of each conversion.
+                    w.set_eocs(vals::Eocs::EACH_CONVERSION);
+                });
+            }
+        }
+    }
 
-        let presc = Prescaler::from_pclk2(T::frequency());
-        T::common_regs().ccr().modify(|w| w.set_adcpre(presc.adcpre()));
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
         T::regs().cr2().modify(|reg| {
             reg.set_adon(true);
         });
 
-        blocking_delay_us(3);
+        // Check the sequence is long enough
+        T::regs().sqr1().modify(|r| {
+            r.set_l((sequence.len() - 1).try_into().unwrap());
+        });
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
+        for (i, ((ch, _), sample_time)) in sequence.enumerate() {
+            // Set the channel in the right sequence field.
+            T::regs().sqr3().modify(|w| w.set_sq(i, ch));
+
+            let sample_time = sample_time.into();
+            if ch <= 9 {
+                T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
+            } else {
+                T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
+            }
         }
     }
+}
 
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
+impl<'d, T> Adc<'d, T>
+where
+    T: Instance + super::AnyInstance,
+{
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::new_with_config(adc, Default::default())
     }
 
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        let presc = from_pclk2(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_adcpre(presc));
+        T::enable();
+
+        if let Some(resolution) = config.resolution {
+            T::regs().cr1().modify(|reg| reg.set_res(resolution.into()));
+        }
+
+        Self { adc }
     }
 
     /// Enables internal voltage reference and returns [VrefInt], which can be used in
@@ -152,52 +255,6 @@ where
 
         Vbat {}
     }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        // clear end of conversion flag
-        T::regs().sr().modify(|reg| {
-            reg.set_eoc(false);
-        });
-
-        // Start conversion
-        T::regs().cr2().modify(|reg| {
-            reg.set_swstart(true);
-        });
-
-        while T::regs().sr().read().strt() == false {
-            // spin //wait for actual start
-        }
-        while T::regs().sr().read().eoc() == false {
-            // spin //wait for finish
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        channel.setup();
-
-        // Configure ADC
-        let channel = channel.channel();
-
-        // Select channel
-        T::regs().sqr3().write(|reg| reg.set_sq(0, channel));
-
-        // Configure channel
-        Self::set_channel_sample_time(channel, self.sample_time);
-
-        self.convert()
-    }
-
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
 }
 
 impl<'d, T: Instance> Drop for Adc<'d, T> {
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 16063ce4d..b270588c4 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,19 +1,19 @@
 use cfg_if::cfg_if;
 #[cfg(adc_g0)]
 use heapless::Vec;
-use pac::adc::vals::Dmacfg;
 #[cfg(adc_g0)]
-use pac::adc::vals::{Ckmode, Smpsel};
+use pac::adc::vals::Ckmode;
+use pac::adc::vals::Dmacfg;
 #[cfg(adc_v3)]
 use pac::adc::vals::{OversamplingRatio, OversamplingShift, Rovsm, Trovs};
 #[cfg(adc_g0)]
 pub use pac::adc::vals::{Ovsr, Ovss, Presc};
 
-use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
-};
-use crate::dma::Transfer;
-use crate::{pac, rcc, Peri};
+#[allow(unused_imports)]
+use super::SealedAdcChannel;
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -25,70 +25,64 @@ pub const VREF_CALIB_MV: u32 = 3000;
 // TODO: Use [#![feature(variant_count)]](https://github.com/rust-lang/rust/issues/73662) when stable
 const SAMPLE_TIMES_CAPACITY: usize = 2;
 
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 13;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 17;
-            } else if #[cfg(adc_u0)] {
-                let val = 12;
-            } else {
-                let val = 0;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 13;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 17;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 12;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 0;
 }
 
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 12;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 16;
-            } else if #[cfg(adc_u0)] {
-                let val = 11;
-            } else {
-                let val = 17;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 12;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 11;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 17;
 }
 
-pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        cfg_if! {
-            if #[cfg(adc_g0)] {
-                let val = 14;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 2;
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                let val = 13;
-            } else {
-                let val = 18;
-            }
-        }
-        val
-    }
+#[cfg(adc_g0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 14;
+}
+#[cfg(any(adc_h5, adc_h7rs))]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 16;
+}
+#[cfg(adc_u0)]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 13;
+}
+#[cfg(not(any(adc_g0, adc_h5, adc_h7rs, adc_u0)))]
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 18;
 }
 
 cfg_if! {
     if #[cfg(any(adc_h5, adc_h7rs))] {
         pub struct VddCore;
-        impl<T: Instance> AdcChannel<T> for VddCore {}
+        impl<T: Instance> super::AdcChannel<T> for VddCore {}
         impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
             fn channel(&self) -> u8 {
-                6
+                17
             }
         }
     }
@@ -97,7 +91,7 @@ cfg_if! {
 cfg_if! {
     if #[cfg(adc_u0)] {
         pub struct DacOut;
-        impl<T: Instance> AdcChannel<T> for DacOut {}
+        impl<T: Instance> super::AdcChannel<T> for DacOut {}
         impl<T: Instance> super::SealedAdcChannel<T> for DacOut {
             fn channel(&self) -> u8 {
                 19
@@ -106,21 +100,6 @@ cfg_if! {
     }
 }
 
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-}
-
 cfg_if! { if #[cfg(adc_g0)] {
 
 /// Synchronous PCLK prescaler
@@ -141,91 +120,39 @@ pub enum Clock {
 
 }}
 
-impl<'d, T: Instance> Adc<'d, T> {
-    /// Enable the voltage regulator
-    fn init_regulator() {
-        rcc::enable_and_reset::<T>();
-        T::regs().cr().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_deeppwd(false);
-            reg.set_advregen(true);
-        });
-
-        // If this is false then each ADC_CHSELR bit enables an input channel.
-        // This is the reset value, so has no effect.
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_chselrmod(false);
-        });
-
-        blocking_delay_us(20);
-    }
-
-    /// Calibrate to remove conversion offset
-    fn init_calibrate() {
-        T::regs().cr().modify(|reg| {
-            reg.set_adcal(true);
-        });
-
-        while T::regs().cr().read().adcal() {
-            // spin
-        }
-
-        blocking_delay_us(1);
-    }
-
-    /// Initialize the ADC leaving any analog clock at reset value.
-    /// For G0 and WL, this is the async clock without prescaler.
-    pub fn new(adc: Peri<'d, T>) -> Self {
-        Self::init_regulator();
-        Self::init_calibrate();
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
-    }
-
+#[cfg(adc_u0)]
+type Ovss = u8;
+#[cfg(adc_u0)]
+type Ovsr = u8;
+#[cfg(adc_v3)]
+type Ovss = OversamplingShift;
+#[cfg(adc_v3)]
+type Ovsr = OversamplingRatio;
+
+/// Adc configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_shift: Option<Ovss>,
+    #[cfg(any(adc_u0, adc_g0, adc_v3))]
+    pub oversampling_ratio: Option<Ovsr>,
+    #[cfg(any(adc_u0, adc_g0))]
+    pub oversampling_enable: Option<bool>,
+    #[cfg(adc_v3)]
+    pub oversampling_mode: Option<(Rovsm, Trovs, bool)>,
     #[cfg(adc_g0)]
-    /// Initialize ADC with explicit clock for the analog ADC
-    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
-        Self::init_regulator();
-
-        #[cfg(any(stm32wl5x))]
-        {
-            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
-            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
-            match clock {
-                Clock::Async { div: _ } => {
-                    assert!(async_clock_available);
-                }
-                Clock::Sync { div: _ } => {
-                    if async_clock_available {
-                        warn!("Not using configured ADC clock");
-                    }
-                }
-            }
-        }
-        match clock {
-            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
-            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
-                reg.set_ckmode(match div {
-                    CkModePclk::DIV1 => Ckmode::PCLK,
-                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
-                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
-                })
-            }),
-        }
-
-        Self::init_calibrate();
+    pub clock: Option<Clock>,
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
+}
 
-        Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        }
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
     }
 
     // Enable ADC only when it is not already running.
-    fn enable(&mut self) {
+    fn enable() {
         // Make sure bits are off
         while T::regs().cr().read().addis() {
             // spin
@@ -246,186 +173,95 @@ impl<'d, T: Instance> Adc<'d, T> {
         }
     }
 
-    pub fn enable_vrefint(&self) -> VrefInt {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::common_regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().ccr().modify(|reg| {
-            reg.set_vrefen(true);
+    fn start() {
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
         });
-
-        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
-        // to stabilize the internal voltage reference.
-        blocking_delay_us(15);
-
-        VrefInt {}
     }
 
-    pub fn enable_temperature(&self) -> Temperature {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_tsen(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch17sel(true);
-                });
-            }
+    fn stop() {
+        // Ensure conversions are finished.
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
         }
 
-        Temperature {}
+        // Reset configuration.
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(false);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmaen(false);
+        });
     }
 
-    pub fn enable_vbat(&self) -> Vbat {
-        cfg_if! {
-            if #[cfg(any(adc_g0, adc_u0))] {
-                T::regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_vbaten(true);
-                });
-            } else {
-                T::common_regs().ccr().modify(|reg| {
-                    reg.set_ch18sel(true);
-                });
-            }
-        }
+    /// Perform a single conversion.
+    fn convert() -> u16 {
+        // Some models are affected by an erratum:
+        // If we perform conversions slower than 1 kHz, the first read ADC value can be
+        // corrupted, so we discard it and measure again.
+        //
+        // STM32L471xx: Section 2.7.3
+        // STM32G4: Section 2.7.3
+        #[cfg(any(rcc_l4, rcc_g4))]
+        let len = 2;
 
-        Vbat {}
-    }
+        #[cfg(not(any(rcc_l4, rcc_g4)))]
+        let len = 1;
 
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
+        for _ in 0..len {
+            T::regs().isr().modify(|reg| {
+                reg.set_eos(true);
+                reg.set_eoc(true);
+            });
 
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        self.sample_time
-    }
+            // Start conversion
+            T::regs().cr().modify(|reg| {
+                reg.set_adstart(true);
+            });
 
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
-    }
+            while !T::regs().isr().read().eos() {
+                // spin
+            }
+        }
 
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 0, 1),
-            Averaging::Samples4 => (true, 1, 2),
-            Averaging::Samples8 => (true, 2, 3),
-            Averaging::Samples16 => (true, 3, 4),
-            Averaging::Samples32 => (true, 4, 5),
-            Averaging::Samples64 => (true, 5, 6),
-            Averaging::Samples128 => (true, 6, 7),
-            Averaging::Samples256 => (true, 7, 8),
-        };
-        T::regs().cfgr2().modify(|reg| {
-            #[cfg(not(any(adc_g0, adc_u0)))]
-            reg.set_rovse(enable);
-            #[cfg(any(adc_g0, adc_u0))]
-            reg.set_ovse(enable);
-            #[cfg(any(adc_h5, adc_h7rs))]
-            reg.set_ovsr(samples.into());
-            #[cfg(not(any(adc_h5, adc_h7rs)))]
-            reg.set_ovsr(samples.into());
-            reg.set_ovss(right_shift.into());
-        })
-    }
-    /*
-    /// Convert a raw sample from the `Temperature` to deg C
-    pub fn to_degrees_centigrade(sample: u16) -> f32 {
-        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
-            * (sample as f32 - VtempCal30::get().read() as f32)
-            + 30.0
+        T::regs().dr().read().0 as u16
     }
-     */
 
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
+    fn configure_dma(conversion_mode: ConversionMode) {
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
         T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_ovr(true);
         });
 
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        let regs = T::regs().cfgr();
 
-        T::regs().dr().read().0 as u16
-    }
+        #[cfg(any(adc_g0, adc_u0))]
+        let regs = T::regs().cfgr1();
 
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.read_channel(channel)
+        regs.modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(match conversion_mode {
+                ConversionMode::Singular => Dmacfg::ONE_SHOT,
+                #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+                ConversionMode::Repeated(_) => Dmacfg::CIRCULAR,
+            });
+            reg.set_dmaen(true);
+        });
     }
 
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `readings` must have a length that is a multiple of the length of the
-    /// `sequence` iterator.
-    ///
-    /// Note: The order of values in `readings` is defined by the pin ADC
-    /// channel number and not the pin order in `sequence`.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
-    /// let mut adc_pin1 = p.PA1.degrade_adc();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA1_CH2.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
-    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            readings.len() % sequence.len() == 0,
-            "Readings length must be a multiple of sequence length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        // Ensure no conversions are ongoing and ADC is enabled.
-        Self::cancel_conversions();
-        self.enable();
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        #[cfg(adc_h5)]
+        T::regs().cr().modify(|w| w.set_aden(false));
 
         // Set sequence length
         #[cfg(not(any(adc_g0, adc_u0)))]
@@ -439,10 +275,10 @@ impl<'d, T: Instance> Adc<'d, T> {
 
             T::regs().chselr().write(|chselr| {
                 T::regs().smpr().write(|smpr| {
-                    for (channel, sample_time) in sequence {
-                        chselr.set_chsel(channel.channel.into(), true);
+                    for ((channel, _), sample_time) in sequence {
+                        chselr.set_chsel(channel.into(), true);
                         if let Some(i) = sample_times.iter().position(|&t| t == sample_time) {
-                            smpr.set_smpsel(channel.channel.into(), (i as u8).into());
+                            smpr.set_smpsel(channel.into(), (i as u8).into());
                         } else {
                             smpr.set_sample_time(sample_times.len(), sample_time);
                             if let Err(_) = sample_times.push(sample_time) {
@@ -461,42 +297,86 @@ impl<'d, T: Instance> Adc<'d, T> {
             #[cfg(adc_u0)]
             let mut channel_mask = 0;
 
+            #[cfg(adc_h5)]
+            let mut difsel = 0u32;
+
             // Configure channels and ranks
-            for (_i, (channel, sample_time)) in sequence.enumerate() {
-                Self::configure_channel(channel, sample_time);
+            for (_i, ((channel, _is_differential), sample_time)) in sequence.enumerate() {
+                // RM0492, RM0481, etc.
+                // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
+                #[cfg(any(adc_h5, adc_h7rs))]
+                if channel == 0 {
+                    T::regs().or().modify(|reg| reg.set_op0(true));
+                }
+
+                // Configure channel
+                cfg_if! {
+                    if #[cfg(adc_u0)] {
+                        // On G0 and U6 all channels use the same sampling time.
+                        T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+                    } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                        match channel {
+                            0..=9 => T::regs().smpr1().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                            _ => T::regs().smpr2().modify(|w| w.set_smp(channel as usize % 10, sample_time.into())),
+                        }
+                    } else {
+                        let sample_time = sample_time.into();
+                        T::regs()
+                            .smpr(channel as usize / 10)
+                            .modify(|reg| reg.set_smp(channel as usize % 10, sample_time));
+                    }
+                }
+
+                #[cfg(stm32h7)]
+                {
+                    use crate::pac::adc::vals::Pcsel;
+
+                    T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                    T::regs()
+                        .pcsel()
+                        .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
+                }
 
                 // Each channel is sampled according to sequence
                 #[cfg(not(any(adc_g0, adc_u0)))]
                 match _i {
                     0..=3 => {
                         T::regs().sqr1().modify(|w| {
-                            w.set_sq(_i, channel.channel());
+                            w.set_sq(_i, channel);
                         });
                     }
                     4..=8 => {
                         T::regs().sqr2().modify(|w| {
-                            w.set_sq(_i - 4, channel.channel());
+                            w.set_sq(_i - 4, channel);
                         });
                     }
                     9..=13 => {
                         T::regs().sqr3().modify(|w| {
-                            w.set_sq(_i - 9, channel.channel());
+                            w.set_sq(_i - 9, channel);
                         });
                     }
                     14..=15 => {
                         T::regs().sqr4().modify(|w| {
-                            w.set_sq(_i - 14, channel.channel());
+                            w.set_sq(_i - 14, channel);
                         });
                     }
                     _ => unreachable!(),
                 }
 
+                #[cfg(adc_h5)]
+                {
+                    difsel |= (_is_differential as u32) << channel;
+                }
+
                 #[cfg(adc_u0)]
                 {
-                    channel_mask |= 1 << channel.channel();
+                    channel_mask |= 1 << channel;
                 }
             }
 
+            #[cfg(adc_h5)]
+            T::regs().difsel().write(|w| w.set_difsel(difsel));
+
             // On G0 and U0 enabled channels are sampled from 0 to last channel.
             // It is possible to add up to 8 sequences if CHSELRMOD = 1.
             // However for supporting more than 8 channels alternative CHSELRMOD = 0 approach is used.
@@ -505,181 +385,234 @@ impl<'d, T: Instance> Adc<'d, T> {
                 reg.set_chsel(channel_mask);
             });
         }
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
+    }
+}
 
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+impl<'d, T: Instance> Adc<'d, T> {
+    /// Enable the voltage regulator
+    fn init_regulator() {
+        rcc::enable_and_reset::<T>();
+        T::regs().cr().modify(|reg| {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            reg.set_deeppwd(false);
+            reg.set_advregen(true);
         });
+
+        // If this is false then each ADC_CHSELR bit enables an input channel.
+        // This is the reset value, so has no effect.
         #[cfg(any(adc_g0, adc_u0))]
         T::regs().cfgr1().modify(|reg| {
-            reg.set_discen(false);
-            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONE_SHOT);
-            reg.set_dmaen(true);
+            reg.set_chselrmod(false);
         });
 
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
+        blocking_delay_us(20);
+    }
 
-        // Start conversion
+    /// Calibrate to remove conversion offset
+    fn init_calibrate() {
         T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
+            reg.set_adcal(true);
         });
 
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
+        while T::regs().cr().read().adcal() {
+            // spin
+        }
 
-        // Reset configuration.
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-        });
-        #[cfg(any(adc_g0, adc_u0))]
-        T::regs().cfgr1().modify(|reg| {
-            reg.set_cont(false);
-        });
+        blocking_delay_us(1);
     }
 
-    #[cfg(not(adc_g0))]
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(true));
-        }
-
-        // Configure channel
-        Self::set_channel_sample_time(channel.channel(), sample_time);
+    /// Initialize the ADC leaving any analog clock at reset value.
+    /// For G0 and WL, this is the async clock without prescaler.
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        Self::init_regulator();
+        Self::init_calibrate();
+        Self { adc }
     }
 
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.enable();
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
         #[cfg(not(adc_g0))]
-        Self::configure_channel(channel, self.sample_time);
+        let s = Self::new(adc);
+
         #[cfg(adc_g0)]
-        T::regs().smpr().write(|reg| {
-            reg.set_sample_time(0, self.sample_time);
-            reg.set_smpsel(channel.channel().into(), Smpsel::SMP1);
-        });
-        // Select channel
-        #[cfg(not(any(adc_g0, adc_u0)))]
-        T::regs().sqr1().write(|reg| reg.set_sq(0, channel.channel()));
+        let s = match config.clock {
+            Some(clock) => Self::new_with_clock(adc, clock),
+            None => Self::new(adc),
+        };
+
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(shift) = config.oversampling_shift {
+            T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+        }
+
+        #[cfg(any(adc_g0, adc_u0, adc_v3))]
+        if let Some(ratio) = config.oversampling_ratio {
+            T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+        }
+
         #[cfg(any(adc_g0, adc_u0))]
-        T::regs().chselr().write(|reg| {
-            #[cfg(adc_g0)]
-            reg.set_chsel(channel.channel().into(), true);
-            #[cfg(adc_u0)]
-            reg.set_chsel(1 << channel.channel());
-        });
+        if let Some(enable) = config.oversampling_enable {
+            T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
+        }
 
-        // Some models are affected by an erratum:
-        // If we perform conversions slower than 1 kHz, the first read ADC value can be
-        // corrupted, so we discard it and measure again.
-        //
-        // STM32L471xx: Section 2.7.3
-        // STM32G4: Section 2.7.3
-        #[cfg(any(rcc_l4, rcc_g4))]
-        let _ = self.convert();
-        let val = self.convert();
+        #[cfg(adc_v3)]
+        if let Some((mode, trig_mode, enable)) = config.oversampling_mode {
+            T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+            T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        }
 
-        T::regs().cr().modify(|reg| reg.set_addis(true));
+        if let Some(resolution) = config.resolution {
+            #[cfg(not(any(adc_g0, adc_u0)))]
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+            #[cfg(any(adc_g0, adc_u0))]
+            T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
+        }
 
-        // RM0492, RM0481, etc.
-        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(any(adc_h5, adc_h7rs))]
-        if channel.channel() == 0 {
-            T::regs().or().modify(|reg| reg.set_op0(false));
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 0, 1),
+                Averaging::Samples4 => (true, 1, 2),
+                Averaging::Samples8 => (true, 2, 3),
+                Averaging::Samples16 => (true, 3, 4),
+                Averaging::Samples32 => (true, 4, 5),
+                Averaging::Samples64 => (true, 5, 6),
+                Averaging::Samples128 => (true, 6, 7),
+                Averaging::Samples256 => (true, 7, 8),
+            };
+            T::regs().cfgr2().modify(|reg| {
+                #[cfg(not(any(adc_g0, adc_u0)))]
+                reg.set_rovse(enable);
+                #[cfg(any(adc_g0, adc_u0))]
+                reg.set_ovse(enable);
+                #[cfg(any(adc_h5, adc_h7rs))]
+                reg.set_ovsr(samples.into());
+                #[cfg(not(any(adc_h5, adc_h7rs)))]
+                reg.set_ovsr(samples.into());
+                reg.set_ovss(right_shift.into());
+            })
         }
 
-        val
+        s
     }
 
     #[cfg(adc_g0)]
-    pub fn set_oversampling_shift(&mut self, shift: Ovss) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_shift(&mut self, shift: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
-    }
+    /// Initialize ADC with explicit clock for the analog ADC
+    pub fn new_with_clock(adc: Peri<'d, T>, clock: Clock) -> Self {
+        Self::init_regulator();
 
-    #[cfg(adc_g0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: Ovsr) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
-    #[cfg(adc_u0)]
-    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
-    }
+        #[cfg(any(stm32wl5x))]
+        {
+            // Reset value 0 is actually _No clock selected_ in the STM32WL5x reference manual
+            let async_clock_available = pac::RCC.ccipr().read().adcsel() != pac::rcc::vals::Adcsel::_RESERVED_0;
+            match clock {
+                Clock::Async { div: _ } => {
+                    assert!(async_clock_available);
+                }
+                Clock::Sync { div: _ } => {
+                    if async_clock_available {
+                        warn!("Not using configured ADC clock");
+                    }
+                }
+            }
+        }
+        match clock {
+            Clock::Async { div } => T::regs().ccr().modify(|reg| reg.set_presc(div)),
+            Clock::Sync { div } => T::regs().cfgr2().modify(|reg| {
+                reg.set_ckmode(match div {
+                    CkModePclk::DIV1 => Ckmode::PCLK,
+                    CkModePclk::DIV2 => Ckmode::PCLK_DIV2,
+                    CkModePclk::DIV4 => Ckmode::PCLK_DIV4,
+                })
+            }),
+        }
 
-    #[cfg(any(adc_g0, adc_u0))]
-    pub fn oversampling_enable(&mut self, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovse(enable));
-    }
+        Self::init_calibrate();
 
-    #[cfg(adc_v3)]
-    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
-        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
-        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+        Self { adc }
     }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_ratio(&mut self, ratio: OversamplingRatio) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    pub fn enable_vrefint(&self) -> VrefInt {
+        #[cfg(not(any(adc_g0, adc_u0)))]
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+        #[cfg(any(adc_g0, adc_u0))]
+        T::regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+
+        // "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
+        // to stabilize the internal voltage reference.
+        blocking_delay_us(15);
+
+        VrefInt {}
     }
 
-    #[cfg(adc_v3)]
-    pub fn set_oversampling_shift(&mut self, shift: OversamplingShift) {
-        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    pub fn enable_temperature(&self) -> Temperature {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_tsen(true);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch17sel(true);
+                });
+            }
+        }
+
+        Temperature {}
     }
 
-    #[cfg(not(adc_g0))]
-    fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
+    pub fn enable_vbat(&self) -> Vbat {
         cfg_if! {
-            if #[cfg(adc_u0)] {
-                // On G0 and U6 all channels use the same sampling time.
-                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
             } else if #[cfg(any(adc_h5, adc_h7rs))] {
-                match _ch {
-                    0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                    _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
-                }
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(true);
+                });
             } else {
-                let sample_time = sample_time.into();
-                T::regs()
-                    .smpr(_ch as usize / 10)
-                    .modify(|reg| reg.set_smp(_ch as usize % 10, sample_time));
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(true);
+                });
             }
         }
+
+        Vbat {}
     }
 
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(true);
-            });
-            while T::regs().cr().read().adstart() {}
+    pub fn disable_vbat(&self) {
+        cfg_if! {
+            if #[cfg(any(adc_g0, adc_u0))] {
+                T::regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_vbaten(false);
+                });
+            } else {
+                T::common_regs().ccr().modify(|reg| {
+                    reg.set_ch18sel(false);
+                });
+            }
         }
     }
+
+    /*
+    /// Convert a raw sample from the `Temperature` to deg C
+    pub fn to_degrees_centigrade(sample: u16) -> f32 {
+        (130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
+            * (sample as f32 - VtempCal30::get().read() as f32)
+            + 30.0
+    }
+     */
 }
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index b66437e6e..a3d9e6176 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -4,12 +4,10 @@ use pac::adc::vals::{Adcaldif, Boost};
 use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 
-use super::{
-    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
-};
-use crate::dma::Transfer;
+use super::{Adc, Averaging, Instance, Resolution, SampleTime, Temperature, Vbat, VrefInt, blocking_delay_us};
+use crate::adc::ConversionMode;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peri};
+use crate::{Peri, pac, rcc};
 
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -25,153 +23,234 @@ const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 
 #[cfg(stm32g4)]
-const VREF_CHANNEL: u8 = 18;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 18;
+}
 #[cfg(stm32g4)]
-const TEMP_CHANNEL: u8 = 16;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 16;
+}
 
 #[cfg(stm32h7)]
-const VREF_CHANNEL: u8 = 19;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 19;
+}
 #[cfg(stm32h7)]
-const TEMP_CHANNEL: u8 = 18;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 18;
+}
 
 // TODO this should be 14 for H7a/b/35
 #[cfg(not(stm32u5))]
-const VBAT_CHANNEL: u8 = 17;
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 17;
+}
 
 #[cfg(stm32u5)]
-const VREF_CHANNEL: u8 = 0;
+impl<T: Instance> super::SealedSpecialConverter<super::VrefInt> for T {
+    const CHANNEL: u8 = 0;
+}
 #[cfg(stm32u5)]
-const TEMP_CHANNEL: u8 = 19;
+impl<T: Instance> super::SealedSpecialConverter<super::Temperature> for T {
+    const CHANNEL: u8 = 19;
+}
 #[cfg(stm32u5)]
-const VBAT_CHANNEL: u8 = 18;
-
-// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
-/// Internal voltage reference channel.
-pub struct VrefInt;
-impl<T: Instance> AdcChannel<T> for VrefInt {}
-impl<T: Instance> SealedAdcChannel<T> for VrefInt {
-    fn channel(&self) -> u8 {
-        VREF_CHANNEL
-    }
+impl<T: Instance> super::SealedSpecialConverter<super::Vbat> for T {
+    const CHANNEL: u8 = 18;
 }
 
-/// Internal temperature channel.
-pub struct Temperature;
-impl<T: Instance> AdcChannel<T> for Temperature {}
-impl<T: Instance> SealedAdcChannel<T> for Temperature {
-    fn channel(&self) -> u8 {
-        TEMP_CHANNEL
+fn from_ker_ck(frequency: Hertz) -> Presc {
+    let raw_prescaler = rcc::raw_prescaler(frequency.0, MAX_ADC_CLK_FREQ.0);
+    match raw_prescaler {
+        0 => Presc::DIV1,
+        1 => Presc::DIV2,
+        2..=3 => Presc::DIV4,
+        4..=5 => Presc::DIV6,
+        6..=7 => Presc::DIV8,
+        8..=9 => Presc::DIV10,
+        10..=11 => Presc::DIV12,
+        _ => unimplemented!(),
     }
 }
 
-/// Internal battery voltage channel.
-pub struct Vbat;
-impl<T: Instance> AdcChannel<T> for Vbat {}
-impl<T: Instance> SealedAdcChannel<T> for Vbat {
-    fn channel(&self) -> u8 {
-        VBAT_CHANNEL
-    }
+/// Adc configuration
+#[derive(Default)]
+pub struct AdcConfig {
+    pub resolution: Option<Resolution>,
+    pub averaging: Option<Averaging>,
 }
 
-// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
-// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
-#[allow(unused)]
-enum Prescaler {
-    NotDivided,
-    DividedBy2,
-    DividedBy4,
-    DividedBy6,
-    DividedBy8,
-    DividedBy10,
-    DividedBy12,
-    DividedBy16,
-    DividedBy32,
-    DividedBy64,
-    DividedBy128,
-    DividedBy256,
-}
+impl<T: Instance> super::SealedAnyInstance for T {
+    fn dr() -> *mut u16 {
+        T::regs().dr().as_ptr() as *mut u16
+    }
+
+    fn enable() {
+        T::regs().isr().write(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        while !T::regs().isr().read().adrdy() {}
+        T::regs().isr().write(|w| w.set_adrdy(true));
+    }
 
-impl Prescaler {
-    fn from_ker_ck(frequency: Hertz) -> Self {
-        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
-        match raw_prescaler {
-            0 => Self::NotDivided,
-            1 => Self::DividedBy2,
-            2..=3 => Self::DividedBy4,
-            4..=5 => Self::DividedBy6,
-            6..=7 => Self::DividedBy8,
-            8..=9 => Self::DividedBy10,
-            10..=11 => Self::DividedBy12,
-            _ => unimplemented!(),
+    fn start() {
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+    }
+
+    fn stop() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
         }
+
+        // Reset configuration.
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmngt(Dmngt::from_bits(0));
+        });
     }
 
-    fn divisor(&self) -> u32 {
-        match self {
-            Prescaler::NotDivided => 1,
-            Prescaler::DividedBy2 => 2,
-            Prescaler::DividedBy4 => 4,
-            Prescaler::DividedBy6 => 6,
-            Prescaler::DividedBy8 => 8,
-            Prescaler::DividedBy10 => 10,
-            Prescaler::DividedBy12 => 12,
-            Prescaler::DividedBy16 => 16,
-            Prescaler::DividedBy32 => 32,
-            Prescaler::DividedBy64 => 64,
-            Prescaler::DividedBy128 => 128,
-            Prescaler::DividedBy256 => 256,
+    fn convert() -> u16 {
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+
+        while !T::regs().isr().read().eos() {
+            // spin
         }
+
+        T::regs().dr().read().0 as u16
     }
 
-    fn presc(&self) -> Presc {
-        match self {
-            Prescaler::NotDivided => Presc::DIV1,
-            Prescaler::DividedBy2 => Presc::DIV2,
-            Prescaler::DividedBy4 => Presc::DIV4,
-            Prescaler::DividedBy6 => Presc::DIV6,
-            Prescaler::DividedBy8 => Presc::DIV8,
-            Prescaler::DividedBy10 => Presc::DIV10,
-            Prescaler::DividedBy12 => Presc::DIV12,
-            Prescaler::DividedBy16 => Presc::DIV16,
-            Prescaler::DividedBy32 => Presc::DIV32,
-            Prescaler::DividedBy64 => Presc::DIV64,
-            Prescaler::DividedBy128 => Presc::DIV128,
-            Prescaler::DividedBy256 => Presc::DIV256,
+    fn configure_dma(conversion_mode: ConversionMode) {
+        match conversion_mode {
+            ConversionMode::Singular => {
+                T::regs().isr().modify(|reg| {
+                    reg.set_ovr(true);
+                });
+                T::regs().cfgr().modify(|reg| {
+                    reg.set_cont(true);
+                    reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
+                });
+            }
+            #[cfg(any(adc_v2, adc_g4, adc_v3, adc_g0, adc_u0))]
+            _ => unreachable!(),
         }
     }
-}
 
-/// Number of samples used for averaging.
-#[derive(Copy, Clone, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub enum Averaging {
-    Disabled,
-    Samples2,
-    Samples4,
-    Samples8,
-    Samples16,
-    Samples32,
-    Samples64,
-    Samples128,
-    Samples256,
-    Samples512,
-    Samples1024,
+    fn configure_sequence(sequence: impl ExactSizeIterator<Item = ((u8, bool), SampleTime)>) {
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+
+        // Configure channels and ranks
+        for (i, ((channel, _), sample_time)) in sequence.enumerate() {
+            let sample_time = sample_time.into();
+            if channel <= 9 {
+                T::regs().smpr(0).modify(|reg| reg.set_smp(channel as _, sample_time));
+            } else {
+                T::regs()
+                    .smpr(1)
+                    .modify(|reg| reg.set_smp((channel - 10) as _, sample_time));
+            }
+
+            #[cfg(any(stm32h7, stm32u5))]
+            {
+                T::regs().cfgr2().modify(|w| w.set_lshift(0));
+                T::regs()
+                    .pcsel()
+                    .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
+            }
+
+            match i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(i, channel);
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(i - 4, channel);
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(i - 9, channel);
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(i - 14, channel);
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+    }
 }
 
-impl<'d, T: Instance> Adc<'d, T> {
+impl<'d, T: Instance + super::AnyInstance> Adc<'d, T> {
+    pub fn new_with_config(adc: Peri<'d, T>, config: AdcConfig) -> Self {
+        let s = Self::new(adc);
+
+        // Set the ADC resolution.
+        if let Some(resolution) = config.resolution {
+            T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
+        }
+
+        // Set hardware averaging.
+        if let Some(averaging) = config.averaging {
+            let (enable, samples, right_shift) = match averaging {
+                Averaging::Disabled => (false, 0, 0),
+                Averaging::Samples2 => (true, 1, 1),
+                Averaging::Samples4 => (true, 3, 2),
+                Averaging::Samples8 => (true, 7, 3),
+                Averaging::Samples16 => (true, 15, 4),
+                Averaging::Samples32 => (true, 31, 5),
+                Averaging::Samples64 => (true, 63, 6),
+                Averaging::Samples128 => (true, 127, 7),
+                Averaging::Samples256 => (true, 255, 8),
+                Averaging::Samples512 => (true, 511, 9),
+                Averaging::Samples1024 => (true, 1023, 10),
+            };
+
+            T::regs().cfgr2().modify(|reg| {
+                reg.set_rovse(enable);
+                reg.set_ovsr(samples);
+                reg.set_ovss(right_shift);
+            })
+        }
+
+        s
+    }
+
     /// Create a new ADC driver.
     pub fn new(adc: Peri<'d, T>) -> Self {
         rcc::enable_and_reset::<T>();
 
-        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        let prescaler = from_ker_ck(T::frequency());
 
-        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler));
 
-        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        let frequency = T::frequency() / prescaler;
         info!("ADC frequency set to {}", frequency);
 
         if frequency > MAX_ADC_CLK_FREQ {
-            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+            panic!(
+                "Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.",
+                MAX_ADC_CLK_FREQ.0 / 1_000_000
+            );
         }
 
         #[cfg(stm32h7)]
@@ -187,40 +266,20 @@ impl<'d, T: Instance> Adc<'d, T> {
             };
             T::regs().cr().modify(|w| w.set_boost(boost));
         }
-        let mut s = Self {
-            adc,
-            sample_time: SampleTime::from_bits(0),
-        };
-        s.power_up();
-        s.configure_differential_inputs();
-
-        s.calibrate();
-        blocking_delay_us(1);
-
-        s.enable();
-        s.configure();
-
-        s
-    }
 
-    fn power_up(&mut self) {
         T::regs().cr().modify(|reg| {
             reg.set_deeppwd(false);
             reg.set_advregen(true);
         });
 
         blocking_delay_us(10);
-    }
 
-    fn configure_differential_inputs(&mut self) {
         T::regs().difsel().modify(|w| {
             for n in 0..20 {
                 w.set_difsel(n, Difsel::SINGLE_ENDED);
             }
         });
-    }
 
-    fn calibrate(&mut self) {
         T::regs().cr().modify(|w| {
             #[cfg(not(adc_u5))]
             w.set_adcaldif(Adcaldif::SINGLE_ENDED);
@@ -230,21 +289,18 @@ impl<'d, T: Instance> Adc<'d, T> {
         T::regs().cr().modify(|w| w.set_adcal(true));
 
         while T::regs().cr().read().adcal() {}
-    }
 
-    fn enable(&mut self) {
-        T::regs().isr().write(|w| w.set_adrdy(true));
-        T::regs().cr().modify(|w| w.set_aden(true));
-        while !T::regs().isr().read().adrdy() {}
-        T::regs().isr().write(|w| w.set_adrdy(true));
-    }
+        blocking_delay_us(1);
+
+        T::enable();
 
-    fn configure(&mut self) {
         // single conversion mode, software trigger
         T::regs().cfgr().modify(|w| {
             w.set_cont(false);
             w.set_exten(Exten::DISABLED);
         });
+
+        Self { adc }
     }
 
     /// Enable reading the voltage reference internal channel.
@@ -273,228 +329,4 @@ impl<'d, T: Instance> Adc<'d, T> {
 
         Vbat {}
     }
-
-    /// Set the ADC sample time.
-    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
-        self.sample_time = sample_time;
-    }
-
-    /// Get the ADC sample time.
-    pub fn sample_time(&self) -> SampleTime {
-        self.sample_time
-    }
-
-    /// Set the ADC resolution.
-    pub fn set_resolution(&mut self, resolution: Resolution) {
-        T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
-    }
-
-    /// Set hardware averaging.
-    pub fn set_averaging(&mut self, averaging: Averaging) {
-        let (enable, samples, right_shift) = match averaging {
-            Averaging::Disabled => (false, 0, 0),
-            Averaging::Samples2 => (true, 1, 1),
-            Averaging::Samples4 => (true, 3, 2),
-            Averaging::Samples8 => (true, 7, 3),
-            Averaging::Samples16 => (true, 15, 4),
-            Averaging::Samples32 => (true, 31, 5),
-            Averaging::Samples64 => (true, 63, 6),
-            Averaging::Samples128 => (true, 127, 7),
-            Averaging::Samples256 => (true, 255, 8),
-            Averaging::Samples512 => (true, 511, 9),
-            Averaging::Samples1024 => (true, 1023, 10),
-        };
-
-        T::regs().cfgr2().modify(|reg| {
-            reg.set_rovse(enable);
-            reg.set_ovsr(samples);
-            reg.set_ovss(right_shift);
-        })
-    }
-
-    /// Perform a single conversion.
-    fn convert(&mut self) -> u16 {
-        T::regs().isr().modify(|reg| {
-            reg.set_eos(true);
-            reg.set_eoc(true);
-        });
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        while !T::regs().isr().read().eos() {
-            // spin
-        }
-
-        T::regs().dr().read().0 as u16
-    }
-
-    /// Read an ADC channel.
-    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        self.read_channel(channel)
-    }
-
-    /// Read one or multiple ADC channels using DMA.
-    ///
-    /// `sequence` iterator and `readings` must have the same length.
-    ///
-    /// Example
-    /// ```rust,ignore
-    /// use embassy_stm32::adc::{Adc, AdcChannel}
-    ///
-    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin2 = p.PA2.into();
-    /// let mut measurements = [0u16; 2];
-    ///
-    /// adc.read(
-    ///     p.DMA2_CH0.reborrow(),
-    ///     [
-    ///         (&mut *adc_pin0, SampleTime::CYCLES112),
-    ///         (&mut *adc_pin2, SampleTime::CYCLES112),
-    ///     ]
-    ///     .into_iter(),
-    ///     &mut measurements,
-    /// )
-    /// .await;
-    /// defmt::info!("measurements: {}", measurements);
-    /// ```
-    pub async fn read(
-        &mut self,
-        rx_dma: Peri<'_, impl RxDma<T>>,
-        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
-        readings: &mut [u16],
-    ) {
-        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
-        assert!(
-            sequence.len() == readings.len(),
-            "Sequence length must be equal to readings length"
-        );
-        assert!(
-            sequence.len() <= 16,
-            "Asynchronous read sequence cannot be more than 16 in length"
-        );
-
-        // Ensure no conversions are ongoing
-        Self::cancel_conversions();
-
-        // Set sequence length
-        T::regs().sqr1().modify(|w| {
-            w.set_l(sequence.len() as u8 - 1);
-        });
-
-        // Configure channels and ranks
-        for (i, (channel, sample_time)) in sequence.enumerate() {
-            Self::configure_channel(channel, sample_time);
-            match i {
-                0..=3 => {
-                    T::regs().sqr1().modify(|w| {
-                        w.set_sq(i, channel.channel());
-                    });
-                }
-                4..=8 => {
-                    T::regs().sqr2().modify(|w| {
-                        w.set_sq(i - 4, channel.channel());
-                    });
-                }
-                9..=13 => {
-                    T::regs().sqr3().modify(|w| {
-                        w.set_sq(i - 9, channel.channel());
-                    });
-                }
-                14..=15 => {
-                    T::regs().sqr4().modify(|w| {
-                        w.set_sq(i - 14, channel.channel());
-                    });
-                }
-                _ => unreachable!(),
-            }
-        }
-
-        // Set continuous mode with oneshot dma.
-        // Clear overrun flag before starting transfer.
-
-        T::regs().isr().modify(|reg| {
-            reg.set_ovr(true);
-        });
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(true);
-            reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
-        });
-
-        let request = rx_dma.request();
-        let transfer = unsafe {
-            Transfer::new_read(
-                rx_dma,
-                request,
-                T::regs().dr().as_ptr() as *mut u16,
-                readings,
-                Default::default(),
-            )
-        };
-
-        // Start conversion
-        T::regs().cr().modify(|reg| {
-            reg.set_adstart(true);
-        });
-
-        // Wait for conversion sequence to finish.
-        transfer.await;
-
-        // Ensure conversions are finished.
-        Self::cancel_conversions();
-
-        // Reset configuration.
-        T::regs().cfgr().modify(|reg| {
-            reg.set_cont(false);
-            reg.set_dmngt(Dmngt::from_bits(0));
-        });
-    }
-
-    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
-        channel.setup();
-
-        let channel = channel.channel();
-
-        Self::set_channel_sample_time(channel, sample_time);
-
-        #[cfg(any(stm32h7, stm32u5))]
-        {
-            T::regs().cfgr2().modify(|w| w.set_lshift(0));
-            T::regs()
-                .pcsel()
-                .modify(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
-        }
-    }
-
-    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
-        Self::configure_channel(channel, self.sample_time);
-
-        T::regs().sqr1().modify(|reg| {
-            reg.set_sq(0, channel.channel());
-            reg.set_l(0);
-        });
-
-        self.convert()
-    }
-
-    fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
-        let sample_time = sample_time.into();
-        if ch <= 9 {
-            T::regs().smpr(0).modify(|reg| reg.set_smp(ch as _, sample_time));
-        } else {
-            T::regs().smpr(1).modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
-        }
-    }
-
-    fn cancel_conversions() {
-        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
-            T::regs().cr().modify(|reg| {
-                reg.set_adstp(Adstp::STOP);
-            });
-            while T::regs().cr().read().adstart() {}
-        }
-    }
 }
diff --git a/embassy-stm32/src/adc/watchdog_v1.rs b/embassy-stm32/src/adc/watchdog_v1.rs
index bbe8e1971..b12e0d333 100644
--- a/embassy-stm32/src/adc/watchdog_v1.rs
+++ b/embassy-stm32/src/adc/watchdog_v1.rs
@@ -1,7 +1,7 @@
 use core::future::poll_fn;
 use core::task::Poll;
 
-use stm32_metapac::adc::vals::{Align, Awdsgl, Res};
+use stm32_metapac::adc::vals::{Align, Awdsgl, Res, SampleTime};
 
 use crate::adc::{Adc, AdcChannel, Instance};
 
@@ -67,7 +67,7 @@ impl<'d, T: Instance> Adc<'d, T> {
     /// let v_high = adc.monitor_watchdog().await;
     /// info!("ADC sample is high {}", v_high);
     /// ```
-    pub async fn monitor_watchdog(&mut self) -> u16 {
+    pub async fn monitor_watchdog(&mut self, sample_time: SampleTime) -> u16 {
         assert!(
             match T::regs().cfgr1().read().awdsgl() {
                 Awdsgl::SINGLE_CHANNEL => T::regs().cfgr1().read().awdch() != 0,
@@ -76,7 +76,7 @@ impl<'d, T: Instance> Adc<'d, T> {
             "`set_channel` should be called before `monitor`",
         );
         assert!(T::regs().chselr().read().0 != 0);
-        T::regs().smpr().modify(|reg| reg.set_smp(self.sample_time.into()));
+        T::regs().smpr().modify(|reg| reg.set_smp(sample_time.into()));
         Self::start_awd();
 
         let sample = poll_fn(|cx| {
diff --git a/embassy-stm32/src/backup_sram.rs b/embassy-stm32/src/backup_sram.rs
new file mode 100644
index 000000000..31b373c6c
--- /dev/null
+++ b/embassy-stm32/src/backup_sram.rs
@@ -0,0 +1,28 @@
+//! Battary backed SRAM
+
+use core::slice;
+
+use embassy_hal_internal::Peri;
+
+use crate::_generated::{BKPSRAM_BASE, BKPSRAM_SIZE};
+use crate::peripherals::BKPSRAM;
+
+/// Struct used to initilize backup sram
+pub struct BackupMemory {}
+
+impl BackupMemory {
+    /// Setup battery backed sram
+    ///
+    /// Returns slice to sram and whether the sram was retained
+    pub fn new(_backup_sram: Peri<'static, BKPSRAM>) -> (&'static mut [u8], bool) {
+        // Assert bksram has been enabled in rcc
+        assert!(crate::pac::PWR.bdcr().read().bren() == crate::pac::pwr::vals::Retention::PRESERVED);
+
+        unsafe {
+            (
+                slice::from_raw_parts_mut(BKPSRAM_BASE as *mut u8, BKPSRAM_SIZE),
+                critical_section::with(|_| crate::rcc::BKSRAM_RETAINED),
+            )
+        }
+    }
+}
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 8eb188560..507350c42 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -5,8 +5,8 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -22,7 +22,7 @@ use crate::can::enums::{BusError, RefCountOp, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 /// Interrupt handler.
 pub struct TxInterruptHandler<T: Instance> {
@@ -186,10 +186,10 @@ impl<'d> Can<'d> {
         rx: Peri<'d, if_afio!(impl RxPin<T, A>)>,
         tx: Peri<'d, if_afio!(impl TxPin<T, A>)>,
         _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
+        + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
+        + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
+        + 'd,
     ) -> Self {
         let info = T::info();
         let regs = &T::info().regs;
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index c6a66b469..4fe634ce4 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -1,7 +1,7 @@
 //! Configuration for FDCAN Module
 // Note: This file is copied and modified from fdcan crate by Richard Meadows
 
-use core::num::{NonZeroU16, NonZeroU8};
+use core::num::{NonZeroU8, NonZeroU16};
 
 /// Configures the bit timings.
 ///
@@ -360,6 +360,8 @@ pub struct FdCanConfig {
     pub global_filter: GlobalFilter,
     /// TX buffer mode (FIFO or priority queue)
     pub tx_buffer_mode: TxBufferMode,
+    /// Automatic recovery from bus off state
+    pub automatic_bus_off_recovery: bool,
 }
 
 impl FdCanConfig {
@@ -456,6 +458,16 @@ impl FdCanConfig {
         self.tx_buffer_mode = txbm;
         self
     }
+
+    /// Enables or disables automatic recovery from bus off state
+    ///
+    /// Automatic recovery is performed by clearing the INIT bit in the CCCR register if
+    /// the BO bit is active in the IR register in the IT0 interrupt.
+    #[inline]
+    pub const fn set_automatic_bus_off_recovery(mut self, enabled: bool) -> Self {
+        self.automatic_bus_off_recovery = enabled;
+        self
+    }
 }
 
 impl Default for FdCanConfig {
@@ -474,6 +486,7 @@ impl Default for FdCanConfig {
             timestamp_source: TimestampSource::None,
             global_filter: GlobalFilter::default(),
             tx_buffer_mode: TxBufferMode::Priority,
+            automatic_bus_off_recovery: true,
         }
     }
 }
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index d8f71e03e..9883aff57 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -3,8 +3,8 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
 
-use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::interrupt::InterruptExt;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -13,7 +13,7 @@ use crate::can::fd::peripheral::Registers;
 use crate::gpio::{AfType, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 pub(crate) mod fd;
 
@@ -53,7 +53,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             regs.ir().write(|w| w.set_tefn(true));
         }
 
-        T::info().state.lock(|s| {
+        let recover_from_bo = T::info().state.lock(|s| {
             let state = s.borrow_mut();
             match &state.tx_mode {
                 TxMode::NonBuffered(waker) => waker.wake(),
@@ -85,11 +85,15 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
             if ir.rfn(1) {
                 state.rx_mode.on_interrupt::<T>(1, state.ns_per_timer_tick);
             }
+
+            state.automatic_bus_off_recovery
         });
 
         if ir.bo() {
             regs.ir().write(|w| w.set_bo(true));
-            if regs.psr().read().bo() {
+            if let Some(true) = recover_from_bo
+                && regs.psr().read().bo()
+            {
                 // Initiate bus-off recovery sequence by resetting CCCR.INIT
                 regs.cccr().modify(|w| w.set_init(false));
             }
@@ -182,8 +186,8 @@ impl<'d> CanConfigurator<'d> {
         rx: Peri<'d, impl RxPin<T>>,
         tx: Peri<'d, impl TxPin<T>>,
         _irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
+        + 'd,
     ) -> CanConfigurator<'d> {
         set_as_af!(rx, AfType::input(Pull::None));
         set_as_af!(tx, AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -263,7 +267,9 @@ impl<'d> CanConfigurator<'d> {
     pub fn start(self, mode: OperatingMode) -> Can<'d> {
         let ns_per_timer_tick = calc_ns_per_timer_tick(&self.info, self.periph_clock, self.config.frame_transmit);
         self.info.state.lock(|s| {
-            s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
+            let mut state = s.borrow_mut();
+            state.ns_per_timer_tick = ns_per_timer_tick;
+            state.automatic_bus_off_recovery = Some(self.config.automatic_bus_off_recovery);
         });
         self.info.regs.into_mode(self.config, mode);
         Can {
@@ -459,7 +465,7 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
     pub async fn write(&mut self, frame: Frame) {
         self.tx_buf.send(frame).await;
         self.info.interrupt0.pend(); // Wake for Tx
-                                     //T::IT0Interrupt::pend(); // Wake for Tx
+        //T::IT0Interrupt::pend(); // Wake for Tx
     }
 
     /// Async read frame from RX buffer.
@@ -548,7 +554,7 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
     pub async fn write(&mut self, frame: FdFrame) {
         self.tx_buf.send(frame).await;
         self.info.interrupt0.pend(); // Wake for Tx
-                                     //T::IT0Interrupt::pend(); // Wake for Tx
+        //T::IT0Interrupt::pend(); // Wake for Tx
     }
 
     /// Async read frame from RX buffer.
@@ -861,7 +867,7 @@ struct State {
     sender_instance_count: usize,
     tx_pin_port: Option<u8>,
     rx_pin_port: Option<u8>,
-
+    automatic_bus_off_recovery: Option<bool>, // controlled by CanConfigurator::start()
     pub err_waker: AtomicWaker,
 }
 
@@ -876,6 +882,7 @@ impl State {
             sender_instance_count: 0,
             tx_pin_port: None,
             rx_pin_port: None,
+            automatic_bus_off_recovery: None,
         }
     }
 }
diff --git a/embassy-stm32/src/can/util.rs b/embassy-stm32/src/can/util.rs
index fcdbbad62..6d7f0c16a 100644
--- a/embassy-stm32/src/can/util.rs
+++ b/embassy-stm32/src/can/util.rs
@@ -1,6 +1,6 @@
 //! Utility functions shared between CAN controller types.
 
-use core::num::{NonZeroU16, NonZeroU8};
+use core::num::{NonZeroU8, NonZeroU16};
 
 /// Shared struct to represent bit timings used by calc_can_timings.
 #[derive(Clone, Copy, Debug)]
diff --git a/embassy-stm32/src/crc/v1.rs b/embassy-stm32/src/crc/v1.rs
index 13e5263de..836228599 100644
--- a/embassy-stm32/src/crc/v1.rs
+++ b/embassy-stm32/src/crc/v1.rs
@@ -1,6 +1,6 @@
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// CRC driver.
 pub struct Crc<'d> {
diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs
index d834d0971..a566a2e04 100644
--- a/embassy-stm32/src/crc/v2v3.rs
+++ b/embassy-stm32/src/crc/v2v3.rs
@@ -1,7 +1,7 @@
-use crate::pac::crc::vals;
 use crate::pac::CRC as PAC_CRC;
+use crate::pac::crc::vals;
 use crate::peripherals::CRC;
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// CRC driver.
 pub struct Crc<'d> {
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 0173b2b5d..4f1115fb7 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1236,7 +1236,10 @@ impl<'d, T: Instance, M: Mode> Cryp<'d, T, M> {
         }
         if C::REQUIRES_PADDING {
             if last_block_remainder != 0 {
-                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
+                panic!(
+                    "Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.",
+                    C::BLOCK_SIZE
+                );
             }
         }
         if last_block {
@@ -1703,7 +1706,10 @@ impl<'d, T: Instance> Cryp<'d, T, Async> {
         }
         if C::REQUIRES_PADDING {
             if last_block_remainder != 0 {
-                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
+                panic!(
+                    "Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.",
+                    C::BLOCK_SIZE
+                );
             }
         }
         if last_block {
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 08e001337..d74d4a4be 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -8,7 +8,7 @@ use crate::mode::{Async, Blocking, Mode as PeriMode};
 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
 use crate::pac::dac;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 mod tsel;
 use embassy_hal_internal::PeripheralType;
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index bd03f1e00..dcae9f298 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 use crate::dma::Transfer;
 use crate::gpio::{AfType, Pull};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, rcc, Peri};
+use crate::{Peri, interrupt, rcc};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 73ecab070..b46ae2813 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -1,6 +1,6 @@
-use core::future::{poll_fn, Future};
+use core::future::{Future, poll_fn};
 use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicUsize, Ordering, fence};
 use core::task::{Context, Poll, Waker};
 
 use embassy_hal_internal::Peri;
@@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 use super::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use super::word::{Word, WordSize};
-use super::{AnyChannel, Channel, Dir, Request, STATE};
+use super::{AnyChannel, BusyChannel, Channel, Dir, Request, STATE};
 use crate::interrupt::typelevel::Interrupt;
 use crate::{interrupt, pac};
 
@@ -602,7 +602,7 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a> Transfer<'a> {
@@ -713,7 +713,9 @@ impl<'a> Transfer<'a> {
             _request, dir, peri_addr, mem_addr, mem_len, incr_mem, mem_size, peri_size, options,
         );
         channel.start();
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
@@ -816,7 +818,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 
 /// Ringbuffer for receiving data using DMA circular mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: ReadableDmaRingBuffer<'a, W>,
 }
 
@@ -853,7 +855,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         );
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: ReadableDmaRingBuffer::new(buffer),
         }
     }
@@ -972,7 +974,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 
 /// Ringbuffer for writing data using DMA circular mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: WritableDmaRingBuffer<'a, W>,
 }
 
@@ -1009,7 +1011,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
         );
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: WritableDmaRingBuffer::new(buffer),
         }
     }
diff --git a/embassy-stm32/src/dma/gpdma/mod.rs b/embassy-stm32/src/dma/gpdma/mod.rs
index 4a14c2a8e..383c74a78 100644
--- a/embassy-stm32/src/dma/gpdma/mod.rs
+++ b/embassy-stm32/src/dma/gpdma/mod.rs
@@ -2,7 +2,7 @@
 
 use core::future::Future;
 use core::pin::Pin;
-use core::sync::atomic::{fence, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicUsize, Ordering, fence};
 use core::task::{Context, Poll};
 
 use embassy_hal_internal::Peri;
@@ -11,6 +11,7 @@ use linked_list::Table;
 
 use super::word::{Word, WordSize};
 use super::{AnyChannel, Channel, Dir, Request, STATE};
+use crate::dma::BusyChannel;
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac;
 use crate::pac::gpdma::vals;
@@ -136,6 +137,7 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: c
 
 impl AnyChannel {
     /// Safety: Must be called with a matching set of parameters for a valid dma channel
+    #[cfg(not(stm32n6))]
     pub(crate) unsafe fn on_irq(&self) {
         let info = self.info();
         #[cfg(feature = "_dual-core")]
@@ -407,7 +409,7 @@ impl AnyChannel {
 /// Linked-list DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct LinkedListTransfer<'a, const ITEM_COUNT: usize> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
@@ -428,7 +430,9 @@ impl<'a, const ITEM_COUNT: usize> LinkedListTransfer<'a, ITEM_COUNT> {
         channel.configure_linked_list(&table, options);
         channel.start();
 
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
@@ -504,7 +508,7 @@ impl<'a, const ITEM_COUNT: usize> Future for LinkedListTransfer<'a, ITEM_COUNT>
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
 }
 
 impl<'a> Transfer<'a> {
@@ -624,7 +628,9 @@ impl<'a> Transfer<'a> {
         );
         channel.start();
 
-        Self { channel }
+        Self {
+            channel: BusyChannel::new(channel),
+        }
     }
 
     /// Request the transfer to pause, keeping the existing configuration for this channel.
diff --git a/embassy-stm32/src/dma/gpdma/ringbuffered.rs b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
index 9ee52193b..54e4d5f71 100644
--- a/embassy-stm32/src/dma/gpdma/ringbuffered.rs
+++ b/embassy-stm32/src/dma/gpdma/ringbuffered.rs
@@ -3,16 +3,16 @@
 //! FIXME: Add request_pause functionality?
 //! FIXME: Stop the DMA, if a user does not queue new transfers (chain of linked-list items ends automatically).
 use core::future::poll_fn;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 use core::task::Waker;
 
 use embassy_hal_internal::Peri;
 
-use super::{AnyChannel, TransferOptions, STATE};
+use super::{AnyChannel, STATE, TransferOptions};
 use crate::dma::gpdma::linked_list::{RunMode, Table};
 use crate::dma::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use crate::dma::word::Word;
-use crate::dma::{Channel, Dir, Request};
+use crate::dma::{BusyChannel, Channel, Dir, Request};
 
 struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
 
@@ -49,7 +49,7 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 
 /// Ringbuffer for receiving data using GPDMA linked-list mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: ReadableDmaRingBuffer<'a, W>,
     table: Table<2>,
     options: TransferOptions,
@@ -70,7 +70,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
         let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::PeripheralToMemory);
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: ReadableDmaRingBuffer::new(buffer),
             table,
             options,
@@ -189,7 +189,7 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 
 /// Ringbuffer for writing data using GPDMA linked-list mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: Peri<'a, AnyChannel>,
+    channel: BusyChannel<'a>,
     ringbuf: WritableDmaRingBuffer<'a, W>,
     table: Table<2>,
     options: TransferOptions,
@@ -210,7 +210,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
         let table = Table::<2>::new_ping_pong::<W>(request, peri_addr, buffer, Dir::MemoryToPeripheral);
 
         Self {
-            channel,
+            channel: BusyChannel::new(channel),
             ringbuf: WritableDmaRingBuffer::new(buffer),
             table,
             options,
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 5989bfd7c..4becc2d87 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -3,11 +3,14 @@
 
 #[cfg(any(bdma, dma))]
 mod dma_bdma;
+use core::ops;
+
 #[cfg(any(bdma, dma))]
 pub use dma_bdma::*;
 
 #[cfg(gpdma)]
 pub(crate) mod gpdma;
+use embassy_hal_internal::Peri;
 #[cfg(gpdma)]
 pub use gpdma::ringbuffered::*;
 #[cfg(gpdma)]
@@ -24,7 +27,7 @@ pub(crate) use util::*;
 pub(crate) mod ringbuffer;
 pub mod word;
 
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::{PeripheralType, impl_peripheral};
 
 use crate::interrupt;
 
@@ -46,9 +49,13 @@ pub type Request = u8;
 pub type Request = ();
 
 pub(crate) trait SealedChannel {
+    #[cfg(not(stm32n6))]
     fn id(&self) -> u8;
+    #[cfg(feature = "low-power")]
+    fn stop_mode(&self) -> crate::rcc::StopMode;
 }
 
+#[cfg(not(stm32n6))]
 pub(crate) trait ChannelInterrupt {
     #[cfg_attr(not(feature = "rt"), allow(unused))]
     unsafe fn on_irq();
@@ -58,16 +65,27 @@ pub(crate) trait ChannelInterrupt {
 #[allow(private_bounds)]
 pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
 
+#[cfg(not(stm32n6))]
 macro_rules! dma_channel_impl {
-    ($channel_peri:ident, $index:expr) => {
+    ($channel_peri:ident, $index:expr, $stop_mode:ident) => {
         impl crate::dma::SealedChannel for crate::peripherals::$channel_peri {
             fn id(&self) -> u8 {
                 $index
             }
+
+            #[cfg(feature = "low-power")]
+            fn stop_mode(&self) -> crate::rcc::StopMode {
+                crate::rcc::StopMode::$stop_mode
+            }
         }
         impl crate::dma::ChannelInterrupt for crate::peripherals::$channel_peri {
             unsafe fn on_irq() {
-                crate::dma::AnyChannel { id: $index }.on_irq();
+                crate::dma::AnyChannel {
+                    id: $index,
+                    #[cfg(feature = "low-power")]
+                    stop_mode: crate::rcc::StopMode::$stop_mode,
+                }
+                .on_irq();
             }
         }
 
@@ -77,15 +95,57 @@ macro_rules! dma_channel_impl {
             fn from(val: crate::peripherals::$channel_peri) -> Self {
                 Self {
                     id: crate::dma::SealedChannel::id(&val),
+                    #[cfg(feature = "low-power")]
+                    stop_mode: crate::dma::SealedChannel::stop_mode(&val),
                 }
             }
         }
     };
 }
 
+pub(crate) struct BusyChannel<'a> {
+    channel: Peri<'a, AnyChannel>,
+}
+
+impl<'a> BusyChannel<'a> {
+    pub fn new(channel: Peri<'a, AnyChannel>) -> Self {
+        #[cfg(feature = "low-power")]
+        critical_section::with(|cs| {
+            crate::rcc::increment_stop_refcount(cs, channel.stop_mode);
+        });
+
+        Self { channel }
+    }
+}
+
+impl<'a> Drop for BusyChannel<'a> {
+    fn drop(&mut self) {
+        #[cfg(feature = "low-power")]
+        critical_section::with(|cs| {
+            crate::rcc::decrement_stop_refcount(cs, self.stop_mode);
+        });
+    }
+}
+
+impl<'a> ops::Deref for BusyChannel<'a> {
+    type Target = Peri<'a, AnyChannel>;
+
+    fn deref(&self) -> &Self::Target {
+        &self.channel
+    }
+}
+
+impl<'a> ops::DerefMut for BusyChannel<'a> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.channel
+    }
+}
+
 /// Type-erased DMA channel.
 pub struct AnyChannel {
     pub(crate) id: u8,
+    #[cfg(feature = "low-power")]
+    pub(crate) stop_mode: crate::rcc::StopMode,
 }
 impl_peripheral!(AnyChannel);
 
@@ -96,9 +156,15 @@ impl AnyChannel {
 }
 
 impl SealedChannel for AnyChannel {
+    #[cfg(not(stm32n6))]
     fn id(&self) -> u8 {
         self.id
     }
+
+    #[cfg(feature = "low-power")]
+    fn stop_mode(&self) -> crate::rcc::StopMode {
+        self.stop_mode
+    }
 }
 impl Channel for AnyChannel {}
 
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
index 661fb1728..eff5b4058 100644
--- a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
+++ b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
@@ -2,7 +2,7 @@ use std::task::Waker;
 
 use proptest::prop_oneof;
 use proptest::strategy::{self, BoxedStrategy, Strategy as _};
-use proptest_state_machine::{prop_state_machine, ReferenceStateMachine, StateMachineTest};
+use proptest_state_machine::{ReferenceStateMachine, StateMachineTest, prop_state_machine};
 
 use super::*;
 
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index deda956af..b8945820c 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -5,17 +5,10 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 //use crate::gpio::{AnyPin, SealedPin};
+use crate::block_for_us;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
-
-/// Performs a busy-wait delay for a specified number of microseconds.
-pub fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
+use crate::{Peri, peripherals};
 
 /// PacketTypes extracted from CubeMX
 #[repr(u8)]
@@ -121,17 +114,15 @@ impl<'d, T: Instance> DsiHost<'d, T> {
 
     /// DCS or Generic short/long write command
     pub fn write_cmd(&mut self, channel_id: u8, address: u8, data: &[u8]) -> Result<(), Error> {
-        assert!(data.len() > 0);
-
-        if data.len() == 1 {
-            self.short_write(channel_id, PacketType::DcsShortPktWriteP1, address, data[0])
-        } else {
-            self.long_write(
+        match data.len() {
+            0 => self.short_write(channel_id, PacketType::DcsShortPktWriteP0, address, 0),
+            1 => self.short_write(channel_id, PacketType::DcsShortPktWriteP1, address, data[0]),
+            _ => self.long_write(
                 channel_id,
                 PacketType::DcsLongPktWrite, // FIXME: This might be a generic long packet, as well...
                 address,
                 data,
-            )
+            ),
         }
     }
 
@@ -336,7 +327,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if T::regs().gpsr().read().cmdfe() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
@@ -347,7 +338,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !T::regs().gpsr().read().cmdff() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
@@ -358,7 +349,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !self.read_busy() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::ReadTimeout)
     }
@@ -369,7 +360,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
             if !T::regs().gpsr().read().prdfe() {
                 return Ok(());
             }
-            blocking_delay_ms(1);
+            block_for_us(1_000);
         }
         Err(Error::FifoTimeout)
     }
diff --git a/embassy-stm32/src/dts/mod.rs b/embassy-stm32/src/dts/mod.rs
index 1f39c8db5..a75ae0560 100644
--- a/embassy-stm32/src/dts/mod.rs
+++ b/embassy-stm32/src/dts/mod.rs
@@ -1,7 +1,7 @@
 //! Digital Temperature Sensor (DTS)
 
 use core::future::poll_fn;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_hal_internal::Peri;
diff --git a/embassy-stm32/src/dts/tsel.rs b/embassy-stm32/src/dts/tsel.rs
index 99eab6dd8..79c697c8d 100644
--- a/embassy-stm32/src/dts/tsel.rs
+++ b/embassy-stm32/src/dts/tsel.rs
@@ -49,3 +49,20 @@ pub enum TriggerSel {
     /// EXTI13
     Exti13 = 4,
 }
+
+/// Trigger selection for N6
+#[cfg(stm32n6)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM4 OUT
+    Lptim4 = 1,
+    /// LPTIM2 CH1
+    Lptim2 = 2,
+    /// LPTIM3 CH1
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
diff --git a/embassy-stm32/src/eth/generic_phy.rs b/embassy-stm32/src/eth/generic_phy.rs
index 774beef80..0a5f41de0 100644
--- a/embassy-stm32/src/eth/generic_phy.rs
+++ b/embassy-stm32/src/eth/generic_phy.rs
@@ -8,6 +8,7 @@ use embassy_time::{Duration, Timer};
 use futures_util::FutureExt;
 
 use super::{Phy, StationManagement};
+use crate::block_for_us as blocking_delay_us;
 
 #[allow(dead_code)]
 mod phy_consts {
@@ -43,21 +44,23 @@ mod phy_consts {
 use self::phy_consts::*;
 
 /// Generic SMI Ethernet PHY implementation
-pub struct GenericPhy {
+pub struct GenericPhy<SM: StationManagement> {
     phy_addr: u8,
+    sm: SM,
     #[cfg(feature = "time")]
     poll_interval: Duration,
 }
 
-impl GenericPhy {
+impl<SM: StationManagement> GenericPhy<SM> {
     /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
     ///
     /// # Panics
     /// `phy_addr` must be in range `0..32`
-    pub fn new(phy_addr: u8) -> Self {
+    pub fn new(sm: SM, phy_addr: u8) -> Self {
         assert!(phy_addr < 32);
         Self {
             phy_addr,
+            sm,
             #[cfg(feature = "time")]
             poll_interval: Duration::from_millis(500),
         }
@@ -67,8 +70,9 @@ impl GenericPhy {
     ///
     /// # Panics
     /// Initialization panics if PHY didn't respond on any address
-    pub fn new_auto() -> Self {
+    pub fn new_auto(sm: SM) -> Self {
         Self {
+            sm,
             phy_addr: 0xFF,
             #[cfg(feature = "time")]
             poll_interval: Duration::from_millis(500),
@@ -76,27 +80,14 @@ impl GenericPhy {
     }
 }
 
-// TODO: Factor out to shared functionality
-fn blocking_delay_us(us: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(Duration::from_micros(us as u64));
-    #[cfg(not(feature = "time"))]
-    {
-        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
-        let us = us as u64;
-        let cycles = freq * us / 1_000_000;
-        cortex_m::asm::delay(cycles as u32);
-    }
-}
-
-impl Phy for GenericPhy {
-    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
+impl<SM: StationManagement> Phy for GenericPhy<SM> {
+    fn phy_reset(&mut self) {
         // Detect SMI address
         if self.phy_addr == 0xFF {
             for addr in 0..32 {
-                sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
+                self.sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
                 for _ in 0..10 {
-                    if sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {
+                    if self.sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {
                         trace!("Found ETH PHY on address {}", addr);
                         self.phy_addr = addr;
                         return;
@@ -108,30 +99,30 @@ impl Phy for GenericPhy {
             panic!("PHY did not respond");
         }
 
-        sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
-        while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
+        self.sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
+        while self.sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
     }
 
-    fn phy_init<S: StationManagement>(&mut self, sm: &mut S) {
+    fn phy_init(&mut self) {
         // Clear WU CSR
-        self.smi_write_ext(sm, PHY_REG_WUCSR, 0);
+        self.smi_write_ext(PHY_REG_WUCSR, 0);
 
         // Enable auto-negotiation
-        sm.smi_write(
+        self.sm.smi_write(
             self.phy_addr,
             PHY_REG_BCR,
             PHY_REG_BCR_AN | PHY_REG_BCR_ANRST | PHY_REG_BCR_100M,
         );
     }
 
-    fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool {
+    fn poll_link(&mut self, cx: &mut Context) -> bool {
         #[cfg(not(feature = "time"))]
         cx.waker().wake_by_ref();
 
         #[cfg(feature = "time")]
         let _ = Timer::after(self.poll_interval).poll_unpin(cx);
 
-        let bsr = sm.smi_read(self.phy_addr, PHY_REG_BSR);
+        let bsr = self.sm.smi_read(self.phy_addr, PHY_REG_BSR);
 
         // No link without autonegotiate
         if bsr & PHY_REG_BSR_ANDONE == 0 {
@@ -148,7 +139,7 @@ impl Phy for GenericPhy {
 }
 
 /// Public functions for the PHY
-impl GenericPhy {
+impl<SM: StationManagement> GenericPhy<SM> {
     /// Set the SMI polling interval.
     #[cfg(feature = "time")]
     pub fn set_poll_interval(&mut self, poll_interval: Duration) {
@@ -156,10 +147,15 @@ impl GenericPhy {
     }
 
     // Writes a value to an extended PHY register in MMD address space
-    fn smi_write_ext<S: StationManagement>(&mut self, sm: &mut S, reg_addr: u16, reg_data: u16) {
-        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
-        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
-        sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
-        sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
+    fn smi_write_ext(&mut self, reg_addr: u16, reg_data: u16) {
+        self.sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x0003); // set address
+        self.sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_addr);
+        self.sm.smi_write(self.phy_addr, PHY_REG_CTL, 0x4003); // set data
+        self.sm.smi_write(self.phy_addr, PHY_REG_ADDAR, reg_data);
+    }
+
+    /// Access the underlying station management.
+    pub fn station_management(&mut self) -> &mut SM {
+        &mut self.sm
     }
 }
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index 10b3a0517..c8bce0e8a 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -5,6 +5,7 @@
 #[cfg_attr(eth_v2, path = "v2/mod.rs")]
 mod _version;
 mod generic_phy;
+mod sma;
 
 use core::mem::MaybeUninit;
 use core::task::Context;
@@ -15,6 +16,7 @@ use embassy_sync::waitqueue::AtomicWaker;
 
 pub use self::_version::{InterruptHandler, *};
 pub use self::generic_phy::*;
+pub use self::sma::{Sma, StationManagement};
 use crate::rcc::RccPeripheral;
 
 #[allow(unused)]
@@ -109,7 +111,7 @@ impl<'d, T: Instance, P: Phy> embassy_net_driver::Driver for Ethernet<'d, T, P>
     }
 
     fn link_state(&mut self, cx: &mut Context) -> LinkState {
-        if self.phy.poll_link(&mut self.station_management, cx) {
+        if self.phy.poll_link(cx) {
             LinkState::Up
         } else {
             LinkState::Down
@@ -157,32 +159,17 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> {
     }
 }
 
-/// Station Management Interface (SMI) on an ethernet PHY
-pub trait StationManagement {
-    /// Read a register over SMI.
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
-    /// Write a register over SMI.
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
-}
-
 /// Trait for an Ethernet PHY
 pub trait Phy {
     /// Reset PHY and wait for it to come out of reset.
-    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S);
+    fn phy_reset(&mut self);
     /// PHY initialisation.
-    fn phy_init<S: StationManagement>(&mut self, sm: &mut S);
+    fn phy_init(&mut self);
     /// Poll link to see if it is up and FD with 100Mbps
-    fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool;
+    fn poll_link(&mut self, cx: &mut Context) -> bool;
 }
 
 impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
-    /// Directly expose the SMI interface used by the Ethernet driver.
-    ///
-    /// This can be used to for example configure special PHY registers for compliance testing.
-    pub fn station_management(&mut self) -> &mut impl StationManagement {
-        &mut self.station_management
-    }
-
     /// Access the user-supplied `Phy`.
     pub fn phy(&self) -> &P {
         &self.phy
@@ -212,8 +199,8 @@ impl Instance for crate::peripherals::ETH {}
 pin_trait!(RXClkPin, Instance, @A);
 pin_trait!(TXClkPin, Instance, @A);
 pin_trait!(RefClkPin, Instance, @A);
-pin_trait!(MDIOPin, Instance, @A);
-pin_trait!(MDCPin, Instance, @A);
+pin_trait!(MDIOPin, sma::Instance, @A);
+pin_trait!(MDCPin, sma::Instance, @A);
 pin_trait!(RXDVPin, Instance, @A);
 pin_trait!(CRSPin, Instance, @A);
 pin_trait!(RXD0Pin, Instance, @A);
diff --git a/embassy-stm32/src/eth/sma/mod.rs b/embassy-stm32/src/eth/sma/mod.rs
new file mode 100644
index 000000000..6c851911d
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/mod.rs
@@ -0,0 +1,42 @@
+//! Station Management Agent (also known as MDIO or SMI).
+
+#![macro_use]
+
+#[cfg_attr(eth_v2, path = "v2.rs")]
+#[cfg_attr(any(eth_v1a, eth_v1b, eth_v1c), path = "v1.rs")]
+mod _version;
+
+use embassy_hal_internal::PeripheralType;
+use stm32_metapac::common::{RW, Reg};
+
+pub use self::_version::*;
+
+/// Station Management Interface (SMI).
+pub trait StationManagement {
+    /// Read a register over SMI.
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
+    /// Write a register over SMI.
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
+}
+
+trait SealedInstance {
+    fn regs() -> (Reg<AddressRegister, RW>, Reg<DataRegister, RW>);
+}
+
+/// MDIO instance.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + Send + 'static {}
+
+impl SealedInstance for crate::peripherals::ETH_SMA {
+    fn regs() -> (Reg<AddressRegister, RW>, Reg<DataRegister, RW>) {
+        let mac = crate::pac::ETH.ethernet_mac();
+
+        #[cfg(any(eth_v1a, eth_v1b, eth_v1c))]
+        return (mac.macmiiar(), mac.macmiidr());
+
+        #[cfg(eth_v2)]
+        return (mac.macmdioar(), mac.macmdiodr());
+    }
+}
+
+impl Instance for crate::peripherals::ETH_SMA {}
diff --git a/embassy-stm32/src/eth/sma/v1.rs b/embassy-stm32/src/eth/sma/v1.rs
new file mode 100644
index 000000000..db64a6c78
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/v1.rs
@@ -0,0 +1,102 @@
+use embassy_hal_internal::Peri;
+pub(crate) use regs::{Macmiiar as AddressRegister, Macmiidr as DataRegister};
+use stm32_metapac::eth::regs;
+use stm32_metapac::eth::vals::{Cr, MbProgress, Mw};
+
+use super::{Instance, StationManagement};
+use crate::eth::{MDCPin, MDIOPin};
+use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+
+/// Station Management Agent.
+///
+/// This peripheral is used for SMI reads and writes to the connected
+/// ethernet PHY/device(s).
+pub struct Sma<'d, T: Instance> {
+    _peri: Peri<'d, T>,
+    clock_range: Cr,
+    pins: [Peri<'d, AnyPin>; 2],
+}
+
+impl<'d, T: Instance> Sma<'d, T> {
+    /// Create a new instance of this peripheral.
+    pub fn new<#[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
+    ) -> Self {
+        set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+
+        // Enable necessary clocks.
+        critical_section::with(|_| {
+            #[cfg(eth_v1a)]
+            let reg = crate::pac::RCC.ahbenr();
+
+            #[cfg(any(eth_v1b, eth_v1c))]
+            let reg = crate::pac::RCC.ahb1enr();
+
+            reg.modify(|w| {
+                w.set_ethen(true);
+            })
+        });
+
+        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };
+        let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not.");
+        let hclk_mhz = hclk.0 / 1_000_000;
+
+        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
+        let clock_range = match hclk_mhz {
+            0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
+            25..=34 => Cr::CR_20_35,     // Divide by 16
+            35..=59 => Cr::CR_35_60,     // Divide by 26
+            60..=99 => Cr::CR_60_100,    // Divide by 42
+            100..=149 => Cr::CR_100_150, // Divide by 62
+            150..=216 => Cr::CR_150_168, // Divide by 102
+            _ => {
+                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
+            }
+        };
+
+        Self {
+            _peri: peri,
+            clock_range,
+            pins: [mdio.into(), mdc.into()],
+        }
+    }
+}
+
+impl<T: Instance> StationManagement for Sma<'_, T> {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
+        let (macmiiar, macmiidr) = T::regs();
+
+        macmiiar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_mr(reg);
+            w.set_mw(Mw::READ); // read operation
+            w.set_cr(self.clock_range);
+            w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
+        });
+        while macmiiar.read().mb() == MbProgress::BUSY {}
+        macmiidr.read().md()
+    }
+
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
+        let (macmiiar, macmiidr) = T::regs();
+
+        macmiidr.write(|w| w.set_md(val));
+        macmiiar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_mr(reg);
+            w.set_mw(Mw::WRITE); // write
+            w.set_cr(self.clock_range);
+            w.set_mb(MbProgress::BUSY);
+        });
+        while macmiiar.read().mb() == MbProgress::BUSY {}
+    }
+}
+
+impl<T: Instance> Drop for Sma<'_, T> {
+    fn drop(&mut self) {
+        self.pins.iter_mut().for_each(|p| p.set_as_disconnected());
+    }
+}
diff --git a/embassy-stm32/src/eth/sma/v2.rs b/embassy-stm32/src/eth/sma/v2.rs
new file mode 100644
index 000000000..6bc5230b5
--- /dev/null
+++ b/embassy-stm32/src/eth/sma/v2.rs
@@ -0,0 +1,94 @@
+use embassy_hal_internal::Peri;
+pub(crate) use regs::{Macmdioar as AddressRegister, Macmdiodr as DataRegister};
+use stm32_metapac::eth::regs;
+
+use super::{Instance, StationManagement};
+use crate::eth::{MDCPin, MDIOPin};
+use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+
+/// Station Management Agent.
+///
+/// This peripheral is used for SMI reads and writes to the connected
+/// ethernet PHY/device(s).
+pub struct Sma<'d, T: Instance> {
+    _peri: Peri<'d, T>,
+    pins: [Peri<'d, AnyPin>; 2],
+    clock_range: u8,
+}
+
+impl<'d, T: Instance> Sma<'d, T> {
+    /// Create a new instance of this peripheral.
+    pub fn new(peri: Peri<'d, T>, mdio: Peri<'d, impl MDIOPin<T>>, mdc: Peri<'d, impl MDCPin<T>>) -> Self {
+        set_as_af!(mdio, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        set_as_af!(mdc, AfType::output(OutputType::PushPull, Speed::VeryHigh));
+
+        // Enable necessary clocks.
+        critical_section::with(|_| {
+            crate::pac::RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+            })
+        });
+
+        let hclk = unsafe { crate::rcc::get_freqs().hclk1.to_hertz() };
+        let hclk = unwrap!(hclk, "SMA requires HCLK to be enabled, but it was not.");
+        let hclk_mhz = hclk.0 / 1_000_000;
+
+        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
+        let clock_range = match hclk_mhz {
+            0..=34 => 2,    // Divide by 16
+            35..=59 => 3,   // Divide by 26
+            60..=99 => 0,   // Divide by 42
+            100..=149 => 1, // Divide by 62
+            150..=249 => 4, // Divide by 102
+            250..=310 => 5, // Divide by 124
+            _ => {
+                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
+            }
+        };
+
+        Self {
+            _peri: peri,
+            clock_range,
+            pins: [mdio.into(), mdc.into()],
+        }
+    }
+}
+
+impl<T: Instance> StationManagement for Sma<'_, T> {
+    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
+        let (macmdioar, macmdiodr) = T::regs();
+
+        macmdioar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_rda(reg);
+            w.set_goc(0b11); // read
+            w.set_cr(self.clock_range);
+            w.set_mb(true);
+        });
+
+        while macmdioar.read().mb() {}
+
+        macmdiodr.read().md()
+    }
+
+    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
+        let (macmdioar, macmdiodr) = T::regs();
+
+        macmdiodr.write(|w| w.set_md(val));
+        macmdioar.modify(|w| {
+            w.set_pa(phy_addr);
+            w.set_rda(reg);
+            w.set_goc(0b01); // write
+            w.set_cr(self.clock_range);
+            w.set_mb(true);
+        });
+
+        while macmdioar.read().mb() {}
+    }
+}
+
+impl<T: Instance> Drop for Sma<'_, T> {
+    fn drop(&mut self) {
+        self.pins.iter_mut().for_each(|p| p.set_as_disconnected());
+    }
+}
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index 5be1c9739..8de26ce9d 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -3,11 +3,10 @@
 mod rx_desc;
 mod tx_desc;
 
-use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
-use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
+use stm32_metapac::eth::vals::{Apcs, Dm, DmaomrSr, Fes, Ftf, Ifg, Pbl, Rsf, St, Tsf};
 
 pub(crate) use self::rx_desc::{RDes, RDesRing};
 pub(crate) use self::tx_desc::{TDes, TDesRing};
@@ -22,7 +21,6 @@ use crate::pac::AFIO;
 #[cfg(any(eth_v1b, eth_v1c))]
 use crate::pac::SYSCFG;
 use crate::pac::{ETH, RCC};
-use crate::rcc::SealedRccPeripheral;
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -53,14 +51,13 @@ pub struct Ethernet<'d, T: Instance, P: Phy> {
 
     pins: Pins<'d>,
     pub(crate) phy: P,
-    pub(crate) station_management: EthernetStationManagement<T>,
     pub(crate) mac_addr: [u8; 6],
 }
 
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([Peri<'d, AnyPin>; 9]),
-    Mii([Peri<'d, AnyPin>; 14]),
+    Rmii([Peri<'d, AnyPin>; 7]),
+    Mii([Peri<'d, AnyPin>; 12]),
 }
 
 #[cfg(eth_v1a)]
@@ -97,68 +94,105 @@ macro_rules! config_pins {
     };
 }
 
-impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+impl<'d, T: Instance, SMA: sma::Instance> Ethernet<'d, T, GenericPhy<Sma<'d, SMA>>> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    ///
     /// safety: the returned instance is not leak-safe
     pub fn new<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         ref_clk: Peri<'d, if_afio!(impl RefClkPin<T, A>)>,
-        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
-        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
         crs: Peri<'d, if_afio!(impl CRSPin<T, A>)>,
         rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
         rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
         tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
         tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
         tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
-        phy: P,
         mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<SMA, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<SMA, A>)>,
     ) -> Self {
-        // Enable the necessary Clocks
-        #[cfg(eth_v1a)]
-        critical_section::with(|_| {
-            RCC.apb2enr().modify(|w| w.set_afioen(true));
-
-            // Select RMII (Reduced Media Independent Interface)
-            // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| {
-                w.set_mii_rmii_sel(true);
-                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
-            });
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            RCC.ahbenr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-        });
+        Self::new_with_phy(
+            queue, peri, irq, ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en, mac_addr, phy,
+        )
+    }
 
-        #[cfg(any(eth_v1b, eth_v1c))]
-        critical_section::with(|_| {
-            RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
+    /// Create a new MII ethernet driver using 14 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_mii_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    pub fn new_mii<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        rx_clk: Peri<'d, if_afio!(impl RXClkPin<T, A>)>,
+        tx_clk: Peri<'d, if_afio!(impl TXClkPin<T, A>)>,
+        rxdv: Peri<'d, if_afio!(impl RXDVPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        rx_d2: Peri<'d, if_afio!(impl RXD2Pin<T, A>)>,
+        rx_d3: Peri<'d, if_afio!(impl RXD3Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_d2: Peri<'d, if_afio!(impl TXD2Pin<T, A>)>,
+        tx_d3: Peri<'d, if_afio!(impl TXD3Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
+        mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, if_afio!(impl MDIOPin<SMA, A>)>,
+        mdc: Peri<'d, if_afio!(impl MDCPin<SMA, A>)>,
+    ) -> Self {
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            // RMII (Reduced Media Independent Interface)
-            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
-        });
+        Self::new_mii_with_phy(
+            queue, peri, irq, rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en,
+            mac_addr, phy,
+        )
+    }
+}
 
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+    /// safety: the returned instance is not leak-safe
+    pub fn new_with_phy<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        ref_clk: Peri<'d, if_afio!(impl RefClkPin<T, A>)>,
+        crs: Peri<'d, if_afio!(impl CRSPin<T, A>)>,
+        rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
+        rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
+        tx_d0: Peri<'d, if_afio!(impl TXD0Pin<T, A>)>,
+        tx_d1: Peri<'d, if_afio!(impl TXD1Pin<T, A>)>,
+        tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
+        mac_addr: [u8; 6],
+        phy: P,
+    ) -> Self {
         #[cfg(eth_v1a)]
         {
             config_in_pins!(ref_clk, rx_d0, rx_d1);
-            config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_en);
+            config_af_pins!(tx_d0, tx_d1, tx_en);
         }
 
         #[cfg(any(eth_v1b, eth_v1c))]
-        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+        config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
         let pins = Pins::Rmii([
             ref_clk.into(),
-            mdio.into(),
-            mdc.into(),
             crs.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -167,7 +201,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, true)
     }
 
     fn new_inner<const TX: usize, const RX: usize>(
@@ -177,7 +211,39 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         pins: Pins<'d>,
         phy: P,
         mac_addr: [u8; 6],
+        rmii_mii_sel: bool,
     ) -> Self {
+        // Enable the necessary Clocks
+        #[cfg(eth_v1a)]
+        critical_section::with(|_| {
+            RCC.apb2enr().modify(|w| w.set_afioen(true));
+
+            // Select (R)MII (Reduced Media Independent Interface)
+            // Must be done prior to enabling peripheral clock
+            AFIO.mapr().modify(|w| {
+                w.set_mii_rmii_sel(rmii_mii_sel);
+                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
+            });
+
+            RCC.ahbenr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+        });
+
+        #[cfg(any(eth_v1b, eth_v1c))]
+        critical_section::with(|_| {
+            RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+
+            // (R)MII ((Reduced) Media Independent Interface)
+            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(rmii_mii_sel));
+        });
+
         let dma = T::regs().ethernet_dma();
         let mac = T::regs().ethernet_mac();
 
@@ -190,7 +256,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
             w.set_fes(Fes::FES100); // fast ethernet speed
             w.set_dm(Dm::FULL_DUPLEX); // full duplex
-                                       // TODO: Carrier sense ? ECRSFD
+            // TODO: Carrier sense ? ECRSFD
         });
 
         // Set the mac to pass all multicast packets
@@ -226,30 +292,10 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
 
         // TODO MTU size setting not found for v1 ethernet, check if correct
 
-        let hclk = <T as SealedRccPeripheral>::frequency();
-        let hclk_mhz = hclk.0 / 1_000_000;
-
-        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
-        let clock_range = match hclk_mhz {
-            0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
-            25..=34 => Cr::CR_20_35,     // Divide by 16
-            35..=59 => Cr::CR_35_60,     // Divide by 26
-            60..=99 => Cr::CR_60_100,    // Divide by 42
-            100..=149 => Cr::CR_100_150, // Divide by 62
-            150..=216 => Cr::CR_150_168, // Divide by 102
-            _ => {
-                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
-            }
-        };
-
         let mut this = Self {
             _peri: peri,
             pins,
             phy: phy,
-            station_management: EthernetStationManagement {
-                peri: PhantomData,
-                clock_range: clock_range,
-            },
             mac_addr,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
             rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
@@ -279,8 +325,8 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_tie(true);
         });
 
-        this.phy.phy_reset(&mut this.station_management);
-        this.phy.phy_init(&mut this.station_management);
+        this.phy.phy_reset();
+        this.phy.phy_init();
 
         interrupt::ETH.unpend();
         unsafe { interrupt::ETH.enable() };
@@ -288,15 +334,13 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         this
     }
 
-    /// Create a new MII ethernet driver using 14 pins.
-    pub fn new_mii<const TX: usize, const RX: usize, #[cfg(afio)] A>(
+    /// Create a new MII ethernet driver using 12 pins.
+    pub fn new_mii_with_phy<const TX: usize, const RX: usize, #[cfg(afio)] A>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         rx_clk: Peri<'d, if_afio!(impl RXClkPin<T, A>)>,
         tx_clk: Peri<'d, if_afio!(impl TXClkPin<T, A>)>,
-        mdio: Peri<'d, if_afio!(impl MDIOPin<T, A>)>,
-        mdc: Peri<'d, if_afio!(impl MDCPin<T, A>)>,
         rxdv: Peri<'d, if_afio!(impl RXDVPin<T, A>)>,
         rx_d0: Peri<'d, if_afio!(impl RXD0Pin<T, A>)>,
         rx_d1: Peri<'d, if_afio!(impl RXD1Pin<T, A>)>,
@@ -307,56 +351,23 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         tx_d2: Peri<'d, if_afio!(impl TXD2Pin<T, A>)>,
         tx_d3: Peri<'d, if_afio!(impl TXD3Pin<T, A>)>,
         tx_en: Peri<'d, if_afio!(impl TXEnPin<T, A>)>,
-        phy: P,
         mac_addr: [u8; 6],
+        phy: P,
     ) -> Self {
-        // TODO: Handle optional signals like CRS, MII_COL, RX_ER?
-
-        // Enable the necessary Clocks
-        #[cfg(eth_v1a)]
-        critical_section::with(|_| {
-            RCC.apb2enr().modify(|w| w.set_afioen(true));
-
-            // Select MII (Media Independent Interface)
-            // Must be done prior to enabling peripheral clock
-            AFIO.mapr().modify(|w| {
-                w.set_mii_rmii_sel(false);
-                w.set_swj_cfg(crate::pac::afio::vals::SwjCfg::NO_OP);
-            });
-
-            RCC.ahbenr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-        });
-
-        #[cfg(any(eth_v1b, eth_v1c))]
-        critical_section::with(|_| {
-            RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-
-            // MII (Media Independent Interface)
-            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(false));
-        });
-
         #[cfg(eth_v1a)]
         {
             config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv);
-            config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+            config_af_pins!(tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
         }
 
         #[cfg(any(eth_v1b, eth_v1c))]
-        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        config_pins!(
+            rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+        );
 
         let pins = Pins::Mii([
             rx_clk.into(),
             tx_clk.into(),
-            mdio.into(),
-            mdc.into(),
             rxdv.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -369,43 +380,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
-    }
-}
-
-/// Ethernet station management interface.
-pub(crate) struct EthernetStationManagement<T: Instance> {
-    peri: PhantomData<T>,
-    clock_range: Cr,
-}
-
-impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmiiar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_mr(reg);
-            w.set_mw(Mw::READ); // read operation
-            w.set_cr(self.clock_range);
-            w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
-        });
-        while mac.macmiiar().read().mb() == MbProgress::BUSY {}
-        mac.macmiidr().read().md()
-    }
-
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmiidr().write(|w| w.set_md(val));
-        mac.macmiiar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_mr(reg);
-            w.set_mw(Mw::WRITE); // write
-            w.set_cr(self.clock_range);
-            w.set_mb(MbProgress::BUSY);
-        });
-        while mac.macmiiar().read().mb() == MbProgress::BUSY {}
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, false)
     }
 }
 
diff --git a/embassy-stm32/src/eth/v1/rx_desc.rs b/embassy-stm32/src/eth/v1/rx_desc.rs
index 2a46c1895..6ade1f29c 100644
--- a/embassy-stm32/src/eth/v1/rx_desc.rs
+++ b/embassy-stm32/src/eth/v1/rx_desc.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{compiler_fence, fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence, fence};
 
 use stm32_metapac::eth::vals::{Rpd, Rps};
 use vcell::VolatileCell;
diff --git a/embassy-stm32/src/eth/v1/tx_desc.rs b/embassy-stm32/src/eth/v1/tx_desc.rs
index 1317d20f4..ba99b66cb 100644
--- a/embassy-stm32/src/eth/v1/tx_desc.rs
+++ b/embassy-stm32/src/eth/v1/tx_desc.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{compiler_fence, fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence, fence};
 
 use vcell::VolatileCell;
 
diff --git a/embassy-stm32/src/eth/v2/descriptors.rs b/embassy-stm32/src/eth/v2/descriptors.rs
index 645bfdb14..e335ed8f3 100644
--- a/embassy-stm32/src/eth/v2/descriptors.rs
+++ b/embassy-stm32/src/eth/v2/descriptors.rs
@@ -1,4 +1,4 @@
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use vcell::VolatileCell;
 
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index cf7a9901b..7f92e351c 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -1,7 +1,6 @@
 mod descriptors;
 
-use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::Peri;
 use stm32_metapac::syscfg::vals::EthSelPhy;
@@ -12,7 +11,6 @@ use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
 use crate::interrupt;
 use crate::interrupt::InterruptExt;
 use crate::pac::ETH;
-use crate::rcc::SealedRccPeripheral;
 
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -42,14 +40,13 @@ pub struct Ethernet<'d, T: Instance, P: Phy> {
     pub(crate) rx: RDesRing<'d>,
     pins: Pins<'d>,
     pub(crate) phy: P,
-    pub(crate) station_management: EthernetStationManagement<T>,
     pub(crate) mac_addr: [u8; 6],
 }
 
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([Peri<'d, AnyPin>; 9]),
-    Mii([Peri<'d, AnyPin>; 14]),
+    Rmii([Peri<'d, AnyPin>; 7]),
+    Mii([Peri<'d, AnyPin>; 12]),
 }
 
 macro_rules! config_pins {
@@ -63,41 +60,96 @@ macro_rules! config_pins {
     };
 }
 
-impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
-    /// Create a new RMII ethernet driver using 9 pins.
+impl<'d, T: Instance, SMA: sma::Instance> Ethernet<'d, T, GenericPhy<Sma<'d, SMA>>> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
     pub fn new<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         ref_clk: Peri<'d, impl RefClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
         crs: Peri<'d, impl CRSPin<T>>,
         rx_d0: Peri<'d, impl RXD0Pin<T>>,
         rx_d1: Peri<'d, impl RXD1Pin<T>>,
         tx_d0: Peri<'d, impl TXD0Pin<T>>,
         tx_d1: Peri<'d, impl TXD1Pin<T>>,
         tx_en: Peri<'d, impl TXEnPin<T>>,
-        phy: P,
         mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, impl MDIOPin<SMA>>,
+        mdc: Peri<'d, impl MDCPin<SMA>>,
     ) -> Self {
-        // Enable the necessary clocks
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
 
-            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
-        });
+        Self::new_with_phy(
+            queue, peri, irq, ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en, mac_addr, phy,
+        )
+    }
+
+    /// Create a new MII ethernet driver using 14 pins.
+    ///
+    /// This function uses a [`GenericPhy::new_auto`] as PHY, created using the
+    /// provided [`SMA`](sma::Instance), and MDIO and MDC pins.
+    ///
+    /// See [`Ethernet::new_mii_with_phy`] for creating an RMII ethernet
+    /// river with a non-standard PHY.
+    pub fn new_mii<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        rx_clk: Peri<'d, impl RXClkPin<T>>,
+        tx_clk: Peri<'d, impl TXClkPin<T>>,
+        rxdv: Peri<'d, impl RXDVPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        rx_d2: Peri<'d, impl RXD2Pin<T>>,
+        rx_d3: Peri<'d, impl RXD3Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_d2: Peri<'d, impl TXD2Pin<T>>,
+        tx_d3: Peri<'d, impl TXD3Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
+        mac_addr: [u8; 6],
+        sma: Peri<'d, SMA>,
+        mdio: Peri<'d, impl MDIOPin<SMA>>,
+        mdc: Peri<'d, impl MDCPin<SMA>>,
+    ) -> Self {
+        let sma = Sma::new(sma, mdio, mdc);
+        let phy = GenericPhy::new_auto(sma);
+
+        Self::new_mii_with_phy(
+            queue, peri, irq, rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en,
+            mac_addr, phy,
+        )
+    }
+}
 
-        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+    /// Create a new RMII ethernet driver using 7 pins.
+    pub fn new_with_phy<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
+        crs: Peri<'d, impl CRSPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
+        mac_addr: [u8; 6],
+        phy: P,
+    ) -> Self {
+        config_pins!(ref_clk, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
 
         let pins = Pins::Rmii([
             ref_clk.into(),
-            mdio.into(),
-            mdc.into(),
             crs.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -106,18 +158,16 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::RMII)
     }
 
-    /// Create a new MII ethernet driver using 14 pins.
-    pub fn new_mii<const TX: usize, const RX: usize>(
+    /// Create a new MII ethernet driver using 12 pins.
+    pub fn new_mii_with_phy<const TX: usize, const RX: usize>(
         queue: &'d mut PacketQueue<TX, RX>,
         peri: Peri<'d, T>,
         irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
         rx_clk: Peri<'d, impl RXClkPin<T>>,
         tx_clk: Peri<'d, impl TXClkPin<T>>,
-        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: Peri<'d, impl MDCPin<T>>,
         rxdv: Peri<'d, impl RXDVPin<T>>,
         rx_d0: Peri<'d, impl RXD0Pin<T>>,
         rx_d1: Peri<'d, impl RXD1Pin<T>>,
@@ -128,29 +178,16 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         tx_d2: Peri<'d, impl TXD2Pin<T>>,
         tx_d3: Peri<'d, impl TXD3Pin<T>>,
         tx_en: Peri<'d, impl TXEnPin<T>>,
-        phy: P,
         mac_addr: [u8; 6],
+        phy: P,
     ) -> Self {
-        // Enable the necessary clocks
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_ethen(true);
-                w.set_ethtxen(true);
-                w.set_ethrxen(true);
-            });
-
-            crate::pac::SYSCFG
-                .pmcr()
-                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
-        });
-
-        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        config_pins!(
+            rx_clk, tx_clk, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en
+        );
 
         let pins = Pins::Mii([
             rx_clk.into(),
             tx_clk.into(),
-            mdio.into(),
-            mdc.into(),
             rxdv.into(),
             rx_d0.into(),
             rx_d1.into(),
@@ -163,7 +200,7 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             tx_en.into(),
         ]);
 
-        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr, EthSelPhy::MII_GMII)
     }
 
     fn new_inner<const TX: usize, const RX: usize>(
@@ -173,7 +210,19 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
         pins: Pins<'d>,
         phy: P,
         mac_addr: [u8; 6],
+        eth_sel_phy: EthSelPhy,
     ) -> Self {
+        // Enable the necessary clocks
+        critical_section::with(|_| {
+            crate::pac::RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+
+            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(eth_sel_phy));
+        });
+
         let dma = T::regs().ethernet_dma();
         let mac = T::regs().ethernet_mac();
         let mtl = T::regs().ethernet_mtl();
@@ -235,32 +284,12 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_rbsz(RX_BUFFER_SIZE as u16);
         });
 
-        let hclk = <T as SealedRccPeripheral>::frequency();
-        let hclk_mhz = hclk.0 / 1_000_000;
-
-        // Set the MDC clock frequency in the range 1MHz - 2.5MHz
-        let clock_range = match hclk_mhz {
-            0..=34 => 2,    // Divide by 16
-            35..=59 => 3,   // Divide by 26
-            60..=99 => 0,   // Divide by 42
-            100..=149 => 1, // Divide by 62
-            150..=249 => 4, // Divide by 102
-            250..=310 => 5, // Divide by 124
-            _ => {
-                panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
-            }
-        };
-
         let mut this = Self {
             _peri: peri,
             tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
             rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
             pins,
             phy,
-            station_management: EthernetStationManagement {
-                peri: PhantomData,
-                clock_range: clock_range,
-            },
             mac_addr,
         };
 
@@ -286,8 +315,8 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
             w.set_tie(true);
         });
 
-        this.phy.phy_reset(&mut this.station_management);
-        this.phy.phy_init(&mut this.station_management);
+        this.phy.phy_reset();
+        this.phy.phy_init();
 
         interrupt::ETH.unpend();
         unsafe { interrupt::ETH.enable() };
@@ -296,42 +325,6 @@ impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
     }
 }
 
-/// Ethernet SMI driver.
-pub struct EthernetStationManagement<T: Instance> {
-    peri: PhantomData<T>,
-    clock_range: u8,
-}
-
-impl<T: Instance> StationManagement for EthernetStationManagement<T> {
-    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmdioar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_rda(reg);
-            w.set_goc(0b11); // read
-            w.set_cr(self.clock_range);
-            w.set_mb(true);
-        });
-        while mac.macmdioar().read().mb() {}
-        mac.macmdiodr().read().md()
-    }
-
-    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16) {
-        let mac = T::regs().ethernet_mac();
-
-        mac.macmdiodr().write(|w| w.set_md(val));
-        mac.macmdioar().modify(|w| {
-            w.set_pa(phy_addr);
-            w.set_rda(reg);
-            w.set_goc(0b01); // write
-            w.set_cr(self.clock_range);
-            w.set_mb(true);
-        });
-        while mac.macmdioar().read().mb() {}
-    }
-}
-
 impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
     fn drop(&mut self) {
         let dma = T::regs().ethernet_dma();
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 9fce78f95..7b7896d46 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,13 +5,16 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
 
-use embassy_hal_internal::{impl_peripheral, PeripheralType};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
+use futures_util::FutureExt;
 
-use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
-use crate::pac::exti::regs::Lines;
+use crate::gpio::{AnyPin, ExtiPin, Input, Level, Pin as GpioPin, PinNumber, Pull};
+use crate::interrupt::Interrupt as InterruptEnum;
+use crate::interrupt::typelevel::{Binding, Handler, Interrupt as InterruptType};
 use crate::pac::EXTI;
-use crate::{interrupt, pac, peripherals, Peri};
+use crate::pac::exti::regs::Lines;
+use crate::{Peri, pac};
 
 const EXTI_COUNT: usize = 16;
 static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
@@ -31,11 +34,11 @@ fn cpu_regs() -> pac::exti::Exti {
     EXTI
 }
 
-#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50)))]
+#[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, gpio_v1, exti_u5, exti_h5, exti_h50, exti_n6)))]
 fn exticr_regs() -> pac::syscfg::Syscfg {
     pac::SYSCFG
 }
-#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+#[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
 fn exticr_regs() -> pac::exti::Exti {
     EXTI
 }
@@ -45,9 +48,9 @@ fn exticr_regs() -> pac::afio::Afio {
 }
 
 unsafe fn on_irq() {
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
     let bits = EXTI.pr(0).read().0;
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
     let bits = EXTI.rpr(0).read().0 | EXTI.fpr(0).read().0;
 
     // We don't handle or change any EXTI lines above 16.
@@ -62,16 +65,16 @@ unsafe fn on_irq() {
     }
 
     // Clear pending
-    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
     EXTI.pr(0).write_value(Lines(bits));
-    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
     {
         EXTI.rpr(0).write_value(Lines(bits));
         EXTI.fpr(0).write_value(Lines(bits));
     }
 
     #[cfg(feature = "low-power")]
-    crate::low_power::on_wakeup_irq();
+    crate::low_power::Executor::on_wakeup_irq();
 }
 
 struct BitIter(u32);
@@ -105,10 +108,17 @@ impl<'d> Unpin for ExtiInput<'d> {}
 
 impl<'d> ExtiInput<'d> {
     /// Create an EXTI input.
-    pub fn new<T: GpioPin>(pin: Peri<'d, T>, ch: Peri<'d, T::ExtiChannel>, pull: Pull) -> Self {
-        // Needed if using AnyPin+AnyChannel.
-        assert_eq!(pin.pin(), ch.number());
-
+    ///
+    /// The Binding must bind the Channel's IRQ to [InterruptHandler].
+    pub fn new<T: ExtiPin + GpioPin>(
+        pin: Peri<'d, T>,
+        _ch: Peri<'d, T::ExtiChannel>,
+        pull: Pull,
+        _irq: impl Binding<
+            <<T as ExtiPin>::ExtiChannel as Channel>::IRQ,
+            InterruptHandler<<<T as ExtiPin>::ExtiChannel as Channel>::IRQ>,
+        >,
+    ) -> Self {
         Self {
             pin: Input::new(pin, pull),
         }
@@ -133,7 +143,7 @@ impl<'d> ExtiInput<'d> {
     ///
     /// This returns immediately if the pin is already high.
     pub async fn wait_for_high(&mut self) {
-        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false);
+        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, true);
         if self.is_high() {
             return;
         }
@@ -144,7 +154,7 @@ impl<'d> ExtiInput<'d> {
     ///
     /// This returns immediately if the pin is already low.
     pub async fn wait_for_low(&mut self) {
-        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true);
+        let fut = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, true);
         if self.is_low() {
             return;
         }
@@ -155,19 +165,40 @@ impl<'d> ExtiInput<'d> {
     ///
     /// If the pin is already high, it will wait for it to go low then back high.
     pub async fn wait_for_rising_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, true).await
+    }
+
+    /// Asynchronously wait until the pin sees a rising edge.
+    ///
+    /// If the pin is already high, it will wait for it to go low then back high.
+    pub fn poll_for_rising_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ =
+            ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, false, false).poll_unpin(cx);
     }
 
     /// Asynchronously wait until the pin sees a falling edge.
     ///
     /// If the pin is already low, it will wait for it to go high then back low.
     pub async fn wait_for_falling_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, true).await
+    }
+
+    /// Asynchronously wait until the pin sees a falling edge.
+    ///
+    /// If the pin is already low, it will wait for it to go high then back low.
+    pub fn poll_for_falling_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ =
+            ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), false, true, false).poll_unpin(cx);
     }
 
     /// Asynchronously wait until the pin sees any edge (either rising or falling).
     pub async fn wait_for_any_edge(&mut self) {
-        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true).await
+        ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true, true).await
+    }
+
+    /// Asynchronously wait until the pin sees any edge (either rising or falling).
+    pub fn poll_for_any_edge<'a>(&mut self, cx: &mut Context<'a>) {
+        let _ = ExtiInputFuture::new(self.pin.pin.pin.pin(), self.pin.pin.pin.port(), true, true, false).poll_unpin(cx);
     }
 }
 
@@ -226,12 +257,13 @@ impl<'d> embedded_hal_async::digital::Wait for ExtiInput<'d> {
 
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 struct ExtiInputFuture<'a> {
-    pin: u8,
+    pin: PinNumber,
+    drop: bool,
     phantom: PhantomData<&'a mut AnyPin>,
 }
 
 impl<'a> ExtiInputFuture<'a> {
-    fn new(pin: u8, port: u8, rising: bool, falling: bool) -> Self {
+    fn new(pin: PinNumber, port: PinNumber, rising: bool, falling: bool, drop: bool) -> Self {
         critical_section::with(|_| {
             let pin = pin as usize;
             exticr_regs().exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
@@ -239,9 +271,9 @@ impl<'a> ExtiInputFuture<'a> {
             EXTI.ftsr(0).modify(|w| w.set_line(pin, falling));
 
             // clear pending bit
-            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
+            #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6)))]
             EXTI.pr(0).write(|w| w.set_line(pin, true));
-            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
+            #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50, exti_n6))]
             {
                 EXTI.rpr(0).write(|w| w.set_line(pin, true));
                 EXTI.fpr(0).write(|w| w.set_line(pin, true));
@@ -252,6 +284,7 @@ impl<'a> ExtiInputFuture<'a> {
 
         Self {
             pin,
+            drop,
             phantom: PhantomData,
         }
     }
@@ -259,10 +292,12 @@ impl<'a> ExtiInputFuture<'a> {
 
 impl<'a> Drop for ExtiInputFuture<'a> {
     fn drop(&mut self) {
-        critical_section::with(|_| {
-            let pin = self.pin as _;
-            cpu_regs().imr(0).modify(|w| w.set_line(pin, false));
-        });
+        if self.drop {
+            critical_section::with(|_| {
+                let pin = self.pin as _;
+                cpu_regs().imr(0).modify(|w| w.set_line(pin, false));
+            });
+        }
     }
 }
 
@@ -302,7 +337,7 @@ macro_rules! foreach_exti_irq {
             (EXTI15) => { $action!(EXTI15); };
 
             // plus the weird ones
-            (EXTI0_1)   => { $action!( EXTI0_1 ); };
+            (EXTI0_1)   => { $action!(EXTI0_1); };
             (EXTI15_10) => { $action!(EXTI15_10); };
             (EXTI15_4)  => { $action!(EXTI15_4); };
             (EXTI1_0)   => { $action!(EXTI1_0); };
@@ -315,57 +350,67 @@ macro_rules! foreach_exti_irq {
     };
 }
 
-macro_rules! impl_irq {
-    ($e:ident) => {
-        #[allow(non_snake_case)]
-        #[cfg(feature = "rt")]
-        #[interrupt]
-        unsafe fn $e() {
-            on_irq()
-        }
-    };
+///EXTI interrupt handler. All EXTI interrupt vectors should be bound to this handler.
+///
+/// It is generic over the [Interrupt](InterruptType) rather
+/// than the [Channel] because it should not be bound multiple
+/// times to the same vector on chips which multiplex multiple EXTI interrupts into one vector.
+//
+// It technically doesn't need to be generic at all, except to satisfy the generic argument
+// of [Handler]. All EXTI interrupts eventually land in the same on_irq() function.
+pub struct InterruptHandler<T: crate::interrupt::typelevel::Interrupt> {
+    _phantom: PhantomData<T>,
 }
 
-foreach_exti_irq!(impl_irq);
+impl<T: InterruptType> Handler<T> for InterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        on_irq()
+    }
+}
 
 trait SealedChannel {}
 
 /// EXTI channel trait.
 #[allow(private_bounds)]
 pub trait Channel: PeripheralType + SealedChannel + Sized {
-    /// Get the EXTI channel number.
-    fn number(&self) -> u8;
+    /// EXTI channel number.
+    fn number(&self) -> PinNumber;
+    /// [Enum-level Interrupt](InterruptEnum), which may be the same for multiple channels.
+    fn irq(&self) -> InterruptEnum;
+    /// [Type-level Interrupt](InterruptType), which may be the same for multiple channels.
+    type IRQ: InterruptType;
 }
 
-/// Type-erased EXTI channel.
+//Doc isn't hidden in order to surface the explanation to users, even though it's completely inoperable, not just deprecated.
+//Entire type along with doc can probably be removed after deprecation has appeared in a release once.
+/// Deprecated type-erased EXTI channel.
 ///
-/// This represents ownership over any EXTI channel, known at runtime.
+/// Support for AnyChannel was removed in order to support manually bindable EXTI interrupts via bind_interrupts; [ExtiInput::new()]
+/// must know the required IRQ at compile time, and therefore cannot support type-erased channels.
+#[deprecated = "type-erased EXTI channels are no longer supported, in order to support manually bindable EXTI interrupts (more info: https://github.com/embassy-rs/embassy/pull/4922)"]
 pub struct AnyChannel {
-    number: u8,
-}
-
-impl_peripheral!(AnyChannel);
-impl SealedChannel for AnyChannel {}
-impl Channel for AnyChannel {
-    fn number(&self) -> u8 {
-        self.number
-    }
+    #[allow(unused)]
+    number: PinNumber,
 }
 
 macro_rules! impl_exti {
     ($type:ident, $number:expr) => {
-        impl SealedChannel for peripherals::$type {}
-        impl Channel for peripherals::$type {
-            fn number(&self) -> u8 {
+        impl SealedChannel for crate::peripherals::$type {}
+        impl Channel for crate::peripherals::$type {
+            fn number(&self) -> PinNumber {
                 $number
             }
+            fn irq(&self) -> InterruptEnum {
+                crate::_generated::peripheral_interrupts::EXTI::$type::IRQ
+            }
+            type IRQ = crate::_generated::peripheral_interrupts::EXTI::$type;
         }
 
-        impl From<peripherals::$type> for AnyChannel {
-            fn from(val: peripherals::$type) -> Self {
-                Self {
-                    number: val.number() as u8,
-                }
+        //Still here to surface deprecation messages to the user - remove when removing AnyChannel
+        #[allow(deprecated)]
+        impl From<crate::peripherals::$type> for AnyChannel {
+            fn from(_val: crate::peripherals::$type) -> Self {
+                Self { number: $number }
             }
         }
     };
diff --git a/embassy-stm32/src/flash/asynch.rs b/embassy-stm32/src/flash/asynch.rs
index 006dcddeb..a131217b7 100644
--- a/embassy-stm32/src/flash/asynch.rs
+++ b/embassy-stm32/src/flash/asynch.rs
@@ -1,17 +1,17 @@
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::mutex::Mutex;
 
 use super::{
-    blocking_read, ensure_sector_aligned, family, get_flash_regions, get_sector, Async, Error, Flash, FlashLayout,
-    FLASH_BASE, FLASH_SIZE, WRITE_SIZE,
+    Async, Error, FLASH_BASE, FLASH_SIZE, Flash, FlashLayout, WRITE_SIZE, blocking_read, ensure_sector_aligned, family,
+    get_flash_regions, get_sector,
 };
 use crate::interrupt::InterruptExt;
 use crate::peripherals::FLASH;
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 pub(super) static REGION_ACCESS: Mutex<CriticalSectionRawMutex, ()> = Mutex::new(());
 
diff --git a/embassy-stm32/src/flash/c.rs b/embassy-stm32/src/flash/c.rs
new file mode 100644
index 000000000..0ad1002b0
--- /dev/null
+++ b/embassy-stm32/src/flash/c.rs
@@ -0,0 +1,131 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{Ordering, fence};
+
+use cortex_m::interrupt;
+
+use super::{FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    // Wait, while the memory interface is busy.
+    wait_busy();
+
+    // Unlock flash
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write_value(0x4567_0123);
+        pac::FLASH.keyr().write_value(0xCDEF_89AB);
+    }
+}
+
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    pac::FLASH.cr().write(|w| w.set_pg(true));
+}
+
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+}
+
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+
+    wait_ready_blocking()
+}
+
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+
+    #[cfg(feature = "defmt")]
+    defmt::trace!(
+        "STM32C0 Erase: addr=0x{:08x}, idx={}, erase_size={}",
+        sector.start,
+        idx,
+        super::BANK1_REGION.erase_size
+    );
+
+    wait_busy();
+    clear_all_err();
+
+    // Explicitly unlock before erase
+    unlock();
+
+    interrupt::free(|_| {
+        #[cfg(feature = "defmt")]
+        {
+            let cr_before = pac::FLASH.cr().read();
+            defmt::trace!("FLASH_CR before: 0x{:08x}", cr_before.0);
+        }
+
+        pac::FLASH.cr().modify(|w| {
+            w.set_per(true);
+            w.set_pnb(idx as u8);
+            w.set_strt(true);
+        });
+
+        #[cfg(feature = "defmt")]
+        {
+            let cr_after = pac::FLASH.cr().read();
+            defmt::trace!(
+                "FLASH_CR after: 0x{:08x}, PER={}, PNB={}, STRT={}",
+                cr_after.0,
+                cr_after.per(),
+                cr_after.pnb(),
+                cr_after.strt()
+            );
+        }
+    });
+
+    let ret: Result<(), Error> = wait_ready_blocking();
+
+    // Clear erase bit
+    pac::FLASH.cr().modify(|w| w.set_per(false));
+
+    // Explicitly lock after erase
+    lock();
+
+    // Extra wait to ensure operation completes
+    wait_busy();
+
+    ret
+}
+
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
+    while pac::FLASH.sr().read().bsy() {}
+
+    let sr = pac::FLASH.sr().read();
+
+    if sr.progerr() {
+        return Err(Error::Prog);
+    }
+
+    if sr.wrperr() {
+        return Err(Error::Protected);
+    }
+
+    if sr.pgaerr() {
+        return Err(Error::Unaligned);
+    }
+
+    Ok(())
+}
+
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
+
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() {}
+}
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index 10023e637..60d00e766 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -1,14 +1,14 @@
 use core::marker::PhantomData;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use embassy_hal_internal::drop::OnDrop;
 
 use super::{
-    family, get_flash_regions, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE,
-    MAX_ERASE_SIZE, READ_SIZE, WRITE_SIZE,
+    Async, Blocking, Error, FLASH_SIZE, FlashBank, FlashLayout, FlashRegion, FlashSector, MAX_ERASE_SIZE, READ_SIZE,
+    WRITE_SIZE, family, get_flash_regions,
 };
-use crate::Peri;
 use crate::_generated::FLASH_BASE;
+use crate::Peri;
 use crate::peripherals::FLASH;
 
 /// Internal flash memory driver.
@@ -102,7 +102,13 @@ pub(super) unsafe fn blocking_write(
     }
 
     let mut address = base + offset;
-    trace!("Writing {} bytes at 0x{:x}", bytes.len(), address);
+    trace!(
+        "Writing {} bytes at 0x{:x} (base=0x{:x}, offset=0x{:x})",
+        bytes.len(),
+        address,
+        base,
+        offset
+    );
 
     for chunk in bytes.chunks(WRITE_SIZE) {
         write_chunk(address, chunk)?;
diff --git a/embassy-stm32/src/flash/eeprom.rs b/embassy-stm32/src/flash/eeprom.rs
index cc3529eb9..39c497e3f 100644
--- a/embassy-stm32/src/flash/eeprom.rs
+++ b/embassy-stm32/src/flash/eeprom.rs
@@ -1,6 +1,6 @@
 use embassy_hal_internal::drop::OnDrop;
 
-use super::{family, Blocking, Error, Flash, EEPROM_BASE, EEPROM_SIZE};
+use super::{Blocking, EEPROM_BASE, EEPROM_SIZE, Error, Flash, family};
 
 #[cfg(eeprom)]
 impl<'d> Flash<'d, Blocking> {
diff --git a/embassy-stm32/src/flash/f0.rs b/embassy-stm32/src/flash/f0.rs
index 3f9dbe945..5c01fce9c 100644
--- a/embassy-stm32/src/flash/f0.rs
+++ b/embassy-stm32/src/flash/f0.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/f1f3.rs b/embassy-stm32/src/flash/f1f3.rs
index bf9ad2893..9e469ffbc 100644
--- a/embassy-stm32/src/flash/f1f3.rs
+++ b/embassy-stm32/src/flash/f1f3.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/f2.rs b/embassy-stm32/src/flash/f2.rs
index 67e380619..b48ab3b76 100644
--- a/embassy-stm32/src/flash/f2.rs
+++ b/embassy-stm32/src/flash/f2.rs
@@ -1,9 +1,9 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, Ordering, fence};
 
 use pac::flash::regs::Sr;
 
-use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use super::{FlashBank, FlashSector, WRITE_SIZE, get_flash_regions};
 use crate::flash::Error;
 use crate::pac;
 
diff --git a/embassy-stm32/src/flash/f4.rs b/embassy-stm32/src/flash/f4.rs
index 62e0492b5..9c5051492 100644
--- a/embassy-stm32/src/flash/f4.rs
+++ b/embassy-stm32/src/flash/f4.rs
@@ -1,10 +1,10 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, AtomicBool, Ordering};
+use core::sync::atomic::{AtomicBool, Ordering, fence};
 
 use embassy_sync::waitqueue::AtomicWaker;
 use pac::flash::regs::Sr;
 
-use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use super::{FlashBank, FlashSector, WRITE_SIZE, get_flash_regions};
 use crate::_generated::FLASH_SIZE;
 use crate::flash::Error;
 use crate::pac;
@@ -246,7 +246,9 @@ pub(crate) fn assert_not_corrupted_read(end_address: u32) {
         feature = "stm32f439zi",
     ))]
     if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
-        panic!("Read corruption for stm32f42xxI and stm32f43xxI when PA12 is in use for chips below revision 3, see errata 2.2.11");
+        panic!(
+            "Read corruption for stm32f42xxI and stm32f43xxI when PA12 is in use for chips below revision 3, see errata 2.2.11"
+        );
     }
 
     #[cfg(any(
@@ -270,14 +272,16 @@ pub(crate) fn assert_not_corrupted_read(end_address: u32) {
         feature = "stm32f439zg",
     ))]
     if second_bank_read && pac::DBGMCU.idcode().read().rev_id() < REVISION_3 && !pa12_is_output_pull_low() {
-        panic!("Read corruption for stm32f42xxG and stm32f43xxG in dual bank mode when PA12 is in use for chips below revision 3, see errata 2.2.11");
+        panic!(
+            "Read corruption for stm32f42xxG and stm32f43xxG in dual bank mode when PA12 is in use for chips below revision 3, see errata 2.2.11"
+        );
     }
 }
 
 #[allow(unused)]
 fn pa12_is_output_pull_low() -> bool {
-    use pac::gpio::vals;
     use pac::GPIOA;
+    use pac::gpio::vals;
     const PIN: usize = 12;
     GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
         && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
@@ -287,7 +291,7 @@ fn pa12_is_output_pull_low() -> bool {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use crate::flash::{get_sector, FlashBank};
+    use crate::flash::{FlashBank, get_sector};
 
     #[test]
     #[cfg(stm32f429)]
@@ -370,9 +374,13 @@ mod tests {
 #[cfg(all(bank_setup_configurable))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optcr().read().db1m() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optcr().read().db1m() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/f7.rs b/embassy-stm32/src/flash/f7.rs
index 0547c747a..09389c417 100644
--- a/embassy-stm32/src/flash/f7.rs
+++ b/embassy-stm32/src/flash/f7.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
@@ -99,7 +99,7 @@ unsafe fn blocking_wait_ready() -> Result<(), Error> {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use crate::flash::{get_sector, FlashBank};
+    use crate::flash::{FlashBank, get_sector};
 
     #[test]
     #[cfg(stm32f732)]
@@ -218,9 +218,13 @@ mod tests {
 #[cfg(all(bank_setup_configurable))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && !pac::FLASH.optcr().read().n_dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && pac::FLASH.optcr().read().n_dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index bc1fd360c..d7ba2f571 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use cortex_m::interrupt;
 
@@ -44,7 +44,6 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 }
 
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
-    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
     wait_busy();
     clear_all_err();
 
@@ -54,9 +53,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
             #[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
             w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
             #[cfg(flash_g0x0)]
-            w.set_pnb(idx as u16);
+            w.set_pnb(sector.index_in_bank as u16);
             #[cfg(not(flash_g0x0))]
-            w.set_pnb(idx as u8);
+            w.set_pnb(sector.index_in_bank as u8);
             w.set_strt(true);
         });
     });
@@ -105,19 +104,27 @@ fn wait_busy() {
 #[cfg(all(bank_setup_configurable, any(flash_g4c2, flash_g4c3, flash_g4c4)))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
 
 #[cfg(all(bank_setup_configurable, flash_g0x1))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dual_bank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dual_bank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/h5.rs b/embassy-stm32/src/flash/h5.rs
index fd9bfcc75..88f247879 100644
--- a/embassy-stm32/src/flash/h5.rs
+++ b/embassy-stm32/src/flash/h5.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/flash/h50.rs b/embassy-stm32/src/flash/h50.rs
index f8e210556..91d5da4d6 100644
--- a/embassy-stm32/src/flash/h50.rs
+++ b/embassy-stm32/src/flash/h50.rs
@@ -1,7 +1,7 @@
 /// STM32H50 series flash impl. See RM0492
 use core::{
     ptr::write_volatile,
-    sync::atomic::{fence, Ordering},
+    sync::atomic::{Ordering, fence},
 };
 
 use cortex_m::interrupt;
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index f1d84101c..b342f4a83 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -1,10 +1,31 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
-use super::{FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
+use embassy_sync::waitqueue::AtomicWaker;
+use pac::flash::regs::Sr;
+
+use super::{BANK1_REGION, FLASH_REGIONS, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
 
+static WAKER: AtomicWaker = AtomicWaker::new();
+
+pub(crate) unsafe fn on_interrupt() {
+    // Clear IRQ flags
+    pac::FLASH.bank(0).ccr().write(|w| {
+        w.set_clr_eop(true);
+        w.set_clr_operr(true);
+    });
+    if is_dual_bank() {
+        pac::FLASH.bank(1).ccr().write(|w| {
+            w.set_clr_eop(true);
+            w.set_clr_operr(true);
+        });
+    }
+
+    WAKER.wake();
+}
+
 const fn is_dual_bank() -> bool {
     FLASH_REGIONS.len() >= 2
 }
@@ -29,12 +50,68 @@ pub(crate) unsafe fn unlock() {
     }
 }
 
+pub(crate) unsafe fn enable_write() {
+    enable_blocking_write();
+}
+
+pub(crate) unsafe fn disable_write() {
+    disable_blocking_write();
+}
+
 pub(crate) unsafe fn enable_blocking_write() {
     assert_eq!(0, WRITE_SIZE % 4);
 }
 
 pub(crate) unsafe fn disable_blocking_write() {}
 
+pub(crate) async unsafe fn write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    // We cannot have the write setup sequence in begin_write as it depends on the address
+    let bank = if start_address < BANK1_REGION.end() {
+        pac::FLASH.bank(0)
+    } else {
+        pac::FLASH.bank(1)
+    };
+    bank.cr().write(|w| {
+        w.set_pg(true);
+        #[cfg(flash_h7)]
+        w.set_psize(2); // 32 bits at once
+        w.set_eopie(true);
+        w.set_operrie(true);
+    });
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    let mut res = None;
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+
+        res = Some(wait_ready(bank).await);
+        bank.sr().modify(|w| {
+            if w.eop() {
+                w.set_eop(true);
+            }
+        });
+        if unwrap!(res).is_err() {
+            break;
+        }
+    }
+
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    bank.cr().write(|w| {
+        w.set_pg(false);
+        w.set_eopie(false);
+        w.set_operrie(false);
+    });
+
+    unwrap!(res)
+}
+
 pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
     // We cannot have the write setup sequence in begin_write as it depends on the address
     let bank = if start_address < BANK1_REGION.end() {
@@ -77,6 +154,36 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
     unwrap!(res)
 }
 
+pub(crate) async unsafe fn erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    let bank = pac::FLASH.bank(sector.bank as usize);
+    bank.cr().modify(|w| {
+        w.set_ser(true);
+        #[cfg(flash_h7)]
+        w.set_snb(sector.index_in_bank);
+        #[cfg(flash_h7ab)]
+        w.set_ssn(sector.index_in_bank);
+        w.set_eopie(true);
+        w.set_operrie(true);
+    });
+
+    bank.cr().modify(|w| {
+        w.set_start(true);
+    });
+
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+
+    let ret: Result<(), Error> = wait_ready(bank).await;
+    bank.cr().modify(|w| {
+        w.set_ser(false);
+        w.set_eopie(false);
+        w.set_operrie(false);
+    });
+    bank_clear_all_err(bank);
+    ret
+}
+
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
     let bank = pac::FLASH.bank(sector.bank as usize);
     bank.cr().modify(|w| {
@@ -112,46 +219,59 @@ unsafe fn bank_clear_all_err(bank: pac::flash::Bank) {
     bank.sr().modify(|_| {});
 }
 
+async fn wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
+    use core::future::poll_fn;
+    use core::task::Poll;
+
+    poll_fn(|cx| {
+        WAKER.register(cx.waker());
+
+        let sr = bank.sr().read();
+        if !sr.bsy() && !sr.qw() {
+            Poll::Ready(get_result(sr))
+        } else {
+            return Poll::Pending;
+        }
+    })
+    .await
+}
+
 unsafe fn blocking_wait_ready(bank: pac::flash::Bank) -> Result<(), Error> {
     loop {
         let sr = bank.sr().read();
 
         if !sr.bsy() && !sr.qw() {
-            if sr.wrperr() {
-                return Err(Error::Protected);
-            }
-            if sr.pgserr() {
-                error!("pgserr");
-                return Err(Error::Seq);
-            }
-            if sr.incerr() {
-                // writing to a different address when programming 256 bit word was not finished
-                error!("incerr");
-                return Err(Error::Seq);
-            }
-            if sr.crcrderr() {
-                error!("crcrderr");
-                return Err(Error::Seq);
-            }
-            if sr.operr() {
-                return Err(Error::Prog);
-            }
-            if sr.sneccerr1() {
-                // single ECC error
-                return Err(Error::Prog);
-            }
-            if sr.dbeccerr() {
-                // double ECC error
-                return Err(Error::Prog);
-            }
-            if sr.rdperr() {
-                return Err(Error::Protected);
-            }
-            if sr.rdserr() {
-                return Err(Error::Protected);
-            }
-
-            return Ok(());
+            return get_result(sr);
         }
     }
 }
+
+fn get_result(sr: Sr) -> Result<(), Error> {
+    if sr.wrperr() {
+        Err(Error::Protected)
+    } else if sr.pgserr() {
+        error!("pgserr");
+        Err(Error::Seq)
+    } else if sr.incerr() {
+        // writing to a different address when programming 256 bit word was not finished
+        error!("incerr");
+        Err(Error::Seq)
+    } else if sr.crcrderr() {
+        error!("crcrderr");
+        Err(Error::Seq)
+    } else if sr.operr() {
+        Err(Error::Prog)
+    } else if sr.sneccerr1() {
+        // single ECC error
+        Err(Error::Prog)
+    } else if sr.dbeccerr() {
+        // double ECC error
+        Err(Error::Prog)
+    } else if sr.rdperr() {
+        Err(Error::Protected)
+    } else if sr.rdserr() {
+        Err(Error::Protected)
+    } else {
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/flash/l.rs b/embassy-stm32/src/flash/l.rs
index 1b82704ec..b3281f2d5 100644
--- a/embassy-stm32/src/flash/l.rs
+++ b/embassy-stm32/src/flash/l.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
@@ -96,14 +96,20 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
     #[cfg(any(flash_wl, flash_wb, flash_l4, flash_l5))]
     {
         let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
+        #[cfg(any(flash_l4, flash_l5))]
+        let pgn = super::BANK1_REGION.size as u32 / super::BANK1_REGION.erase_size as u32;
 
         #[cfg(flash_l4)]
-        let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
+        let (idx, bank) = if idx > (pgn - 1) {
+            (idx - pgn, true)
+        } else {
+            (idx, false)
+        };
 
         #[cfg(flash_l5)]
         let (idx, bank) = if pac::FLASH.optr().read().dbank() {
-            if idx > 255 {
-                (idx - 256, Some(true))
+            if idx > (pgn - 1) {
+                (idx - pgn, Some(true))
             } else {
                 (idx, Some(false))
             }
@@ -234,19 +240,27 @@ pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
 #[cfg(all(bank_setup_configurable, flash_l5))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
 
 #[cfg(all(bank_setup_configurable, flash_l4))]
 pub(crate) fn check_bank_setup() {
     if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dualbank() {
-        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use dual-bank config");
+        panic!(
+            "Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use dual-bank config"
+        );
     }
     if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dualbank() {
-        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use single-bank config");
+        panic!(
+            "Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use single-bank config"
+        );
     }
 }
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index 3e74d857a..6211a37b7 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -1,14 +1,14 @@
 //! Flash memory (FLASH)
 use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
 
-#[cfg(flash_f4)]
+#[cfg(any(flash_f4, flash_h7, flash_h7ab))]
 mod asynch;
 #[cfg(flash)]
 mod common;
 #[cfg(eeprom)]
 mod eeprom;
 
-#[cfg(flash_f4)]
+#[cfg(any(flash_f4, flash_h7, flash_h7ab))]
 pub use asynch::InterruptHandler;
 #[cfg(flash)]
 pub use common::*;
@@ -99,6 +99,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(flash_f4, path = "f4.rs")]
 #[cfg_attr(flash_f7, path = "f7.rs")]
 #[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
+#[cfg_attr(flash_c0, path = "c.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(any(flash_u5, flash_wba), path = "u5.rs")]
@@ -108,7 +109,7 @@ compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is
 #[cfg_attr(
     not(any(
         flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
-        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
+        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_c0, flash_h7, flash_h7ab, flash_u5,
         flash_wba, flash_h50, flash_u0, flash_h5,
     )),
     path = "other.rs"
diff --git a/embassy-stm32/src/flash/u0.rs b/embassy-stm32/src/flash/u0.rs
index 68d847eca..a64f6c492 100644
--- a/embassy-stm32/src/flash/u0.rs
+++ b/embassy-stm32/src/flash/u0.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use cortex_m::interrupt;
 
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
index 6c3d4b422..5f1f562c0 100644
--- a/embassy-stm32/src/flash/u5.rs
+++ b/embassy-stm32/src/flash/u5.rs
@@ -1,5 +1,5 @@
 use core::ptr::write_volatile;
-use core::sync::atomic::{fence, Ordering};
+use core::sync::atomic::{Ordering, fence};
 
 use super::{FlashBank, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index ff18a8bee..a7c6c90bb 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -4,7 +4,7 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Pull, Speed};
-use crate::{rcc, Peri};
+use crate::{Peri, rcc};
 
 /// FMC driver
 pub struct Fmc<'d, T: Instance> {
@@ -236,6 +236,42 @@ impl<'d, T: Instance> Fmc<'d, T> {
             (sdcke: SDCKE1Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE1Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
         ]
     ));
+
+    fmc_sdram_constructor!(sdram_a13bits_d16bits_4banks_bank1: (
+        bank: stm32_fmc::SdramTargetBank::Bank1,
+        addr: [
+            (a0: A0Pin), (a1: A1Pin), (a2: A2Pin), (a3: A3Pin), (a4: A4Pin), (a5: A5Pin), (a6: A6Pin), (a7: A7Pin), (a8: A8Pin), (a9: A9Pin), (a10: A10Pin), (a11: A11Pin), (a12: A12Pin)
+        ],
+        ba: [(ba0: BA0Pin), (ba1: BA1Pin)],
+        d: [
+            (d0: D0Pin), (d1: D1Pin), (d2: D2Pin), (d3: D3Pin), (d4: D4Pin), (d5: D5Pin), (d6: D6Pin), (d7: D7Pin),
+            (d8: D8Pin), (d9: D9Pin), (d10: D10Pin), (d11: D11Pin), (d12: D12Pin), (d13: D13Pin), (d14: D14Pin), (d15: D15Pin)
+        ],
+        nbl: [
+            (nbl0: NBL0Pin), (nbl1: NBL1Pin)
+        ],
+        ctrl: [
+            (sdcke: SDCKE0Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE0Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
+        ]
+    ));
+
+    fmc_sdram_constructor!(sdram_a13bits_d16bits_4banks_bank2: (
+        bank: stm32_fmc::SdramTargetBank::Bank2,
+        addr: [
+            (a0: A0Pin), (a1: A1Pin), (a2: A2Pin), (a3: A3Pin), (a4: A4Pin), (a5: A5Pin), (a6: A6Pin), (a7: A7Pin), (a8: A8Pin), (a9: A9Pin), (a10: A10Pin), (a11: A11Pin), (a12: A12Pin)
+        ],
+        ba: [(ba0: BA0Pin), (ba1: BA1Pin)],
+        d: [
+            (d0: D0Pin), (d1: D1Pin), (d2: D2Pin), (d3: D3Pin), (d4: D4Pin), (d5: D5Pin), (d6: D6Pin), (d7: D7Pin),
+            (d8: D8Pin), (d9: D9Pin), (d10: D10Pin), (d11: D11Pin), (d12: D12Pin), (d13: D13Pin), (d14: D14Pin), (d15: D15Pin)
+        ],
+        nbl: [
+            (nbl0: NBL0Pin), (nbl1: NBL1Pin)
+        ],
+        ctrl: [
+            (sdcke: SDCKE1Pin), (sdclk: SDCLKPin), (sdncas: SDNCASPin), (sdne: SDNE1Pin), (sdnras: SDNRASPin), (sdnwe: SDNWEPin)
+        ]
+    ));
 }
 
 trait SealedInstance: crate::rcc::RccPeripheral {
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 5a8d23183..e7d4e9ad3 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -4,7 +4,7 @@
 use core::convert::Infallible;
 
 use critical_section::CriticalSection;
-use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
+use embassy_hal_internal::{Peri, PeripheralType, impl_peripheral};
 
 use crate::pac::gpio::{self, vals};
 use crate::peripherals;
@@ -592,7 +592,7 @@ impl AfType {
 
 #[inline(never)]
 #[cfg(gpio_v1)]
-fn set_as_af(pin_port: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_type: AfType) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -649,7 +649,7 @@ impl AfType {
 
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
+fn set_as_af(pin_port: PinNumber, af_num: u8, af_type: AfType) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -663,7 +663,7 @@ fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
 
 #[inline(never)]
 #[cfg(gpio_v2)]
-fn set_speed(pin_port: u8, speed: Speed) {
+fn set_speed(pin_port: PinNumber, speed: Speed) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -672,7 +672,7 @@ fn set_speed(pin_port: u8, speed: Speed) {
 }
 
 #[inline(never)]
-fn set_as_analog(pin_port: u8) {
+fn set_as_analog(pin_port: PinNumber) {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -688,7 +688,7 @@ fn set_as_analog(pin_port: u8) {
 }
 
 #[inline(never)]
-fn get_pull(pin_port: u8) -> Pull {
+fn get_pull(pin_port: PinNumber) -> Pull {
     let pin = unsafe { AnyPin::steal(pin_port) };
     let r = pin.block();
     let n = pin._pin() as usize;
@@ -727,15 +727,15 @@ pub struct AfioRemapBool<const V: bool>;
 pub struct AfioRemapNotApplicable;
 
 pub(crate) trait SealedPin {
-    fn pin_port(&self) -> u8;
+    fn pin_port(&self) -> PinNumber;
 
     #[inline]
-    fn _pin(&self) -> u8 {
+    fn _pin(&self) -> PinNumber {
         self.pin_port() % 16
     }
 
     #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
         self.pin_port() / 16
     }
 
@@ -798,31 +798,49 @@ pub(crate) trait SealedPin {
     }
 }
 
-/// GPIO pin trait.
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(not(stm32n6))]
+pub type PinNumber = u8;
+
+/// GPIO pin number type.
+///
+/// Some chips have a total number of ports that exceeds 8, a larger integer
+/// is needed to hold the total pin number `(ports * number)`.
+#[cfg(stm32n6)]
+pub type PinNumber = u16;
+
+/// Pin that can be used to configure an [ExtiInput](crate::exti::ExtiInput). This trait is lost when converting to [AnyPin].
+#[cfg(feature = "exti")]
 #[allow(private_bounds)]
-pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
+pub trait ExtiPin: PeripheralType + SealedPin {
     /// EXTI channel assigned to this pin.
     ///
     /// For example, PC4 uses EXTI4.
-    #[cfg(feature = "exti")]
     type ExtiChannel: crate::exti::Channel;
+}
 
+/// GPIO pin trait.
+#[allow(private_bounds)]
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
     /// Number of the pin within the port (0..31)
     #[inline]
-    fn pin(&self) -> u8 {
+    fn pin(&self) -> PinNumber {
         self._pin()
     }
 
     /// Port of the pin
     #[inline]
-    fn port(&self) -> u8 {
+    fn port(&self) -> PinNumber {
         self._port()
     }
 }
 
-/// Type-erased GPIO pin
+/// Type-erased GPIO pin.
 pub struct AnyPin {
-    pin_port: u8,
+    pin_port: PinNumber,
 }
 
 impl AnyPin {
@@ -830,12 +848,12 @@ impl AnyPin {
     ///
     /// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
     #[inline]
-    pub unsafe fn steal(pin_port: u8) -> Peri<'static, Self> {
+    pub unsafe fn steal(pin_port: PinNumber) -> Peri<'static, Self> {
         Peri::new_unchecked(Self { pin_port })
     }
 
     #[inline]
-    fn _port(&self) -> u8 {
+    fn _port(&self) -> PinNumber {
         self.pin_port / 16
     }
 
@@ -848,13 +866,10 @@ impl AnyPin {
 }
 
 impl_peripheral!(AnyPin);
-impl Pin for AnyPin {
-    #[cfg(feature = "exti")]
-    type ExtiChannel = crate::exti::AnyChannel;
-}
+impl Pin for AnyPin {}
 impl SealedPin for AnyPin {
     #[inline]
-    fn pin_port(&self) -> u8 {
+    fn pin_port(&self) -> PinNumber {
         self.pin_port
     }
 }
@@ -864,12 +879,14 @@ impl SealedPin for AnyPin {
 foreach_pin!(
     ($pin_name:ident, $port_name:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => {
         impl Pin for peripherals::$pin_name {
-            #[cfg(feature = "exti")]
+        }
+        #[cfg(feature = "exti")]
+        impl ExtiPin for peripherals::$pin_name {
             type ExtiChannel = peripherals::$exti_ch;
         }
         impl SealedPin for peripherals::$pin_name {
             #[inline]
-            fn pin_port(&self) -> u8 {
+            fn pin_port(&self) -> PinNumber {
                 $port_num * 16 + $pin_num
             }
         }
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 90c06c0d8..ba573267c 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -19,7 +19,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::mode::Async;
 use crate::mode::{Blocking, Mode};
 use crate::peripherals::HASH;
-use crate::{interrupt, pac, peripherals, rcc, Peri};
+use crate::{Peri, interrupt, pac, peripherals, rcc};
 
 #[cfg(hash_v1)]
 const NUM_CONTEXT_REGS: usize = 51;
@@ -514,11 +514,7 @@ impl<'d, T: Instance> Hash<'d, T, Async> {
             T::regs().imr().modify(|reg| reg.set_dcie(true));
             // Check for completion.
             let bits = T::regs().sr().read();
-            if bits.dcis() {
-                Poll::Ready(())
-            } else {
-                Poll::Pending
-            }
+            if bits.dcis() { Poll::Ready(()) } else { Poll::Pending }
         })
         .await;
 
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index 6fece5eb2..6c6807479 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -10,6 +10,7 @@ pub use traits::Instance;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc;
 use crate::time::Hertz;
+pub use crate::timer::simple_pwm::PwmPinConfig;
 
 /// HRTIM burst controller instance.
 pub struct BurstController<T: Instance> {
@@ -73,7 +74,7 @@ pub struct ComplementaryPwmPin<'d, T, C> {
 }
 
 macro_rules! advanced_channel_impl {
-    ($new_chx:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
+    ($new_chx:ident, $new_chx_with_config:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
         impl<'d, T: Instance> PwmPin<'d, T, $channel<T>> {
             #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
             pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
@@ -86,6 +87,21 @@ macro_rules! advanced_channel_impl {
                     phantom: PhantomData,
                 }
             }
+
+            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with a specific configuration.")]
+            pub fn $new_chx_with_config(
+                pin: Peri<'d, impl $pin_trait<T>>,
+                pin_config: PwmPinConfig,
+            ) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+                });
+                PwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
         }
 
         impl<'d, T: Instance> ComplementaryPwmPin<'d, T, $channel<T>> {
@@ -100,6 +116,21 @@ macro_rules! advanced_channel_impl {
                     phantom: PhantomData,
                 }
             }
+
+            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance with a specific configuration.")]
+            pub fn $new_chx_with_config(
+                pin: Peri<'d, impl $complementary_pin_trait<T>>,
+                pin_config: PwmPinConfig,
+            ) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    set_as_af!(pin, AfType::output(pin_config.output_type, pin_config.speed));
+                });
+                ComplementaryPwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
         }
 
         impl<T: Instance> SealedAdvancedChannel<T> for $channel<T> {
@@ -111,13 +142,55 @@ macro_rules! advanced_channel_impl {
     };
 }
 
-advanced_channel_impl!(new_cha, ChA, 0, ChannelAPin, ChannelAComplementaryPin);
-advanced_channel_impl!(new_chb, ChB, 1, ChannelBPin, ChannelBComplementaryPin);
-advanced_channel_impl!(new_chc, ChC, 2, ChannelCPin, ChannelCComplementaryPin);
-advanced_channel_impl!(new_chd, ChD, 3, ChannelDPin, ChannelDComplementaryPin);
-advanced_channel_impl!(new_che, ChE, 4, ChannelEPin, ChannelEComplementaryPin);
+advanced_channel_impl!(
+    new_cha,
+    new_cha_with_config,
+    ChA,
+    0,
+    ChannelAPin,
+    ChannelAComplementaryPin
+);
+advanced_channel_impl!(
+    new_chb,
+    new_chb_with_config,
+    ChB,
+    1,
+    ChannelBPin,
+    ChannelBComplementaryPin
+);
+advanced_channel_impl!(
+    new_chc,
+    new_chc_with_config,
+    ChC,
+    2,
+    ChannelCPin,
+    ChannelCComplementaryPin
+);
+advanced_channel_impl!(
+    new_chd,
+    new_chd_with_config,
+    ChD,
+    3,
+    ChannelDPin,
+    ChannelDComplementaryPin
+);
+advanced_channel_impl!(
+    new_che,
+    new_che_with_config,
+    ChE,
+    4,
+    ChannelEPin,
+    ChannelEComplementaryPin
+);
 #[cfg(hrtim_v2)]
-advanced_channel_impl!(new_chf, ChF, 5, ChannelFPin, ChannelFComplementaryPin);
+advanced_channel_impl!(
+    new_chf,
+    new_chf_with_config,
+    ChF,
+    5,
+    ChannelFPin,
+    ChannelFComplementaryPin
+);
 
 /// Struct used to divide a high resolution timer into multiple channels
 pub struct AdvancedPwm<'d, T: Instance> {
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 573a1851d..e62de0454 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -1,14 +1,22 @@
 //! Hardware Semaphore (HSEM)
 
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
+use core::task::Poll;
+
+#[cfg(all(stm32wb, feature = "low-power"))]
+use critical_section::CriticalSection;
 use embassy_hal_internal::PeripheralType;
+use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::pac;
-use crate::rcc::{self, RccPeripheral};
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
 // which is not yet supported by this code.
 use crate::Peri;
+use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, pac};
 
 /// HSEM error.
 #[derive(Debug)]
@@ -41,63 +49,152 @@ pub enum CoreId {
     Core1 = 0x8,
 }
 
-/// Get the current core id
-/// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.
-#[inline(always)]
-pub fn get_current_coreid() -> CoreId {
-    let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
-    match (cpuid & 0x000000F0) >> 4 {
-        #[cfg(any(stm32wb, stm32wl))]
-        0x0 => CoreId::Core1,
+impl CoreId {
+    /// Get the current core id
+    /// This code assume that it is only executed on a Cortex-M M0+, M4 or M7 core.
+    pub fn current() -> Self {
+        let cpuid = unsafe { cortex_m::peripheral::CPUID::PTR.read_volatile().base.read() };
+        match (cpuid & 0x000000F0) >> 4 {
+            #[cfg(any(stm32wb, stm32wl))]
+            0x0 => CoreId::Core1,
 
-        #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
-        0x4 => CoreId::Core0,
+            #[cfg(not(any(stm32h745, stm32h747, stm32h755, stm32h757)))]
+            0x4 => CoreId::Core0,
 
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
-        0x4 => CoreId::Core1,
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
+            0x4 => CoreId::Core1,
 
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
-        0x7 => CoreId::Core0,
-        _ => panic!("Unknown Cortex-M core"),
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757))]
+            0x7 => CoreId::Core0,
+            _ => panic!("Unknown Cortex-M core"),
+        }
+    }
+
+    /// Translates the core ID to an index into the interrupt registers.
+    pub fn to_index(&self) -> usize {
+        match &self {
+            CoreId::Core0 => 0,
+            #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
+            CoreId::Core1 => 1,
+        }
     }
 }
 
-/// Translates the core ID to an index into the interrupt registers.
-#[inline(always)]
-fn core_id_to_index(core: CoreId) -> usize {
-    match core {
-        CoreId::Core0 => 0,
-        #[cfg(any(stm32h745, stm32h747, stm32h755, stm32h757, stm32wb, stm32wl))]
-        CoreId::Core1 => 1,
+#[cfg(not(all(stm32wb, feature = "low-power")))]
+const PUB_CHANNELS: usize = 6;
+
+#[cfg(all(stm32wb, feature = "low-power"))]
+const PUB_CHANNELS: usize = 4;
+
+/// TX interrupt handler.
+pub struct HardwareSemaphoreInterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+
+impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for HardwareSemaphoreInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        let core_id = CoreId::current();
+
+        for number in 0..5 {
+            if T::regs().isr(core_id.to_index()).read().isf(number as usize) {
+                T::regs()
+                    .icr(core_id.to_index())
+                    .write(|w| w.set_isc(number as usize, true));
+
+                T::regs()
+                    .ier(core_id.to_index())
+                    .modify(|w| w.set_ise(number as usize, false));
+
+                T::state().waker_for(number).wake();
+            }
+        }
     }
 }
 
-/// HSEM driver
-pub struct HardwareSemaphore<'d, T: Instance> {
-    _peri: Peri<'d, T>,
+/// Hardware semaphore mutex
+pub struct HardwareSemaphoreMutex<'a, T: Instance> {
+    index: u8,
+    process_id: u8,
+    _lifetime: PhantomData<&'a mut T>,
 }
 
-impl<'d, T: Instance> HardwareSemaphore<'d, T> {
-    /// Creates a new HardwareSemaphore instance.
-    pub fn new(peripheral: Peri<'d, T>) -> Self {
-        rcc::enable_and_reset::<T>();
+impl<'a, T: Instance> Drop for HardwareSemaphoreMutex<'a, T> {
+    fn drop(&mut self) {
+        HardwareSemaphoreChannel::<'a, T> {
+            index: self.index,
+            _lifetime: PhantomData,
+        }
+        .unlock(self.process_id);
+    }
+}
+
+/// Hardware semaphore channel
+pub struct HardwareSemaphoreChannel<'a, T: Instance> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut T>,
+}
+
+impl<'a, T: Instance> HardwareSemaphoreChannel<'a, T> {
+    pub(crate) const fn new(number: u8) -> Self {
+        core::assert!(number > 0 && number <= 6);
+
+        Self {
+            index: number - 1,
+            _lifetime: PhantomData,
+        }
+    }
+
+    /// Locks the semaphore.
+    /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
+    /// check if the lock has been successful, carried out from the HSEM_Rx register.
+    pub async fn lock(&mut self, process_id: u8) -> HardwareSemaphoreMutex<'a, T> {
+        let core_id = CoreId::current();
+
+        poll_fn(|cx| {
+            T::state().waker_for(self.index).register(cx.waker());
+
+            compiler_fence(Ordering::SeqCst);
+
+            T::regs()
+                .ier(core_id.to_index())
+                .modify(|w| w.set_ise(self.index as usize, true));
 
-        HardwareSemaphore { _peri: peripheral }
+            match self.try_lock(process_id) {
+                Some(mutex) => Poll::Ready(mutex),
+                None => Poll::Pending,
+            }
+        })
+        .await
+    }
+
+    /// Try to lock the semaphor
+    /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
+    /// check if the lock has been successful, carried out from the HSEM_Rx register.
+    pub fn try_lock(&mut self, process_id: u8) -> Option<HardwareSemaphoreMutex<'a, T>> {
+        if self.two_step_lock(process_id).is_ok() {
+            Some(HardwareSemaphoreMutex {
+                index: self.index,
+                process_id: process_id,
+                _lifetime: PhantomData,
+            })
+        } else {
+            None
+        }
     }
 
     /// Locks the semaphore.
     /// The 2-step lock procedure consists in a write to lock the semaphore, followed by a read to
     /// check if the lock has been successful, carried out from the HSEM_Rx register.
-    pub fn two_step_lock(&mut self, sem_id: u8, process_id: u8) -> Result<(), HsemError> {
-        T::regs().r(sem_id as usize).write(|w| {
+    pub fn two_step_lock(&mut self, process_id: u8) -> Result<(), HsemError> {
+        T::regs().r(self.index as usize).write(|w| {
             w.set_procid(process_id);
-            w.set_coreid(get_current_coreid() as u8);
+            w.set_coreid(CoreId::current() as u8);
             w.set_lock(true);
         });
-        let reg = T::regs().r(sem_id as usize).read();
+        let reg = T::regs().r(self.index as usize).read();
         match (
             reg.lock(),
-            reg.coreid() == get_current_coreid() as u8,
+            reg.coreid() == CoreId::current() as u8,
             reg.procid() == process_id,
         ) {
             (true, true, true) => Ok(()),
@@ -108,9 +205,9 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Locks the semaphore.
     /// The 1-step procedure consists in a read to lock and check the semaphore in a single step,
     /// carried out from the HSEM_RLRx register.
-    pub fn one_step_lock(&mut self, sem_id: u8) -> Result<(), HsemError> {
-        let reg = T::regs().rlr(sem_id as usize).read();
-        match (reg.lock(), reg.coreid() == get_current_coreid() as u8, reg.procid()) {
+    pub fn one_step_lock(&mut self) -> Result<(), HsemError> {
+        let reg = T::regs().rlr(self.index as usize).read();
+        match (reg.lock(), reg.coreid() == CoreId::current() as u8, reg.procid()) {
             (false, true, 0) => Ok(()),
             _ => Err(HsemError::LockFailed),
         }
@@ -119,14 +216,60 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     /// Unlocks the semaphore.
     /// Unlocking a semaphore is a protected process, to prevent accidental clearing by a AHB bus
     /// core ID or by a process not having the semaphore lock right.
-    pub fn unlock(&mut self, sem_id: u8, process_id: u8) {
-        T::regs().r(sem_id as usize).write(|w| {
+    pub fn unlock(&mut self, process_id: u8) {
+        T::regs().r(self.index as usize).write(|w| {
             w.set_procid(process_id);
-            w.set_coreid(get_current_coreid() as u8);
+            w.set_coreid(CoreId::current() as u8);
             w.set_lock(false);
         });
     }
 
+    /// Return the channel number
+    pub const fn channel(&self) -> u8 {
+        self.index + 1
+    }
+}
+
+/// HSEM driver
+pub struct HardwareSemaphore<T: Instance> {
+    _type: PhantomData<T>,
+}
+
+impl<T: Instance> HardwareSemaphore<T> {
+    /// Creates a new HardwareSemaphore instance.
+    pub fn new<'d>(
+        _peripheral: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, HardwareSemaphoreInterruptHandler<T>> + 'd,
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        HardwareSemaphore { _type: PhantomData }
+    }
+
+    /// Get a single channel, and keep the global struct
+    pub const fn channel_for<'a>(&'a mut self, number: u8) -> HardwareSemaphoreChannel<'a, T> {
+        #[cfg(all(stm32wb, feature = "low-power"))]
+        core::assert!(number != 3 && number != 4);
+
+        HardwareSemaphoreChannel::new(number)
+    }
+
+    /// Split the global struct into channels
+    ///
+    /// If using low-power mode, channels 3 and 4 will not be returned
+    pub const fn split<'a>(self) -> [HardwareSemaphoreChannel<'a, T>; PUB_CHANNELS] {
+        [
+            HardwareSemaphoreChannel::new(1),
+            HardwareSemaphoreChannel::new(2),
+            #[cfg(not(all(stm32wb, feature = "low-power")))]
+            HardwareSemaphoreChannel::new(3),
+            #[cfg(not(all(stm32wb, feature = "low-power")))]
+            HardwareSemaphoreChannel::new(4),
+            HardwareSemaphoreChannel::new(5),
+            HardwareSemaphoreChannel::new(6),
+        ]
+    }
+
     /// Unlocks all semaphores.
     /// All semaphores locked by a COREID can be unlocked at once by using the HSEM_CR
     /// register. Write COREID and correct KEY value in HSEM_CR. All locked semaphores with a
@@ -138,11 +281,6 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
         });
     }
 
-    /// Checks if the semaphore is locked.
-    pub fn is_semaphore_locked(&self, sem_id: u8) -> bool {
-        T::regs().r(sem_id as usize).read().lock()
-    }
-
     /// Sets the clear (unlock) key
     pub fn set_clear_key(&mut self, key: u16) {
         T::regs().keyr().modify(|w| w.set_key(key));
@@ -152,38 +290,61 @@ impl<'d, T: Instance> HardwareSemaphore<'d, T> {
     pub fn get_clear_key(&mut self) -> u16 {
         T::regs().keyr().read().key()
     }
+}
 
-    /// Sets the interrupt enable bit for the semaphore.
-    pub fn enable_interrupt(&mut self, core_id: CoreId, sem_x: usize, enable: bool) {
-        T::regs()
-            .ier(core_id_to_index(core_id))
-            .modify(|w| w.set_ise(sem_x, enable));
+#[cfg(all(stm32wb, feature = "low-power"))]
+pub(crate) fn init_hsem(cs: CriticalSection) {
+    rcc::enable_and_reset_with_cs::<crate::peripherals::HSEM>(cs);
+
+    unsafe {
+        crate::rcc::REFCOUNT_STOP1 = 0;
+        crate::rcc::REFCOUNT_STOP2 = 0;
     }
+}
 
-    /// Gets the interrupt flag for the semaphore.
-    pub fn is_interrupt_active(&mut self, core_id: CoreId, sem_x: usize) -> bool {
-        T::regs().isr(core_id_to_index(core_id)).read().isf(sem_x)
+struct State {
+    wakers: [AtomicWaker; 6],
+}
+
+impl State {
+    const fn new() -> Self {
+        Self {
+            wakers: [const { AtomicWaker::new() }; 6],
+        }
     }
 
-    /// Clears the interrupt flag for the semaphore.
-    pub fn clear_interrupt(&mut self, core_id: CoreId, sem_x: usize) {
-        T::regs()
-            .icr(core_id_to_index(core_id))
-            .write(|w| w.set_isc(sem_x, false));
+    const fn waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.wakers[index as usize]
     }
 }
 
 trait SealedInstance {
     fn regs() -> pac::hsem::Hsem;
+    fn state() -> &'static State;
 }
 
 /// HSEM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {
+    /// Interrupt for this peripheral.
+    type Interrupt: interrupt::typelevel::Interrupt;
+}
 
 impl SealedInstance for crate::peripherals::HSEM {
     fn regs() -> crate::pac::hsem::Hsem {
         crate::pac::HSEM
     }
+
+    fn state() -> &'static State {
+        static STATE: State = State::new();
+        &STATE
+    }
 }
-impl Instance for crate::peripherals::HSEM {}
+
+foreach_interrupt!(
+    ($inst:ident, hsem, $block:ident, $signal_name:ident, $irq:ident) => {
+        impl Instance for crate::peripherals::$inst {
+            type Interrupt = crate::interrupt::typelevel::$irq;
+        }
+    };
+);
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
index 59dd7ca16..1d3560678 100644
--- a/embassy-stm32/src/hspi/mod.rs
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -16,7 +16,7 @@ use embassy_embedded_hal::{GetConfig, SetConfig};
 use embassy_hal_internal::{Peri, PeripheralType};
 pub use enums::*;
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::hspi::Hspi as Regs;
diff --git a/embassy-stm32/src/i2c/config.rs b/embassy-stm32/src/i2c/config.rs
index 4e3b736c7..74fac14b2 100644
--- a/embassy-stm32/src/i2c/config.rs
+++ b/embassy-stm32/src/i2c/config.rs
@@ -4,7 +4,7 @@ use crate::gpio::{AfType, OutputType, Speed};
 use crate::time::Hertz;
 
 #[repr(u8)]
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// Bits of the I2C OA2 register to mask out.
 pub enum AddrMask {
@@ -60,7 +60,7 @@ impl Address {
     }
 }
 
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// The second Own Address register.
 pub struct OA2 {
@@ -70,7 +70,7 @@ pub struct OA2 {
     pub mask: AddrMask,
 }
 
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// The Own Address(es) of the I2C peripheral.
 pub enum OwnAddresses {
@@ -88,7 +88,7 @@ pub enum OwnAddresses {
 }
 
 /// Slave Configuration
-#[derive(Copy, Clone)]
+#[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct SlaveAddrConfig {
     /// Target Address(es)
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 249bac41c..ee60c3f44 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -154,8 +154,8 @@ impl<'d> I2c<'d, Async, Master> {
         scl: Peri<'d, if_afio!(impl SclPin<T, A>)>,
         sda: Peri<'d, if_afio!(impl SdaPin<T, A>)>,
         _irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
-            + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
-            + 'd,
+        + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
+        + 'd,
         tx_dma: Peri<'d, impl TxDma<T>>,
         rx_dma: Peri<'d, impl RxDma<T>>,
         config: Config,
@@ -219,6 +219,7 @@ impl<'d, M: Mode> I2c<'d, M, Master> {
                 sda,
             },
         };
+
         this.enable_and_init(config);
 
         this
@@ -437,15 +438,15 @@ impl<'d, IM: MasterMode> embedded_hal_async::i2c::I2c for I2c<'d, Async, IM> {
 
 /// Frame type in I2C transaction.
 ///
-/// This tells each method what kind of framing to use, to generate a (repeated) start condition (ST
+/// This tells each method what kind of frame to use, to generate a (repeated) start condition (ST
 /// or SR), and/or a stop condition (SP). For read operations, this also controls whether to send an
 /// ACK or NACK after the last byte received.
 ///
 /// For write operations, the following options are identical because they differ only in the (N)ACK
 /// treatment relevant for read operations:
 ///
-/// - `FirstFrame` and `FirstAndNextFrame`
-/// - `NextFrame` and `LastFrameNoStop`
+/// - `FirstFrame` and `FirstAndNextFrame` behave identically for writes
+/// - `NextFrame` and `LastFrameNoStop` behave identically for writes
 ///
 /// Abbreviations used below:
 ///
@@ -474,7 +475,7 @@ enum FrameOptions {
 
 #[allow(dead_code)]
 impl FrameOptions {
-    /// Sends start or repeated start condition before transfer.
+    /// Returns true if a start or repeated start condition should be generated before this operation.
     fn send_start(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::FirstFrame | Self::FirstAndNextFrame => true,
@@ -482,7 +483,7 @@ impl FrameOptions {
         }
     }
 
-    /// Sends stop condition after transfer.
+    /// Returns true if a stop condition should be generated after this operation.
     fn send_stop(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::LastFrame => true,
@@ -490,7 +491,10 @@ impl FrameOptions {
         }
     }
 
-    /// Sends NACK after last byte received, indicating end of read operation.
+    /// Returns true if NACK should be sent after the last byte received in a read operation.
+    ///
+    /// This signals the end of a read sequence and releases the bus for the master's
+    /// next transmission (or stop condition).
     fn send_nack(self) -> bool {
         match self {
             Self::FirstAndLastFrame | Self::FirstFrame | Self::LastFrame | Self::LastFrameNoStop => true,
@@ -499,24 +503,44 @@ impl FrameOptions {
     }
 }
 
-/// Iterates over operations in transaction.
+/// Analyzes I2C transaction operations and assigns appropriate frame to each.
+///
+/// This function processes a sequence of I2C operations and determines the correct
+/// frame configuration for each operation to ensure proper I2C protocol compliance.
+/// It handles the complex logic of:
+///
+/// - Generating start conditions for the first operation of each type (read/write)
+/// - Generating stop conditions for the final operation in the entire transaction
+/// - Managing ACK/NACK behavior for read operations, including merging consecutive reads
+/// - Ensuring proper bus handoff between different operation types
+///
+/// **Transaction Contract Compliance:**
+/// The frame assignments ensure compliance with the embedded-hal I2C transaction contract,
+/// where consecutive operations of the same type are logically merged while maintaining
+/// proper protocol boundaries.
 ///
-/// Returns necessary frame options for each operation to uphold the [transaction contract] and have
-/// the right start/stop/(N)ACK conditions on the wire.
+/// **Error Handling:**
+/// Returns an error if any read operation has an empty buffer, as this would create
+/// an invalid I2C transaction that could halt mid-execution.
+///
+/// # Arguments
+/// * `operations` - Mutable slice of I2C operations from embedded-hal
+///
+/// # Returns
+/// An iterator over (operation, frame) pairs, or an error if the transaction is invalid
 ///
-/// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
 #[allow(dead_code)]
 fn operation_frames<'a, 'b: 'a>(
     operations: &'a mut [embedded_hal_1::i2c::Operation<'b>],
 ) -> Result<impl IntoIterator<Item = (&'a mut embedded_hal_1::i2c::Operation<'b>, FrameOptions)>, Error> {
     use embedded_hal_1::i2c::Operation::{Read, Write};
 
-    // Check empty read buffer before starting transaction. Otherwise, we would risk halting with an
-    // error in the middle of the transaction.
+    // Validate that no read operations have empty buffers before starting the transaction.
+    // Empty read operations would risk halting with an error mid-transaction.
     //
-    // In principle, we could allow empty read frames within consecutive read operations, as long as
-    // at least one byte remains in the final (merged) read operation, but that makes the logic more
-    // complicated and error-prone.
+    // Note: We could theoretically allow empty read operations within consecutive read
+    // sequences as long as the final merged read has at least one byte, but this would
+    // complicate the logic significantly and create error-prone edge cases.
     if operations.iter().any(|op| match op {
         Read(read) => read.is_empty(),
         Write(_) => false,
@@ -525,46 +549,52 @@ fn operation_frames<'a, 'b: 'a>(
     }
 
     let mut operations = operations.iter_mut().peekable();
-
-    let mut next_first_frame = true;
+    let mut next_first_operation = true;
 
     Ok(iter::from_fn(move || {
-        let op = operations.next()?;
+        let current_op = operations.next()?;
 
-        // Is `op` first frame of its type?
-        let first_frame = next_first_frame;
+        // Determine if this is the first operation of its type (read or write)
+        let is_first_of_type = next_first_operation;
         let next_op = operations.peek();
 
-        // Get appropriate frame options as combination of the following properties:
+        // Compute the appropriate frame based on three key properties:
         //
-        // - For each first operation of its type, generate a (repeated) start condition.
-        // - For the last operation overall in the entire transaction, generate a stop condition.
-        // - For read operations, check the next operation: if it is also a read operation, we merge
-        //   these and send ACK for all bytes in the current operation; send NACK only for the final
-        //   read operation's last byte (before write or end of entire transaction) to indicate last
-        //   byte read and release the bus for transmission of the bus master's next byte (or stop).
+        // 1. **Start Condition**: Generate (repeated) start for first operation of each type
+        // 2. **Stop Condition**: Generate stop for the final operation in the entire transaction
+        // 3. **ACK/NACK for Reads**: For read operations, send ACK if more reads follow in the
+        //    sequence, or NACK for the final read in a sequence (before write or transaction end)
         //
-        // We check the third property unconditionally, i.e. even for write opeartions. This is okay
-        // because the resulting frame options are identical for write operations.
-        let frame = match (first_frame, next_op) {
+        // The third property is checked for all operations since the resulting frame
+        // configurations are identical for write operations regardless of ACK/NACK treatment.
+        let frame = match (is_first_of_type, next_op) {
+            // First operation of type, and it's also the final operation overall
             (true, None) => FrameOptions::FirstAndLastFrame,
+            // First operation of type, next operation is also a read (continue read sequence)
             (true, Some(Read(_))) => FrameOptions::FirstAndNextFrame,
+            // First operation of type, next operation is write (end current sequence)
             (true, Some(Write(_))) => FrameOptions::FirstFrame,
-            //
+
+            // Continuation operation, and it's the final operation overall
             (false, None) => FrameOptions::LastFrame,
+            // Continuation operation, next operation is also a read (continue read sequence)
             (false, Some(Read(_))) => FrameOptions::NextFrame,
+            // Continuation operation, next operation is write (end current sequence, no stop)
             (false, Some(Write(_))) => FrameOptions::LastFrameNoStop,
         };
 
-        // Pre-calculate if `next_op` is the first operation of its type. We do this here and not at
-        // the beginning of the loop because we hand out `op` as iterator value and cannot access it
-        // anymore in the next iteration.
-        next_first_frame = match (&op, next_op) {
+        // Pre-calculate whether the next operation will be the first of its type.
+        // This is done here because we consume `current_op` as the iterator value
+        // and cannot access it in the next iteration.
+        next_first_operation = match (&current_op, next_op) {
+            // No next operation
             (_, None) => false,
+            // Operation type changes: next will be first of its type
             (Read(_), Some(Write(_))) | (Write(_), Some(Read(_))) => true,
+            // Operation type continues: next will not be first of its type
             (Read(_), Some(Read(_))) | (Write(_), Some(Write(_))) => false,
         };
 
-        Some((op, frame))
+        Some((current_op, frame))
     }))
 }
diff --git a/embassy-stm32/src/i2c/v1.rs b/embassy-stm32/src/i2c/v1.rs
index 081eb1191..128a58db7 100644
--- a/embassy-stm32/src/i2c/v1.rs
+++ b/embassy-stm32/src/i2c/v1.rs
@@ -8,7 +8,7 @@ use core::future::poll_fn;
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_futures::select::{select, Either};
+use embassy_futures::select::{Either, select};
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
 use mode::Master;
@@ -30,6 +30,7 @@ use crate::pac::i2c;
 // hit a case like this!
 pub unsafe fn on_interrupt<T: Instance>() {
     let regs = T::info().regs;
+    trace!("I2C interrupt triggered");
     // i2c v2 only woke the task on transfer complete interrupts. v1 uses interrupts for a bunch of
     // other stuff, so we wake the task on every interrupt.
     T::state().waker.wake();
@@ -92,6 +93,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(true);
         });
+        trace!("i2c v1 init complete");
     }
 
     fn check_and_clear_error_flags(info: &'static Info) -> Result<i2c::regs::Sr1, Error> {
@@ -151,7 +153,13 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         Ok(sr1)
     }
 
-    fn write_bytes(&mut self, addr: u8, bytes: &[u8], timeout: Timeout, frame: FrameOptions) -> Result<(), Error> {
+    fn write_bytes(
+        &mut self,
+        address: u8,
+        write_buffer: &[u8],
+        timeout: Timeout,
+        frame: FrameOptions,
+    ) -> Result<(), Error> {
         if frame.send_start() {
             // Send a START condition
 
@@ -170,7 +178,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
             }
 
             // Set up current address we're trying to talk to
-            self.info.regs.dr().write(|reg| reg.set_dr(addr << 1));
+            self.info.regs.dr().write(|reg| reg.set_dr(address << 1));
 
             // Wait until address was sent
             // Wait for the address to be acknowledged
@@ -184,7 +192,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         }
 
         // Send bytes
-        for c in bytes {
+        for c in write_buffer {
             self.send_byte(*c, timeout)?;
         }
 
@@ -236,12 +244,12 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
 
     fn blocking_read_timeout(
         &mut self,
-        addr: u8,
-        buffer: &mut [u8],
+        address: u8,
+        read_buffer: &mut [u8],
         timeout: Timeout,
         frame: FrameOptions,
     ) -> Result<(), Error> {
-        let Some((last, buffer)) = buffer.split_last_mut() else {
+        let Some((last_byte, read_buffer)) = read_buffer.split_last_mut() else {
             return Err(Error::Overrun);
         };
 
@@ -263,7 +271,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
             }
 
             // Set up current address we're trying to talk to
-            self.info.regs.dr().write(|reg| reg.set_dr((addr << 1) + 1));
+            self.info.regs.dr().write(|reg| reg.set_dr((address << 1) + 1));
 
             // Wait until address was sent
             // Wait for the address to be acknowledged
@@ -276,7 +284,7 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         }
 
         // Receive bytes into buffer
-        for c in buffer {
+        for c in read_buffer {
             *c = self.recv_byte(timeout)?;
         }
 
@@ -291,37 +299,42 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
         });
 
         // Receive last byte
-        *last = self.recv_byte(timeout)?;
+        *last_byte = self.recv_byte(timeout)?;
 
         // Fallthrough is success
         Ok(())
     }
 
     /// Blocking read.
-    pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
-        self.blocking_read_timeout(addr, read, self.timeout(), FrameOptions::FirstAndLastFrame)
+    pub fn blocking_read(&mut self, address: u8, read_buffer: &mut [u8]) -> Result<(), Error> {
+        self.blocking_read_timeout(address, read_buffer, self.timeout(), FrameOptions::FirstAndLastFrame)
     }
 
     /// Blocking write.
-    pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_bytes(addr, write, self.timeout(), FrameOptions::FirstAndLastFrame)?;
+    pub fn blocking_write(&mut self, address: u8, write_buffer: &[u8]) -> Result<(), Error> {
+        self.write_bytes(address, write_buffer, self.timeout(), FrameOptions::FirstAndLastFrame)?;
 
         // Fallthrough is success
         Ok(())
     }
 
     /// Blocking write, restart, read.
-    pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+    pub fn blocking_write_read(
+        &mut self,
+        address: u8,
+        write_buffer: &[u8],
+        read_buffer: &mut [u8],
+    ) -> Result<(), Error> {
         // Check empty read buffer before starting transaction. Otherwise, we would not generate the
         // stop condition below.
-        if read.is_empty() {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
         let timeout = self.timeout();
 
-        self.write_bytes(addr, write, timeout, FrameOptions::FirstFrame)?;
-        self.blocking_read_timeout(addr, read, timeout, FrameOptions::FirstAndLastFrame)?;
+        self.write_bytes(address, write_buffer, timeout, FrameOptions::FirstFrame)?;
+        self.blocking_read_timeout(address, read_buffer, timeout, FrameOptions::FirstAndLastFrame)?;
 
         Ok(())
     }
@@ -331,32 +344,43 @@ impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
     /// Consecutive operations of same type are merged. See [transaction contract] for details.
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
-    pub fn blocking_transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+    pub fn blocking_transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
         let timeout = self.timeout();
 
         for (op, frame) in operation_frames(operations)? {
             match op {
-                Operation::Read(read) => self.blocking_read_timeout(addr, read, timeout, frame)?,
-                Operation::Write(write) => self.write_bytes(addr, write, timeout, frame)?,
+                Operation::Read(read_buffer) => self.blocking_read_timeout(address, read_buffer, timeout, frame)?,
+                Operation::Write(write_buffer) => self.write_bytes(address, write_buffer, timeout, frame)?,
             }
         }
 
         Ok(())
     }
 
-    // Async
-
+    /// Can be used by both blocking and async implementations  
     #[inline] // pretty sure this should always be inlined
-    fn enable_interrupts(info: &'static Info) -> () {
-        info.regs.cr2().modify(|w| {
-            w.set_iterren(true);
-            w.set_itevten(true);
+    fn enable_interrupts(info: &'static Info) {
+        // The interrupt handler disables interrupts globally, so we need to re-enable them
+        // This must be done in a critical section to avoid races
+        critical_section::with(|_| {
+            info.regs.cr2().modify(|w| {
+                w.set_iterren(true);
+                w.set_itevten(true);
+            });
         });
     }
+
+    /// Can be used by both blocking and async implementations
+    fn clear_stop_flag(info: &'static Info) {
+        trace!("I2C slave: clearing STOPF flag (v1 sequence)");
+        // v1 requires: READ SR1 then WRITE CR1 to clear STOPF
+        let _ = info.regs.sr1().read();
+        info.regs.cr1().modify(|_| {}); // Dummy write to clear STOPF
+    }
 }
 
 impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
-    async fn write_frame(&mut self, address: u8, write: &[u8], frame: FrameOptions) -> Result<(), Error> {
+    async fn write_frame(&mut self, address: u8, write_buffer: &[u8], frame: FrameOptions) -> Result<(), Error> {
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
             // reception.
@@ -439,7 +463,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             // this address from the memory after each TxE event.
             let dst = self.info.regs.dr().as_ptr() as *mut u8;
 
-            self.tx_dma.as_mut().unwrap().write(write, dst, Default::default())
+            self.tx_dma
+                .as_mut()
+                .unwrap()
+                .write(write_buffer, dst, Default::default())
         };
 
         // Wait for bytes to be sent, or an error to occur.
@@ -501,28 +528,28 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     }
 
     /// Write.
-    pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
-        self.write_frame(address, write, FrameOptions::FirstAndLastFrame)
+    pub async fn write(&mut self, address: u8, write_buffer: &[u8]) -> Result<(), Error> {
+        self.write_frame(address, write_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
         Ok(())
     }
 
     /// Read.
-    pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
-        self.read_frame(address, buffer, FrameOptions::FirstAndLastFrame)
+    pub async fn read(&mut self, address: u8, read_buffer: &mut [u8]) -> Result<(), Error> {
+        self.read_frame(address, read_buffer, FrameOptions::FirstAndLastFrame)
             .await?;
 
         Ok(())
     }
 
-    async fn read_frame(&mut self, address: u8, buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error> {
-        if buffer.is_empty() {
+    async fn read_frame(&mut self, address: u8, read_buffer: &mut [u8], frame: FrameOptions) -> Result<(), Error> {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
         // Some branches below depend on whether the buffer contains only a single byte.
-        let single_byte = buffer.len() == 1;
+        let single_byte = read_buffer.len() == 1;
 
         self.info.regs.cr2().modify(|w| {
             // Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for
@@ -612,7 +639,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             self.info.regs.sr2().read();
         } else {
             // Before starting reception of single byte (but without START condition, i.e. in case
-            // of continued frame), program NACK to emit at end of this byte.
+            // of merged operations), program NACK to emit at end of this byte.
             if frame.send_nack() && single_byte {
                 self.info.regs.cr1().modify(|w| {
                     w.set_ack(false);
@@ -634,7 +661,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             // from this address from the memory after each RxE event.
             let src = self.info.regs.dr().as_ptr() as *mut u8;
 
-            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+            self.rx_dma.as_mut().unwrap().read(src, read_buffer, Default::default())
         };
 
         // Wait for bytes to be received, or an error to occur.
@@ -673,15 +700,17 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     }
 
     /// Write, restart, read.
-    pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+    pub async fn write_read(&mut self, address: u8, write_buffer: &[u8], read_buffer: &mut [u8]) -> Result<(), Error> {
         // Check empty read buffer before starting transaction. Otherwise, we would not generate the
         // stop condition below.
-        if read.is_empty() {
+        if read_buffer.is_empty() {
             return Err(Error::Overrun);
         }
 
-        self.write_frame(address, write, FrameOptions::FirstFrame).await?;
-        self.read_frame(address, read, FrameOptions::FirstAndLastFrame).await
+        self.write_frame(address, write_buffer, FrameOptions::FirstFrame)
+            .await?;
+        self.read_frame(address, read_buffer, FrameOptions::FirstAndLastFrame)
+            .await
     }
 
     /// Transaction with operations.
@@ -689,11 +718,11 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     /// Consecutive operations of same type are merged. See [transaction contract] for details.
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
-    pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
+    pub async fn transaction(&mut self, address: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
         for (op, frame) in operation_frames(operations)? {
             match op {
-                Operation::Read(read) => self.read_frame(addr, read, frame).await?,
-                Operation::Write(write) => self.write_frame(addr, write, frame).await?,
+                Operation::Read(read_buffer) => self.read_frame(address, read_buffer, frame).await?,
+                Operation::Write(write_buffer) => self.write_frame(address, write_buffer, frame).await?,
             }
         }
 
@@ -729,12 +758,956 @@ impl Duty {
     }
 }
 
+/// Result of attempting to send a byte in slave transmitter mode
+#[derive(Debug, PartialEq)]
+enum TransmitResult {
+    /// Byte sent and ACKed by master - continue transmission
+    Acknowledged,
+    /// Byte sent but NACKed by master - normal end of read transaction
+    NotAcknowledged,
+    /// STOP condition detected - master terminated transaction
+    Stopped,
+    /// RESTART condition detected - master starting new transaction
+    Restarted,
+}
+
+/// Result of attempting to receive a byte in slave receiver mode
+#[derive(Debug, PartialEq)]
+enum ReceiveResult {
+    /// Data byte successfully received
+    Data(u8),
+    /// STOP condition detected - end of write transaction
+    Stopped,
+    /// RESTART condition detected - master starting new transaction
+    Restarted,
+}
+
+/// Enumeration of slave transaction termination conditions
+#[derive(Debug, Clone, Copy, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+enum SlaveTermination {
+    /// STOP condition received - normal end of transaction
+    Stop,
+    /// RESTART condition received - master starting new transaction  
+    Restart,
+    /// NACK received - normal end of read transaction
+    Nack,
+}
+
+impl<'d, M: PeriMode> I2c<'d, M, Master> {
+    /// Configure the I2C driver for slave operations, allowing for the driver to be used as a slave and a master (multimaster)
+    pub fn into_slave_multimaster(mut self, slave_addr_config: SlaveAddrConfig) -> I2c<'d, M, MultiMaster> {
+        let mut slave = I2c {
+            info: self.info,
+            state: self.state,
+            kernel_clock: self.kernel_clock,
+            tx_dma: self.tx_dma.take(), // Use take() to move ownership
+            rx_dma: self.rx_dma.take(), // Use take() to move ownership
+            #[cfg(feature = "time")]
+            timeout: self.timeout,
+            _phantom: PhantomData,
+            _phantom2: PhantomData,
+            _drop_guard: self._drop_guard, // Move the drop guard
+        };
+        slave.init_slave(slave_addr_config);
+        slave
+    }
+}
+
+// Address configuration methods
+impl<'d, M: PeriMode, IM: MasterMode> I2c<'d, M, IM> {
+    /// Initialize slave mode with address configuration
+    pub(crate) fn init_slave(&mut self, config: SlaveAddrConfig) {
+        trace!("I2C slave: initializing with config={:?}", config);
+
+        // Disable peripheral for configuration
+        self.info.regs.cr1().modify(|reg| reg.set_pe(false));
+
+        // Configure slave addresses
+        self.apply_address_configuration(config);
+
+        // Enable peripheral with slave settings
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(true);
+            reg.set_ack(true); // Enable acknowledgment for slave mode
+            reg.set_nostretch(false); // Allow clock stretching for processing time
+        });
+
+        trace!("I2C slave: initialization complete");
+    }
+
+    /// Apply the complete address configuration for slave mode
+    fn apply_address_configuration(&mut self, config: SlaveAddrConfig) {
+        match config.addr {
+            OwnAddresses::OA1(addr) => {
+                self.configure_primary_address(addr);
+                self.disable_secondary_address();
+            }
+            OwnAddresses::OA2(oa2) => {
+                self.configure_default_primary_address();
+                self.configure_secondary_address(oa2.addr); // v1 ignores mask
+            }
+            OwnAddresses::Both { oa1, oa2 } => {
+                self.configure_primary_address(oa1);
+                self.configure_secondary_address(oa2.addr); // v1 ignores mask
+            }
+        }
+
+        // Configure general call detection
+        if config.general_call {
+            self.info.regs.cr1().modify(|w| w.set_engc(true));
+        }
+    }
+
+    /// Configure the primary address (OA1) register
+    fn configure_primary_address(&mut self, addr: Address) {
+        match addr {
+            Address::SevenBit(addr) => {
+                self.info.regs.oar1().write(|reg| {
+                    let hw_addr = (addr as u16) << 1; // Address in bits [7:1]
+                    reg.set_add(hw_addr);
+                    reg.set_addmode(i2c::vals::Addmode::BIT7);
+                });
+            }
+            Address::TenBit(addr) => {
+                self.info.regs.oar1().write(|reg| {
+                    reg.set_add(addr);
+                    reg.set_addmode(i2c::vals::Addmode::BIT10);
+                });
+            }
+        }
+
+        // Set required bit 14 as per reference manual
+        self.info.regs.oar1().modify(|reg| reg.0 |= 1 << 14);
+    }
+
+    /// Configure the secondary address (OA2) register  
+    fn configure_secondary_address(&mut self, addr: u8) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_add2(addr);
+            reg.set_endual(i2c::vals::Endual::DUAL);
+        });
+    }
+
+    /// Set a default primary address when using OA2-only mode
+    fn configure_default_primary_address(&mut self) {
+        self.info.regs.oar1().write(|reg| {
+            reg.set_add(0); // Reserved address, safe to use
+            reg.set_addmode(i2c::vals::Addmode::BIT7);
+        });
+        self.info.regs.oar1().modify(|reg| reg.0 |= 1 << 14);
+    }
+
+    /// Disable secondary address when not needed
+    fn disable_secondary_address(&mut self) {
+        self.info.regs.oar2().write(|reg| {
+            reg.set_endual(i2c::vals::Endual::SINGLE);
+        });
+    }
+}
+
+impl<'d, M: PeriMode> I2c<'d, M, MultiMaster> {
+    /// Listen for incoming I2C address match and return the command type
+    ///
+    /// This method blocks until the slave address is matched by a master.
+    /// Returns the command type (Read/Write) and the matched address.
+    pub fn blocking_listen(&mut self) -> Result<SlaveCommand, Error> {
+        trace!("I2C slave: starting blocking listen for address match");
+        let result = self.blocking_listen_with_timeout(self.timeout());
+        trace!("I2C slave: blocking listen complete, result={:?}", result);
+        result
+    }
+
+    /// Respond to a master read request by transmitting data
+    ///
+    /// Sends the provided data to the master. If the master requests more bytes
+    /// than available, padding bytes (0x00) are sent until the master terminates
+    /// the transaction with NACK.
+    ///
+    /// Returns the total number of bytes transmitted (including padding).
+    pub fn blocking_respond_to_read(&mut self, data: &[u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting blocking respond_to_read, data_len={}", data.len());
+
+        if let Some(zero_length_result) = self.detect_zero_length_read(self.timeout())? {
+            trace!("I2C slave: zero-length read detected");
+            return Ok(zero_length_result);
+        }
+
+        let result = self.transmit_to_master(data, self.timeout());
+        trace!("I2C slave: blocking respond_to_read complete, result={:?}", result);
+        result
+    }
+
+    /// Respond to a master write request by receiving data
+    ///
+    /// Receives data from the master into the provided buffer. If the master
+    /// sends more bytes than the buffer can hold, excess bytes are acknowledged
+    /// but discarded.
+    ///
+    /// Returns the number of bytes stored in the buffer (not total received).
+    pub fn blocking_respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        trace!(
+            "I2C slave: starting blocking respond_to_write, buffer_len={}",
+            buffer.len()
+        );
+        let result = self.receive_from_master(buffer, self.timeout());
+        trace!("I2C slave: blocking respond_to_write complete, result={:?}", result);
+        result
+    }
+
+    // Private implementation methods
+
+    /// Wait for address match and determine transaction type
+    fn blocking_listen_with_timeout(&mut self, timeout: Timeout) -> Result<SlaveCommand, Error> {
+        // Ensure interrupts are disabled for blocking operation
+        self.disable_i2c_interrupts();
+
+        // Wait for address match (ADDR flag)
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            if sr1.addr() {
+                // Address matched - read SR2 to get direction and clear ADDR flag
+                let sr2 = self.info.regs.sr2().read();
+                let direction = if sr2.tra() {
+                    SlaveCommandKind::Read
+                } else {
+                    SlaveCommandKind::Write
+                };
+
+                // Use the static method instead of the instance method
+                let matched_address = Self::decode_matched_address(sr2, self.info)?;
+                trace!(
+                    "I2C slave: address matched, direction={:?}, addr={:?}",
+                    direction, matched_address
+                );
+
+                return Ok(SlaveCommand {
+                    kind: direction,
+                    address: matched_address,
+                });
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Transmit data to master in response to read request
+    fn transmit_to_master(&mut self, data: &[u8], timeout: Timeout) -> Result<usize, Error> {
+        let mut bytes_transmitted = 0;
+        let mut padding_count = 0;
+
+        loop {
+            let byte_to_send = if bytes_transmitted < data.len() {
+                data[bytes_transmitted]
+            } else {
+                padding_count += 1;
+                0x00 // Send padding bytes when data is exhausted
+            };
+
+            match self.transmit_byte(byte_to_send, timeout)? {
+                TransmitResult::Acknowledged => {
+                    bytes_transmitted += 1;
+                }
+                TransmitResult::NotAcknowledged => {
+                    bytes_transmitted += 1; // Count the NACKed byte
+                    break;
+                }
+                TransmitResult::Stopped | TransmitResult::Restarted => {
+                    break;
+                }
+            }
+        }
+
+        if padding_count > 0 {
+            trace!(
+                "I2C slave: sent {} data bytes + {} padding bytes = {} total",
+                data.len(),
+                padding_count,
+                bytes_transmitted
+            );
+        }
+
+        Ok(bytes_transmitted)
+    }
+
+    /// Receive data from master during write request
+    fn receive_from_master(&mut self, buffer: &mut [u8], timeout: Timeout) -> Result<usize, Error> {
+        let mut bytes_stored = 0;
+
+        // Receive bytes that fit in buffer
+        while bytes_stored < buffer.len() {
+            match self.receive_byte(timeout)? {
+                ReceiveResult::Data(byte) => {
+                    buffer[bytes_stored] = byte;
+                    bytes_stored += 1;
+                }
+                ReceiveResult::Stopped | ReceiveResult::Restarted => {
+                    return Ok(bytes_stored);
+                }
+            }
+        }
+
+        // Handle buffer overflow by discarding excess bytes
+        if bytes_stored == buffer.len() {
+            trace!("I2C slave: buffer full, discarding excess bytes");
+            self.discard_excess_bytes(timeout)?;
+        }
+
+        Ok(bytes_stored)
+    }
+
+    /// Detect zero-length read pattern early
+    ///
+    /// Zero-length reads occur when a master sends START+ADDR+R followed immediately
+    /// by NACK+STOP without wanting any data. This must be detected before attempting
+    /// to transmit any bytes to avoid SDA line issues.
+    fn detect_zero_length_read(&mut self, _timeout: Timeout) -> Result<Option<usize>, Error> {
+        // Quick check for immediate termination signals
+        let sr1 = self.info.regs.sr1().read();
+
+        // Check for immediate NACK (fastest zero-length pattern)
+        if sr1.af() {
+            self.clear_acknowledge_failure();
+            return Ok(Some(0));
+        }
+
+        // Check for immediate STOP (alternative zero-length pattern)
+        if sr1.stopf() {
+            Self::clear_stop_flag(self.info);
+            return Ok(Some(0));
+        }
+
+        // Give a brief window for master to send termination signals
+        // This handles masters that have slight delays between address ACK and NACK
+        const ZERO_LENGTH_DETECTION_CYCLES: u32 = 20; // ~5-10µs window
+
+        for _ in 0..ZERO_LENGTH_DETECTION_CYCLES {
+            let sr1 = self.info.regs.sr1().read();
+
+            // Immediate NACK indicates zero-length read
+            if sr1.af() {
+                self.clear_acknowledge_failure();
+                return Ok(Some(0));
+            }
+
+            // Immediate STOP indicates zero-length read
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(Some(0));
+            }
+
+            // If TXE becomes ready, master is waiting for data - not zero-length
+            if sr1.txe() {
+                return Ok(None); // Proceed with normal transmission
+            }
+
+            // If RESTART detected, handle as zero-length
+            if sr1.addr() {
+                return Ok(Some(0));
+            }
+        }
+
+        // No zero-length pattern detected within the window
+        Ok(None)
+    }
+
+    /// Discard excess bytes when buffer is full
+    fn discard_excess_bytes(&mut self, timeout: Timeout) -> Result<(), Error> {
+        let mut discarded_count = 0;
+
+        loop {
+            match self.receive_byte(timeout)? {
+                ReceiveResult::Data(_) => {
+                    discarded_count += 1;
+                    continue;
+                }
+                ReceiveResult::Stopped | ReceiveResult::Restarted => {
+                    if discarded_count > 0 {
+                        trace!("I2C slave: discarded {} excess bytes", discarded_count);
+                    }
+                    break;
+                }
+            }
+        }
+        Ok(())
+    }
+
+    /// Send a single byte and wait for master's response
+    fn transmit_byte(&mut self, byte: u8, timeout: Timeout) -> Result<TransmitResult, Error> {
+        // Wait for transmit buffer ready
+        self.wait_for_transmit_ready(timeout)?;
+
+        // Send the byte
+        self.info.regs.dr().write(|w| w.set_dr(byte));
+
+        // Wait for transmission completion or master response
+        self.wait_for_transmit_completion(timeout)
+    }
+
+    /// Wait until transmit buffer is ready (TXE flag set)
+    fn wait_for_transmit_ready(&mut self, timeout: Timeout) -> Result<(), Error> {
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            // Check for early termination conditions
+            if let Some(result) = Self::check_early_termination(sr1) {
+                return Err(self.handle_early_termination(result));
+            }
+
+            if sr1.txe() {
+                return Ok(()); // Ready to transmit
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Wait for byte transmission completion or master response
+    fn wait_for_transmit_completion(&mut self, timeout: Timeout) -> Result<TransmitResult, Error> {
+        loop {
+            let sr1 = self.info.regs.sr1().read();
+
+            // Check flags in priority order
+            if sr1.af() {
+                self.clear_acknowledge_failure();
+                return Ok(TransmitResult::NotAcknowledged);
+            }
+
+            if sr1.btf() {
+                return Ok(TransmitResult::Acknowledged);
+            }
+
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(TransmitResult::Stopped);
+            }
+
+            if sr1.addr() {
+                return Ok(TransmitResult::Restarted);
+            }
+
+            // Check for other error conditions
+            self.check_for_hardware_errors(sr1)?;
+
+            timeout.check()?;
+        }
+    }
+
+    /// Receive a single byte or detect transaction termination
+    fn receive_byte(&mut self, timeout: Timeout) -> Result<ReceiveResult, Error> {
+        loop {
+            let sr1 = Self::read_status_and_handle_errors(self.info)?;
+
+            // Check for received data first (prioritize data over control signals)
+            if sr1.rxne() {
+                let byte = self.info.regs.dr().read().dr();
+                return Ok(ReceiveResult::Data(byte));
+            }
+
+            // Check for transaction termination
+            if sr1.addr() {
+                return Ok(ReceiveResult::Restarted);
+            }
+
+            if sr1.stopf() {
+                Self::clear_stop_flag(self.info);
+                return Ok(ReceiveResult::Stopped);
+            }
+
+            timeout.check()?;
+        }
+    }
+
+    /// Determine which slave address was matched based on SR2 flags
+    fn decode_matched_address(sr2: i2c::regs::Sr2, info: &'static Info) -> Result<Address, Error> {
+        if sr2.gencall() {
+            Ok(Address::SevenBit(0x00)) // General call address
+        } else if sr2.dualf() {
+            // OA2 (secondary address) was matched
+            let oar2 = info.regs.oar2().read();
+            if oar2.endual() != i2c::vals::Endual::DUAL {
+                return Err(Error::Bus); // Hardware inconsistency
+            }
+            Ok(Address::SevenBit(oar2.add2()))
+        } else {
+            // OA1 (primary address) was matched
+            let oar1 = info.regs.oar1().read();
+            match oar1.addmode() {
+                i2c::vals::Addmode::BIT7 => {
+                    let addr = (oar1.add() >> 1) as u8;
+                    Ok(Address::SevenBit(addr))
+                }
+                i2c::vals::Addmode::BIT10 => Ok(Address::TenBit(oar1.add())),
+            }
+        }
+    }
+
+    // Helper methods for hardware interaction
+
+    /// Read status register and handle I2C errors (except NACK in slave mode)
+    fn read_status_and_handle_errors(info: &'static Info) -> Result<i2c::regs::Sr1, Error> {
+        match Self::check_and_clear_error_flags(info) {
+            Ok(sr1) => Ok(sr1),
+            Err(Error::Nack) => {
+                // In slave mode, NACK is normal protocol behavior, not an error
+                Ok(info.regs.sr1().read())
+            }
+            Err(other_error) => Err(other_error),
+        }
+    }
+
+    /// Check for conditions that cause early termination of operations
+    fn check_early_termination(sr1: i2c::regs::Sr1) -> Option<TransmitResult> {
+        if sr1.stopf() {
+            Some(TransmitResult::Stopped)
+        } else if sr1.addr() {
+            Some(TransmitResult::Restarted)
+        } else if sr1.af() {
+            Some(TransmitResult::NotAcknowledged)
+        } else {
+            None
+        }
+    }
+
+    /// Convert early termination to appropriate error
+    fn handle_early_termination(&mut self, result: TransmitResult) -> Error {
+        match result {
+            TransmitResult::Stopped => {
+                Self::clear_stop_flag(self.info);
+                Error::Bus // Unexpected STOP during setup
+            }
+            TransmitResult::Restarted => {
+                Error::Bus // Unexpected RESTART during setup
+            }
+            TransmitResult::NotAcknowledged => {
+                self.clear_acknowledge_failure();
+                Error::Bus // Unexpected NACK during setup
+            }
+            TransmitResult::Acknowledged => {
+                unreachable!() // This should never be passed to this function
+            }
+        }
+    }
+
+    /// Check for hardware-level I2C errors during transmission
+    fn check_for_hardware_errors(&self, sr1: i2c::regs::Sr1) -> Result<(), Error> {
+        if sr1.timeout() || sr1.ovr() || sr1.arlo() || sr1.berr() {
+            // Delegate to existing error handling
+            Self::check_and_clear_error_flags(self.info)?;
+        }
+        Ok(())
+    }
+
+    /// Disable I2C event and error interrupts for blocking operations
+    fn disable_i2c_interrupts(&mut self) {
+        self.info.regs.cr2().modify(|w| {
+            w.set_itevten(false);
+            w.set_iterren(false);
+        });
+    }
+
+    /// Clear the acknowledge failure flag
+    fn clear_acknowledge_failure(&mut self) {
+        self.info.regs.sr1().write(|reg| {
+            reg.0 = !0;
+            reg.set_af(false);
+        });
+    }
+
+    /// Configure DMA settings for slave operations (shared between read/write)
+    fn setup_slave_dma_base(&mut self) {
+        self.info.regs.cr2().modify(|w| {
+            w.set_itbufen(false); // Always disable buffer interrupts when using DMA
+            w.set_dmaen(true); // Enable DMA requests
+            w.set_last(false); // LAST bit not used in slave mode for v1 hardware
+        });
+    }
+
+    /// Disable DMA and interrupts in a critical section
+    fn disable_dma_and_interrupts(info: &'static Info) {
+        critical_section::with(|_| {
+            info.regs.cr2().modify(|w| {
+                w.set_dmaen(false);
+                w.set_iterren(false);
+                w.set_itevten(false);
+            });
+        });
+    }
+
+    /// Check for early termination conditions during slave operations
+    /// Returns Some(result) if termination detected, None to continue
+    fn check_slave_termination_conditions(sr1: i2c::regs::Sr1) -> Option<SlaveTermination> {
+        if sr1.stopf() {
+            Some(SlaveTermination::Stop)
+        } else if sr1.addr() {
+            Some(SlaveTermination::Restart)
+        } else if sr1.af() {
+            Some(SlaveTermination::Nack)
+        } else {
+            None
+        }
+    }
+}
+
+impl<'d> I2c<'d, Async, MultiMaster> {
+    /// Async listen for incoming I2C messages using interrupts
+    ///
+    /// Waits for a master to address this slave and returns the command type
+    /// (Read/Write) and the matched address. This method will suspend until
+    /// an address match occurs.
+    pub async fn listen(&mut self) -> Result<SlaveCommand, Error> {
+        trace!("I2C slave: starting async listen for address match");
+        let state = self.state;
+        let info = self.info;
+
+        Self::enable_interrupts(info);
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        let result = poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(e) => {
+                    error!("I2C slave: error during listen: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if sr1.addr() {
+                        let sr2 = info.regs.sr2().read();
+                        let direction = if sr2.tra() {
+                            SlaveCommandKind::Read
+                        } else {
+                            SlaveCommandKind::Write
+                        };
+
+                        let matched_address = match Self::decode_matched_address(sr2, info) {
+                            Ok(addr) => {
+                                trace!("I2C slave: address matched, direction={:?}, addr={:?}", direction, addr);
+                                addr
+                            }
+                            Err(e) => {
+                                error!("I2C slave: failed to decode matched address: {:?}", e);
+                                return Poll::Ready(Err(e));
+                            }
+                        };
+
+                        Poll::Ready(Ok(SlaveCommand {
+                            kind: direction,
+                            address: matched_address,
+                        }))
+                    } else {
+                        Self::enable_interrupts(info);
+                        Poll::Pending
+                    }
+                }
+            }
+        })
+        .await;
+
+        drop(on_drop);
+        trace!("I2C slave: listen complete, result={:?}", result);
+        result
+    }
+
+    /// Async respond to write command using RX DMA
+    ///
+    /// Receives data from the master into the provided buffer using DMA.
+    /// If the master sends more bytes than the buffer can hold, excess bytes
+    /// are acknowledged but discarded to prevent interrupt flooding.
+    ///
+    /// Returns the number of bytes stored in the buffer (not total received).
+    pub async fn respond_to_write(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting respond_to_write, buffer_len={}", buffer.len());
+
+        if buffer.is_empty() {
+            warn!("I2C slave: respond_to_write called with empty buffer");
+            return Err(Error::Overrun);
+        }
+
+        let state = self.state;
+        let info = self.info;
+
+        self.setup_slave_dma_base();
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        info.regs.sr2().read();
+
+        let result = self.execute_slave_receive_transfer(buffer, state, info).await;
+
+        drop(on_drop);
+        trace!("I2C slave: respond_to_write complete, result={:?}", result);
+        result
+    }
+
+    /// Async respond to read command using TX DMA
+    ///
+    /// Transmits data to the master using DMA. If the master requests more bytes
+    /// than available in the data buffer, padding bytes (0x00) are sent until
+    /// the master terminates the transaction with NACK, STOP, or RESTART.
+    ///
+    /// Returns the total number of bytes transmitted (data + padding).
+    pub async fn respond_to_read(&mut self, data: &[u8]) -> Result<usize, Error> {
+        trace!("I2C slave: starting respond_to_read, data_len={}", data.len());
+
+        if data.is_empty() {
+            warn!("I2C slave: respond_to_read called with empty data");
+            return Err(Error::Overrun);
+        }
+
+        let state = self.state;
+        let info = self.info;
+
+        self.setup_slave_dma_base();
+
+        let on_drop = OnDrop::new(|| {
+            Self::disable_dma_and_interrupts(info);
+        });
+
+        info.regs.sr2().read();
+
+        let result = self.execute_slave_transmit_transfer(data, state, info).await;
+
+        drop(on_drop);
+        trace!("I2C slave: respond_to_read complete, result={:?}", result);
+        result
+    }
+
+    // === Private Transfer Execution Methods ===
+
+    /// Execute complete slave receive transfer with excess byte handling
+    async fn execute_slave_receive_transfer(
+        &mut self,
+        buffer: &mut [u8],
+        state: &'static State,
+        info: &'static Info,
+    ) -> Result<usize, Error> {
+        let dma_transfer = unsafe {
+            let src = info.regs.dr().as_ptr() as *mut u8;
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let i2c_monitor =
+            Self::create_termination_monitor(state, info, &[SlaveTermination::Stop, SlaveTermination::Restart]);
+
+        match select(dma_transfer, i2c_monitor).await {
+            Either::Second(Err(e)) => {
+                error!("I2C slave: error during receive transfer: {:?}", e);
+                Self::disable_dma_and_interrupts(info);
+                Err(e)
+            }
+            Either::First(_) => {
+                trace!("I2C slave: DMA receive completed, handling excess bytes");
+                Self::disable_dma_and_interrupts(info);
+                self.handle_excess_bytes(state, info).await?;
+                Ok(buffer.len())
+            }
+            Either::Second(Ok(termination)) => {
+                trace!("I2C slave: receive terminated by I2C event: {:?}", termination);
+                Self::disable_dma_and_interrupts(info);
+                Ok(buffer.len())
+            }
+        }
+    }
+
+    /// Execute complete slave transmit transfer with padding byte handling
+    async fn execute_slave_transmit_transfer(
+        &mut self,
+        data: &[u8],
+        state: &'static State,
+        info: &'static Info,
+    ) -> Result<usize, Error> {
+        let dma_transfer = unsafe {
+            let dst = info.regs.dr().as_ptr() as *mut u8;
+            self.tx_dma.as_mut().unwrap().write(data, dst, Default::default())
+        };
+
+        let i2c_monitor = Self::create_termination_monitor(
+            state,
+            info,
+            &[
+                SlaveTermination::Stop,
+                SlaveTermination::Restart,
+                SlaveTermination::Nack,
+            ],
+        );
+
+        match select(dma_transfer, i2c_monitor).await {
+            Either::Second(Err(e)) => {
+                error!("I2C slave: error during transmit transfer: {:?}", e);
+                Self::disable_dma_and_interrupts(info);
+                Err(e)
+            }
+            Either::First(_) => {
+                trace!("I2C slave: DMA transmit completed, handling padding bytes");
+                Self::disable_dma_and_interrupts(info);
+                let padding_count = self.handle_padding_bytes(state, info).await?;
+                let total_bytes = data.len() + padding_count;
+                trace!(
+                    "I2C slave: sent {} data bytes + {} padding bytes = {} total",
+                    data.len(),
+                    padding_count,
+                    total_bytes
+                );
+                Ok(total_bytes)
+            }
+            Either::Second(Ok(termination)) => {
+                trace!("I2C slave: transmit terminated by I2C event: {:?}", termination);
+                Self::disable_dma_and_interrupts(info);
+                Ok(data.len())
+            }
+        }
+    }
+
+    /// Create a future that monitors for specific slave termination conditions
+    fn create_termination_monitor(
+        state: &'static State,
+        info: &'static Info,
+        allowed_terminations: &'static [SlaveTermination],
+    ) -> impl Future<Output = Result<SlaveTermination, Error>> {
+        poll_fn(move |cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(Error::Nack) if allowed_terminations.contains(&SlaveTermination::Nack) => {
+                    Poll::Ready(Ok(SlaveTermination::Nack))
+                }
+                Err(e) => Poll::Ready(Err(e)),
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        if allowed_terminations.contains(&termination) {
+                            // Handle the specific termination condition
+                            match termination {
+                                SlaveTermination::Stop => Self::clear_stop_flag(info),
+                                SlaveTermination::Nack => {
+                                    info.regs.sr1().write(|reg| {
+                                        reg.0 = !0;
+                                        reg.set_af(false);
+                                    });
+                                }
+                                SlaveTermination::Restart => {
+                                    // ADDR flag will be handled by next listen() call
+                                }
+                            }
+                            Poll::Ready(Ok(termination))
+                        } else {
+                            // Unexpected termination condition
+                            Poll::Ready(Err(Error::Bus))
+                        }
+                    } else {
+                        Self::enable_interrupts(info);
+                        Poll::Pending
+                    }
+                }
+            }
+        })
+    }
+
+    /// Handle excess bytes after DMA buffer is full
+    ///
+    /// Reads and discards bytes until transaction termination to prevent interrupt flooding
+    async fn handle_excess_bytes(&mut self, state: &'static State, info: &'static Info) -> Result<(), Error> {
+        let mut discarded_count = 0;
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(e) => {
+                    error!("I2C slave: error while discarding excess bytes: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        match termination {
+                            SlaveTermination::Stop => Self::clear_stop_flag(info),
+                            SlaveTermination::Restart => {}
+                            SlaveTermination::Nack => unreachable!("NACK not expected during receive"),
+                        }
+                        if discarded_count > 0 {
+                            trace!("I2C slave: discarded {} excess bytes", discarded_count);
+                        }
+                        return Poll::Ready(Ok(()));
+                    }
+
+                    if sr1.rxne() {
+                        let _discarded_byte = info.regs.dr().read().dr();
+                        discarded_count += 1;
+                        Self::enable_interrupts(info);
+                        return Poll::Pending;
+                    }
+
+                    Self::enable_interrupts(info);
+                    Poll::Pending
+                }
+            }
+        })
+        .await
+    }
+
+    /// Handle padding bytes after DMA data is exhausted
+    ///
+    /// Sends 0x00 bytes until transaction termination to prevent interrupt flooding
+    async fn handle_padding_bytes(&mut self, state: &'static State, info: &'static Info) -> Result<usize, Error> {
+        let mut padding_count = 0;
+
+        poll_fn(|cx| {
+            state.waker.register(cx.waker());
+
+            match Self::check_and_clear_error_flags(info) {
+                Err(Error::Nack) => Poll::Ready(Ok(padding_count)),
+                Err(e) => {
+                    error!("I2C slave: error while sending padding bytes: {:?}", e);
+                    Poll::Ready(Err(e))
+                }
+                Ok(sr1) => {
+                    if let Some(termination) = Self::check_slave_termination_conditions(sr1) {
+                        match termination {
+                            SlaveTermination::Stop => Self::clear_stop_flag(info),
+                            SlaveTermination::Restart => {}
+                            SlaveTermination::Nack => {
+                                info.regs.sr1().write(|reg| {
+                                    reg.0 = !0;
+                                    reg.set_af(false);
+                                });
+                            }
+                        }
+                        return Poll::Ready(Ok(padding_count));
+                    }
+
+                    if sr1.txe() {
+                        info.regs.dr().write(|w| w.set_dr(0x00));
+                        padding_count += 1;
+                        Self::enable_interrupts(info);
+                        return Poll::Pending;
+                    }
+
+                    Self::enable_interrupts(info);
+                    Poll::Pending
+                }
+            }
+        })
+        .await
+    }
+}
+
+/// Timing configuration for I2C v1 hardware
+///
+/// This struct encapsulates the complex timing calculations required for STM32 I2C v1
+/// peripherals, which use three separate registers (CR2.FREQ, CCR, TRISE) instead of
+/// the unified TIMINGR register found in v2 hardware.
 struct Timings {
-    freq: u8,
-    mode: Mode,
-    trise: u8,
-    ccr: u16,
-    duty: Duty,
+    freq: u8,   // APB frequency in MHz for CR2.FREQ register
+    mode: Mode, // Standard or Fast mode selection
+    trise: u8,  // Rise time compensation value
+    ccr: u16,   // Clock control register value
+    duty: Duty, // Fast mode duty cycle selection
 }
 
 impl Timings {
@@ -762,11 +1735,7 @@ impl Timings {
             mode = Mode::Standard;
             ccr = {
                 let ccr = clock / (frequency * 2);
-                if ccr < 4 {
-                    4
-                } else {
-                    ccr
-                }
+                if ccr < 4 { 4 } else { ccr }
             };
         } else {
             const DUTYCYCLE: u8 = 0;
@@ -775,14 +1744,10 @@ impl Timings {
                 duty = Duty::Duty2_1;
                 ccr = clock / (frequency * 3);
                 ccr = if ccr < 1 { 1 } else { ccr };
-
-                // Set clock to fast mode with appropriate parameters for selected speed (2:1 duty cycle)
             } else {
                 duty = Duty::Duty16_9;
                 ccr = clock / (frequency * 25);
                 ccr = if ccr < 1 { 1 } else { ccr };
-
-                // Set clock to fast mode with appropriate parameters for selected speed (16:9 duty cycle)
             }
         }
 
@@ -792,11 +1757,6 @@ impl Timings {
             ccr: ccr as u16,
             duty,
             mode,
-            //prescale: presc_reg,
-            //scll,
-            //sclh,
-            //sdadel,
-            //scldel,
         }
     }
 }
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 0bfc795ac..61e550ad4 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -2,7 +2,7 @@ use core::cmp;
 use core::future::poll_fn;
 use core::task::Poll;
 
-use config::{Address, OwnAddresses, OA2};
+use config::{Address, OA2, OwnAddresses};
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
 use embedded_hal_1::i2c::Operation;
@@ -70,6 +70,11 @@ fn debug_print_interrupts(isr: stm32_metapac::i2c::regs::Isr) {
 }
 
 pub(crate) unsafe fn on_interrupt<T: Instance>() {
+    // restore the clocks to their last configured state as
+    // much is lost in STOP modes
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    crate::low_power::Executor::on_wakeup_irq();
+
     let regs = T::info().regs;
     let isr = regs.isr().read();
 
@@ -93,6 +98,27 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
 }
 
 impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
+    #[inline]
+    fn to_reload(reload: bool) -> i2c::vals::Reload {
+        if reload {
+            i2c::vals::Reload::NOT_COMPLETED
+        } else {
+            i2c::vals::Reload::COMPLETED
+        }
+    }
+
+    /// Calculate total bytes in a group of operations
+    #[inline]
+    fn total_operation_bytes(operations: &[Operation<'_>]) -> usize {
+        operations
+            .iter()
+            .map(|op| match op {
+                Operation::Write(buf) => buf.len(),
+                Operation::Read(buf) => buf.len(),
+            })
+            .sum()
+    }
+
     pub(crate) fn init(&mut self, config: Config) {
         self.info.regs.cr1().modify(|reg| {
             reg.set_pe(false);
@@ -142,12 +168,6 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         // `buffer`. The START bit can be set even if the bus
         // is BUSY or I2C is in slave mode.
 
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         info.regs.cr2().modify(|w| {
             w.set_sadd(address.addr() << 1);
             w.set_add10(address.add_mode());
@@ -155,7 +175,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             w.set_nbytes(length as u8);
             w.set_start(true);
             w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
         });
 
         Ok(())
@@ -167,28 +187,25 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         length: usize,
         stop: Stop,
         reload: bool,
+        restart: bool,
         timeout: Timeout,
     ) -> Result<(), Error> {
         assert!(length < 256);
 
-        // Wait for any previous address sequence to end
-        // automatically. This could be up to 50% of a bus
-        // cycle (ie. up to 0.5/freq)
-        while info.regs.cr2().read().start() {
-            timeout.check()?;
-        }
+        if !restart {
+            // Wait for any previous address sequence to end
+            // automatically. This could be up to 50% of a bus
+            // cycle (ie. up to 0.5/freq)
+            while info.regs.cr2().read().start() {
+                timeout.check()?;
+            }
 
-        // Wait for the bus to be free
-        while info.regs.isr().read().busy() {
-            timeout.check()?;
+            // Wait for the bus to be free
+            while info.regs.isr().read().busy() {
+                timeout.check()?;
+            }
         }
 
-        let reload = if reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         // Set START and prepare to send `bytes`. The
         // START bit can be set even if the bus is BUSY or
         // I2C is in slave mode.
@@ -199,28 +216,36 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             w.set_nbytes(length as u8);
             w.set_start(true);
             w.set_autoend(stop.autoend());
-            w.set_reload(reload);
+            w.set_reload(Self::to_reload(reload));
         });
 
         Ok(())
     }
 
-    fn reload(info: &'static Info, length: usize, will_reload: bool, timeout: Timeout) -> Result<(), Error> {
+    fn reload(
+        info: &'static Info,
+        length: usize,
+        will_reload: bool,
+        stop: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
         assert!(length < 256 && length > 0);
 
-        while !info.regs.isr().read().tcr() {
+        // Wait for either TCR (Transfer Complete Reload) or TC (Transfer Complete)
+        // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+        // Both indicate the peripheral is ready for the next transfer
+        loop {
+            let isr = info.regs.isr().read();
+            if isr.tcr() || isr.tc() {
+                break;
+            }
             timeout.check()?;
         }
 
-        let will_reload = if will_reload {
-            i2c::vals::Reload::NOT_COMPLETED
-        } else {
-            i2c::vals::Reload::COMPLETED
-        };
-
         info.regs.cr2().modify(|w| {
             w.set_nbytes(length as u8);
-            w.set_reload(will_reload);
+            w.set_reload(Self::to_reload(will_reload));
+            w.set_autoend(stop.autoend());
         });
 
         Ok(())
@@ -364,7 +389,9 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
         loop {
             let isr = self.info.regs.isr().read();
             self.error_occurred(&isr, timeout)?;
-            if isr.tc() {
+            // Wait for either TC or TCR - both indicate transfer completion
+            // TCR occurs when RELOAD=1, TC occurs when RELOAD=0
+            if isr.tc() || isr.tcr() {
                 return Ok(());
             }
             timeout.check()?;
@@ -391,14 +418,20 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             address,
             read.len().min(255),
             Stop::Automatic,
-            last_chunk_idx != 0,
+            last_chunk_idx != 0, // reload
             restart,
             timeout,
         )?;
 
         for (number, chunk) in read.chunks_mut(255).enumerate() {
             if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Automatic,
+                    timeout,
+                )?;
             }
 
             for byte in chunk {
@@ -436,6 +469,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             write.len().min(255),
             Stop::Software,
             last_chunk_idx != 0,
+            false, // restart
             timeout,
         ) {
             if send_stop {
@@ -446,7 +480,13 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
 
         for (number, chunk) in write.chunks(255).enumerate() {
             if number != 0 {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             for byte in chunk {
@@ -502,9 +542,215 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub fn blocking_transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
-        let _ = addr;
-        let _ = operations;
-        todo!()
+        if operations.is_empty() {
+            return Err(Error::ZeroLengthTransfer);
+        }
+
+        let address = addr.into();
+        let timeout = self.timeout();
+
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            } else {
+                self.execute_write_group(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )?;
+            }
+
+            is_first_group = false;
+        }
+
+        Ok(())
+    }
+
+    fn execute_write_group(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty write group - just send address
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                for chunk in buffer.chunks(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        // If not first group, use RESTART instead of START
+                        Self::master_write(
+                            self.info,
+                            address,
+                            chunk_len,
+                            Stop::Software,
+                            will_reload,
+                            !is_first_group,
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        // Always use Software stop for writes
+                        Self::reload(self.info, chunk_len, will_reload, Stop::Software, timeout)?;
+                    }
+
+                    // Send data bytes
+                    for byte in chunk {
+                        self.wait_txis(timeout)?;
+                        self.info.regs.txdr().write(|w| w.set_txdata(*byte));
+                    }
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_tc(timeout)?;
+            self.master_stop();
+            self.wait_stop(timeout)?;
+        } else {
+            // Wait for TC before next group (enables RESTART)
+            self.wait_tc(timeout)?;
+        }
+
+        Ok(())
+    }
+
+    fn execute_read_group(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty read group
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+
+        let mut total_remaining = total_bytes;
+        let mut first_chunk = true;
+
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                for chunk in buffer.chunks_mut(255) {
+                    let chunk_len = chunk.len();
+                    total_remaining -= chunk_len;
+                    let is_last_chunk = total_remaining == 0;
+                    let will_reload = !is_last_chunk;
+
+                    if first_chunk {
+                        // First chunk: initiate transfer
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+
+                        Self::master_read(
+                            self.info,
+                            address,
+                            chunk_len,
+                            stop,
+                            will_reload,
+                            !is_first_group, // restart if not first group
+                            timeout,
+                        )?;
+                        first_chunk = false;
+                    } else {
+                        // Subsequent chunks: use reload
+                        let stop = if is_last_group && is_last_chunk {
+                            Stop::Automatic
+                        } else {
+                            Stop::Software
+                        };
+                        Self::reload(self.info, chunk_len, will_reload, stop, timeout)?;
+                    }
+
+                    // Receive data bytes
+                    for byte in chunk {
+                        self.wait_rxne(timeout)?;
+                        *byte = self.info.regs.rxdr().read().rxdata();
+                    }
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+        // For non-last read groups, don't wait for TC - the peripheral may hold SCL low
+        // in Software AUTOEND mode until the next START is issued. Just proceed directly
+        // to the next group which will issue RESTART and release the clock.
+
+        Ok(())
     }
 
     /// Blocking write multiple buffers.
@@ -526,6 +772,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
             first_length.min(255),
             Stop::Software,
             (first_length > 255) || (last_slice_index != 0),
+            false, // restart
             timeout,
         ) {
             self.master_stop();
@@ -547,6 +794,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                     self.info,
                     slice_len.min(255),
                     (idx != last_slice_index) || (slice_len > 255),
+                    Stop::Software,
                     timeout,
                 ) {
                     if err != Error::Nack {
@@ -562,6 +810,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
                         self.info,
                         chunk.len(),
                         (number != last_chunk_idx) || (idx != last_slice_index),
+                        Stop::Software,
                         timeout,
                     ) {
                         if err != Error::Nack {
@@ -605,6 +854,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         first_slice: bool,
         last_slice: bool,
         send_stop: bool,
+        restart: bool,
         timeout: Timeout,
     ) -> Result<(), Error> {
         let total_len = write.len();
@@ -671,10 +921,17 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                         total_len.min(255),
                         Stop::Software,
                         (total_len > 255) || !last_slice,
+                        restart,
                         timeout,
                     )?;
                 } else {
-                    Self::reload(self.info, total_len.min(255), (total_len > 255) || !last_slice, timeout)?;
+                    Self::reload(
+                        self.info,
+                        total_len.min(255),
+                        (total_len > 255) || !last_slice,
+                        Stop::Software,
+                        timeout,
+                    )?;
                     self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 }
             } else if !(isr.tcr() || isr.tc()) {
@@ -683,9 +940,13 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
             } else if remaining_len == 0 {
                 return Poll::Ready(Ok(()));
             } else {
-                let last_piece = (remaining_len <= 255) && last_slice;
-
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    (remaining_len > 255) || !last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
@@ -697,10 +958,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
         .await?;
 
         dma_transfer.await;
-        if last_slice {
-            // This should be done already
-            self.wait_tc(timeout)?;
-        }
+
+        // Always wait for TC after DMA completes - needed for consecutive buffers
+        self.wait_tc(timeout)?;
 
         if last_slice & send_stop {
             self.master_stop();
@@ -775,7 +1035,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     address,
                     total_len.min(255),
                     Stop::Automatic,
-                    total_len > 255,
+                    total_len > 255, // reload
                     restart,
                     timeout,
                 )?;
@@ -783,12 +1043,10 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     return Poll::Ready(Ok(()));
                 }
             } else if isr.tcr() {
-                // poll_fn was woken without an interrupt present
-                return Poll::Pending;
-            } else {
+                // Transfer Complete Reload - need to set up next chunk
                 let last_piece = remaining_len <= 255;
 
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, Stop::Automatic, timeout) {
                     return Poll::Ready(Err(e));
                 }
                 // Return here if we are on last chunk,
@@ -797,6 +1055,9 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                     return Poll::Ready(Ok(()));
                 }
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
             }
 
             remaining_len = remaining_len.saturating_sub(255);
@@ -814,12 +1075,14 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write.
     pub async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
         if write.is_empty() {
             self.write_internal(address.into(), write, true, timeout)
         } else {
             timeout
-                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, false, timeout))
                 .await
         }
     }
@@ -828,21 +1091,31 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// The buffers are concatenated in a single write transaction.
     pub async fn write_vectored(&mut self, address: Address, write: &[&[u8]]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
             return Err(Error::ZeroLengthTransfer);
         }
-        let mut iter = write.iter();
 
+        let mut iter = write.iter();
         let mut first = true;
         let mut current = iter.next();
+
         while let Some(c) = current {
             let next = iter.next();
             let is_last = next.is_none();
 
-            let fut = self.write_dma_internal(address, c, first, is_last, is_last, timeout);
+            let fut = self.write_dma_internal(
+                address, c, first,   // first_slice
+                is_last, // last_slice
+                is_last, // send_stop (only on last buffer)
+                false,   // restart (false for all - they're one continuous write)
+                timeout,
+            );
             timeout.with(fut).await?;
+
             first = false;
             current = next;
         }
@@ -851,6 +1124,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Read.
     pub async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if buffer.is_empty() {
@@ -863,12 +1138,14 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
 
     /// Write, restart, read.
     pub async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
         let timeout = self.timeout();
 
         if write.is_empty() {
             self.write_internal(address.into(), write, false, timeout)?;
         } else {
-            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, false, timeout);
             timeout.with(fut).await?;
         }
 
@@ -888,9 +1165,301 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
     ///
     /// [transaction contract]: embedded_hal_1::i2c::I2c::transaction
     pub async fn transaction(&mut self, addr: u8, operations: &mut [Operation<'_>]) -> Result<(), Error> {
-        let _ = addr;
-        let _ = operations;
-        todo!()
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        let _device_busy = crate::low_power::DeviceBusy::new_stop1();
+
+        if operations.is_empty() {
+            return Err(Error::ZeroLengthTransfer);
+        }
+
+        let address = addr.into();
+        let timeout = self.timeout();
+
+        // Group consecutive operations of the same type
+        let mut op_idx = 0;
+        let mut is_first_group = true;
+
+        while op_idx < operations.len() {
+            // Determine the type of current group and find all consecutive operations of same type
+            let is_read = matches!(operations[op_idx], Operation::Read(_));
+            let group_start = op_idx;
+
+            // Find end of this group (consecutive operations of same type)
+            while op_idx < operations.len() && matches!(operations[op_idx], Operation::Read(_)) == is_read {
+                op_idx += 1;
+            }
+            let group_end = op_idx;
+            let is_last_group = op_idx >= operations.len();
+
+            // Execute this group of operations
+            if is_read {
+                self.execute_read_group_async(
+                    address,
+                    &mut operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            } else {
+                self.execute_write_group_async(
+                    address,
+                    &operations[group_start..group_end],
+                    is_first_group,
+                    is_last_group,
+                    timeout,
+                )
+                .await?;
+            }
+
+            is_first_group = false;
+        }
+
+        Ok(())
+    }
+
+    async fn execute_write_group_async(
+        &mut self,
+        address: Address,
+        operations: &[Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty write group using blocking call
+            if is_first_group {
+                Self::master_write(self.info, address, 0, Stop::Software, false, !is_first_group, timeout)?;
+            }
+            if is_last_group {
+                self.master_stop();
+            }
+            return Ok(());
+        }
+
+        // Collect all write buffers
+        let mut write_buffers: heapless::Vec<&[u8], 16> = heapless::Vec::new();
+        for operation in operations {
+            if let Operation::Write(buffer) = operation {
+                if !buffer.is_empty() {
+                    let _ = write_buffers.push(buffer);
+                }
+            }
+        }
+
+        if write_buffers.is_empty() {
+            return Ok(());
+        }
+
+        // Send each buffer using DMA
+        let num_buffers = write_buffers.len();
+        for (idx, buffer) in write_buffers.iter().enumerate() {
+            let is_first_buffer = idx == 0;
+            let is_last_buffer = idx == num_buffers - 1;
+
+            let fut = self.write_dma_internal(
+                address,
+                buffer,
+                is_first_buffer,                    // first_slice
+                is_last_buffer,                     // last_slice
+                is_last_buffer && is_last_group,    // send_stop
+                is_first_buffer && !is_first_group, // restart (only for first buffer if not first group)
+                timeout,
+            );
+            timeout.with(fut).await?;
+        }
+
+        Ok(())
+    }
+
+    async fn execute_read_group_async(
+        &mut self,
+        address: Address,
+        operations: &mut [Operation<'_>],
+        is_first_group: bool,
+        is_last_group: bool,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        // Calculate total bytes across all operations in this group
+        let total_bytes = Self::total_operation_bytes(operations);
+
+        if total_bytes == 0 {
+            // Handle empty read group using blocking call
+            if is_first_group {
+                Self::master_read(
+                    self.info,
+                    address,
+                    0,
+                    if is_last_group { Stop::Automatic } else { Stop::Software },
+                    false, // reload
+                    !is_first_group,
+                    timeout,
+                )?;
+            }
+            if is_last_group {
+                self.wait_stop(timeout)?;
+            }
+            return Ok(());
+        }
+
+        // Use DMA for read operations - need to handle multiple buffers
+        let restart = !is_first_group;
+        let mut total_remaining = total_bytes;
+        let mut is_first_in_group = true;
+
+        for operation in operations {
+            if let Operation::Read(buffer) = operation {
+                if buffer.is_empty() {
+                    // Skip empty buffers
+                    continue;
+                }
+
+                let buf_len = buffer.len();
+                total_remaining -= buf_len;
+                let is_last_in_group = total_remaining == 0;
+
+                // Perform DMA read
+                if is_first_in_group {
+                    // First buffer: use read_dma_internal which handles restart properly
+                    // Only use Automatic stop if this is the last buffer in the last group
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+
+                    // We need a custom DMA read that respects our stop mode
+                    self.read_dma_group_internal(address, buffer, restart, stop_mode, timeout)
+                        .await?;
+                    is_first_in_group = false;
+                } else {
+                    // Subsequent buffers: need to reload and continue
+                    let stop_mode = if is_last_group && is_last_in_group {
+                        Stop::Automatic
+                    } else {
+                        Stop::Software
+                    };
+
+                    self.read_dma_group_internal(
+                        address, buffer, false, // no restart for subsequent buffers in same group
+                        stop_mode, timeout,
+                    )
+                    .await?;
+                }
+            }
+        }
+
+        // Wait for transfer to complete
+        if is_last_group {
+            self.wait_stop(timeout)?;
+        }
+
+        Ok(())
+    }
+
+    /// Internal DMA read helper for transaction groups
+    async fn read_dma_group_internal(
+        &mut self,
+        address: Address,
+        buffer: &mut [u8],
+        restart: bool,
+        stop_mode: Stop,
+        timeout: Timeout,
+    ) -> Result<(), Error> {
+        let total_len = buffer.len();
+
+        let dma_transfer = unsafe {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(true);
+                w.set_tcie(true);
+                w.set_nackie(true);
+                w.set_errie(true);
+            });
+            let src = regs.rxdr().as_ptr() as *mut u8;
+
+            self.rx_dma.as_mut().unwrap().read(src, buffer, Default::default())
+        };
+
+        let mut remaining_len = total_len;
+
+        let on_drop = OnDrop::new(|| {
+            let regs = self.info.regs;
+            regs.cr1().modify(|w| {
+                w.set_rxdmaen(false);
+                w.set_tcie(false);
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
+        });
+
+        poll_fn(|cx| {
+            self.state.waker.register(cx.waker());
+
+            let isr = self.info.regs.isr().read();
+
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
+
+            if remaining_len == total_len {
+                Self::master_read(
+                    self.info,
+                    address,
+                    total_len.min(255),
+                    stop_mode,
+                    total_len > 255, // reload
+                    restart,
+                    timeout,
+                )?;
+                if total_len <= 255 {
+                    return Poll::Ready(Ok(()));
+                }
+            } else if isr.tcr() {
+                // Transfer Complete Reload - need to set up next chunk
+                let last_piece = remaining_len <= 255;
+
+                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, stop_mode, timeout) {
+                    return Poll::Ready(Err(e));
+                }
+                // Return here if we are on last chunk,
+                // end of transfer will be awaited with the DMA below
+                if last_piece {
+                    return Poll::Ready(Ok(()));
+                }
+                self.info.regs.cr1().modify(|w| w.set_tcie(true));
+            } else {
+                // poll_fn was woken without TCR interrupt
+                return Poll::Pending;
+            }
+
+            remaining_len = remaining_len.saturating_sub(255);
+            Poll::Pending
+        })
+        .await?;
+
+        dma_transfer.await;
+        drop(on_drop);
+
+        Ok(())
     }
 }
 
@@ -1028,7 +1597,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
             if number == 0 {
                 Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
             } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             let mut index = 0;
@@ -1077,7 +1652,13 @@ impl<'d, M: Mode> I2c<'d, M, MultiMaster> {
             if number == 0 {
                 Self::slave_start(self.info, chunk.len(), number != last_chunk_idx);
             } else {
-                Self::reload(self.info, chunk.len(), number != last_chunk_idx, timeout)?;
+                Self::reload(
+                    self.info,
+                    chunk.len(),
+                    number != last_chunk_idx,
+                    Stop::Software,
+                    timeout,
+                )?;
             }
 
             let mut index = 0;
@@ -1181,7 +1762,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
 
         let regs = self.info.regs;
 
-        let dma_transfer = unsafe {
+        let mut dma_transfer = unsafe {
             regs.cr1().modify(|w| {
                 w.set_rxdmaen(true);
                 w.set_stopie(true);
@@ -1213,13 +1794,20 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                 Poll::Pending
             } else if isr.tcr() {
                 let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 remaining_len = remaining_len.saturating_sub(255);
                 regs.cr1().modify(|w| w.set_tcie(true));
                 Poll::Pending
             } else if isr.stopf() {
+                remaining_len = remaining_len.saturating_add(dma_transfer.get_remaining_transfers() as usize);
                 regs.icr().write(|reg| reg.set_stopcf(true));
                 let poll = Poll::Ready(Ok(total_len - remaining_len));
                 poll
@@ -1229,6 +1817,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
         })
         .await?;
 
+        dma_transfer.request_pause();
         dma_transfer.await;
 
         drop(on_drop);
@@ -1258,7 +1847,8 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                 w.set_txdmaen(false);
                 w.set_stopie(false);
                 w.set_tcie(false);
-            })
+            });
+            regs.isr().write(|w| w.set_txe(true));
         });
 
         let state = self.state;
@@ -1274,13 +1864,24 @@ impl<'d> I2c<'d, Async, MultiMaster> {
                 Poll::Pending
             } else if isr.tcr() {
                 let is_last_slice = remaining_len <= 255;
-                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !is_last_slice, timeout) {
+                if let Err(e) = Self::reload(
+                    self.info,
+                    remaining_len.min(255),
+                    !is_last_slice,
+                    Stop::Software,
+                    timeout,
+                ) {
                     return Poll::Ready(Err(e));
                 }
                 remaining_len = remaining_len.saturating_sub(255);
                 self.info.regs.cr1().modify(|w| w.set_tcie(true));
                 Poll::Pending
             } else if isr.stopf() {
+                let mut leftover_bytes = dma_transfer.get_remaining_transfers();
+                if !self.info.regs.isr().read().txe() {
+                    leftover_bytes = leftover_bytes.saturating_add(1);
+                }
+                remaining_len = remaining_len.saturating_add(leftover_bytes as usize);
                 self.info.regs.icr().write(|reg| reg.set_stopcf(true));
                 if remaining_len > 0 {
                     dma_transfer.request_pause();
@@ -1294,6 +1895,7 @@ impl<'d> I2c<'d, Async, MultiMaster> {
         })
         .await?;
 
+        dma_transfer.request_pause();
         dma_transfer.await;
 
         drop(on_drop);
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index b6d3daf54..df077a3ae 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -3,12 +3,13 @@
 use embassy_futures::join::join;
 use stm32_metapac::spi::vals;
 
-use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
+use crate::Peri;
+use crate::dma::{ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer, ringbuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
+use crate::spi::mode::Master;
 use crate::spi::{Config as SpiConfig, RegsExt as _, *};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// I2S mode
 #[derive(Copy, Clone)]
@@ -225,7 +226,7 @@ impl<'s, 'd, W: Word> Reader<'s, 'd, W> {
 pub struct I2S<'d, W: Word> {
     #[allow(dead_code)]
     mode: Mode,
-    spi: Spi<'d, Async>,
+    spi: Spi<'d, Async, Master>,
     txsd: Option<Peri<'d, AnyPin>>,
     rxsd: Option<Peri<'d, AnyPin>>,
     ws: Option<Peri<'d, AnyPin>>,
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 670d8332c..10c4a820b 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -1,9 +1,11 @@
 //! Inter-Process Communication Controller (IPCC)
 
 use core::future::poll_fn;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::marker::PhantomData;
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
@@ -17,25 +19,16 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for Receive
     unsafe fn on_interrupt() {
         let regs = IPCC::regs();
 
-        let channels = [
-            IpccChannel::Channel1,
-            IpccChannel::Channel2,
-            IpccChannel::Channel3,
-            IpccChannel::Channel4,
-            IpccChannel::Channel5,
-            IpccChannel::Channel6,
-        ];
-
         // Status register gives channel occupied status. For rx, use cpu1.
         let sr = regs.cpu(1).sr().read();
         regs.cpu(0).mr().modify(|w| {
-            for channel in channels {
-                if sr.chf(channel as usize) {
+            for index in 0..5 {
+                if sr.chf(index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    w.set_chom(channel as usize, true);
+                    w.set_chom(index as usize, true);
 
                     // There shouldn't be a race because the channel is masked only if the interrupt has fired
-                    IPCC::state().rx_waker_for(channel).wake();
+                    IPCC::state().rx_waker_for(index).wake();
                 }
             }
         })
@@ -49,25 +42,16 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for Transmi
     unsafe fn on_interrupt() {
         let regs = IPCC::regs();
 
-        let channels = [
-            IpccChannel::Channel1,
-            IpccChannel::Channel2,
-            IpccChannel::Channel3,
-            IpccChannel::Channel4,
-            IpccChannel::Channel5,
-            IpccChannel::Channel6,
-        ];
-
         // Status register gives channel occupied status. For tx, use cpu0.
         let sr = regs.cpu(0).sr().read();
         regs.cpu(0).mr().modify(|w| {
-            for channel in channels {
-                if !sr.chf(channel as usize) {
+            for index in 0..5 {
+                if !sr.chf(index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    w.set_chfm(channel as usize, true);
+                    w.set_chfm(index as usize, true);
 
                     // There shouldn't be a race because the channel is masked only if the interrupt has fired
-                    IPCC::state().tx_waker_for(channel).wake();
+                    IPCC::state().tx_waker_for(index).wake();
                 }
             }
         });
@@ -82,76 +66,55 @@ pub struct Config {
     // reserved for future use
 }
 
-/// Channel.
-#[allow(missing_docs)]
-#[derive(Debug, Clone, Copy)]
-#[repr(C)]
-pub enum IpccChannel {
-    Channel1 = 0,
-    Channel2 = 1,
-    Channel3 = 2,
-    Channel4 = 3,
-    Channel5 = 4,
-    Channel6 = 5,
+/// IPCC TX Channel
+pub struct IpccTxChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
 }
 
-/// IPCC driver.
-pub struct Ipcc;
-
-impl Ipcc {
-    /// Enable IPCC.
-    pub fn enable(_config: Config) {
-        rcc::enable_and_reset::<IPCC>();
-        IPCC::set_cpu2(true);
-
-        let regs = IPCC::regs();
-
-        regs.cpu(0).cr().modify(|w| {
-            w.set_rxoie(true);
-            w.set_txfie(true);
-        });
-
-        // enable interrupts
-        crate::interrupt::typelevel::IPCC_C1_RX::unpend();
-        crate::interrupt::typelevel::IPCC_C1_TX::unpend();
+impl<'a> IpccTxChannel<'a> {
+    pub(crate) const fn new(index: u8) -> Self {
+        core::assert!(index < 6);
 
-        unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
-        unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
+        Self {
+            index: index,
+            _lifetime: PhantomData,
+        }
     }
 
     /// Send data to an IPCC channel. The closure is called to write the data when appropriate.
-    pub async fn send(channel: IpccChannel, f: impl FnOnce()) {
+    pub async fn send(&mut self, f: impl FnOnce()) {
         let regs = IPCC::regs();
 
-        Self::flush(channel).await;
+        self.flush().await;
 
         f();
 
         compiler_fence(Ordering::SeqCst);
 
-        trace!("ipcc: ch {}: send data", channel as u8);
-        regs.cpu(0).scr().write(|w| w.set_chs(channel as usize, true));
+        trace!("ipcc: ch {}: send data", self.index as u8);
+        regs.cpu(0).scr().write(|w| w.set_chs(self.index as usize, true));
     }
 
     /// Wait for the tx channel to become clear
-    pub async fn flush(channel: IpccChannel) {
+    pub async fn flush(&mut self) {
         let regs = IPCC::regs();
 
         // This is a race, but is nice for debugging
-        if regs.cpu(0).sr().read().chf(channel as usize) {
-            trace!("ipcc: ch {}: wait for tx free", channel as u8);
+        if regs.cpu(0).sr().read().chf(self.index as usize) {
+            trace!("ipcc: ch {}: wait for tx free", self.index as u8);
         }
 
         poll_fn(|cx| {
-            IPCC::state().tx_waker_for(channel).register(cx.waker());
+            IPCC::state().tx_waker_for(self.index).register(cx.waker());
             // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
-            regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, false));
+            regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, false));
 
             compiler_fence(Ordering::SeqCst);
 
-            if !regs.cpu(0).sr().read().chf(channel as usize) {
+            if !regs.cpu(0).sr().read().chf(self.index as usize) {
                 // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
+                regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, true));
 
                 Poll::Ready(())
             } else {
@@ -160,27 +123,44 @@ impl Ipcc {
         })
         .await;
     }
+}
+
+/// IPCC RX Channel
+pub struct IpccRxChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
+}
+
+impl<'a> IpccRxChannel<'a> {
+    pub(crate) const fn new(index: u8) -> Self {
+        core::assert!(index < 6);
+
+        Self {
+            index: index,
+            _lifetime: PhantomData,
+        }
+    }
 
     /// Receive data from an IPCC channel. The closure is called to read the data when appropriate.
-    pub async fn receive<R>(channel: IpccChannel, mut f: impl FnMut() -> Option<R>) -> R {
+    pub async fn receive<R>(&mut self, mut f: impl FnMut() -> Option<R>) -> R {
         let regs = IPCC::regs();
 
         loop {
             // This is a race, but is nice for debugging
-            if !regs.cpu(1).sr().read().chf(channel as usize) {
-                trace!("ipcc: ch {}: wait for rx occupied", channel as u8);
+            if !regs.cpu(1).sr().read().chf(self.index as usize) {
+                trace!("ipcc: ch {}: wait for rx occupied", self.index as u8);
             }
 
             poll_fn(|cx| {
-                IPCC::state().rx_waker_for(channel).register(cx.waker());
+                IPCC::state().rx_waker_for(self.index).register(cx.waker());
                 // If bit is set to 1 then interrupt is disabled; we want to enable the interrupt
-                regs.cpu(0).mr().modify(|w| w.set_chom(channel as usize, false));
+                regs.cpu(0).mr().modify(|w| w.set_chom(self.index as usize, false));
 
                 compiler_fence(Ordering::SeqCst);
 
-                if regs.cpu(1).sr().read().chf(channel as usize) {
+                if regs.cpu(1).sr().read().chf(self.index as usize) {
                     // If bit is set to 1 then interrupt is disabled; we want to disable the interrupt
-                    regs.cpu(0).mr().modify(|w| w.set_chfm(channel as usize, true));
+                    regs.cpu(0).mr().modify(|w| w.set_chfm(self.index as usize, true));
 
                     Poll::Ready(())
                 } else {
@@ -189,21 +169,111 @@ impl Ipcc {
             })
             .await;
 
-            trace!("ipcc: ch {}: read data", channel as u8);
+            trace!("ipcc: ch {}: read data", self.index as u8);
 
             match f() {
                 Some(ret) => return ret,
                 None => {}
             }
 
-            trace!("ipcc: ch {}: clear rx", channel as u8);
+            trace!("ipcc: ch {}: clear rx", self.index as u8);
             compiler_fence(Ordering::SeqCst);
             // If the channel is clear and the read function returns none, fetch more data
-            regs.cpu(0).scr().write(|w| w.set_chc(channel as usize, true));
+            regs.cpu(0).scr().write(|w| w.set_chc(self.index as usize, true));
         }
     }
 }
 
+/// IPCC Channel
+pub struct IpccChannel<'a> {
+    index: u8,
+    _lifetime: PhantomData<&'a mut usize>,
+}
+
+impl<'a> IpccChannel<'a> {
+    pub(crate) const fn new(number: u8) -> Self {
+        core::assert!(number > 0 && number <= 6);
+
+        Self {
+            index: number - 1,
+            _lifetime: PhantomData,
+        }
+    }
+
+    /// Split into a tx and rx channel
+    pub const fn split(self) -> (IpccTxChannel<'a>, IpccRxChannel<'a>) {
+        (IpccTxChannel::new(self.index), IpccRxChannel::new(self.index))
+    }
+}
+
+/// IPCC driver.
+pub struct Ipcc {
+    _private: (),
+}
+
+impl Ipcc {
+    /// Creates a new HardwareSemaphore instance.
+    pub fn new<'d>(
+        _peripheral: Peri<'d, crate::peripherals::IPCC>,
+        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
+        + interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>
+        + 'd,
+        _config: Config,
+    ) -> Self {
+        rcc::enable_and_reset::<IPCC>();
+        IPCC::set_cpu2(true);
+
+        let regs = IPCC::regs();
+
+        regs.cpu(0).cr().modify(|w| {
+            w.set_rxoie(true);
+            w.set_txfie(true);
+        });
+
+        // enable interrupts
+        crate::interrupt::typelevel::IPCC_C1_RX::unpend();
+        crate::interrupt::typelevel::IPCC_C1_TX::unpend();
+
+        unsafe { crate::interrupt::typelevel::IPCC_C1_RX::enable() };
+        unsafe { crate::interrupt::typelevel::IPCC_C1_TX::enable() };
+
+        Self { _private: () }
+    }
+
+    /// Split into a tx and rx channel
+    pub const fn split<'a>(self) -> [(IpccTxChannel<'a>, IpccRxChannel<'a>); 6] {
+        [
+            IpccChannel::new(1).split(),
+            IpccChannel::new(2).split(),
+            IpccChannel::new(3).split(),
+            IpccChannel::new(4).split(),
+            IpccChannel::new(5).split(),
+            IpccChannel::new(6).split(),
+        ]
+    }
+
+    /// Receive from a channel number
+    pub async unsafe fn receive<R>(number: u8, f: impl FnMut() -> Option<R>) -> R {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccRxChannel::new(number - 1).receive(f).await
+    }
+
+    /// Send to a channel number
+    pub async unsafe fn send(number: u8, f: impl FnOnce()) {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccTxChannel::new(number - 1).send(f).await
+    }
+
+    /// Send to a channel number
+    pub async unsafe fn flush(number: u8) {
+        core::assert!(number > 0 && number <= 6);
+
+        IpccTxChannel::new(number - 1).flush().await
+    }
+}
+
 impl SealedInstance for crate::peripherals::IPCC {
     fn regs() -> crate::pac::ipcc::Ipcc {
         crate::pac::IPCC
@@ -232,26 +302,12 @@ impl State {
         }
     }
 
-    const fn rx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
-        match channel {
-            IpccChannel::Channel1 => &self.rx_wakers[0],
-            IpccChannel::Channel2 => &self.rx_wakers[1],
-            IpccChannel::Channel3 => &self.rx_wakers[2],
-            IpccChannel::Channel4 => &self.rx_wakers[3],
-            IpccChannel::Channel5 => &self.rx_wakers[4],
-            IpccChannel::Channel6 => &self.rx_wakers[5],
-        }
+    const fn rx_waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.rx_wakers[index as usize]
     }
 
-    const fn tx_waker_for(&self, channel: IpccChannel) -> &AtomicWaker {
-        match channel {
-            IpccChannel::Channel1 => &self.tx_wakers[0],
-            IpccChannel::Channel2 => &self.tx_wakers[1],
-            IpccChannel::Channel3 => &self.tx_wakers[2],
-            IpccChannel::Channel4 => &self.tx_wakers[3],
-            IpccChannel::Channel5 => &self.tx_wakers[4],
-            IpccChannel::Channel6 => &self.tx_wakers[5],
-        }
+    const fn tx_waker_for(&self, index: u8) -> &AtomicWaker {
+        &self.tx_wakers[index as usize]
     }
 }
 
diff --git a/embassy-stm32/src/lcd.rs b/embassy-stm32/src/lcd.rs
new file mode 100644
index 000000000..ea29f1398
--- /dev/null
+++ b/embassy-stm32/src/lcd.rs
@@ -0,0 +1,510 @@
+//! LCD
+use core::marker::PhantomData;
+
+use embassy_hal_internal::{Peri, PeripheralType};
+
+use crate::gpio::{AfType, AnyPin, SealedPin};
+use crate::peripherals;
+use crate::rcc::{self, RccPeripheral};
+use crate::time::Hertz;
+
+#[cfg(any(stm32u0, stm32l073, stm32l083))]
+const NUM_SEGMENTS: u8 = 52;
+#[cfg(any(stm32wb, stm32l4x6, stm32l15x, stm32l162, stm32l4x3, stm32l4x6))]
+const NUM_SEGMENTS: u8 = 44;
+#[cfg(any(stm32l053, stm32l063, stm32l100))]
+const NUM_SEGMENTS: u8 = 32;
+
+/// LCD configuration struct
+#[non_exhaustive]
+#[derive(Debug, Clone, Copy)]
+pub struct Config {
+    #[cfg(lcd_v2)]
+    /// Enable the voltage output buffer for higher driving capability.
+    ///
+    /// The LCD driving capability is improved as buffers prevent the LCD capacitive loads from loading the resistor
+    /// bridge unacceptably and interfering with its voltage generation.
+    pub use_voltage_output_buffer: bool,
+    /// Enable SEG pin remapping. SEG[31:28] multiplexed with SEG[43:40]
+    pub use_segment_muxing: bool,
+    /// Bias selector
+    pub bias: Bias,
+    /// Duty selector
+    pub duty: Duty,
+    /// Internal or external voltage source
+    pub voltage_source: VoltageSource,
+    /// The frequency used to update the LCD with.
+    /// Should be between ~30 and ~100. Lower is better for power consumption, but has lower visual fidelity.
+    pub target_fps: Hertz,
+    /// LCD driver selector
+    pub drive: Drive,
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            #[cfg(lcd_v2)]
+            use_voltage_output_buffer: false,
+            use_segment_muxing: false,
+            bias: Default::default(),
+            duty: Default::default(),
+            voltage_source: Default::default(),
+            target_fps: Hertz(60),
+            drive: Drive::Medium,
+        }
+    }
+}
+
+/// The number of voltage levels used when driving an LCD.
+/// Your LCD datasheet should tell you what to use.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Bias {
+    /// 1/4 bias
+    #[default]
+    Quarter = 0b00,
+    /// 1/2 bias
+    Half = 0b01,
+    /// 1/3 bias
+    Third = 0b10,
+}
+
+/// The duty used by the LCD driver.
+///
+/// This is essentially how many COM pins you're using.
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum Duty {
+    #[default]
+    /// Use a single COM pin
+    Static = 0b000,
+    /// Use two COM pins
+    Half = 0b001,
+    /// Use three COM pins
+    Third = 0b010,
+    /// Use four COM pins
+    Quarter = 0b011,
+    /// Use eight COM pins.
+    ///
+    /// In this mode, `COM[7:4]` outputs are available on `SEG[51:48]`.
+    /// This allows reducing the number of available segments.
+    Eigth = 0b100,
+}
+
+impl Duty {
+    fn num_com_pins(&self) -> u8 {
+        match self {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        }
+    }
+}
+
+/// Whether to use the internal or external voltage source to drive the LCD
+#[repr(u8)]
+#[derive(Debug, Default, Clone, Copy)]
+pub enum VoltageSource {
+    #[default]
+    /// Voltage stepup converter
+    Internal,
+    /// VLCD pin
+    External,
+}
+
+/// Defines the pulse duration in terms of ck_ps pulses.
+///
+/// A short pulse leads to lower power consumption, but displays with high internal resistance
+/// may need a longer pulse to achieve satisfactory contrast.
+/// Note that the pulse is never longer than one half prescaled LCD clock period.
+///
+/// Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast.
+/// `PermanentHighDrive` is useful in this case if some additional power consumption can be tolerated.
+///
+/// Basically, for power usage, you want this as low as possible while still being able to use the LCD
+/// with a good enough contrast.
+#[repr(u8)]
+#[derive(Debug, Clone, Copy)]
+pub enum Drive {
+    /// Zero clock pulse on duration
+    Lowest = 0x00,
+    /// One clock pulse on duration
+    VeryLow = 0x01,
+    /// Two clock pulse on duration
+    Low = 0x02,
+    /// Three clock pulse on duration
+    Medium = 0x03,
+    /// Four clock pulse on duration
+    MediumHigh = 0x04,
+    /// Five clock pulse on duration
+    High = 0x05,
+    /// Six clock pulse on duration
+    VeryHigh = 0x06,
+    /// Seven clock pulse on duration
+    Highest = 0x07,
+    /// Enables the highdrive bit of the hardware
+    PermanentHighDrive = 0x09,
+}
+
+/// LCD driver.
+pub struct Lcd<'d, T: Instance> {
+    _peri: PhantomData<&'d mut T>,
+    duty: Duty,
+    ck_div: u32,
+}
+
+impl<'d, T: Instance> Lcd<'d, T> {
+    /// Initialize the lcd driver.
+    ///
+    /// The `pins` parameter must contain *all* segment and com pins that are connected to the LCD.
+    /// This is not further checked by this driver. Pins not routed to the LCD can be used for other purposes.
+    pub fn new<const N: usize>(
+        _peripheral: Peri<'d, T>,
+        config: Config,
+        vlcd_pin: Peri<'_, impl VlcdPin<T>>,
+        pins: [LcdPin<'d, T>; N],
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+
+        vlcd_pin.set_as_af(
+            vlcd_pin.af_num(),
+            AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+        );
+
+        assert_eq!(
+            pins.iter().filter(|pin| !pin.is_seg).count(),
+            config.duty.num_com_pins() as usize,
+            "The number of provided COM pins is not the same as the duty configures"
+        );
+
+        // Set the pins
+        for pin in pins {
+            pin.pin.set_as_af(
+                pin.af_num,
+                AfType::output(crate::gpio::OutputType::PushPull, crate::gpio::Speed::VeryHigh),
+            );
+        }
+
+        // Initialize the display ram to 0
+        for i in 0..8 {
+            T::regs().ram_com(i).low().write_value(0);
+            T::regs().ram_com(i).high().write_value(0);
+        }
+
+        // Calculate the clock dividers
+        let Some(lcd_clk) = (unsafe { rcc::get_freqs().rtc.to_hertz() }) else {
+            panic!("The LCD driver needs the RTC/LCD clock to be running");
+        };
+        let duty_divider = match config.duty {
+            Duty::Static => 1,
+            Duty::Half => 2,
+            Duty::Third => 3,
+            Duty::Quarter => 4,
+            Duty::Eigth => 8,
+        };
+        let target_clock = config.target_fps.0 * duty_divider;
+        let target_division = lcd_clk.0 / target_clock;
+
+        let mut ps = 0;
+        let mut div = 0;
+        let mut best_fps_match = u32::MAX;
+
+        for trial_div in 0..0xF {
+            let trial_ps = (target_division / (trial_div + 16))
+                .next_power_of_two()
+                .trailing_zeros();
+            let fps = lcd_clk.0 / ((1 << trial_ps) * (trial_div + 16)) / duty_divider;
+
+            if fps < config.target_fps.0 {
+                continue;
+            }
+
+            if fps < best_fps_match {
+                ps = trial_ps;
+                div = trial_div;
+                best_fps_match = fps;
+            }
+        }
+
+        let ck_div = lcd_clk.0 / ((1 << ps) * (div + 16));
+
+        trace!(
+            "lcd_clk: {}, fps: {}, ps: {}, div: {}, ck_div: {}",
+            lcd_clk, best_fps_match, ps, div, ck_div
+        );
+
+        if best_fps_match == u32::MAX || ps > 0xF {
+            panic!("Lcd clock error");
+        }
+
+        // Set the frame control
+        T::regs().fcr().modify(|w| {
+            w.set_ps(ps as u8);
+            w.set_div(div as u8);
+            w.set_cc(0b100); // Init in the middle-ish
+            w.set_dead(0b000);
+            w.set_pon(config.drive as u8 & 0x07);
+            w.set_hd((config.drive as u8 & !0x07) != 0);
+        });
+
+        // Wait for the frame control to synchronize
+        while !T::regs().sr().read().fcrsf() {}
+
+        // Set the control register values
+        T::regs().cr().modify(|w| {
+            #[cfg(lcd_v2)]
+            w.set_bufen(config.use_voltage_output_buffer);
+            w.set_mux_seg(config.use_segment_muxing);
+            w.set_bias(config.bias as u8);
+            w.set_duty(config.duty as u8);
+            w.set_vsel(matches!(config.voltage_source, VoltageSource::External));
+        });
+
+        // Enable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(true));
+
+        // Wait for the lcd to be enabled
+        while !T::regs().sr().read().ens() {}
+
+        // Wait for the stepup converter to be ready
+        while !T::regs().sr().read().rdy() {}
+
+        Self {
+            _peri: PhantomData,
+            duty: config.duty,
+            ck_div,
+        }
+    }
+
+    /// Change the contrast by changing the voltage being used.
+    ///
+    /// This is from low at 0 to high at 7.
+    pub fn set_contrast_control(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs().fcr().modify(|w| w.set_cc(value));
+    }
+
+    /// Change the contrast by introducing a deadtime to the signals
+    /// where the voltages are held at 0V.
+    ///
+    /// This is from no dead time at 0 to high dead time at 7.
+    pub fn set_dead_time(&mut self, value: u8) {
+        assert!((0..=7).contains(&value));
+        T::regs()
+            .fcr()
+            .modify(|w: &mut stm32_metapac::lcd::regs::Fcr| w.set_dead(value));
+    }
+
+    /// Write data into the display RAM. This overwrites the data already in it for the specified com index.
+    ///
+    /// The `com_index` value determines which part of the RAM is written to.
+    /// The `segments` value is a bitmap where each bit represents whether a pixel is turned on or off.
+    ///
+    /// This function waits last update request to be finished, but does not submit the buffer to the LCD with a new request.
+    /// Submission has to be done manually using [Self::submit_frame].
+    pub fn write_com_segments(&mut self, com_index: u8, segments: u64) {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        assert!(
+            segments.leading_zeros() >= 64 - self.num_segments() as u32,
+            "Invalid segment pixel set",
+        );
+
+        T::regs()
+            .ram_com(com_index as usize)
+            .low()
+            .write_value((segments & 0xFFFF_FFFF) as u32);
+        T::regs()
+            .ram_com(com_index as usize)
+            .high()
+            .write_value(((segments >> 32) & 0xFFFF_FFFF) as u32);
+    }
+
+    /// Read the data from the display RAM.
+    ///
+    /// The `com_index` value determines which part of the RAM is read from.
+    ///
+    /// This function waits for the last update request to be finished.
+    pub fn read_com_segments(&self, com_index: u8) -> u64 {
+        while T::regs().sr().read().udr() {}
+
+        assert!(
+            com_index < self.duty.num_com_pins(),
+            "Com index cannot be higher than number of configured com pins (through the Duty setting in the config)"
+        );
+
+        let low = T::regs().ram_com(com_index as usize).low().read();
+        let high = T::regs().ram_com(com_index as usize).high().read();
+
+        ((high as u64) << 32) | low as u64
+    }
+
+    /// Submit the current RAM data to the LCD.
+    ///
+    /// This function waits until the RAM is writable, but does not wait for the frame to be drawn.
+    pub fn submit_frame(&mut self) {
+        while T::regs().sr().read().udr() {}
+        // Clear the update done flag
+        T::regs().sr().write(|w| w.set_udd(true));
+        // Set the update request flag
+        T::regs().sr().write(|w| w.set_udr(true));
+    }
+
+    /// Get the number of segments that are supported on this LCD
+    pub fn num_segments(&self) -> u8 {
+        match self.duty {
+            Duty::Eigth => NUM_SEGMENTS - 4, // With 8 coms, 4 of the segment pins turn into com pins
+            _ => NUM_SEGMENTS,
+        }
+    }
+
+    /// Get the pixel mask for the current LCD setup.
+    /// This is a mask of all bits that are allowed to be set in the [Self::write_com_segments] function.
+    pub fn segment_pixel_mask(&self) -> u64 {
+        (1 << self.num_segments()) - 1
+    }
+
+    /// Get the number of COM pins that were configured through the Drive config
+    pub fn num_com_pins(&self) -> u8 {
+        self.duty.num_com_pins()
+    }
+
+    /// Set the blink behavior on some pixels.
+    ///
+    /// The blink frequency is an approximation. It's divided from the clock selected by the FPS.
+    /// Play with the FPS value if you want the blink frequency to be more accurate.
+    ///
+    /// If a blink frequency cannot be attained, this function will panic.
+    pub fn set_blink(&mut self, selector: BlinkSelector, freq: BlinkFreq) {
+        // Freq * 100 to be able to do integer math
+        let scaled_blink_freq = match freq {
+            BlinkFreq::Hz0_25 => 25,
+            BlinkFreq::Hz0_5 => 50,
+            BlinkFreq::Hz1 => 100,
+            BlinkFreq::Hz2 => 200,
+            BlinkFreq::Hz4 => 400,
+        };
+
+        let desired_divider = self.ck_div * 100 / scaled_blink_freq;
+        let target_divider = desired_divider.next_power_of_two();
+        let power_divisions = target_divider.trailing_zeros();
+
+        trace!(
+            "Setting LCD blink frequency -> desired_divider: {}, target_divider: {}",
+            desired_divider, target_divider
+        );
+
+        assert!(
+            (8..=1024).contains(&target_divider),
+            "LCD blink frequency cannot be attained"
+        );
+
+        T::regs().fcr().modify(|reg| {
+            reg.set_blinkf((power_divisions - 3) as u8);
+            reg.set_blink(selector as u8);
+        })
+    }
+}
+
+impl<'d, T: Instance> Drop for Lcd<'d, T> {
+    fn drop(&mut self) {
+        // Disable the lcd
+        T::regs().cr().modify(|w| w.set_lcden(false));
+        rcc::disable::<T>();
+    }
+}
+
+/// Blink frequency
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum BlinkFreq {
+    /// 0.25 hz
+    Hz0_25,
+    /// 0.5 hz
+    Hz0_5,
+    /// 1 hz
+    Hz1,
+    /// 2 hz
+    Hz2,
+    /// 4 hz
+    Hz4,
+}
+
+/// Blink pixel selector
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+#[repr(u8)]
+pub enum BlinkSelector {
+    /// No pixels blink
+    None = 0b00,
+    /// The SEG0, COM0 pixel blinks if the pixel is set
+    Seg0Com0 = 0b01,
+    /// The SEG0 pixel of all COMs blinks if the pixel is set
+    Seg0ComAll = 0b10,
+    /// All pixels blink if the pixel is set
+    All = 0b11,
+}
+
+/// A type-erased pin that can be configured as an LCD pin.
+/// This is used for passing pins to the new function in the array.
+pub struct LcdPin<'d, T: Instance> {
+    pin: Peri<'d, AnyPin>,
+    af_num: u8,
+    is_seg: bool,
+    _phantom: PhantomData<T>,
+}
+
+impl<'d, T: Instance> LcdPin<'d, T> {
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_seg(pin: Peri<'d, impl SegPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: true,
+            _phantom: PhantomData,
+        }
+    }
+
+    /// Construct an LCD pin from any pin that supports it
+    pub fn new_com(pin: Peri<'d, impl ComPin<T>>) -> Self {
+        let af = pin.af_num();
+
+        Self {
+            pin: pin.into(),
+            af_num: af,
+            is_seg: false,
+            _phantom: PhantomData,
+        }
+    }
+}
+
+trait SealedInstance: crate::rcc::SealedRccPeripheral + PeripheralType {
+    fn regs() -> crate::pac::lcd::Lcd;
+}
+
+/// DSI instance trait.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+
+pin_trait!(SegPin, Instance);
+pin_trait!(ComPin, Instance);
+pin_trait!(VlcdPin, Instance);
+
+foreach_peripheral!(
+    (lcd, $inst:ident) => {
+        impl crate::lcd::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::lcd::Lcd {
+                crate::pac::$inst
+            }
+        }
+
+        impl crate::lcd::Instance for peripherals::$inst {}
+    };
+);
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 7e0f7884e..2f783bf64 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -1,5 +1,6 @@
 #![cfg_attr(not(test), no_std)]
 #![allow(async_fn_in_trait)]
+#![allow(unsafe_op_in_unsafe_fn)]
 #![cfg_attr(
     docsrs,
     doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-stm32'>browse the `embassy-stm32` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (stm32h7, stm32h7rs55 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
@@ -53,6 +54,8 @@ pub mod timer;
 
 #[cfg(adc)]
 pub mod adc;
+#[cfg(backup_sram)]
+pub mod backup_sram;
 #[cfg(can)]
 pub mod can;
 // FIXME: Cordic driver cause stm32u5a5zj crash
@@ -74,6 +77,7 @@ pub mod dts;
 pub mod eth;
 #[cfg(feature = "exti")]
 pub mod exti;
+#[cfg(flash)]
 pub mod flash;
 #[cfg(fmc)]
 pub mod fmc;
@@ -91,6 +95,8 @@ pub mod i2c;
 pub mod i2s;
 #[cfg(stm32wb)]
 pub mod ipcc;
+#[cfg(lcd)]
+pub mod lcd;
 #[cfg(feature = "low-power")]
 pub mod low_power;
 #[cfg(lptim)]
@@ -147,7 +153,7 @@ pub use crate::_generated::interrupt;
 /// Macro to bind interrupts to handlers.
 ///
 /// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
-/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
+/// and implements the right [`Binding`](crate::interrupt::typelevel::Binding)s for it. You can pass this struct to drivers to
 /// prove at compile-time that the right interrupts have been bound.
 ///
 /// Example of how to bind one interrupt:
@@ -174,7 +180,10 @@ pub use crate::_generated::interrupt;
 ///     }
 /// );
 /// ```
-
+///
+/// Some chips collate multiple interrupt signals into a single interrupt vector. In the above example, I2C2_3 is a
+/// single vector which is activated by events and errors on both peripherals I2C2 and I2C3. Check your chip's list
+/// of interrupt vectors if you get an unexpected compile error trying to bind the standard name.
 // developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
 #[macro_export]
 macro_rules! bind_interrupts {
@@ -194,7 +203,7 @@ macro_rules! bind_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             $(#[cfg($cond_irq)])?
             $(#[doc = $doc])*
             unsafe extern "C" fn $irq() {
@@ -222,7 +231,7 @@ macro_rules! bind_interrupts {
 }
 
 // Reexports
-pub use _generated::{peripherals, Peripherals};
+pub use _generated::{Peripherals, peripherals};
 pub use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(feature = "unstable-pac")]
 pub use stm32_metapac as pac;
@@ -240,6 +249,14 @@ pub struct Config {
     /// RCC config.
     pub rcc: rcc::Config,
 
+    #[cfg(feature = "low-power")]
+    /// RTC config
+    pub rtc: rtc::RtcConfig,
+
+    #[cfg(feature = "low-power")]
+    /// Minimum time to stop
+    pub min_stop_pause: embassy_time::Duration,
+
     /// Enable debug during sleep and stop.
     ///
     /// May increase power consumption. Defaults to true.
@@ -293,6 +310,10 @@ impl Default for Config {
     fn default() -> Self {
         Self {
             rcc: Default::default(),
+            #[cfg(feature = "low-power")]
+            rtc: Default::default(),
+            #[cfg(feature = "low-power")]
+            min_stop_pause: embassy_time::Duration::from_millis(250),
             #[cfg(dbgmcu)]
             enable_debug_during_sleep: true,
             #[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba))]
@@ -495,6 +516,16 @@ fn init_hw(config: Config) -> Peripherals {
     critical_section::with(|cs| {
         let p = Peripherals::take_with_cs(cs);
 
+        #[cfg(dbgmcu_n6)]
+        {
+            crate::pac::RCC.miscensr().write(|w| w.set_dbgens(true));
+            crate::pac::RCC.miscenr().read(); // volatile read
+            crate::pac::DBGMCU
+                .cr()
+                .modify(|w| w.set_dbgclken(stm32_metapac::dbgmcu::vals::Dbgclken::B_0X1));
+            crate::pac::DBGMCU.cr().read();
+        }
+
         #[cfg(dbgmcu)]
         crate::pac::DBGMCU.cr().modify(|cr| {
             #[cfg(dbgmcu_h5)]
@@ -509,7 +540,7 @@ fn init_hw(config: Config) -> Peripherals {
             }
             #[cfg(any(
                 dbgmcu_f1, dbgmcu_f2, dbgmcu_f3, dbgmcu_f4, dbgmcu_f7, dbgmcu_g4, dbgmcu_f7, dbgmcu_l0, dbgmcu_l1,
-                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl
+                dbgmcu_l4, dbgmcu_wb, dbgmcu_wl, dbgmcu_n6
             ))]
             {
                 cr.set_dbg_sleep(config.enable_debug_during_sleep);
@@ -530,7 +561,7 @@ fn init_hw(config: Config) -> Peripherals {
         rcc::enable_and_reset_with_cs::<peripherals::SYSCFG>(cs);
         #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
         rcc::enable_and_reset_with_cs::<peripherals::PWR>(cs);
-        #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs)))]
+        #[cfg(all(flash, not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs))))]
         rcc::enable_and_reset_with_cs::<peripherals::FLASH>(cs);
 
         // Enable the VDDIO2 power supply on chips that have it.
@@ -590,7 +621,7 @@ fn init_hw(config: Config) -> Peripherals {
             #[cfg(ucpd)]
             ucpd::init(
                 cs,
-                #[cfg(peri_ucpd1)]
+                #[cfg(all(peri_ucpd1, not(stm32n6)))]
                 config.enable_ucpd1_dead_battery,
                 #[cfg(peri_ucpd2)]
                 config.enable_ucpd2_dead_battery,
@@ -622,8 +653,28 @@ fn init_hw(config: Config) -> Peripherals {
             exti::init(cs);
 
             rcc::init_rcc(cs, config.rcc);
+
+            #[cfg(feature = "low-power")]
+            rtc::init_rtc(cs, config.rtc, config.min_stop_pause);
+
+            #[cfg(all(stm32wb, feature = "low-power"))]
+            hsem::init_hsem(cs);
         }
 
         p
     })
 }
+
+/// Performs a busy-wait delay for a specified number of microseconds.
+#[allow(unused)]
+pub(crate) fn block_for_us(us: u64) {
+    cfg_if::cfg_if! {
+        // this does strange things on stm32wlx in low power mode depending on exactly when it's called
+        // as in sometimes 15 us (1 tick) would take > 20 seconds.
+        if #[cfg(all(feature = "time", all(not(feature = "low-power"), not(stm32wlex))))] {
+            embassy_time::block_for(embassy_time::Duration::from_micros(us));
+        } else {
+            cortex_m::asm::delay(unsafe { rcc::get_freqs().sys.to_hertz().unwrap().0 as u64 * us  / 1_000_000 } as u32);
+        }
+    }
+}
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 342f73bc8..bd8290da0 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -14,7 +14,7 @@
 //!
 //! Since entering and leaving low-power modes typically incurs a significant latency, the
 //! low-power executor will only attempt to enter when the next timer event is at least
-//! [`time_driver::MIN_STOP_PAUSE`] in the future.
+//! [`time_driver::min_stop_pause`] in the future.
 //!
 //! Currently there is no macro analogous to `embassy_executor::main` for this executor;
 //! consequently one must define their entrypoint manually. Moreover, you must relinquish control
@@ -22,53 +22,73 @@
 //!
 //! ```rust,no_run
 //! use embassy_executor::Spawner;
-//! use embassy_stm32::low_power::Executor;
+//! use embassy_stm32::low_power;
 //! use embassy_stm32::rtc::{Rtc, RtcConfig};
-//! use static_cell::StaticCell;
+//! use embassy_time::Duration;
 //!
-//! #[cortex_m_rt::entry]
-//! fn main() -> ! {
-//!     Executor::take().run(|spawner| {
-//!         spawner.spawn(unwrap!(async_main(spawner)));
-//!     });
-//! }
-//!
-//! #[embassy_executor::task]
+//! #[embassy_executor::main(executor = "low_power::Executor")]
 //! async fn async_main(spawner: Spawner) {
 //!     // initialize the platform...
 //!     let mut config = embassy_stm32::Config::default();
+//!     // the default value, but can be adjusted
+//!     config.min_stop_pause = Duration::from_millis(250);
 //!     // when enabled the power-consumption is much higher during stop, but debugging and RTT is working
 //!     config.enable_debug_during_sleep = false;
 //!     let p = embassy_stm32::init(config);
 //!
-//!     // give the RTC to the executor...
-//!     let mut rtc = Rtc::new(p.RTC, RtcConfig::default());
-//!     static RTC: StaticCell<Rtc> = StaticCell::new();
-//!     let rtc = RTC.init(rtc);
-//!     embassy_stm32::low_power::stop_with_rtc(rtc);
-//!
 //!     // your application here...
 //! }
 //! ```
 
-// TODO: Usage of `static mut` here is unsound. Fix then remove this `allow`.`
-#![allow(static_mut_refs)]
-
 use core::arch::asm;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::mem;
+use core::sync::atomic::{Ordering, compiler_fence};
 
 use cortex_m::peripheral::SCB;
+use critical_section::CriticalSection;
 use embassy_executor::*;
 
 use crate::interrupt;
-use crate::time_driver::{get_driver, RtcDriver};
+pub use crate::rcc::StopMode;
+use crate::rcc::{RCC_CONFIG, REFCOUNT_STOP1, REFCOUNT_STOP2, decrement_stop_refcount, increment_stop_refcount};
+use crate::time_driver::get_driver;
 
 const THREAD_PENDER: usize = usize::MAX;
 
-use crate::rtc::Rtc;
+static mut EXECUTOR_TAKEN: bool = false;
+
+/// Prevent the device from going into the stop mode if held
+pub struct DeviceBusy(StopMode);
+
+impl DeviceBusy {
+    /// Create a new DeviceBusy with stop1.
+    pub fn new_stop1() -> Self {
+        Self::new(StopMode::Stop1)
+    }
+
+    /// Create a new DeviceBusy with stop2.
+    pub fn new_stop2() -> Self {
+        Self::new(StopMode::Stop2)
+    }
 
-static mut EXECUTOR: Option<Executor> = None;
+    /// Create a new DeviceBusy.
+    pub fn new(stop_mode: StopMode) -> Self {
+        critical_section::with(|cs| {
+            increment_stop_refcount(cs, stop_mode);
+        });
+
+        Self(stop_mode)
+    }
+}
+
+impl Drop for DeviceBusy {
+    fn drop(&mut self) {
+        critical_section::with(|cs| {
+            decrement_stop_refcount(cs, self.0);
+        });
+    }
+}
 
 #[cfg(not(stm32u0))]
 foreach_interrupt! {
@@ -76,7 +96,7 @@ foreach_interrupt! {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+            Executor::on_wakeup_irq();
         }
     };
 }
@@ -87,55 +107,35 @@ foreach_interrupt! {
         #[interrupt]
         #[allow(non_snake_case)]
         unsafe fn $irq() {
-            EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+            Executor::on_wakeup_irq();
         }
     };
 }
 
-#[allow(dead_code)]
-pub(crate) unsafe fn on_wakeup_irq() {
-    EXECUTOR.as_mut().unwrap().on_wakeup_irq();
-}
-
-/// Configure STOP mode with RTC.
-pub fn stop_with_rtc(rtc: &'static Rtc) {
-    unsafe { EXECUTOR.as_mut().unwrap() }.stop_with_rtc(rtc)
-}
-
 /// Get whether the core is ready to enter the given stop mode.
 ///
 /// This will return false if some peripheral driver is in use that
 /// prevents entering the given stop mode.
 pub fn stop_ready(stop_mode: StopMode) -> bool {
-    match unsafe { EXECUTOR.as_mut().unwrap() }.stop_mode() {
-        Some(StopMode::Stop2) => true,
+    critical_section::with(|cs| match Executor::stop_mode(cs) {
+        Some(StopMode::Standby | StopMode::Stop2) => true,
         Some(StopMode::Stop1) => stop_mode == StopMode::Stop1,
         None => false,
-    }
-}
-
-/// Available Stop modes.
-#[non_exhaustive]
-#[derive(PartialEq)]
-pub enum StopMode {
-    /// STOP 1
-    Stop1,
-    /// STOP 2
-    Stop2,
+    })
 }
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
-use stm32_metapac::pwr::vals::Lpms;
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wb, stm32wlex, stm32u0))]
+use crate::pac::pwr::vals::Lpms;
 
-#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32u0))]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32wba, stm32wb, stm32wlex, stm32u0))]
 impl Into<Lpms> for StopMode {
     fn into(self) -> Lpms {
         match self {
             StopMode::Stop1 => Lpms::STOP1,
-            #[cfg(not(stm32wba))]
-            StopMode::Stop2 => Lpms::STOP2,
-            #[cfg(stm32wba)]
-            StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
+            #[cfg(not(any(stm32wb, stm32wba)))]
+            StopMode::Standby | StopMode::Stop2 => Lpms::STOP2,
+            #[cfg(any(stm32wb, stm32wba))]
+            StopMode::Standby | StopMode::Stop2 => Lpms::STOP1, // TODO: WBA has no STOP2?
         }
     }
 }
@@ -153,55 +153,139 @@ impl Into<Lpms> for StopMode {
 pub struct Executor {
     inner: raw::Executor,
     not_send: PhantomData<*mut ()>,
-    scb: SCB,
-    time_driver: &'static RtcDriver,
 }
 
 impl Executor {
     /// Create a new Executor.
-    pub fn take() -> &'static mut Self {
-        critical_section::with(|_| unsafe {
-            assert!(EXECUTOR.is_none());
-
-            EXECUTOR = Some(Self {
-                inner: raw::Executor::new(THREAD_PENDER as *mut ()),
-                not_send: PhantomData,
-                scb: cortex_m::Peripherals::steal().SCB,
-                time_driver: get_driver(),
-            });
-
-            let executor = EXECUTOR.as_mut().unwrap();
+    pub fn new() -> Self {
+        unsafe {
+            if EXECUTOR_TAKEN {
+                panic!("Low power executor can only be taken once.");
+            } else {
+                EXECUTOR_TAKEN = true;
+            }
+        }
 
-            executor
-        })
+        Self {
+            inner: raw::Executor::new(THREAD_PENDER as *mut ()),
+            not_send: PhantomData,
+        }
     }
 
-    unsafe fn on_wakeup_irq(&mut self) {
-        self.time_driver.resume_time();
-        trace!("low power: resume");
+    pub(crate) unsafe fn on_wakeup_irq() {
+        critical_section::with(|cs| {
+            #[cfg(stm32wlex)]
+            {
+                use crate::pac::rcc::vals::Sw;
+                use crate::pac::{PWR, RCC};
+                use crate::rcc::init as init_rcc;
+
+                let extscr = PWR.extscr().read();
+                if extscr.c1stop2f() || extscr.c1stopf() {
+                    // when we wake from any stop mode we need to re-initialize the rcc
+                    while RCC.cfgr().read().sws() != Sw::MSI {}
+
+                    init_rcc(RCC_CONFIG.unwrap());
+
+                    if extscr.c1stop2f() {
+                        // when we wake from STOP2, we need to re-initialize the time driver
+                        get_driver().init_timer(cs);
+                        // reset the refcounts for STOP2 and STOP1 (initializing the time driver will increment one of them for the timer)
+                        // and given that we just woke from STOP2, we can reset them
+                        REFCOUNT_STOP2 = 0;
+                        REFCOUNT_STOP1 = 0;
+                    }
+                }
+            }
+            get_driver().resume_time(cs);
+            trace!("low power: resume");
+        });
     }
 
-    pub(self) fn stop_with_rtc(&mut self, rtc: &'static Rtc) {
-        self.time_driver.set_rtc(rtc);
-
-        rtc.enable_wakeup_line();
-
-        trace!("low power: stop with rtc configured");
+    const fn get_scb() -> SCB {
+        unsafe { mem::transmute(()) }
     }
 
-    fn stop_mode(&self) -> Option<StopMode> {
-        if unsafe { crate::rcc::REFCOUNT_STOP2 == 0 } && unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+    fn stop_mode(_cs: CriticalSection) -> Option<StopMode> {
+        // We cannot enter standby because we will lose program state.
+        if unsafe { REFCOUNT_STOP2 == 0 && REFCOUNT_STOP1 == 0 } {
+            trace!("low power: stop 2");
             Some(StopMode::Stop2)
-        } else if unsafe { crate::rcc::REFCOUNT_STOP1 == 0 } {
+        } else if unsafe { REFCOUNT_STOP1 == 0 } {
+            trace!("low power: stop 1");
             Some(StopMode::Stop1)
         } else {
+            trace!("low power: not ready to stop (refcount_stop1: {})", unsafe {
+                REFCOUNT_STOP1
+            });
             None
         }
     }
 
+    #[cfg(all(stm32wb, feature = "low-power"))]
+    fn configure_stop_stm32wb(&self, _cs: CriticalSection) -> Result<(), ()> {
+        use core::task::Poll;
+
+        use embassy_futures::poll_once;
+
+        use crate::hsem::HardwareSemaphoreChannel;
+        use crate::pac::rcc::vals::{Smps, Sw};
+        use crate::pac::{PWR, RCC};
+
+        trace!("low power: trying to get sem3");
+
+        let sem3_mutex = match poll_once(HardwareSemaphoreChannel::<crate::peripherals::HSEM>::new(3).lock(0)) {
+            Poll::Pending => None,
+            Poll::Ready(mutex) => Some(mutex),
+        }
+        .ok_or(())?;
+
+        trace!("low power: got sem3");
+
+        let sem4_mutex = HardwareSemaphoreChannel::<crate::peripherals::HSEM>::new(4).try_lock(0);
+        if let Some(sem4_mutex) = sem4_mutex {
+            trace!("low power: got sem4");
+
+            if PWR.extscr().read().c2ds() {
+                drop(sem4_mutex);
+            } else {
+                return Ok(());
+            }
+        }
+
+        // Sem4 not granted
+        // Set HSION
+        RCC.cr().modify(|w| {
+            w.set_hsion(true);
+        });
+
+        // Wait for HSIRDY
+        while !RCC.cr().read().hsirdy() {}
+
+        // Set SW to HSI
+        RCC.cfgr().modify(|w| {
+            w.set_sw(Sw::HSI);
+        });
+
+        // Wait for SWS to report HSI
+        while !RCC.cfgr().read().sws().eq(&Sw::HSI) {}
+
+        // Set SMPSSEL to HSI
+        RCC.smpscr().modify(|w| {
+            w.set_smpssel(Smps::HSI);
+        });
+
+        drop(sem3_mutex);
+
+        Ok(())
+    }
+
     #[allow(unused_variables)]
-    fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wba))]
+    fn configure_stop(&self, _cs: CriticalSection, stop_mode: StopMode) -> Result<(), ()> {
+        #[cfg(all(stm32wb, feature = "low-power"))]
+        self.configure_stop_stm32wb(_cs)?;
+
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0, stm32wb, stm32wba, stm32wlex))]
         crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
         #[cfg(stm32h5)]
         crate::pac::PWR.pmcr().modify(|v| {
@@ -209,34 +293,32 @@ impl Executor {
             v.set_lpms(vals::Lpms::STOP);
             v.set_svos(vals::Svos::SCALE3);
         });
+
+        Ok(())
     }
 
-    fn configure_pwr(&mut self) {
-        self.scb.clear_sleepdeep();
+    fn configure_pwr(&self) {
+        Self::get_scb().clear_sleepdeep();
+        // Clear any previous stop flags
+        #[cfg(stm32wlex)]
+        crate::pac::PWR.extscr().modify(|w| {
+            w.set_c1cssf(true);
+        });
 
         compiler_fence(Ordering::SeqCst);
 
-        let stop_mode = self.stop_mode();
+        critical_section::with(|cs| {
+            let _ = unsafe { RCC_CONFIG }?;
+            let stop_mode = Self::stop_mode(cs)?;
+            get_driver().pause_time(cs).ok()?;
+            self.configure_stop(cs, stop_mode).ok()?;
 
-        if stop_mode.is_none() {
-            trace!("low power: not ready to stop");
-            return;
-        }
-
-        if self.time_driver.pause_time().is_err() {
-            trace!("low power: failed to pause time");
-            return;
-        }
-
-        let stop_mode = stop_mode.unwrap();
-        match stop_mode {
-            StopMode::Stop1 => trace!("low power: stop 1"),
-            StopMode::Stop2 => trace!("low power: stop 2"),
-        }
-        self.configure_stop(stop_mode);
-
-        #[cfg(not(feature = "low-power-debug-with-sleep"))]
-        self.scb.set_sleepdeep();
+            Some(())
+        })
+        .map(|_| {
+            #[cfg(not(feature = "low-power-debug-with-sleep"))]
+            Self::get_scb().set_sleepdeep();
+        });
     }
 
     /// Run the executor.
@@ -258,14 +340,26 @@ impl Executor {
     ///
     /// This function never returns.
     pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
-        let executor = unsafe { EXECUTOR.as_mut().unwrap() };
-        init(executor.inner.spawner());
+        init(self.inner.spawner());
 
         loop {
             unsafe {
-                executor.inner.poll();
+                self.inner.poll();
                 self.configure_pwr();
                 asm!("wfe");
+                #[cfg(stm32wlex)]
+                {
+                    let es = crate::pac::PWR.extscr().read();
+                    match (es.c1stopf(), es.c1stop2f()) {
+                        (true, false) => debug!("low power: wake from STOP1"),
+                        (false, true) => debug!("low power: wake from STOP2"),
+                        (true, true) => debug!("low power: wake from STOP1 and STOP2 ???"),
+                        (false, false) => trace!("low power: stop mode not entered"),
+                    };
+                    crate::pac::PWR.extscr().modify(|w| {
+                        w.set_c1cssf(false);
+                    });
+                }
             };
         }
     }
diff --git a/embassy-stm32/src/lptim/pwm.rs b/embassy-stm32/src/lptim/pwm.rs
index 96af9f4d9..a69db3caf 100644
--- a/embassy-stm32/src/lptim/pwm.rs
+++ b/embassy-stm32/src/lptim/pwm.rs
@@ -4,12 +4,12 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::Peri;
 
-use super::timer::Timer;
 #[cfg(not(any(lptim_v2a, lptim_v2b)))]
 use super::OutputPin;
-#[cfg(any(lptim_v2a, lptim_v2b))]
-use super::{channel::Channel, timer::ChannelDirection, Channel1Pin, Channel2Pin};
+use super::timer::Timer;
 use super::{BasicInstance, Instance};
+#[cfg(any(lptim_v2a, lptim_v2b))]
+use super::{Channel1Pin, Channel2Pin, channel::Channel, timer::ChannelDirection};
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
diff --git a/embassy-stm32/src/ltdc.rs b/embassy-stm32/src/ltdc.rs
index 0f6ef569c..de2db9872 100644
--- a/embassy-stm32/src/ltdc.rs
+++ b/embassy-stm32/src/ltdc.rs
@@ -14,7 +14,7 @@ use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
-use crate::{peripherals, rcc, Peri};
+use crate::{Peri, peripherals, rcc};
 
 static LTDC_WAKER: AtomicWaker = AtomicWaker::new();
 
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index e36719ef3..4a55f5bd3 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -3,19 +3,12 @@
 
 use embassy_hal_internal::PeripheralType;
 
+use crate::Peri;
+#[cfg(opamp_v5)]
+use crate::block_for_us;
 use crate::pac::opamp::vals::*;
 #[cfg(not(any(stm32g4, stm32f3)))]
 use crate::rcc::RccInfo;
-use crate::Peri;
-
-/// Performs a busy-wait delay for a specified number of microseconds.
-#[cfg(opamp_v5)]
-fn blocking_delay_ms(ms: u32) {
-    #[cfg(feature = "time")]
-    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
-    #[cfg(not(feature = "time"))]
-    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
-}
 
 /// Gain
 #[allow(missing_docs)]
@@ -439,7 +432,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
 
             // The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize
             // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
-            blocking_delay_ms(2);
+            block_for_us(2_000);
 
             if !T::regs().csr().read().calout() {
                 if mid == 0 {
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index dbcf07469..2d5dbd95a 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -12,14 +12,14 @@ use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 use stm32_metapac::octospi::vals::{PhaseMode, SizeInBits};
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::octospi::{vals, Octospi as Regs};
+use crate::pac::octospi::{Octospi as Regs, vals};
 #[cfg(octospim_v1)]
 use crate::pac::octospim::Octospim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// OPSI driver config.
 #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index b03cd9009..bb4f4f1d0 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -14,7 +14,7 @@ use crate::gpio::{AfType, AnyPin, OutputType, Pull, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::quadspi::Quadspi as Regs;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// QSPI transfer configuration.
 #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 63fc195dd..219be208f 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -1,6 +1,10 @@
-use core::sync::atomic::{compiler_fence, Ordering};
+#[cfg(not(stm32n6))]
+use core::sync::atomic::{Ordering, compiler_fence};
 
-use crate::pac::common::{Reg, RW};
+#[cfg(not(stm32n6))]
+use crate::pac::common::{RW, Reg};
+#[cfg(backup_sram)]
+use crate::pac::pwr::vals::Retention;
 pub use crate::pac::rcc::vals::Rtcsel as RtcClockSource;
 use crate::time::Hertz;
 
@@ -52,7 +56,7 @@ impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
     }
 }
 
-#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0)))]
+#[cfg(not(any(rtc_v2_l0, rtc_v2_l1, stm32c0, stm32n6)))]
 type Bdcr = crate::pac::rcc::regs::Bdcr;
 #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
 type Bdcr = crate::pac::rcc::regs::Csr;
@@ -62,19 +66,22 @@ type Bdcr = crate::pac::rcc::regs::Csr1;
 #[cfg(any(stm32c0))]
 fn unlock() {}
 
-#[cfg(not(any(stm32c0)))]
+#[cfg(not(any(stm32c0, stm32n6)))]
 fn unlock() {
     #[cfg(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1))]
     let cr = crate::pac::PWR.cr();
-    #[cfg(not(any(stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba)))]
+    #[cfg(not(any(
+        stm32f0, stm32f1, stm32f2, stm32f3, stm32l0, stm32l1, stm32u5, stm32h5, stm32wba, stm32n6
+    )))]
     let cr = crate::pac::PWR.cr1();
-    #[cfg(any(stm32u5, stm32h5, stm32wba))]
+    #[cfg(any(stm32u5, stm32h5, stm32wba, stm32n6))]
     let cr = crate::pac::PWR.dbpcr();
 
     cr.modify(|w| w.set_dbp(true));
     while !cr.read().dbp() {}
 }
 
+#[cfg(not(stm32n6))]
 fn bdcr() -> Reg<Bdcr, RW> {
     #[cfg(any(rtc_v2_l0, rtc_v2_l1))]
     return crate::pac::RCC.csr();
@@ -89,6 +96,8 @@ pub struct LsConfig {
     pub rtc: RtcClockSource,
     pub lsi: bool,
     pub lse: Option<LseConfig>,
+    #[cfg(backup_sram)]
+    pub enable_backup_sram: bool,
 }
 
 impl LsConfig {
@@ -113,6 +122,8 @@ impl LsConfig {
                 peripherals_clocked: false,
             }),
             lsi: false,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -121,6 +132,8 @@ impl LsConfig {
             rtc: RtcClockSource::LSI,
             lsi: true,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 
@@ -129,6 +142,8 @@ impl LsConfig {
             rtc: RtcClockSource::DISABLE,
             lsi: false,
             lse: None,
+            #[cfg(backup_sram)]
+            enable_backup_sram: false,
         }
     }
 }
@@ -140,6 +155,7 @@ impl Default for LsConfig {
 }
 
 impl LsConfig {
+    #[cfg(not(stm32n6))]
     pub(crate) fn init(&self) -> Option<Hertz> {
         let rtc_clk = match self.rtc {
             RtcClockSource::LSI => {
@@ -175,14 +191,19 @@ impl LsConfig {
         if self.lsi {
             #[cfg(any(stm32u5, stm32h5, stm32wba))]
             let csr = crate::pac::RCC.bdcr();
-            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0)))]
+            #[cfg(stm32n6)]
+            let csr = crate::pac::RCC.sr();
+            #[cfg(not(any(stm32u5, stm32h5, stm32wba, stm32c0, stm32n6)))]
             let csr = crate::pac::RCC.csr();
-            #[cfg(any(stm32c0))]
+            #[cfg(stm32c0)]
             let csr = crate::pac::RCC.csr2();
 
-            #[cfg(not(any(rcc_wb, rcc_wba)))]
+            #[cfg(not(any(rcc_wb, rcc_wba, rcc_n6)))]
             csr.modify(|w| w.set_lsion(true));
 
+            #[cfg(rcc_n6)]
+            crate::pac::RCC.cr().modify(|w| w.set_lsion(true));
+
             #[cfg(any(rcc_wb, rcc_wba))]
             csr.modify(|w| w.set_lsi1on(true));
 
@@ -193,28 +214,77 @@ impl LsConfig {
             while !csr.read().lsi1rdy() {}
         }
 
+        // Enable backup regulator for peristent battery backed sram
+        #[cfg(backup_sram)]
+        {
+            unsafe { super::BKSRAM_RETAINED = crate::pac::PWR.bdcr().read().bren() == Retention::PRESERVED };
+
+            crate::pac::PWR.bdcr().modify(|w| {
+                w.set_bren(match self.enable_backup_sram {
+                    true => Retention::PRESERVED,
+                    false => Retention::LOST,
+                });
+            });
+
+            // Wait for backup regulator voltage to stabilize
+            while self.enable_backup_sram && !crate::pac::PWR.bdsr().read().brrdy() {}
+        }
+
         // backup domain configuration (LSEON, RTCEN, RTCSEL) is kept across resets.
         // once set, changing it requires a backup domain reset.
         // first check if the configuration matches what we want.
+        // N6 has all the fields spread across multiple registers under RCC.
 
         // check if it's already enabled and in the source we want.
+        #[cfg(not(rcc_n6))]
         let reg = bdcr().read();
+        #[cfg(rcc_n6)]
+        let reg = crate::pac::RCC.cr().read();
+        #[cfg(rcc_n6)]
+        let apb4lenr = crate::pac::RCC.apb4lenr().read();
+        #[cfg(rcc_n6)]
+        let ccipr7 = crate::pac::RCC.ccipr7().read();
+        #[cfg(rcc_n6)]
+        let lsecfgr = crate::pac::RCC.lsecfgr().read();
+
         let mut ok = true;
-        ok &= reg.rtcsel() == self.rtc;
-        #[cfg(not(rcc_wba))]
+        #[cfg(not(rcc_n6))]
+        {
+            ok &= reg.rtcsel() == self.rtc;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= ccipr7.rtcsel() == self.rtc;
+        }
+        #[cfg(not(any(rcc_wba, rcc_n6)))]
         {
             ok &= reg.rtcen() == (self.rtc != RtcClockSource::DISABLE);
         }
+        #[cfg(rcc_n6)]
+        {
+            ok &= apb4lenr.rtcen() == (self.rtc != RtcClockSource::DISABLE);
+        }
         ok &= reg.lseon() == lse_en;
-        ok &= reg.lsebyp() == lse_byp;
+        #[cfg(not(rcc_n6))]
+        {
+            ok &= reg.lsebyp() == lse_byp;
+        }
+        #[cfg(rcc_n6)]
+        {
+            ok &= lsecfgr.lsebyp() == lse_byp;
+        }
         #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
         if let Some(lse_sysen) = lse_sysen {
             ok &= reg.lsesysen() == lse_sysen;
         }
-        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1, rcc_n6)))]
         if let Some(lse_drv) = lse_drv {
             ok &= reg.lsedrv() == lse_drv.into();
         }
+        #[cfg(rcc_n6)]
+        if let Some(lse_drv) = lse_drv {
+            ok &= lsecfgr.lsedrv() == lse_drv.into();
+        }
 
         // if configuration is OK, we're done.
         if ok {
@@ -223,7 +293,7 @@ impl LsConfig {
         }
 
         // If not OK, reset backup domain and configure it.
-        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0)))]
+        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0, stm32n6)))]
         {
             bdcr().modify(|w| w.set_bdrst(true));
             bdcr().modify(|w| w.set_bdrst(false));
@@ -236,7 +306,7 @@ impl LsConfig {
         // STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
         // STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
         //#[cfg(any(stm32h5, stm32h7rs))]
-        #[cfg(any(stm32h7rs))]
+        #[cfg(any(stm32h7rs, stm32n6))]
         {
             bdcr().modify(|w| w.set_vswrst(true));
             bdcr().modify(|w| w.set_vswrst(false));
@@ -248,16 +318,31 @@ impl LsConfig {
         }
 
         if lse_en {
-            bdcr().modify(|w| {
-                #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
-                if let Some(lse_drv) = lse_drv {
-                    w.set_lsedrv(lse_drv.into());
-                }
-                w.set_lsebyp(lse_byp);
-                w.set_lseon(true);
-            });
+            #[cfg(not(rcc_n6))]
+            {
+                bdcr().modify(|w| {
+                    #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
+                    if let Some(lse_drv) = lse_drv {
+                        w.set_lsedrv(lse_drv.into());
+                    }
+                    w.set_lsebyp(lse_byp);
+                    w.set_lseon(true);
+                });
+
+                while !bdcr().read().lserdy() {}
+            }
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.lsecfgr().modify(|w| {
+                    if let Some(lse_drv) = lse_drv {
+                        w.set_lsedrv(lse_drv.into());
+                    }
+                    w.set_lsebyp(lse_byp);
+                });
+                crate::pac::RCC.cr().modify(|w| w.set_lseon(true));
 
-            while !bdcr().read().lserdy() {}
+                while !crate::pac::RCC.sr().read().lserdy() {}
+            }
 
             #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
             if let Some(lse_sysen) = lse_sysen {
@@ -272,6 +357,7 @@ impl LsConfig {
         }
 
         if self.rtc != RtcClockSource::DISABLE {
+            #[cfg(not(rcc_n6))]
             bdcr().modify(|w| {
                 #[cfg(any(rtc_v2_h7, rtc_v2_l4, rtc_v2_wb, rtc_v3_base, rtc_v3_u5))]
                 assert!(!w.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
@@ -280,6 +366,12 @@ impl LsConfig {
                 w.set_rtcen(true);
                 w.set_rtcsel(self.rtc);
             });
+
+            #[cfg(rcc_n6)]
+            {
+                crate::pac::RCC.ccipr7().modify(|w| w.set_rtcsel(self.rtc));
+                crate::pac::RCC.apb4lenr().modify(|w| w.set_rtcen(true))
+            }
         }
 
         trace!("BDCR configured: {:08x}", bdcr().read().0);
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index 8f2e8db5f..d941054cd 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -1,13 +1,13 @@
 use stm32_metapac::flash::vals::Latency;
 
+#[cfg(any(stm32f4, stm32f7))]
+use crate::pac::PWR;
 #[cfg(any(stm32f413, stm32f423, stm32f412))]
 pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource;
 pub use crate::pac::rcc::vals::{
     Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
-#[cfg(any(stm32f4, stm32f7))]
-use crate::pac::PWR;
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
 
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index 331bab7a0..485edd390 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -597,7 +597,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index 81b89046e..2e1cbd702 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -499,9 +499,9 @@ pub use pll::*;
 
 #[cfg(any(stm32l0, stm32l1))]
 mod pll {
-    use super::{pll_enable, PllInstance};
-    pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
+    use super::{PllInstance, pll_enable};
     use crate::pac::RCC;
+    pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
     use crate::time::Hertz;
 
     #[derive(Clone, Copy)]
@@ -563,11 +563,11 @@ mod pll {
 
 #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl, stm32u0))]
 mod pll {
-    use super::{pll_enable, PllInstance};
+    use super::{PllInstance, pll_enable};
+    use crate::pac::RCC;
     pub use crate::pac::rcc::vals::{
         Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource,
     };
-    use crate::pac::RCC;
     use crate::time::Hertz;
 
     #[derive(Clone, Copy)]
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index fa4b45a20..0624fdf26 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -3,6 +3,7 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 use crate::gpio::{AfType, OutputType, Speed};
+use crate::pac::RCC;
 #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
 pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
 #[cfg(not(any(
@@ -15,7 +16,8 @@ pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
     rcc_h7ab,
     rcc_h7rm0433,
     rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 )))]
 pub use crate::pac::rcc::vals::Mcosel as McoSource;
 #[cfg(any(
@@ -28,11 +30,11 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
     rcc_h7ab,
     rcc_h7rm0433,
     rcc_h7,
-    rcc_h7rs
+    rcc_h7rs,
+    rcc_n6
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
-use crate::pac::RCC;
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 #[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -59,10 +61,12 @@ macro_rules! impl_peri {
             type Source = $source;
 
             unsafe fn _apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) {
-                #[cfg(not(any(stm32u5, stm32wba)))]
+                #[cfg(not(any(stm32u5, stm32wba, stm32n6)))]
                 let r = RCC.cfgr();
                 #[cfg(any(stm32u5, stm32wba))]
                 let r = RCC.cfgr1();
+                #[cfg(any(stm32n6))]
+                let r = RCC.ccipr5();
 
                 r.modify(|w| {
                     w.$set_source(source);
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index c41f81816..85434fa83 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -28,12 +28,13 @@ pub use hsi48::*;
 #[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl, stm32u0), path = "l.rs")]
 #[cfg_attr(stm32u5, path = "u5.rs")]
 #[cfg_attr(stm32wba, path = "wba.rs")]
+#[cfg_attr(stm32n6, path = "n6.rs")]
 mod _version;
 
 pub use _version::*;
 use stm32_metapac::RCC;
 
-pub use crate::_generated::{mux, Clocks};
+pub use crate::_generated::{Clocks, mux};
 use crate::time::Hertz;
 
 #[cfg(feature = "low-power")]
@@ -48,6 +49,12 @@ pub(crate) static mut REFCOUNT_STOP1: u32 = 0;
 /// May be read without a critical section
 pub(crate) static mut REFCOUNT_STOP2: u32 = 0;
 
+#[cfg(feature = "low-power")]
+pub(crate) static mut RCC_CONFIG: Option<Config> = None;
+
+#[cfg(backup_sram)]
+pub(crate) static mut BKSRAM_RETAINED: bool = false;
+
 #[cfg(not(feature = "_dual-core"))]
 /// Frozen clock frequencies
 ///
@@ -104,6 +111,32 @@ pub fn clocks<'a>(_rcc: &'a crate::Peri<'a, crate::peripherals::RCC>) -> &'a Clo
     unsafe { get_freqs() }
 }
 
+#[cfg(feature = "low-power")]
+pub(crate) fn increment_stop_refcount(_cs: CriticalSection, stop_mode: StopMode) {
+    match stop_mode {
+        StopMode::Standby => {}
+        StopMode::Stop2 => unsafe {
+            REFCOUNT_STOP2 += 1;
+        },
+        StopMode::Stop1 => unsafe {
+            REFCOUNT_STOP1 += 1;
+        },
+    }
+}
+
+#[cfg(feature = "low-power")]
+pub(crate) fn decrement_stop_refcount(_cs: CriticalSection, stop_mode: StopMode) {
+    match stop_mode {
+        StopMode::Standby => {}
+        StopMode::Stop2 => unsafe {
+            REFCOUNT_STOP2 -= 1;
+        },
+        StopMode::Stop1 => unsafe {
+            REFCOUNT_STOP1 -= 1;
+        },
+    }
+}
+
 pub(crate) trait SealedRccPeripheral {
     fn frequency() -> Hertz;
     #[allow(dead_code)]
@@ -134,12 +167,19 @@ pub(crate) struct RccInfo {
     stop_mode: StopMode,
 }
 
+/// Specifies a limit for the stop mode of the peripheral or the stop mode to be entered.
+/// E.g. if `StopMode::Stop1` is selected, the peripheral prevents the chip from entering Stop1 mode.
 #[cfg(feature = "low-power")]
 #[allow(dead_code)]
-pub(crate) enum StopMode {
-    Standby,
-    Stop2,
+#[derive(Debug, Clone, Copy, PartialEq, Default)]
+pub enum StopMode {
+    #[default]
+    /// Peripheral prevents chip from entering Stop1 or executor will enter Stop1
     Stop1,
+    /// Peripheral prevents chip from entering Stop2 or executor will enter Stop2
+    Stop2,
+    /// Peripheral does not prevent chip from entering Stop
+    Standby,
 }
 
 impl RccInfo {
@@ -195,15 +235,7 @@ impl RccInfo {
         }
 
         #[cfg(feature = "low-power")]
-        match self.stop_mode {
-            StopMode::Standby => {}
-            StopMode::Stop2 => unsafe {
-                REFCOUNT_STOP2 += 1;
-            },
-            StopMode::Stop1 => unsafe {
-                REFCOUNT_STOP1 += 1;
-            },
-        }
+        increment_stop_refcount(_cs, self.stop_mode);
 
         // set the xxxRST bit
         let reset_ptr = self.reset_ptr();
@@ -261,15 +293,7 @@ impl RccInfo {
         }
 
         #[cfg(feature = "low-power")]
-        match self.stop_mode {
-            StopMode::Standby => {}
-            StopMode::Stop2 => unsafe {
-                REFCOUNT_STOP2 -= 1;
-            },
-            StopMode::Stop1 => unsafe {
-                REFCOUNT_STOP1 -= 1;
-            },
-        }
+        decrement_stop_refcount(_cs, self.stop_mode);
 
         // clear the xxxEN bit
         let enable_ptr = self.enable_ptr();
@@ -390,7 +414,7 @@ pub fn disable<T: RccPeripheral>() {
 ///
 /// This should only be called after `init`.
 #[cfg(not(feature = "_dual-core"))]
-pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
+pub fn reinit(config: Config, _rcc: &'_ mut crate::Peri<'_, crate::peripherals::RCC>) {
     critical_section::with(|cs| init_rcc(cs, config))
 }
 
@@ -404,8 +428,39 @@ pub(crate) fn init_rcc(_cs: CriticalSection, config: Config) {
 
         #[cfg(feature = "low-power")]
         {
+            RCC_CONFIG = Some(config);
             REFCOUNT_STOP2 = 0;
             REFCOUNT_STOP1 = 0;
         }
     }
 }
+
+/// Calculate intermediate prescaler number used to calculate peripheral prescalers
+///
+/// This function is intended to calculate a number indicating a minimum division
+/// necessary to result in a frequency lower than the provided `freq_max`.
+///
+/// The returned value indicates the `val + 1` divider is necessary to result in
+/// the output frequency that is below the maximum provided.
+///
+/// For example:
+/// 0 = divider of 1 => no division necessary as the input frequency is below max
+/// 1 = divider of 2 => division by 2 necessary
+/// ...
+///
+/// The provided max frequency is inclusive. So if `freq_in == freq_max` the result
+/// will be 0, indicating that no division is necessary. To accomplish that we subtract
+/// 1 from the input frequency so that the integer rounding plays in our favor.
+///
+/// For example:
+/// Let the input frequency be 110 and the max frequency be 55.
+/// If we naiively do `110/55 = 2` the renult will indicate that we need a divider by 3
+/// which in reality will be rounded up to 4 as usually a 3 division is not available.
+/// In either case the resulting frequency will be either 36 or 27 which is lower than
+/// what we would want. The result should be 1.
+/// If we do the following instead `109/55 = 1` indicating that we need a divide by 2
+/// which will result in the correct 55.
+#[allow(unused)]
+pub(crate) fn raw_prescaler(freq_in: u32, freq_max: u32) -> u32 {
+    freq_in.saturating_sub(1) / freq_max
+}
diff --git a/embassy-stm32/src/rcc/n6.rs b/embassy-stm32/src/rcc/n6.rs
new file mode 100644
index 000000000..866851bbd
--- /dev/null
+++ b/embassy-stm32/src/rcc/n6.rs
@@ -0,0 +1,1046 @@
+use stm32_metapac::rcc::vals::{
+    Cpusw, Cpusws, Hseext, Hsitrim, Icint, Icsel, Msifreqsel, Plldivm, Pllmodssdis, Pllpdiv, Pllsel, Syssw, Syssws,
+    Timpre,
+};
+pub use stm32_metapac::rcc::vals::{
+    Hpre as AhbPrescaler, Hsidiv as HsiPrescaler, Hsitrim as HsiCalibration, Ppre as ApbPrescaler,
+};
+
+use crate::pac::{PWR, RCC, SYSCFG};
+use crate::time::Hertz;
+
+pub const HSI_FREQ: Hertz = Hertz(64_000_000);
+pub const LSE_FREQ: Hertz = Hertz(32_768);
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub enum HseMode {
+    /// crystal/ceramic oscillator
+    Oscillator,
+    /// oscillator bypassed with external clock (analog)
+    Bypass,
+    /// oscillator bypassed with external digital clock
+    BypassDigital,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hse {
+    /// HSE frequency.
+    pub freq: Hertz,
+    /// HSE oscillator mode.
+    pub mode: HseMode,
+}
+
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+    pub pre: HsiPrescaler,
+    pub trim: Hsitrim,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum SupplyConfig {
+    Smps,
+    External,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum CpuClk {
+    Hse,
+    Ic1 { source: Icsel, divider: Icint },
+    Msi,
+    Hsi,
+}
+
+impl CpuClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic1 { .. } => 0x3,
+        }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub struct IcConfig {
+    source: Icsel,
+    divider: Icint,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum SysClk {
+    Hse,
+    Ic2 {
+        ic2: IcConfig,
+        ic6: IcConfig,
+        ic11: IcConfig,
+    },
+    Msi,
+    Hsi,
+}
+
+impl SysClk {
+    const fn to_bits(self) -> u8 {
+        match self {
+            Self::Hsi => 0x0,
+            Self::Msi => 0x1,
+            Self::Hse => 0x2,
+            Self::Ic2 { .. } => 0x3,
+        }
+    }
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub struct Msi {
+    pub freq: Msifreqsel,
+    pub trim: u8,
+}
+
+#[derive(Clone, Copy, PartialEq)]
+pub enum Pll {
+    Oscillator {
+        source: Pllsel,
+        divm: Plldivm,
+        fractional: u32,
+        divn: u16,
+        divp1: Pllpdiv,
+        divp2: Pllpdiv,
+    },
+    Bypass {
+        source: Pllsel,
+    },
+}
+
+/// Configuration of the core clocks
+#[non_exhaustive]
+#[derive(Clone, Copy)]
+pub struct Config {
+    pub hsi: Option<Hsi>,
+    pub hse: Option<Hse>,
+    pub msi: Option<Msi>,
+    pub lsi: bool,
+    pub lse: bool,
+
+    pub sys: SysClk,
+    pub cpu: CpuClk,
+
+    pub pll1: Option<Pll>,
+    pub pll2: Option<Pll>,
+    pub pll3: Option<Pll>,
+    pub pll4: Option<Pll>,
+
+    pub ahb: AhbPrescaler,
+    pub apb1: ApbPrescaler,
+    pub apb2: ApbPrescaler,
+    pub apb4: ApbPrescaler,
+    pub apb5: ApbPrescaler,
+
+    pub supply_config: SupplyConfig,
+}
+
+impl Config {
+    pub const fn new() -> Self {
+        Self {
+            hsi: Some(Hsi {
+                pre: HsiPrescaler::DIV1,
+                trim: HsiCalibration::from_bits(32),
+            }),
+            hse: None,
+            msi: None,
+            lsi: true,
+            lse: false,
+            sys: SysClk::Hsi,
+            cpu: CpuClk::Hsi,
+            pll1: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll2: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll3: Some(Pll::Bypass { source: Pllsel::HSI }),
+            pll4: Some(Pll::Bypass { source: Pllsel::HSI }),
+
+            ahb: AhbPrescaler::DIV2,
+            apb1: ApbPrescaler::DIV1,
+            apb2: ApbPrescaler::DIV1,
+            apb4: ApbPrescaler::DIV1,
+            apb5: ApbPrescaler::DIV1,
+
+            supply_config: SupplyConfig::Smps,
+        }
+    }
+}
+
+#[allow(dead_code)]
+struct ClocksOutput {
+    cpuclk: Hertz,
+    sysclk: Hertz,
+    pclk_tim: Hertz,
+    ahb: Hertz,
+    apb1: Hertz,
+    apb2: Hertz,
+    apb4: Hertz,
+    apb5: Hertz,
+}
+
+struct ClocksInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+}
+
+fn init_clocks(config: Config, input: &ClocksInput) -> ClocksOutput {
+    // handle increasing dividers
+    debug!("configuring increasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.apb1 > w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 > w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 > w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 > w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+        if config.ahb > w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+    });
+    // cpuclk
+    debug!("configuring cpuclk");
+    match config.cpu {
+        CpuClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        CpuClk::Ic1 { source, divider } => {
+            if !pll_sources_ready(RCC.iccfgr(0).read().icsel().to_bits(), source.to_bits()) {
+                panic!("ICx clock switch requires both origin and destination clock source to be active")
+            }
+
+            RCC.iccfgr(0).write(|w| {
+                w.set_icsel(source);
+                w.set_icint(divider);
+            });
+            RCC.divensr().modify(|w| w.set_ic1ens(true));
+        }
+        CpuClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        CpuClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // set source
+    let cpusw = Cpusw::from_bits(config.cpu.to_bits());
+    RCC.cfgr().modify(|w| w.set_cpusw(cpusw));
+    // wait for changes to take effect
+    while RCC.cfgr().read().cpusws() != Cpusws::from_bits(config.cpu.to_bits()) {}
+
+    // sysclk
+    debug!("configuring sysclk");
+    match config.sys {
+        SysClk::Hse if !RCC.sr().read().hserdy() => panic!("HSE is not ready to be selected as CPU clock source"),
+        SysClk::Ic2 { ic2, ic6, ic11 } => {
+            if !pll_sources_ready(RCC.iccfgr(1).read().icsel().to_bits(), ic2.source.to_bits()) {
+                panic!("IC2 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(5).read().icsel().to_bits(), ic6.source.to_bits()) {
+                panic!("IC6 clock switch requires both origin and destination clock source to be active")
+            }
+            if !pll_sources_ready(RCC.iccfgr(10).read().icsel().to_bits(), ic11.source.to_bits()) {
+                panic!("IC11 clock switch requires both origin and destination clock source to be active")
+            }
+
+            RCC.iccfgr(1).write(|w| {
+                w.set_icsel(ic2.source);
+                w.set_icint(ic2.divider);
+            });
+            RCC.iccfgr(5).write(|w| {
+                w.set_icsel(ic6.source);
+                w.set_icint(ic6.divider);
+            });
+            RCC.iccfgr(10).write(|w| {
+                w.set_icsel(ic11.source);
+                w.set_icint(ic11.divider);
+            });
+            RCC.divensr().modify(|w| {
+                w.set_ic2ens(true);
+                w.set_ic6ens(true);
+                w.set_ic11ens(true);
+            });
+        }
+        SysClk::Msi if !RCC.sr().read().msirdy() => panic!("MSI is not ready to be selected as CPU clock source"),
+        SysClk::Hsi if !RCC.sr().read().hsirdy() => panic!("HSI is not ready to be selected as CPU clock source"),
+        _ => {}
+    }
+    // switch the system bus clock
+    let syssw = Syssw::from_bits(config.sys.to_bits());
+    RCC.cfgr().modify(|w| w.set_syssw(syssw));
+    // wait for changes to be applied
+    while RCC.cfgr().read().syssws() != Syssws::from_bits(config.sys.to_bits()) {}
+
+    // decreasing dividers
+    debug!("configuring decreasing pclk dividers");
+    RCC.cfgr2().modify(|w| {
+        if config.ahb < w.hpre() {
+            debug!("  - AHB");
+            w.set_hpre(config.ahb);
+        }
+        if config.apb1 < w.ppre1() {
+            debug!("  - APB1");
+            w.set_ppre1(config.apb1);
+        }
+        if config.apb2 < w.ppre2() {
+            debug!("  - APB2");
+            w.set_ppre2(config.apb2);
+        }
+        if config.apb4 < w.ppre4() {
+            debug!("  - APB4");
+            w.set_ppre4(config.apb4);
+        }
+        if config.apb5 < w.ppre5() {
+            debug!("  - APB5");
+            w.set_ppre5(config.apb5);
+        }
+    });
+
+    let cpuclk = match config.cpu {
+        CpuClk::Hsi => unwrap!(input.hsi),
+        CpuClk::Msi => unwrap!(input.msi),
+        CpuClk::Hse => unwrap!(input.hse),
+        CpuClk::Ic1 { .. } => todo!(),
+    };
+
+    let sysclk = match config.sys {
+        SysClk::Hsi => unwrap!(input.hsi),
+        SysClk::Msi => unwrap!(input.msi),
+        SysClk::Hse => unwrap!(input.hse),
+        SysClk::Ic2 { .. } => todo!(),
+    };
+
+    let timpre: u32 = match RCC.cfgr2().read().timpre() {
+        Timpre::DIV1 => 1,
+        Timpre::DIV2 => 2,
+        Timpre::DIV4 => 4,
+        Timpre::_RESERVED_3 => 8,
+    };
+
+    let hpre = periph_prescaler_to_value(config.ahb.to_bits());
+    let ppre1 = periph_prescaler_to_value(config.apb1.to_bits());
+    let ppre2 = periph_prescaler_to_value(config.apb2.to_bits());
+    let ppre4 = periph_prescaler_to_value(config.apb4.to_bits());
+    let ppre5 = periph_prescaler_to_value(config.apb5.to_bits());
+
+    // enable all peripherals in sleep mode
+    enable_low_power_peripherals();
+
+    // enable interrupts
+    unsafe {
+        core::arch::asm!("cpsie i");
+    }
+
+    ClocksOutput {
+        sysclk,
+        cpuclk,
+        pclk_tim: sysclk / timpre,
+        ahb: Hertz(sysclk.0 / hpre as u32),
+        apb1: sysclk / hpre / ppre1,
+        apb2: sysclk / hpre / ppre2,
+        apb4: sysclk / hpre / ppre4,
+        apb5: sysclk / hpre / ppre5,
+    }
+}
+
+fn enable_low_power_peripherals() {
+    // AHB1-5
+    RCC.ahb1lpenr().modify(|w| {
+        w.set_adc12lpen(true);
+        w.set_gpdma1lpen(true);
+    });
+    RCC.ahb2lpenr().modify(|w| {
+        w.set_adf1lpen(true);
+        w.set_mdf1lpen(true);
+        w.set_ramcfglpen(true);
+    });
+    RCC.ahb3lpenr().modify(|w| {
+        w.set_risaflpen(true);
+        w.set_iaclpen(true);
+        w.set_rifsclpen(true);
+        w.set_pkalpen(true);
+        w.set_saeslpen(true);
+        w.set_cryplpen(true);
+        w.set_hashlpen(true);
+        w.set_rnglpen(true);
+    });
+    RCC.ahb4lpenr().modify(|w| {
+        w.set_crclpen(true);
+        w.set_pwrlpen(true);
+        w.set_gpioqlpen(true);
+        w.set_gpioplpen(true);
+        w.set_gpioolpen(true);
+        w.set_gpionlpen(true);
+        w.set_gpiohlpen(true);
+        w.set_gpioglpen(true);
+        w.set_gpioflpen(true);
+        w.set_gpioelpen(true);
+        w.set_gpiodlpen(true);
+        w.set_gpioclpen(true);
+        w.set_gpioblpen(true);
+        w.set_gpioalpen(true);
+    });
+    RCC.ahb5lpenr().modify(|w| {
+        w.set_npulpen(true);
+        w.set_npucachelpen(true);
+        w.set_otg2lpen(true);
+        w.set_otgphy2lpen(true);
+        w.set_otgphy1lpen(true);
+        w.set_otg1lpen(true);
+        w.set_eth1lpen(true);
+        w.set_eth1rxlpen(true);
+        w.set_eth1txlpen(true);
+        w.set_eth1maclpen(true);
+        w.set_gpulpen(true);
+        w.set_gfxmmulpen(true);
+        w.set_mce4lpen(true);
+        w.set_xspi3lpen(true);
+        w.set_mce3lpen(true);
+        w.set_mce2lpen(true);
+        w.set_mce1lpen(true);
+        w.set_xspimlpen(true);
+        w.set_xspi2lpen(true);
+        w.set_sdmmc1lpen(true);
+        w.set_sdmmc2lpen(true);
+        w.set_pssilpen(true);
+        w.set_xspi1lpen(true);
+        w.set_fmclpen(true);
+        w.set_jpeglpen(true);
+        w.set_dma2dlpen(true);
+        w.set_hpdma1lpen(true);
+    });
+
+    // APB1-5
+    RCC.apb1llpenr().modify(|w| {
+        w.set_uart8lpen(true);
+        w.set_uart7lpen(true);
+        w.set_i3c2lpen(true);
+        w.set_i3c1lpen(true);
+        w.set_i2c3lpen(true);
+        w.set_i2c2lpen(true);
+        w.set_i2c1lpen(true);
+        w.set_uart5lpen(true);
+        w.set_uart4lpen(true);
+        w.set_usart3lpen(true);
+        w.set_usart2lpen(true);
+        w.set_spdifrx1lpen(true);
+        w.set_spi3lpen(true);
+        w.set_spi2lpen(true);
+        w.set_tim11lpen(true);
+        w.set_tim10lpen(true);
+        w.set_wwdglpen(true);
+        w.set_lptim1lpen(true);
+        w.set_tim14lpen(true);
+        w.set_tim13lpen(true);
+        w.set_tim12lpen(true);
+        w.set_tim7lpen(true);
+        w.set_tim6lpen(true);
+        w.set_tim5lpen(true);
+        w.set_tim4lpen(true);
+        w.set_tim3lpen(true);
+        w.set_tim2lpen(true);
+    });
+    RCC.apb1hlpenr().modify(|w| {
+        w.set_ucpd1lpen(true);
+        w.set_fdcanlpen(true);
+        w.set_mdioslpen(true);
+    });
+    RCC.apb2lpenr().modify(|w| {
+        w.set_sai2lpen(true);
+        w.set_sai1lpen(true);
+        w.set_spi5lpen(true);
+        w.set_tim9lpen(true);
+        w.set_tim17lpen(true);
+        w.set_tim16lpen(true);
+        w.set_tim15lpen(true);
+        w.set_tim18lpen(true);
+        w.set_spi4lpen(true);
+        w.set_spi1lpen(true);
+        w.set_usart10lpen(true);
+        w.set_uart9lpen(true);
+        w.set_usart6lpen(true);
+        w.set_usart1lpen(true);
+        w.set_tim8lpen(true);
+        w.set_tim1lpen(true);
+    });
+    RCC.apb3lpenr().modify(|w| {
+        w.set_dftlpen(true);
+    });
+    RCC.apb4llpenr().modify(|w| {
+        w.set_rtcapblpen(true);
+        w.set_rtclpen(true);
+        w.set_vrefbuflpen(true);
+        w.set_lptim5lpen(true);
+        w.set_lptim4lpen(true);
+        w.set_lptim3lpen(true);
+        w.set_lptim2lpen(true);
+        w.set_i2c4lpen(true);
+        w.set_spi6lpen(true);
+        w.set_lpuart1lpen(true);
+        w.set_hdplpen(true);
+    });
+    RCC.apb4hlpenr().modify(|w| {
+        w.set_dtslpen(true);
+        w.set_bseclpen(true);
+        w.set_syscfglpen(true);
+    });
+    RCC.apb5lpenr().modify(|w| {
+        w.set_csilpen(true);
+        w.set_venclpen(true);
+        w.set_gfxtimlpen(true);
+        w.set_dcmilpen(true);
+        w.set_ltdclpen(true);
+    });
+
+    RCC.buslpenr().modify(|w| {
+        w.set_aclknclpen(true);
+        w.set_aclknlpen(true);
+    });
+
+    RCC.memlpenr().modify(|w| {
+        w.set_bootromlpen(true);
+        w.set_vencramlpen(true);
+        w.set_npucacheramlpen(true);
+        w.set_flexramlpen(true);
+        w.set_axisram2lpen(true);
+        w.set_axisram1lpen(true);
+        w.set_bkpsramlpen(true);
+        w.set_ahbsram2lpen(true);
+        w.set_ahbsram1lpen(true);
+        w.set_axisram6lpen(true);
+        w.set_axisram5lpen(true);
+        w.set_axisram4lpen(true);
+        w.set_axisram3lpen(true);
+    });
+
+    RCC.misclpenr().modify(|w| {
+        w.set_perlpen(true);
+        w.set_xspiphycomplpen(true);
+        w.set_dbglpen(true);
+    });
+}
+
+const fn periph_prescaler_to_value(bits: u8) -> u8 {
+    match bits {
+        0 => 1,
+        1 => 2,
+        2 => 4,
+        3 => 8,
+        4 => 16,
+        5 => 32,
+        6 => 64,
+        7.. => 128,
+    }
+}
+
+fn pll_source_ready(source: u8) -> bool {
+    match source {
+        0x0 if !RCC.sr().read().pllrdy(0) && !RCC.pllcfgr1(0).read().pllbyp() => false,
+        0x1 if !RCC.sr().read().pllrdy(1) && !RCC.pllcfgr1(1).read().pllbyp() => false,
+        0x2 if !RCC.sr().read().pllrdy(2) && !RCC.pllcfgr1(2).read().pllbyp() => false,
+        0x3 if !RCC.sr().read().pllrdy(3) && !RCC.pllcfgr1(3).read().pllbyp() => false,
+        _ => true,
+    }
+}
+
+fn pll_sources_ready(source1: u8, source2: u8) -> bool {
+    pll_source_ready(source1) && pll_source_ready(source2)
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
+
+fn power_supply_config(supply_config: SupplyConfig) {
+    // power supply config
+    PWR.cr1().modify(|w| {
+        w.set_sden(match supply_config {
+            SupplyConfig::External => false,
+            SupplyConfig::Smps => true,
+        });
+    });
+
+    // Validate supply configuration
+    while !PWR.voscr().read().actvosrdy() {}
+}
+
+struct PllInput {
+    hsi: Option<Hertz>,
+    msi: Option<Hertz>,
+    hse: Option<Hertz>,
+    i2s_ckin: Option<Hertz>,
+}
+
+#[derive(Clone, Copy, Default)]
+#[allow(dead_code)]
+struct PllOutput {
+    divm: Option<Hertz>,
+    divn: Option<Hertz>,
+    divp1: Option<Hertz>,
+    divp2: Option<Hertz>,
+    output: Option<Hertz>,
+}
+
+fn init_pll(pll_config: Option<Pll>, pll_index: usize, input: &PllInput) -> PllOutput {
+    let cfgr1 = RCC.pllcfgr1(pll_index);
+    let cfgr2 = RCC.pllcfgr2(pll_index);
+    let cfgr3 = RCC.pllcfgr3(pll_index);
+
+    match pll_config {
+        Some(Pll::Oscillator {
+            source,
+            divm,
+            fractional,
+            divn,
+            divp1,
+            divp2,
+        }) => {
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            // ensure PLLxMODSSDIS=1 to work in fractional mode
+            cfgr3.modify(|w| w.set_pllmodssdis(Pllmodssdis::FRACTIONAL_DIVIDE));
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+            // configure the pll clock source, mul and div factors
+            cfgr1.modify(|w| {
+                w.set_pllsel(source);
+                w.set_plldivm(divm);
+                w.set_plldivn(divn);
+            });
+
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+
+            let m = divm.to_bits() as u32;
+            let n = divn as u32;
+
+            cfgr3.modify(|w| {
+                w.set_pllpdiv1(divp1);
+                w.set_pllpdiv2(divp2);
+            });
+
+            let p1 = divp1.to_bits() as u32;
+            let p2 = divp2.to_bits() as u32;
+
+            // configure pll divnfrac
+            cfgr2.modify(|w| w.set_plldivnfrac(fractional));
+            // clear pllxmoddsen
+            cfgr3.modify(|w| w.set_pllmoddsen(false));
+            // fractional mode
+            if fractional != 0 {
+                cfgr3.modify(|w| {
+                    w.set_pllmoddsen(true);
+                    w.set_plldacen(true);
+                })
+            }
+            // enable pll post divider output
+            cfgr3.modify(|w| {
+                w.set_pllmodssrst(true);
+                w.set_pllpdiven(true);
+            });
+            // enable the pll
+            RCC.csr().write(|w| w.pllons(pll_index));
+            // wait until ready
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            PllOutput {
+                divm: Some(Hertz(m)),
+                divn: Some(Hertz(n)),
+                divp1: Some(Hertz(p1)),
+                divp2: Some(Hertz(p2)),
+                output: Some(Hertz(in_clk.0 / m / n / p1 / p2)),
+            }
+        }
+        Some(Pll::Bypass { source }) => {
+            // check if source is ready
+            if !pll_source_ready(source.to_bits()) {
+                panic!("PLL source is not ready")
+            }
+
+            // ensure pll is disabled
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            cfgr1.modify(|w| {
+                w.set_pllbyp(true);
+                w.set_pllsel(source);
+            });
+
+            let in_clk = match source {
+                Pllsel::HSI => unwrap!(input.hsi),
+                Pllsel::MSI => unwrap!(input.msi),
+                Pllsel::HSE => unwrap!(input.hse),
+                Pllsel::I2S_CKIN => unwrap!(input.i2s_ckin),
+                _ => panic!("reserved PLL source not allowed"),
+            };
+
+            PllOutput {
+                output: Some(in_clk),
+                ..Default::default()
+            }
+        }
+        None => {
+            cfgr3.modify(|w| w.set_pllpdiven(false));
+            RCC.ccr().write(|w| w.set_pllonc(pll_index, true));
+            // wait till disabled
+            while RCC.sr().read().pllrdy(pll_index) {}
+
+            // clear bypass mode
+            cfgr1.modify(|w| w.set_pllbyp(false));
+
+            PllOutput::default()
+        }
+    }
+}
+
+#[allow(dead_code)]
+struct OscOutput {
+    hsi: Option<Hertz>,
+    hse: Option<Hertz>,
+    msi: Option<Hertz>,
+    lsi: Option<Hertz>,
+    lse: Option<Hertz>,
+    pll1: Option<Hertz>,
+    pll2: Option<Hertz>,
+    pll3: Option<Hertz>,
+    pll4: Option<Hertz>,
+    ic1sel: Icsel,
+    ic2sel: Icsel,
+    ic6sel: Icsel,
+    ic11sel: Icsel,
+}
+
+fn init_osc(config: Config) -> OscOutput {
+    let (cpu_src, sys_src) = {
+        let reg = RCC.cfgr().read();
+        (reg.cpusws(), reg.syssws())
+    };
+    let pll1_src = RCC.pllcfgr1(0).read().pllsel();
+    let pll2_src = RCC.pllcfgr1(1).read().pllsel();
+    let pll3_src = RCC.pllcfgr1(2).read().pllsel();
+    let pll4_src = RCC.pllcfgr1(3).read().pllsel();
+    let rcc_sr = RCC.sr().read();
+
+    debug!("configuring HSE");
+
+    // hse configuration
+    let hse = if let Some(hse) = config.hse {
+        match hse.mode {
+            HseMode::Oscillator => {
+                debug!("HSE in oscillator mode");
+            }
+            HseMode::Bypass => {
+                debug!("HSE in bypass mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::ANALOG);
+                });
+            }
+            HseMode::BypassDigital => {
+                debug!("HSE in bypass digital mode");
+                RCC.hsecfgr().modify(|w| {
+                    w.set_hsebyp(true);
+                    w.set_hseext(Hseext::DIGITAL);
+                });
+            }
+        }
+        RCC.csr().write(|w| w.set_hseons(true));
+
+        // wait until the hse is ready
+        while !RCC.sr().read().hserdy() {}
+
+        Some(hse.freq)
+    } else if cpu_src == Cpusws::HSE
+        || sys_src == Syssws::HSE
+        || (pll1_src == Pllsel::HSE && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSE && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSE && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSE && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSE is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSE off");
+
+        RCC.ccr().write(|w| w.set_hseonc(true));
+        RCC.hsecfgr().modify(|w| {
+            w.set_hseext(Hseext::ANALOG);
+            w.set_hsebyp(false);
+        });
+
+        // wait until the hse is disabled
+        while RCC.sr().read().hserdy() {}
+
+        None
+    };
+
+    // hsi configuration
+    debug!("configuring HSI");
+    let hsi = if let Some(hsi) = config.hsi {
+        RCC.csr().write(|w| w.set_hsions(true));
+        while !RCC.sr().read().hsirdy() {}
+
+        // set divider and calibration
+        RCC.hsicfgr().modify(|w| {
+            w.set_hsidiv(hsi.pre);
+            w.set_hsitrim(hsi.trim);
+        });
+
+        Some(HSI_FREQ / hsi.pre)
+    } else if cpu_src == Cpusws::HSI
+        || sys_src == Syssws::HSI
+        || (pll1_src == Pllsel::HSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::HSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::HSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::HSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the HSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        debug!("HSI off");
+
+        RCC.ccr().write(|w| w.set_hsionc(true));
+        while RCC.sr().read().hsirdy() {}
+
+        None
+    };
+
+    // msi configuration
+    debug!("configuring MSI");
+    let msi = if let Some(msi) = config.msi {
+        RCC.msicfgr().modify(|w| w.set_msifreqsel(msi.freq));
+        RCC.csr().write(|w| w.set_msions(true));
+        while !RCC.sr().read().msirdy() {}
+        RCC.msicfgr().modify(|w| w.set_msitrim(msi.trim));
+
+        Some(match msi.freq {
+            Msifreqsel::_4MHZ => Hertz::mhz(4),
+            Msifreqsel::_16MHZ => Hertz::mhz(16),
+        })
+    } else if cpu_src == Cpusws::MSI
+        || sys_src == Syssws::MSI
+        || (pll1_src == Pllsel::MSI && rcc_sr.pllrdy(0))
+        || (pll2_src == Pllsel::MSI && rcc_sr.pllrdy(1))
+        || (pll3_src == Pllsel::MSI && rcc_sr.pllrdy(2))
+        || (pll4_src == Pllsel::MSI && rcc_sr.pllrdy(3))
+    {
+        panic!(
+            "When the MSI is used as cpu/system bus clock or clock source for any PLL, it is not allowed to be disabled"
+        );
+    } else {
+        RCC.ccr().write(|w| w.set_msionc(true));
+        while RCC.sr().read().msirdy() {}
+
+        None
+    };
+
+    // lsi configuration
+    debug!("configuring LSI");
+    let lsi = if config.lsi {
+        RCC.csr().write(|w| w.set_lsions(true));
+        while !RCC.sr().read().lsirdy() {}
+        Some(super::LSI_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lsionc(true));
+        while RCC.sr().read().lsirdy() {}
+        None
+    };
+
+    // lse configuration
+    debug!("configuring LSE");
+    let lse = if config.lse {
+        RCC.csr().write(|w| w.set_lseons(true));
+        while !RCC.sr().read().lserdy() {}
+        Some(LSE_FREQ)
+    } else {
+        RCC.ccr().write(|w| w.set_lseonc(true));
+        while RCC.sr().read().lserdy() {}
+        None
+    };
+
+    let pll_input = PllInput {
+        hse,
+        msi,
+        hsi,
+        i2s_ckin: None,
+    };
+
+    // pll1,2,3,4 config
+    let pll_configs = [config.pll1, config.pll2, config.pll3, config.pll4];
+    let mut pll_outputs: [PllOutput; 4] = [PllOutput::default(); 4];
+
+    let ic1_src = RCC.iccfgr(0).read().icsel();
+    let ic2_src = RCC.iccfgr(1).read().icsel();
+    let ic6_src = RCC.iccfgr(5).read().icsel();
+    let ic11_src = RCC.iccfgr(10).read().icsel();
+
+    for (n, (&pll, out)) in pll_configs.iter().zip(pll_outputs.iter_mut()).enumerate() {
+        debug!("configuring PLL{}", n + 1);
+        let pll_ready = RCC.sr().read().pllrdy(n);
+
+        if is_new_pll_config(pll, 0) {
+            let this_pll = Icsel::from_bits(n as u8);
+
+            if cpu_src == Cpusws::IC1 && ic1_src == this_pll {
+                panic!("PLL should not be disabled / reconfigured if used for IC1 (cpuclksrc)")
+            }
+
+            if sys_src == Syssws::IC2 && (ic2_src == this_pll || ic6_src == this_pll || ic11_src == this_pll) {
+                panic!("PLL should not be disabled / reconfigured if used for IC2, IC6 or IC11 (sysclksrc)")
+            }
+
+            *out = init_pll(pll, 0, &pll_input);
+        } else if pll.is_some() && !pll_ready {
+            RCC.csr().write(|w| w.pllons(n));
+            while !RCC.sr().read().pllrdy(n) {}
+        }
+    }
+
+    OscOutput {
+        hsi,
+        hse,
+        msi,
+        lsi,
+        lse,
+        pll1: pll_outputs[0].output,
+        pll2: pll_outputs[1].output,
+        pll3: pll_outputs[2].output,
+        pll4: pll_outputs[3].output,
+        ic1sel: ic1_src,
+        ic2sel: ic2_src,
+        ic6sel: ic6_src,
+        ic11sel: ic11_src,
+    }
+}
+
+fn is_new_pll_config(pll: Option<Pll>, pll_index: usize) -> bool {
+    let cfgr1 = RCC.pllcfgr1(pll_index).read();
+    let cfgr2 = RCC.pllcfgr2(pll_index).read();
+    let cfgr3 = RCC.pllcfgr3(pll_index).read();
+
+    let ready = RCC.sr().read().pllrdy(pll_index);
+    let bypass = cfgr1.pllbyp();
+
+    match (pll, ready, bypass) {
+        (None, true, _) => return true,
+        (Some(_), false, _) => return true,
+        (Some(conf), true, bypass) => match (conf, bypass) {
+            (Pll::Bypass { .. }, false) => return true,
+            (Pll::Oscillator { .. }, true) => return true,
+            _ => {}
+        },
+        _ => {}
+    }
+
+    match pll {
+        Some(Pll::Bypass { source }) => cfgr1.pllsel() != source,
+        Some(Pll::Oscillator {
+            source,
+            divm: m,
+            fractional,
+            divn: n,
+            divp1: p1,
+            divp2: p2,
+        }) => {
+            cfgr1.pllsel() != source
+                || cfgr1.plldivm() != m
+                || cfgr1.plldivn() != n
+                || cfgr2.plldivnfrac() != fractional
+                || cfgr3.pllpdiv1() != p1
+                || cfgr3.pllpdiv2() != p2
+        }
+        None => false,
+    }
+}
+
+pub(crate) unsafe fn init(config: Config) {
+    debug!("enabling SYSCFG");
+    // system configuration setup
+    RCC.apb4hensr().write(|w| w.set_syscfgens(true));
+    // delay after RCC peripheral clock enabling
+    RCC.apb4hensr().read();
+
+    debug!("setting VTOR");
+
+    let vtor = unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.vtor.read()
+    };
+
+    // set default vector table location after reset or standby
+    SYSCFG.initsvtorcr().write(|w| w.set_svtor_addr(vtor));
+    // read back the value to ensure it is written before deactivating SYSCFG
+    SYSCFG.initsvtorcr().read();
+
+    debug!("deactivating SYSCFG");
+
+    // deactivate SYSCFG
+    RCC.apb4hensr().write(|w| w.set_syscfgens(false));
+
+    debug!("enabling FPU");
+
+    // enable fpu
+    unsafe {
+        let p = cortex_m::Peripherals::steal();
+        p.SCB.cpacr.modify(|w| w | (3 << 20) | (3 << 22));
+    }
+
+    debug!("setting power supply config");
+
+    power_supply_config(config.supply_config);
+
+    let osc = init_osc(config);
+    let clock_inputs = ClocksInput {
+        hsi: osc.hsi,
+        msi: osc.msi,
+        hse: osc.hse,
+    };
+    let clocks = init_clocks(config, &clock_inputs);
+
+    // TODO: sysb, sysc, sysd must have the same clock source
+
+    set_clocks!(
+        sys: Some(clocks.sysclk),
+        hsi: osc.hsi,
+        hsi_div: None,
+        hse: osc.hse,
+        msi: osc.msi,
+        hclk1: Some(clocks.ahb),
+        hclk2: Some(clocks.ahb),
+        hclk3: Some(clocks.ahb),
+        hclk4: Some(clocks.ahb),
+        hclk5: Some(clocks.ahb),
+        pclk1: Some(clocks.apb1),
+        pclk2: Some(clocks.apb2),
+        pclk1_tim: Some(clocks.pclk_tim),
+        pclk2_tim: Some(clocks.pclk_tim),
+        pclk4: Some(clocks.apb4),
+        pclk5: Some(clocks.apb5),
+        per: None,
+        rtc: None,
+        i2s_ckin: None,
+        ic8: None,
+        ic9: None,
+        ic14: None,
+        ic17: None,
+        ic20: None,
+    );
+}
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index 06895a99a..7b0dcb63f 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -6,9 +6,9 @@ pub use crate::pac::rcc::vals::{
     Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::rcc::vals::{Hseext, Msipllfast, Msipllsel, Msirgsel, Pllmboost, Pllrge};
-#[cfg(all(peri_usb_otg_hs))]
-pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, PWR, RCC};
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::{SYSCFG, syscfg::vals::Usbrefcksel};
 use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 
@@ -442,7 +442,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 481437939..2528996d5 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -7,9 +7,9 @@ pub use crate::pac::rcc::vals::{
     Hdiv5, Hpre as AHBPrescaler, Hpre5 as AHB5Prescaler, Hsepre as HsePrescaler, Plldiv as PllDiv, Pllm as PllPreDiv,
     Plln as PllMul, Pllsrc as PllSource, Ppre as APBPrescaler, Sai1sel, Sw as Sysclk,
 };
-#[cfg(all(peri_usb_otg_hs))]
-pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, RCC};
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::{SYSCFG, syscfg::vals::Usbrefcksel};
 use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 
@@ -245,7 +245,10 @@ pub(crate) unsafe fn init(config: Config) {
             Hertz(24_000_000) => Usbrefcksel::MHZ24,
             Hertz(26_000_000) => Usbrefcksel::MHZ26,
             Hertz(32_000_000) => Usbrefcksel::MHZ32,
-            _ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+            _ => panic!(
+                "cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz",
+                clk_val
+            ),
         },
         None => Usbrefcksel::MHZ24,
     };
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index 63654639e..dada9bda1 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -9,7 +9,7 @@ use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, pac, peripherals, rcc, Peri};
+use crate::{Peri, interrupt, pac, peripherals, rcc};
 
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
 
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index a81ac6746..f049d6b12 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -1,10 +1,11 @@
 #[cfg(feature = "time")]
 use embassy_time::{Duration, TICK_HZ};
 
-use super::{bcd2_to_byte, DateTimeError, Rtc, RtcError};
+use super::{DateTimeError, Rtc, RtcError, bcd2_to_byte};
 use crate::interrupt::typelevel::Interrupt;
+use crate::pac::rtc::vals::Wucksel;
 use crate::peripherals::RTC;
-use crate::rtc::SealedInstance;
+use crate::rtc::{RtcTimeProvider, SealedInstance};
 
 /// Represents an instant in time that can be substracted to compute a duration
 pub(super) struct RtcInstant {
@@ -58,66 +59,22 @@ impl core::ops::Sub for RtcInstant {
     }
 }
 
-#[repr(u8)]
-#[derive(Clone, Copy, Debug)]
-pub(crate) enum WakeupPrescaler {
-    Div2 = 2,
-    Div4 = 4,
-    Div8 = 8,
-    Div16 = 16,
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
-))]
-impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
-    fn from(val: WakeupPrescaler) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            WakeupPrescaler::Div2 => Wucksel::DIV2,
-            WakeupPrescaler::Div4 => Wucksel::DIV4,
-            WakeupPrescaler::Div8 => Wucksel::DIV8,
-            WakeupPrescaler::Div16 => Wucksel::DIV16,
-        }
-    }
-}
-
-#[cfg(any(
-    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0, stm32wba
-))]
-impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
-    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            Wucksel::DIV2 => WakeupPrescaler::Div2,
-            Wucksel::DIV4 => WakeupPrescaler::Div4,
-            Wucksel::DIV8 => WakeupPrescaler::Div8,
-            Wucksel::DIV16 => WakeupPrescaler::Div16,
-            _ => unreachable!(),
-        }
-    }
-}
-
-impl WakeupPrescaler {
-    pub fn compute_min(val: u32) -> Self {
-        *[
-            WakeupPrescaler::Div2,
-            WakeupPrescaler::Div4,
-            WakeupPrescaler::Div8,
-            WakeupPrescaler::Div16,
-        ]
-        .iter()
-        .find(|psc| **psc as u32 > val)
-        .unwrap_or(&WakeupPrescaler::Div16)
-    }
+fn wucksel_compute_min(val: u32) -> (Wucksel, u32) {
+    *[
+        (Wucksel::DIV2, 2),
+        (Wucksel::DIV4, 4),
+        (Wucksel::DIV8, 8),
+        (Wucksel::DIV16, 16),
+    ]
+    .iter()
+    .find(|(_, psc)| *psc as u32 > val)
+    .unwrap_or(&(Wucksel::DIV16, 16))
 }
 
 impl Rtc {
     /// Return the current instant.
     fn instant(&self) -> Result<RtcInstant, RtcError> {
-        self.time_provider().read(|_, tr, ss| {
+        RtcTimeProvider::new().read(|_, tr, ss| {
             let second = bcd2_to_byte((tr.st(), tr.su()));
 
             RtcInstant::from(second, ss).map_err(RtcError::InvalidDateTime)
@@ -127,7 +84,7 @@ impl Rtc {
     /// start the wakeup alarm and with a duration that is as close to but less than
     /// the requested duration, and record the instant the wakeup alarm was started
     pub(crate) fn start_wakeup_alarm(
-        &self,
+        &mut self,
         requested_duration: embassy_time::Duration,
         cs: critical_section::CriticalSection,
     ) {
@@ -138,7 +95,7 @@ impl Rtc {
         let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
         let rtc_hz = Self::frequency().0 as u64;
         let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
-        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+        let (wucksel, prescaler) = wucksel_compute_min((rtc_ticks / u16::MAX as u64) as u32);
 
         // adjust the rtc ticks to the prescaler and subtract one rtc tick
         let rtc_ticks = rtc_ticks / prescaler as u64;
@@ -159,7 +116,7 @@ impl Rtc {
                 while !regs.icsr().read().wutwf() {}
             }
 
-            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+            regs.cr().modify(|w| w.set_wucksel(wucksel));
             regs.wutr().write(|w| w.set_wut(rtc_ticks));
             regs.cr().modify(|w| w.set_wute(true));
             regs.cr().modify(|w| w.set_wutie(true));
@@ -179,7 +136,10 @@ impl Rtc {
 
     /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
     /// was called, otherwise none
-    pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
+    pub(crate) fn stop_wakeup_alarm(
+        &mut self,
+        cs: critical_section::CriticalSection,
+    ) -> Option<embassy_time::Duration> {
         let instant = self.instant().unwrap();
         if RTC::regs().cr().read().wute() {
             trace!("rtc: stop wakeup alarm at {}", instant);
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index 92dec0960..e88bd7ab2 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -5,15 +5,19 @@ mod datetime;
 mod low_power;
 
 #[cfg(feature = "low-power")]
-use core::cell::Cell;
+use core::cell::{Cell, RefCell, RefMut};
+#[cfg(feature = "low-power")]
+use core::ops;
 
 #[cfg(feature = "low-power")]
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
+use critical_section::CriticalSection;
 #[cfg(feature = "low-power")]
 use embassy_sync::blocking_mutex::Mutex;
+#[cfg(feature = "low-power")]
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 
-use self::datetime::{day_of_week_from_u8, day_of_week_to_u8};
 pub use self::datetime::{DateTime, DayOfWeek, Error as DateTimeError};
+use self::datetime::{day_of_week_from_u8, day_of_week_to_u8};
 use crate::pac::rtc::regs::{Dr, Tr};
 use crate::time::Hertz;
 
@@ -25,8 +29,8 @@ mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
 
-use crate::peripherals::RTC;
 use crate::Peri;
+use crate::peripherals::RTC;
 
 /// Errors that can occur on methods on [RtcClock]
 #[non_exhaustive]
@@ -44,11 +48,17 @@ pub enum RtcError {
 }
 
 /// Provides immutable access to the current time of the RTC.
+#[derive(Clone)]
 pub struct RtcTimeProvider {
     _private: (),
 }
 
 impl RtcTimeProvider {
+    /// Create a new RTC time provider instance.
+    pub(self) const fn new() -> Self {
+        Self { _private: () }
+    }
+
     /// Return the current datetime.
     ///
     /// # Errors
@@ -106,6 +116,50 @@ impl RtcTimeProvider {
     }
 }
 
+#[cfg(feature = "low-power")]
+/// Contains an RTC driver.
+pub struct RtcContainer {
+    pub(self) mutex: &'static Mutex<CriticalSectionRawMutex, RefCell<Option<Rtc>>>,
+}
+
+#[cfg(feature = "low-power")]
+impl RtcContainer {
+    pub(self) const fn new() -> Self {
+        Self {
+            mutex: &crate::time_driver::get_driver().rtc,
+        }
+    }
+
+    /// Acquire an RTC borrow.
+    pub fn borrow_mut<'a>(&self, cs: CriticalSection<'a>) -> RtcBorrow<'a> {
+        RtcBorrow {
+            ref_mut: self.mutex.borrow(cs).borrow_mut(),
+        }
+    }
+}
+
+#[cfg(feature = "low-power")]
+/// Contains an RTC borrow.
+pub struct RtcBorrow<'a> {
+    pub(self) ref_mut: RefMut<'a, Option<Rtc>>,
+}
+
+#[cfg(feature = "low-power")]
+impl<'a> ops::Deref for RtcBorrow<'a> {
+    type Target = Rtc;
+
+    fn deref(&self) -> &Self::Target {
+        self.ref_mut.as_ref().unwrap()
+    }
+}
+
+#[cfg(feature = "low-power")]
+impl<'a> ops::DerefMut for RtcBorrow<'a> {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        self.ref_mut.as_mut().unwrap()
+    }
+}
+
 /// RTC driver.
 pub struct Rtc {
     #[cfg(feature = "low-power")]
@@ -121,13 +175,21 @@ pub struct RtcConfig {
     ///
     /// A high counter frequency may impact stop power consumption
     pub frequency: Hertz,
+
+    #[cfg(feature = "_allow-disable-rtc")]
+    /// Allow disabling the rtc, even when stop is configured
+    pub _disable_rtc: bool,
 }
 
 impl Default for RtcConfig {
     /// LSI with prescalers assuming 32.768 kHz.
     /// Raw sub-seconds in 1/256.
     fn default() -> Self {
-        RtcConfig { frequency: Hertz(256) }
+        RtcConfig {
+            frequency: Hertz(256),
+            #[cfg(feature = "_allow-disable-rtc")]
+            _disable_rtc: false,
+        }
     }
 }
 
@@ -145,8 +207,19 @@ pub enum RtcCalibrationCyclePeriod {
 }
 
 impl Rtc {
+    #[cfg(not(feature = "low-power"))]
     /// Create a new RTC instance.
-    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> Self {
+    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> (Self, RtcTimeProvider) {
+        (Self::new_inner(rtc_config), RtcTimeProvider::new())
+    }
+
+    #[cfg(feature = "low-power")]
+    /// Create a new RTC instance.
+    pub fn new(_rtc: Peri<'static, RTC>) -> (RtcContainer, RtcTimeProvider) {
+        (RtcContainer::new(), RtcTimeProvider::new())
+    }
+
+    pub(self) fn new_inner(rtc_config: RtcConfig) -> Self {
         #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
         crate::rcc::enable_and_reset::<RTC>();
 
@@ -165,10 +238,13 @@ impl Rtc {
         // Wait for the clock to update after initialization
         #[cfg(not(rtc_v2_f2))]
         {
-            let now = this.time_provider().read(|_, _, ss| Ok(ss)).unwrap();
-            while now == this.time_provider().read(|_, _, ss| Ok(ss)).unwrap() {}
+            let now = RtcTimeProvider::new().read(|_, _, ss| Ok(ss)).unwrap();
+            while now == RtcTimeProvider::new().read(|_, _, ss| Ok(ss)).unwrap() {}
         }
 
+        #[cfg(feature = "low-power")]
+        this.enable_wakeup_line();
+
         this
     }
 
@@ -177,11 +253,6 @@ impl Rtc {
         freqs.rtc.to_hertz().unwrap()
     }
 
-    /// Acquire a [`RtcTimeProvider`] instance.
-    pub const fn time_provider(&self) -> RtcTimeProvider {
-        RtcTimeProvider { _private: () }
-    }
-
     /// Set the datetime to a new value.
     ///
     /// # Errors
@@ -225,15 +296,6 @@ impl Rtc {
         Ok(())
     }
 
-    /// Return the current datetime.
-    ///
-    /// # Errors
-    ///
-    /// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
-    pub fn now(&self) -> Result<DateTime, RtcError> {
-        self.time_provider().now()
-    }
-
     /// Check if daylight savings time is active.
     pub fn get_daylight_savings(&self) -> bool {
         let cr = RTC::regs().cr().read();
@@ -315,3 +377,18 @@ trait SealedInstance {
 
     // fn apply_config(&mut self, rtc_config: RtcConfig);
 }
+
+#[cfg(feature = "low-power")]
+pub(crate) fn init_rtc(cs: CriticalSection, config: RtcConfig, min_stop_pause: embassy_time::Duration) {
+    use crate::time_driver::get_driver;
+
+    #[cfg(feature = "_allow-disable-rtc")]
+    if config._disable_rtc {
+        return;
+    }
+
+    get_driver().set_rtc(cs, Rtc::new_inner(config));
+    get_driver().set_min_stop_pause(cs, min_stop_pause);
+
+    trace!("low power: stop with rtc configured");
+}
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index 23f6ccb0c..8ac022536 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -93,7 +93,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index d0b52049e..f7ebea73e 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -1,4 +1,4 @@
-use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Key, Osel, Pol, TampalrmType};
+use stm32_metapac::rtc::vals::{Calp, Calw8, Calw16, Fmt, Key, Osel, Pol, TampalrmType};
 
 use super::RtcCalibrationCyclePeriod;
 use crate::pac::rtc::Rtc;
@@ -95,7 +95,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(crate::pac::rtc::Rtc) -> R,
     {
@@ -131,7 +131,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             const EXTI_WAKEUP_LINE: usize = 20;
         } else if #[cfg(stm32g0)] {
             const EXTI_WAKEUP_LINE: usize = 19;
@@ -142,7 +142,7 @@ impl SealedInstance for crate::peripherals::RTC {
 
     #[cfg(feature = "low-power")]
     cfg_if::cfg_if!(
-        if #[cfg(stm32g4)] {
+        if #[cfg(any(stm32g4, stm32wlex))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
         } else if #[cfg(any(stm32g0, stm32u0))] {
             type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index fb8b23b79..ce4bc43c3 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -6,12 +6,12 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 
 pub use crate::dma::word;
-use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer};
+use crate::dma::{Channel, ReadableRingBuffer, Request, TransferOptions, WritableRingBuffer, ringbuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 pub use crate::pac::sai::vals::Mckdiv as MasterClockDivider;
-use crate::pac::sai::{vals, Sai as Regs};
+use crate::pac::sai::{Sai as Regs, vals};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// SAI error
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -391,7 +391,7 @@ pub struct Config {
     pub frame_sync_polarity: FrameSyncPolarity,
     pub frame_sync_active_level_length: word::U7,
     pub frame_sync_definition: FrameSyncDefinition,
-    pub frame_length: u8,
+    pub frame_length: u16,
     pub clock_strobe: ClockStrobe,
     pub output_drive: OutputDrive,
     pub master_clock_divider: Option<MasterClockDivider>,
@@ -696,7 +696,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
             w.set_fspol(config.frame_sync_polarity.fspol());
             w.set_fsdef(config.frame_sync_definition.fsdef());
             w.set_fsall(config.frame_sync_active_level_length.0 as u8 - 1);
-            w.set_frl(config.frame_length - 1);
+            w.set_frl((config.frame_length - 1).try_into().unwrap());
         });
 
         ch.slotr().modify(|w| {
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index ccbd16cbf..e05131040 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -11,9 +11,9 @@ use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 use sdio_host::common_cmd::{self, Resp, ResponseLen};
-use sdio_host::emmc::{ExtCSD, EMMC};
-use sdio_host::sd::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CIC, CID, CSD, OCR, RCA, SCR, SD};
-use sdio_host::{emmc_cmd, sd_cmd, Cmd};
+use sdio_host::emmc::{EMMC, ExtCSD};
+use sdio_host::sd::{BusWidth, CIC, CID, CSD, CardCapacity, CardStatus, CurrentState, OCR, RCA, SCR, SD, SDStatus};
+use sdio_host::{Cmd, emmc_cmd, sd_cmd};
 
 #[cfg(sdmmc_v1)]
 use crate::dma::ChannelAndRequest;
@@ -1032,12 +1032,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
 
     /// Wait for a previously started datapath transfer to complete from an interrupt.
     #[inline]
+    #[allow(unused)]
     async fn complete_datapath_transfer(block: bool) -> Result<(), Error> {
-        let regs = T::regs();
-
         let res = poll_fn(|cx| {
+            // Compiler might not be sufficiently constrained here
+            // https://github.com/embassy-rs/embassy/issues/4723
             T::state().register(cx.waker());
-            let status = regs.star().read();
+            let status = T::regs().star().read();
 
             if status.dcrcfail() {
                 return Poll::Ready(Err(Error::Crc));
@@ -1052,10 +1053,13 @@ impl<'d, T: Instance> Sdmmc<'d, T> {
             if status.stbiterr() {
                 return Poll::Ready(Err(Error::StBitErr));
             }
+            #[cfg(sdmmc_v1)]
             let done = match block {
                 true => status.dbckend(),
                 false => status.dataend(),
             };
+            #[cfg(sdmmc_v2)]
+            let done = status.dataend();
             if done {
                 return Poll::Ready(Ok(()));
             }
diff --git a/embassy-stm32/src/spdifrx/mod.rs b/embassy-stm32/src/spdifrx/mod.rs
index b0a32d5d1..6f2d24560 100644
--- a/embassy-stm32/src/spdifrx/mod.rs
+++ b/embassy-stm32/src/spdifrx/mod.rs
@@ -13,7 +13,7 @@ use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::spdifrx::Spdifrx as Regs;
 use crate::rcc::{RccInfo, SealedRccPeripheral};
-use crate::{interrupt, peripherals, Peri};
+use crate::{Peri, interrupt, peripherals};
 
 /// Possible S/PDIF preamble types.
 #[allow(dead_code)]
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index c5373a54d..abb80ed26 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -6,15 +6,15 @@ use core::ptr;
 
 use embassy_embedded_hal::SetConfig;
 use embassy_futures::join::join;
-pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
+pub use embedded_hal_02::spi::{MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity};
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::Peri;
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::spi::{regs, vals, Spi as Regs};
+use crate::pac::spi::{Spi as Regs, regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// SPI error.
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -125,26 +125,69 @@ impl Config {
         )
     }
 }
+
+/// SPI communication mode
+pub mod mode {
+    use stm32_metapac::spi::vals;
+
+    trait SealedMode {}
+
+    /// Trait for SPI communication mode operations.
+    #[allow(private_bounds)]
+    pub trait CommunicationMode: SealedMode {
+        /// Spi communication mode
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr;
+        /// Spi communication mode
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master;
+    }
+
+    /// Mode allowing for SPI master operations.
+    pub struct Master;
+    /// Mode allowing for SPI slave operations.
+    pub struct Slave;
+
+    impl SealedMode for Master {}
+    impl CommunicationMode for Master {
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr = vals::Mstr::MASTER;
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master = vals::Master::MASTER;
+    }
+
+    impl SealedMode for Slave {}
+    impl CommunicationMode for Slave {
+        #[cfg(not(any(spi_v4, spi_v5, spi_v6)))]
+        const MASTER: vals::Mstr = vals::Mstr::SLAVE;
+        #[cfg(any(spi_v4, spi_v5, spi_v6))]
+        const MASTER: vals::Master = vals::Master::SLAVE;
+    }
+}
+use mode::{CommunicationMode, Master, Slave};
+
 /// SPI driver.
-pub struct Spi<'d, M: PeriMode> {
+pub struct Spi<'d, M: PeriMode, CM: CommunicationMode> {
     pub(crate) info: &'static Info,
     kernel_clock: Hertz,
     sck: Option<Peri<'d, AnyPin>>,
     mosi: Option<Peri<'d, AnyPin>>,
     miso: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
     tx_dma: Option<ChannelAndRequest<'d>>,
     rx_dma: Option<ChannelAndRequest<'d>>,
-    _phantom: PhantomData<M>,
+    _phantom: PhantomData<(M, CM)>,
     current_word_size: word_impl::Config,
     gpio_speed: Speed,
 }
 
-impl<'d, M: PeriMode> Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> Spi<'d, M, CM> {
     fn new_inner<T: Instance>(
         _peri: Peri<'d, T>,
         sck: Option<Peri<'d, AnyPin>>,
         mosi: Option<Peri<'d, AnyPin>>,
         miso: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
         tx_dma: Option<ChannelAndRequest<'d>>,
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
@@ -155,6 +198,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
             sck,
             mosi,
             miso,
+            nss,
             tx_dma,
             rx_dma,
             current_word_size: <u8 as SealedWord>::CONFIG,
@@ -183,12 +227,12 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
 
-                w.set_mstr(vals::Mstr::MASTER);
+                w.set_mstr(CM::MASTER);
                 w.set_br(br);
                 w.set_spe(true);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssi(true);
-                w.set_ssm(true);
+                w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 // we're doing "fake rxonly", by actually writing one
@@ -210,11 +254,11 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
 
-                w.set_mstr(vals::Mstr::MASTER);
+                w.set_mstr(CM::MASTER);
                 w.set_br(br);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssi(true);
-                w.set_ssm(true);
+                w.set_ssi(CM::MASTER == vals::Mstr::MASTER);
+                w.set_ssm(CM::MASTER == vals::Mstr::MASTER);
                 w.set_crcen(false);
                 w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
                 w.set_spe(true);
@@ -229,8 +273,8 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                 w.set_cpha(cpha);
                 w.set_cpol(cpol);
                 w.set_lsbfirst(lsbfirst);
-                w.set_ssm(true);
-                w.set_master(vals::Master::MASTER);
+                w.set_ssm(CM::MASTER == vals::Master::MASTER);
+                w.set_master(CM::MASTER);
                 w.set_comm(vals::Comm::FULL_DUPLEX);
                 w.set_ssom(vals::Ssom::ASSERTED);
                 w.set_midi(0);
@@ -469,7 +513,30 @@ impl<'d, M: PeriMode> Spi<'d, M> {
     }
 }
 
-impl<'d> Spi<'d, Blocking> {
+impl<'d> Spi<'d, Blocking, Slave> {
+    /// Create a new blocking SPI slave driver.
+    pub fn new_blocking_slave<T: Instance, #[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        cs: Peri<'d, if_afio!(impl CsPin<T, A>)>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(sck, config.sck_af()),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(miso, AfType::input(config.miso_pull)),
+            new_pin!(cs, AfType::input(Pull::None)),
+            None,
+            None,
+            config,
+        )
+    }
+}
+
+impl<'d> Spi<'d, Blocking, Master> {
     /// Create a new blocking SPI driver.
     pub fn new_blocking<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
@@ -485,6 +552,7 @@ impl<'d> Spi<'d, Blocking> {
             new_pin!(miso, AfType::input(config.miso_pull)),
             None,
             None,
+            None,
             config,
         )
     }
@@ -503,6 +571,7 @@ impl<'d> Spi<'d, Blocking> {
             new_pin!(miso, AfType::input(config.miso_pull)),
             None,
             None,
+            None,
             config,
         )
     }
@@ -521,6 +590,7 @@ impl<'d> Spi<'d, Blocking> {
             None,
             None,
             None,
+            None,
             config,
         )
     }
@@ -540,12 +610,38 @@ impl<'d> Spi<'d, Blocking> {
             None,
             None,
             None,
+            None,
             config,
         )
     }
 }
 
-impl<'d> Spi<'d, Async> {
+impl<'d> Spi<'d, Async, Slave> {
+    /// Create a new SPI slave driver.
+    pub fn new_slave<T: Instance, #[cfg(afio)] A>(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, if_afio!(impl SckPin<T, A>)>,
+        mosi: Peri<'d, if_afio!(impl MosiPin<T, A>)>,
+        miso: Peri<'d, if_afio!(impl MisoPin<T, A>)>,
+        cs: Peri<'d, if_afio!(impl CsPin<T, A>)>,
+        tx_dma: Peri<'d, impl TxDma<T>>,
+        rx_dma: Peri<'d, impl RxDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(sck, config.sck_af()),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
+            new_pin!(miso, AfType::input(config.miso_pull)),
+            new_pin!(cs, AfType::input(Pull::None)),
+            new_dma!(tx_dma),
+            new_dma!(rx_dma),
+            config,
+        )
+    }
+}
+
+impl<'d> Spi<'d, Async, Master> {
     /// Create a new SPI driver.
     pub fn new<T: Instance, #[cfg(afio)] A>(
         peri: Peri<'d, T>,
@@ -561,6 +657,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             new_pin!(miso, AfType::input(config.miso_pull)),
+            None,
             new_dma!(tx_dma),
             new_dma!(rx_dma),
             config,
@@ -581,6 +678,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             None,
             new_pin!(miso, AfType::input(config.miso_pull)),
+            None,
             #[cfg(any(spi_v1, spi_v2, spi_v3))]
             new_dma!(tx_dma),
             #[cfg(any(spi_v4, spi_v5, spi_v6))]
@@ -603,6 +701,7 @@ impl<'d> Spi<'d, Async> {
             new_pin!(sck, config.sck_af()),
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             None,
+            None,
             new_dma!(tx_dma),
             None,
             config,
@@ -623,6 +722,7 @@ impl<'d> Spi<'d, Async> {
             None,
             new_pin!(mosi, AfType::output(OutputType::PushPull, config.gpio_speed)),
             None,
+            None,
             new_dma!(tx_dma),
             None,
             config,
@@ -646,7 +746,7 @@ impl<'d> Spi<'d, Async> {
         config.bit_order = BitOrder::MsbFirst;
         config.frequency = freq;
 
-        Self::new_inner(peri, None, None, None, new_dma!(tx_dma), new_dma!(rx_dma), config)
+        Self::new_inner(peri, None, None, None, None, new_dma!(tx_dma), new_dma!(rx_dma), config)
     }
 
     #[allow(dead_code)]
@@ -656,9 +756,11 @@ impl<'d> Spi<'d, Async> {
         rx_dma: Option<ChannelAndRequest<'d>>,
         config: Config,
     ) -> Self {
-        Self::new_inner(peri, None, None, None, tx_dma, rx_dma, config)
+        Self::new_inner(peri, None, None, None, None, tx_dma, rx_dma, config)
     }
+}
 
+impl<'d, CM: CommunicationMode> Spi<'d, Async, CM> {
     /// SPI write, using DMA.
     pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
         if data.is_empty() {
@@ -888,11 +990,12 @@ impl<'d> Spi<'d, Async> {
     }
 }
 
-impl<'d, M: PeriMode> Drop for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> Drop for Spi<'d, M, CM> {
     fn drop(&mut self) {
         self.sck.as_ref().map(|x| x.set_as_disconnected());
         self.mosi.as_ref().map(|x| x.set_as_disconnected());
         self.miso.as_ref().map(|x| x.set_as_disconnected());
+        self.nss.as_ref().map(|x| x.set_as_disconnected());
 
         self.info.rcc.disable();
     }
@@ -1127,7 +1230,7 @@ fn write_word<W: Word>(regs: Regs, tx_word: W) -> Result<(), Error> {
 // some marker traits. For details, see https://github.com/rust-embedded/embedded-hal/pull/289
 macro_rules! impl_blocking {
     ($w:ident) => {
-        impl<'d, M: PeriMode> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, M> {
+        impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_02::blocking::spi::Write<$w> for Spi<'d, M, CM> {
             type Error = Error;
 
             fn write(&mut self, words: &[$w]) -> Result<(), Self::Error> {
@@ -1135,7 +1238,7 @@ macro_rules! impl_blocking {
             }
         }
 
-        impl<'d, M: PeriMode> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, M> {
+        impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_02::blocking::spi::Transfer<$w> for Spi<'d, M, CM> {
             type Error = Error;
 
             fn transfer<'w>(&mut self, words: &'w mut [$w]) -> Result<&'w [$w], Self::Error> {
@@ -1149,11 +1252,11 @@ macro_rules! impl_blocking {
 impl_blocking!(u8);
 impl_blocking!(u16);
 
-impl<'d, M: PeriMode> embedded_hal_1::spi::ErrorType for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> embedded_hal_1::spi::ErrorType for Spi<'d, M, CM> {
     type Error = Error;
 }
 
-impl<'d, W: Word, M: PeriMode> embedded_hal_1::spi::SpiBus<W> for Spi<'d, M> {
+impl<'d, W: Word, M: PeriMode, CM: CommunicationMode> embedded_hal_1::spi::SpiBus<W> for Spi<'d, M, CM> {
     fn flush(&mut self) -> Result<(), Self::Error> {
         Ok(())
     }
@@ -1186,7 +1289,7 @@ impl embedded_hal_1::spi::Error for Error {
     }
 }
 
-impl<'d, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async> {
+impl<'d, W: Word, CM: CommunicationMode> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async, CM> {
     async fn flush(&mut self) -> Result<(), Self::Error> {
         Ok(())
     }
@@ -1328,7 +1431,7 @@ foreach_peripheral!(
     };
 );
 
-impl<'d, M: PeriMode> SetConfig for Spi<'d, M> {
+impl<'d, M: PeriMode, CM: CommunicationMode> SetConfig for Spi<'d, M, CM> {
     type Config = Config;
     type ConfigError = ();
     fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index 7db74bdf6..0b75aef92 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,14 +1,16 @@
 #![allow(non_snake_case)]
 
 use core::cell::{Cell, RefCell};
-use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
+#[cfg(all(feature = "low-power", stm32wlex))]
+use core::sync::atomic::AtomicU16;
+use core::sync::atomic::{AtomicU32, Ordering, compiler_fence};
 
 use critical_section::CriticalSection;
-use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::blocking_mutex::Mutex;
+use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_time_driver::{Driver, TICK_HZ};
 use embassy_time_queue_utils::Queue;
-use stm32_metapac::timer::{regs, TimGp16};
+use stm32_metapac::timer::{TimGp16, regs};
 
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::timer::vals;
@@ -194,6 +196,11 @@ fn calc_now(period: u32, counter: u16) -> u64 {
     ((period as u64) << 15) + ((counter as u32 ^ ((period & 1) << 15)) as u64)
 }
 
+#[cfg(feature = "low-power")]
+fn calc_period_counter(ticks: u64) -> (u32, u16) {
+    (2 * (ticks >> 16) as u32 + (ticks as u16 >= 0x8000) as u32, ticks as u16)
+}
+
 struct AlarmState {
     timestamp: Cell<u64>,
 }
@@ -213,7 +220,13 @@ pub(crate) struct RtcDriver {
     period: AtomicU32,
     alarm: Mutex<CriticalSectionRawMutex, AlarmState>,
     #[cfg(feature = "low-power")]
-    rtc: Mutex<CriticalSectionRawMutex, Cell<Option<&'static Rtc>>>,
+    pub(crate) rtc: Mutex<CriticalSectionRawMutex, RefCell<Option<Rtc>>>,
+    #[cfg(feature = "low-power")]
+    /// The minimum pause time beyond which the executor will enter a low-power state.
+    min_stop_pause: Mutex<CriticalSectionRawMutex, Cell<embassy_time::Duration>>,
+    /// Saved count for the timer (its value is lost when entering STOP2)
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16,
     queue: Mutex<CriticalSectionRawMutex, RefCell<Queue>>,
 }
 
@@ -221,12 +234,18 @@ embassy_time_driver::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
     period: AtomicU32::new(0),
     alarm: Mutex::const_new(CriticalSectionRawMutex::new(), AlarmState::new()),
     #[cfg(feature = "low-power")]
-    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(None)),
+    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), RefCell::new(None)),
+    #[cfg(feature = "low-power")]
+    min_stop_pause: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(embassy_time::Duration::from_millis(0))),
+    #[cfg(all(feature = "low-power", stm32wlex))]
+    saved_count: AtomicU16::new(0),
     queue: Mutex::new(RefCell::new(Queue::new()))
 });
 
 impl RtcDriver {
-    fn init(&'static self, cs: critical_section::CriticalSection) {
+    /// initialize the timer, but don't start it.  Used for chips like stm32wle5
+    /// for low power where the timer config is lost in STOP2.
+    pub(crate) fn init_timer(&'static self, cs: critical_section::CriticalSection) {
         let r = regs_gp16();
 
         rcc::enable_and_reset_with_cs::<T>(cs);
@@ -259,10 +278,16 @@ impl RtcDriver {
             w.set_ccie(0, true);
         });
 
+        #[cfg(all(feature = "low-power", stm32wlex))]
+        r.cnt().write(|w| w.set_cnt(self.saved_count.load(Ordering::SeqCst)));
+
         <T as GeneralInstance1Channel>::CaptureCompareInterrupt::unpend();
         unsafe { <T as GeneralInstance1Channel>::CaptureCompareInterrupt::enable() };
+    }
 
-        r.cr1().modify(|w| w.set_cen(true));
+    fn init(&'static self, cs: CriticalSection) {
+        self.init_timer(cs);
+        regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
     fn on_interrupt(&self) {
@@ -338,34 +363,10 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Add the given offset to the current time
     fn add_time(&self, offset: embassy_time::Duration, cs: CriticalSection) {
-        let offset = offset.as_ticks();
-        let cnt = regs_gp16().cnt().read().cnt() as u32;
-        let period = self.period.load(Ordering::SeqCst);
-
-        // Correct the race, if it exists
-        let period = if period & 1 == 1 && cnt < u16::MAX as u32 / 2 {
-            period + 1
-        } else {
-            period
-        };
-
-        // Normalize to the full overflow
-        let period = (period / 2) * 2;
-
-        // Add the offset
-        let period = period + 2 * (offset / u16::MAX as u64) as u32;
-        let cnt = cnt + (offset % u16::MAX as u64) as u32;
-
-        let (cnt, period) = if cnt > u16::MAX as u32 {
-            (cnt - u16::MAX as u32, period + 2)
-        } else {
-            (cnt, period)
-        };
-
-        let period = if cnt > u16::MAX as u32 / 2 { period + 1 } else { period };
+        let (period, counter) = calc_period_counter(self.now() + offset.as_ticks());
 
         self.period.store(period, Ordering::SeqCst);
-        regs_gp16().cnt().write(|w| w.set_cnt(cnt as u16));
+        regs_gp16().cnt().write(|w| w.set_cnt(counter));
 
         // Now, recompute alarm
         let alarm = self.alarm.borrow(cs);
@@ -379,70 +380,64 @@ impl RtcDriver {
     #[cfg(feature = "low-power")]
     /// Stop the wakeup alarm, if enabled, and add the appropriate offset
     fn stop_wakeup_alarm(&self, cs: CriticalSection) {
-        if let Some(offset) = self.rtc.borrow(cs).get().unwrap().stop_wakeup_alarm(cs) {
+        if !regs_gp16().cr1().read().cen()
+            && let Some(offset) = self.rtc.borrow(cs).borrow_mut().as_mut().unwrap().stop_wakeup_alarm(cs)
+        {
             self.add_time(offset, cs);
         }
     }
 
     /*
-        Low-power public functions: all create a critical section
+        Low-power public functions: all require a critical section
     */
     #[cfg(feature = "low-power")]
-    /// Set the rtc but panic if it's already been set
-    pub(crate) fn set_rtc(&self, rtc: &'static Rtc) {
-        critical_section::with(|cs| {
-            rtc.stop_wakeup_alarm(cs);
-
-            assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none())
-        });
+    pub(crate) fn set_min_stop_pause(&self, cs: CriticalSection, min_stop_pause: embassy_time::Duration) {
+        self.min_stop_pause.borrow(cs).replace(min_stop_pause);
     }
 
     #[cfg(feature = "low-power")]
-    /// The minimum pause time beyond which the executor will enter a low-power state.
-    pub(crate) const MIN_STOP_PAUSE: embassy_time::Duration = embassy_time::Duration::from_millis(250);
+    /// Set the rtc but panic if it's already been set
+    pub(crate) fn set_rtc(&self, cs: CriticalSection, mut rtc: Rtc) {
+        rtc.stop_wakeup_alarm(cs);
+
+        assert!(self.rtc.borrow(cs).replace(Some(rtc)).is_none());
+    }
 
     #[cfg(feature = "low-power")]
     /// Pause the timer if ready; return err if not
-    pub(crate) fn pause_time(&self) -> Result<(), ()> {
-        critical_section::with(|cs| {
-            /*
-                If the wakeup timer is currently running, then we need to stop it and
-                add the elapsed time to the current time, as this will impact the result
-                of `time_until_next_alarm`.
-            */
-            self.stop_wakeup_alarm(cs);
-
-            let time_until_next_alarm = self.time_until_next_alarm(cs);
-            if time_until_next_alarm < Self::MIN_STOP_PAUSE {
-                Err(())
-            } else {
-                self.rtc
-                    .borrow(cs)
-                    .get()
-                    .unwrap()
-                    .start_wakeup_alarm(time_until_next_alarm, cs);
-
-                regs_gp16().cr1().modify(|w| w.set_cen(false));
-
-                Ok(())
-            }
-        })
+    pub(crate) fn pause_time(&self, cs: CriticalSection) -> Result<(), ()> {
+        self.stop_wakeup_alarm(cs);
+
+        let time_until_next_alarm = self.time_until_next_alarm(cs);
+        if time_until_next_alarm < self.min_stop_pause.borrow(cs).get() {
+            trace!(
+                "time_until_next_alarm < self.min_stop_pause ({})",
+                time_until_next_alarm
+            );
+            Err(())
+        } else {
+            self.rtc
+                .borrow(cs)
+                .borrow_mut()
+                .as_mut()
+                .unwrap()
+                .start_wakeup_alarm(time_until_next_alarm, cs);
+
+            regs_gp16().cr1().modify(|w| w.set_cen(false));
+            // save the count for the timer as its lost in STOP2 for stm32wlex
+            #[cfg(stm32wlex)]
+            self.saved_count
+                .store(regs_gp16().cnt().read().cnt() as u16, Ordering::SeqCst);
+            Ok(())
+        }
     }
 
     #[cfg(feature = "low-power")]
     /// Resume the timer with the given offset
-    pub(crate) fn resume_time(&self) {
-        if regs_gp16().cr1().read().cen() {
-            // Time isn't currently stopped
+    pub(crate) fn resume_time(&self, cs: CriticalSection) {
+        self.stop_wakeup_alarm(cs);
 
-            return;
-        }
-
-        critical_section::with(|cs| {
-            self.stop_wakeup_alarm(cs);
-
-            regs_gp16().cr1().modify(|w| w.set_cen(true));
-        })
+        regs_gp16().cr1().modify(|w| w.set_cen(true));
     }
 
     fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
@@ -514,7 +509,7 @@ impl Driver for RtcDriver {
 }
 
 #[cfg(feature = "low-power")]
-pub(crate) fn get_driver() -> &'static RtcDriver {
+pub(crate) const fn get_driver() -> &'static RtcDriver {
     &DRIVER
 }
 
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 484aae1d0..6d4c70dff 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,16 +2,16 @@
 
 use core::marker::PhantomData;
 
-pub use stm32_metapac::timer::vals::{Ckd, Ossi, Ossr};
+pub use stm32_metapac::timer::vals::{Ckd, Mms2, Ossi, Ossr};
 
 use super::low_level::{CountingMode, OutputPolarity, Timer};
 use super::simple_pwm::PwmPin;
 use super::{AdvancedInstance4Channel, Ch1, Ch2, Ch3, Ch4, Channel, TimerComplementaryPin};
+use crate::Peri;
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
-use crate::timer::low_level::OutputCompareMode;
 use crate::timer::TimerChannel;
-use crate::Peri;
+use crate::timer::low_level::OutputCompareMode;
 
 /// Complementary PWM pin wrapper.
 ///
@@ -77,8 +77,6 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
-        this.inner.start();
-
         this.inner.enable_outputs();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
@@ -89,6 +87,10 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
             });
         this.inner.set_autoreload_preload(true);
 
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
+
         this
     }
 
@@ -136,6 +138,16 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
         self.inner.get_moe()
     }
 
+    /// Set Master Slave Mode 2
+    pub fn set_mms2(&mut self, mms2: Mms2) {
+        self.inner.set_mms2_selection(mms2);
+    }
+
+    /// Set Repetition Counter
+    pub fn set_repetition_counter(&mut self, val: u16) {
+        self.inner.set_repetition_counter(val);
+    }
+
     /// Enable the given channel.
     pub fn enable(&mut self, channel: Channel) {
         self.inner.enable_channel(channel, true);
@@ -150,8 +162,8 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
             2u8
@@ -208,60 +220,57 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
     ///
     /// Note:
     /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    #[inline(always)]
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_duty_state = self.inner.get_compare_value(channel);
-        let original_enable_state = self.inner.get_channel_enable_state(channel);
-        let original_update_dma_state = self.inner.get_update_dma_state();
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        if !original_enable_state {
-            self.inner.enable_channel(channel, true);
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            Transfer::new_write(
-                dma,
-                req,
-                duty,
-                self.inner.regs_gp16().ccr(channel.index()).as_ptr() as *mut u16,
-                dma_transfer_option,
-            )
-            .await
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.inner.enable_channel(channel, false);
-        }
+        self.inner.waveform_up(dma, channel, duty).await
+    }
 
-        self.inner.set_compare_value(channel, original_duty_state);
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// ```rust,ignore
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    /// ```
+    ///
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
+    #[inline(always)]
+    pub async fn waveform_up_multi_channel(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &[u16],
+    ) {
+        self.inner
+            .waveform_up_multi_channel(dma, starting_channel, ending_channel, duty)
+            .await;
+    }
 
-        // Since DMA is closed before timer update event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
+    /// Generate a sequence of PWM waveform
+    #[inline(always)]
+    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
+        self.inner.waveform(dma, duty).await;
     }
 }
 
@@ -388,7 +397,7 @@ fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
 
 #[cfg(test)]
 mod tests {
-    use super::{compute_dead_time_value, Ckd};
+    use super::{Ckd, compute_dead_time_value};
 
     #[test]
     fn test_compute_dead_time_value() {
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 7a25e6c21..9cf0f8c34 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -8,11 +8,11 @@ use core::task::{Context, Poll};
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
 use super::{CaptureCompareInterruptHandler, Channel, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2, Ch3, Ch4};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
-use crate::Peri;
 
 /// Capture pin wrapper.
 ///
@@ -60,6 +60,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.inner.set_tick_freq(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        this.inner.generate_update_event();
         this.inner.start();
 
         // enable NVIC interrupt
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index ac039bb0d..f0105ece8 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -10,12 +10,12 @@ use core::mem::ManuallyDrop;
 
 use embassy_hal_internal::Peri;
 // Re-export useful enums
-pub use stm32_metapac::timer::vals::{FilterValue, Sms as SlaveMode, Ts as TriggerSource};
+pub use stm32_metapac::timer::vals::{FilterValue, Mms as MasterMode, Sms as SlaveMode, Ts as TriggerSource};
 
 use super::*;
 use crate::pac::timer::vals;
-use crate::rcc;
 use crate::time::Hertz;
+use crate::{dma, rcc};
 
 /// Input capture mode.
 #[derive(Clone, Copy)]
@@ -143,20 +143,69 @@ pub enum OutputCompareMode {
     /// TIMx_CNT<TIMx_CCRx else active. In downcounting, channel is active as long as
     /// TIMx_CNT>TIMx_CCRx else inactive.
     PwmMode2,
-    // TODO: there's more modes here depending on the chip family.
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is active until a trigger
+    /// event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
+    /// mode 1 and the channels becomes active again at the next update. In down-counting
+    /// mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
+    /// Then, a comparison is performed as in PWM mode 1 and the channels becomes
+    /// inactive again at the next update.
+    OnePulseMode1,
+
+    #[cfg(timer_v2)]
+    /// In up-counting mode, the channel is inactive until a
+    /// trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
+    /// PWM mode 2 and the channels becomes inactive again at the next update. In down
+    /// counting mode, the channel is active until a trigger event is detected (on tim_trgi
+    /// signal). Then, a comparison is performed as in PWM mode 1 and the channels
+    /// becomes active again at the next update.
+    OnePulseMode2,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 1 - tim_oc1ref has the same behavior as in PWM mode 1.
+    /// tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// Combined PWM mode 2 - tim_oc1ref has the same behavior as in PWM mode 2.
+    /// tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
+    CombinedPwmMode2,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode1,
+
+    #[cfg(timer_v2)]
+    /// tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref
+    /// when the counter is counting up, tim_oc2ref when it is counting down.
+    AsymmetricPwmMode2,
 }
 
-impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
+impl From<OutputCompareMode> for crate::pac::timer::vals::Ocm {
     fn from(mode: OutputCompareMode) -> Self {
         match mode {
-            OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN,
-            OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH,
-            OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH,
-            OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE,
-            OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE,
-            OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE,
-            OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1,
-            OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2,
+            OutputCompareMode::Frozen => crate::pac::timer::vals::Ocm::FROZEN,
+            OutputCompareMode::ActiveOnMatch => crate::pac::timer::vals::Ocm::ACTIVE_ON_MATCH,
+            OutputCompareMode::InactiveOnMatch => crate::pac::timer::vals::Ocm::INACTIVE_ON_MATCH,
+            OutputCompareMode::Toggle => crate::pac::timer::vals::Ocm::TOGGLE,
+            OutputCompareMode::ForceInactive => crate::pac::timer::vals::Ocm::FORCE_INACTIVE,
+            OutputCompareMode::ForceActive => crate::pac::timer::vals::Ocm::FORCE_ACTIVE,
+            OutputCompareMode::PwmMode1 => crate::pac::timer::vals::Ocm::PWM_MODE1,
+            OutputCompareMode::PwmMode2 => crate::pac::timer::vals::Ocm::PWM_MODE2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode1 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::OnePulseMode2 => crate::pac::timer::vals::Ocm::RETRIGERRABLE_OPM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode1 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::CombinedPwmMode2 => crate::pac::timer::vals::Ocm::COMBINED_PWM_MODE_2,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode1 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_1,
+            #[cfg(timer_v2)]
+            OutputCompareMode::AsymmetricPwmMode2 => crate::pac::timer::vals::Ocm::ASYMMETRIC_PWM_MODE_2,
         }
     }
 }
@@ -223,6 +272,17 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
         self.regs_core().cr1().modify(|r| r.set_cen(true));
     }
 
+    /// Generate timer update event from software.
+    ///
+    /// Set URS to avoid generating interrupt or DMA request. This update event is only
+    /// used to load value from pre-load registers. If called when the timer is running,
+    /// it may disrupt the output waveform.
+    pub fn generate_update_event(&self) {
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+        self.regs_core().egr().write(|r| r.set_ug(true));
+        self.regs_core().cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+    }
+
     /// Stop the timer.
     pub fn stop(&self) {
         self.regs_core().cr1().modify(|r| r.set_cen(false));
@@ -273,10 +333,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_core();
                 regs.psc().write_value(psc);
                 regs.arr().write(|r| r.set_arr(arr));
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
             #[cfg(not(stm32l0))]
             TimerBits::Bits32 => {
@@ -286,10 +342,6 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                 let regs = self.regs_gp32_unchecked();
                 regs.psc().write_value(psc);
                 regs.arr().write_value(arr);
-
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
-                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
             }
         }
     }
@@ -607,6 +659,219 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         }
     }
 
+    /// Generate a sequence of PWM waveform
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_update_dma_state = self.get_update_dma_state();
+
+        if !original_update_dma_state {
+            self.enable_update_dma(true);
+        }
+
+        self.waveform_helper(dma, req, channel, duty).await;
+
+        // Since DMA is closed before timer update event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_update_dma_state {
+            self.enable_update_dma(false);
+        }
+    }
+
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// ```rust,ignore
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    /// ```
+    ///
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
+    pub async fn waveform_up_multi_channel(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &[u16],
+    ) {
+        let cr1_addr = self.regs_gp16().cr1().as_ptr() as u32;
+        let start_ch_index = starting_channel.index();
+        let end_ch_index = ending_channel.index();
+
+        assert!(start_ch_index <= end_ch_index);
+
+        let ccrx_addr = self.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
+        self.regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
+        self.regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let original_update_dma_state = self.get_update_dma_state();
+        if !original_update_dma_state {
+            self.enable_update_dma(true);
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr4,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.regs_gp16().dmar().as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+            .await
+        };
+
+        if !original_update_dma_state {
+            self.enable_update_dma(false);
+        }
+    }
+
+    /// Generate a sequence of PWM waveform
+    pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
+        use crate::pac::timer::vals::Ccds;
+
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+
+        let cc_channel = C::CHANNEL;
+
+        let original_cc_dma_on_update = self.get_cc_dma_selection() == Ccds::ON_UPDATE;
+        let original_cc_dma_enabled = self.get_cc_dma_enable_state(cc_channel);
+
+        // redirect CC DMA request onto Update Event
+        if !original_cc_dma_on_update {
+            self.set_cc_dma_selection(Ccds::ON_UPDATE)
+        }
+
+        if !original_cc_dma_enabled {
+            self.set_cc_dma_enable_state(cc_channel, true);
+        }
+
+        self.waveform_helper(dma, req, cc_channel, duty).await;
+
+        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
+        // this can almost always trigger a DMA FIFO error.
+        //
+        // optional TODO:
+        // clean FEIF after disable UDE
+        if !original_cc_dma_enabled {
+            self.set_cc_dma_enable_state(cc_channel, false);
+        }
+
+        if !original_cc_dma_on_update {
+            self.set_cc_dma_selection(Ccds::ON_COMPARE)
+        }
+    }
+
+    async fn waveform_helper(
+        &mut self,
+        dma: Peri<'_, impl dma::Channel>,
+        req: dma::Request,
+        channel: Channel,
+        duty: &[u16],
+    ) {
+        let original_duty_state = self.get_compare_value(channel);
+        let original_enable_state = self.get_channel_enable_state(channel);
+
+        if !original_enable_state {
+            self.enable_channel(channel, true);
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            match self.bits() {
+                TimerBits::Bits16 => {
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+                #[cfg(not(any(stm32l0)))]
+                TimerBits::Bits32 => {
+                    #[cfg(not(any(bdma, gpdma)))]
+                    panic!("unsupported timer bits");
+
+                    #[cfg(any(bdma, gpdma))]
+                    Transfer::new_write(
+                        dma,
+                        req,
+                        duty,
+                        self.regs_1ch().ccr(channel.index()).as_ptr() as *mut u32,
+                        dma_transfer_option,
+                    )
+                    .await
+                }
+            };
+        };
+
+        // restore output compare state
+        if !original_enable_state {
+            self.enable_channel(channel, false);
+        }
+
+        self.set_compare_value(channel, original_duty_state);
+    }
+
     /// Get capture value for a channel.
     pub fn get_capture_value(&self, channel: Channel) -> u32 {
         self.get_compare_value(channel)
@@ -640,6 +905,11 @@ impl<'d, T: GeneralInstance4Channel> Timer<'d, T> {
         self.regs_gp16().dier().modify(|w| w.set_ccde(channel.index(), ccde))
     }
 
+    /// Set Timer Master Mode
+    pub fn set_master_mode(&self, mms: MasterMode) {
+        self.regs_gp16().cr2().modify(|w| w.set_mms(mms));
+    }
+
     /// Set Timer Slave Mode
     pub fn set_slave_mode(&self, sms: SlaveMode) {
         self.regs_gp16().smcr().modify(|r| r.set_sms(sms));
@@ -760,6 +1030,16 @@ impl<'d, T: AdvancedInstance4Channel> Timer<'d, T> {
         self.regs_advanced().cr2().modify(|w| w.set_oisn(channel.index(), val));
     }
 
+    /// Set master mode selection 2
+    pub fn set_mms2_selection(&self, mms2: vals::Mms2) {
+        self.regs_advanced().cr2().modify(|w| w.set_mms2(mms2));
+    }
+
+    /// Set repetition counter
+    pub fn set_repetition_counter(&self, val: u16) {
+        self.regs_advanced().rcr().modify(|w| w.set_rep(val));
+    }
+
     /// Trigger software break 1 or 2
     /// Setting this bit generates a break event. This bit is automatically cleared by the hardware.
     pub fn trigger_software_break(&self, n: usize) {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index b09bc7166..804d1ef37 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -399,7 +399,7 @@ pub struct UpdateInterruptHandler<T: CoreInstance> {
 impl<T: CoreInstance> interrupt::typelevel::Handler<T::UpdateInterrupt> for UpdateInterruptHandler<T> {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq();
 
         let regs = crate::pac::timer::TimCore::from_ptr(T::regs());
 
@@ -429,7 +429,7 @@ impl<T: GeneralInstance1Channel> interrupt::typelevel::Handler<T::CaptureCompare
 {
     unsafe fn on_interrupt() {
         #[cfg(feature = "low-power")]
-        crate::low_power::on_wakeup_irq();
+        crate::low_power::Executor::on_wakeup_irq();
 
         let regs = crate::pac::timer::TimGp16::from_ptr(T::regs());
 
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
index a75b41bd7..fe8681356 100644
--- a/embassy-stm32/src/timer/one_pulse.rs
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -11,12 +11,12 @@ use super::low_level::{
 };
 use super::{CaptureCompareInterruptHandler, Channel, ExternalTriggerPin, GeneralInstance4Channel, TimerPin};
 pub use super::{Ch1, Ch2};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::pac::timer::vals::Etp;
 use crate::time::Hertz;
 use crate::timer::TimerChannel;
-use crate::Peri;
 
 /// External input marker type.
 pub enum Ext {}
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index 159b5a177..057ab011a 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -2,9 +2,9 @@
 
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
 use super::{Ch1, Ch2, Channel, GeneralInstance4Channel, TimerPin};
+use crate::Peri;
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// PWM Input driver.
 ///
@@ -47,6 +47,7 @@ impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
         inner.set_counting_mode(CountingMode::EdgeAlignedUp);
         inner.set_tick_freq(freq);
         inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
+        inner.generate_update_event();
         inner.start();
 
         // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.6
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index bb152731c..a547a2a19 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -5,9 +5,9 @@ use stm32_metapac::timer::vals::{self, Sms};
 use super::low_level::Timer;
 pub use super::{Ch1, Ch2};
 use super::{GeneralInstance4Channel, TimerPin};
+use crate::Peri;
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::timer::TimerChannel;
-use crate::Peri;
 
 /// Qei driver config.
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index e6165e42b..6c9ef17e0 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -4,12 +4,12 @@ use core::marker::PhantomData;
 use core::mem::ManuallyDrop;
 
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerBits, TimerChannel, TimerPin};
+use super::{Ch1, Ch2, Ch3, Ch4, Channel, GeneralInstance4Channel, TimerChannel, TimerPin};
+use crate::Peri;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// PWM pin wrapper.
 ///
@@ -198,7 +198,6 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
         this.inner.enable_outputs(); // Required for advanced timers, see GeneralInstance4Channel for details
-        this.inner.start();
 
         [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
             .iter()
@@ -207,6 +206,11 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
                 this.inner.set_output_compare_preload(channel, true);
             });
+        this.inner.set_autoreload_preload(true);
+
+        // Generate update event so pre-load registers are written to the shadow registers
+        this.inner.generate_update_event();
+        this.inner.start();
 
         this
     }
@@ -285,8 +289,8 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
 
     /// Set PWM frequency.
     ///
-    /// Note: when you call this, the max duty value changes, so you will have to
-    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    /// Note: that the frequency will not be applied in the timer until an update event
+    /// occurs.
     pub fn set_frequency(&mut self, freq: Hertz) {
         // TODO: prevent ARR = u16::MAX?
         let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
@@ -309,61 +313,12 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Generate a sequence of PWM waveform
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    #[inline(always)]
     pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_duty_state = self.channel(channel).current_duty_cycle();
-        let original_enable_state = self.channel(channel).is_enabled();
-        let original_update_dma_state = self.inner.get_update_dma_state();
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        if !original_enable_state {
-            self.channel(channel).enable();
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            Transfer::new_write(
-                dma,
-                req,
-                duty,
-                self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
-                dma_transfer_option,
-            )
-            .await
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.channel(channel).disable();
-        }
-
-        self.channel(channel).set_duty_cycle(original_duty_state);
-
-        // Since DMA is closed before timer update event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
+        self.inner.waveform_up(dma, channel, duty).await;
     }
 
     /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
@@ -378,18 +333,24 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     ///
     /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
     ///
+    /// ```rust,ignore
     /// let dma_buf: [u16; 16] = [
     ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
     ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
     ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
     ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
     /// ];
+    /// ```
     ///
-    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// Each group of `N` values (where `N` is number of channels) is transferred on one update event,
     /// updating the duty cycles of all selected channels simultaneously.
     ///
     /// Note:
-    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    /// You will need to provide corresponding `TIMx_UP` DMA channel to use this method.
+    /// Also be aware that embassy timers use one of timers internally. It is possible to
+    /// switch this timer by using `time-driver-timX` feature.
+    ///
+    #[inline(always)]
     pub async fn waveform_up_multi_channel(
         &mut self,
         dma: Peri<'_, impl super::UpDma<T>>,
@@ -397,148 +358,15 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
         ending_channel: Channel,
         duty: &[u16],
     ) {
-        let cr1_addr = self.inner.regs_gp16().cr1().as_ptr() as u32;
-        let start_ch_index = starting_channel.index();
-        let end_ch_index = ending_channel.index();
-
-        assert!(start_ch_index <= end_ch_index);
-
-        let ccrx_addr = self.inner.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
-        self.inner
-            .regs_gp16()
-            .dcr()
-            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
         self.inner
-            .regs_gp16()
-            .dcr()
-            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
-
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let original_update_dma_state = self.inner.get_update_dma_state();
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(true);
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr4,
-                ..Default::default()
-            };
-
-            Transfer::new_write(
-                dma,
-                req,
-                duty,
-                self.inner.regs_gp16().dmar().as_ptr() as *mut u16,
-                dma_transfer_option,
-            )
-            .await
-        };
-
-        if !original_update_dma_state {
-            self.inner.enable_update_dma(false);
-        }
+            .waveform_up_multi_channel(dma, starting_channel, ending_channel, duty)
+            .await;
     }
-}
 
-impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
     /// Generate a sequence of PWM waveform
+    #[inline(always)]
     pub async fn waveform<C: TimerChannel>(&mut self, dma: Peri<'_, impl super::Dma<T, C>>, duty: &[u16]) {
-        use crate::pac::timer::vals::Ccds;
-
-        #[allow(clippy::let_unit_value)] // eg. stm32f334
-        let req = dma.request();
-
-        let cc_channel = C::CHANNEL;
-
-        let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-        let original_enable_state = self.channel(cc_channel).is_enabled();
-        let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
-        let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
-
-        // redirect CC DMA request onto Update Event
-        if !original_cc_dma_on_update {
-            self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
-        }
-
-        if !original_cc_dma_enabled {
-            self.inner.set_cc_dma_enable_state(cc_channel, true);
-        }
-
-        if !original_enable_state {
-            self.channel(cc_channel).enable();
-        }
-
-        unsafe {
-            #[cfg(not(any(bdma, gpdma)))]
-            use crate::dma::{Burst, FifoThreshold};
-            use crate::dma::{Transfer, TransferOptions};
-
-            let dma_transfer_option = TransferOptions {
-                #[cfg(not(any(bdma, gpdma)))]
-                fifo_threshold: Some(FifoThreshold::Full),
-                #[cfg(not(any(bdma, gpdma)))]
-                mburst: Burst::Incr8,
-                ..Default::default()
-            };
-
-            match self.inner.bits() {
-                TimerBits::Bits16 => {
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-                #[cfg(not(any(stm32l0)))]
-                TimerBits::Bits32 => {
-                    #[cfg(not(any(bdma, gpdma)))]
-                    panic!("unsupported timer bits");
-
-                    #[cfg(any(bdma, gpdma))]
-                    Transfer::new_write(
-                        dma,
-                        req,
-                        duty,
-                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
-                        dma_transfer_option,
-                    )
-                    .await
-                }
-            };
-        };
-
-        // restore output compare state
-        if !original_enable_state {
-            self.channel(cc_channel).disable();
-        }
-
-        self.channel(cc_channel).set_duty_cycle(original_duty_state);
-
-        // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
-        // this can almost always trigger a DMA FIFO error.
-        //
-        // optional TODO:
-        // clean FEIF after disable UDE
-        if !original_cc_dma_enabled {
-            self.inner.set_cc_dma_enable_state(cc_channel, false);
-        }
-
-        if !original_cc_dma_on_update {
-            self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
-        }
+        self.inner.waveform(dma, duty).await;
     }
 }
 
diff --git a/embassy-stm32/src/tsc/acquisition_banks.rs b/embassy-stm32/src/tsc/acquisition_banks.rs
index 7d6442b48..097cf7942 100644
--- a/embassy-stm32/src/tsc/acquisition_banks.rs
+++ b/embassy-stm32/src/tsc/acquisition_banks.rs
@@ -1,11 +1,11 @@
+use super::TSC_NUM_GROUPS;
 use super::io_pin::*;
 #[cfg(any(tsc_v2, tsc_v3))]
 use super::pin_groups::G7;
 #[cfg(tsc_v3)]
 use super::pin_groups::G8;
-use super::pin_groups::{pin_roles, G1, G2, G3, G4, G5, G6};
+use super::pin_groups::{G1, G2, G3, G4, G5, G6, pin_roles};
 use super::types::{Group, GroupStatus};
-use super::TSC_NUM_GROUPS;
 
 /// Represents a collection of TSC (Touch Sensing Controller) pins for an acquisition bank.
 ///
diff --git a/embassy-stm32/src/tsc/pin_groups.rs b/embassy-stm32/src/tsc/pin_groups.rs
index 84421f7ff..9347e6bc0 100644
--- a/embassy-stm32/src/tsc/pin_groups.rs
+++ b/embassy-stm32/src/tsc/pin_groups.rs
@@ -1,11 +1,11 @@
 use core::marker::PhantomData;
 use core::ops::BitOr;
 
+use super::Instance;
 use super::errors::GroupError;
 use super::io_pin::*;
-use super::Instance;
-use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::Peri;
+use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 
 /// Pin type definition to control IO parameters
 #[derive(PartialEq, Clone, Copy)]
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 18aff4fbd..ae86d28f0 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -19,8 +19,8 @@ use core::marker::PhantomData;
 use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 
-use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::waitqueue::AtomicWaker;
 
 use crate::dma::{ChannelAndRequest, TransferOptions};
@@ -28,11 +28,11 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
 pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, Rxordset, TypecVstateCc as CcVState};
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 pub(crate) fn init(
     _cs: critical_section::CriticalSection,
-    #[cfg(peri_ucpd1)] ucpd1_db_enable: bool,
+    #[cfg(all(peri_ucpd1, not(stm32n6)))] ucpd1_db_enable: bool,
     #[cfg(peri_ucpd2)] ucpd2_db_enable: bool,
 ) {
     #[cfg(stm32g0x1)]
@@ -349,6 +349,7 @@ impl<'d, T: Instance> CcPhy<'d, T> {
         critical_section::with(|cs| {
             init(
                 cs,
+                #[cfg(not(stm32n6))]
                 false,
                 #[cfg(peri_ucpd2)]
                 false,
diff --git a/embassy-stm32/src/uid.rs b/embassy-stm32/src/uid.rs
index 5e38532bd..2d3e2b972 100644
--- a/embassy-stm32/src/uid.rs
+++ b/embassy-stm32/src/uid.rs
@@ -1,8 +1,8 @@
 //! Unique ID (UID)
 
 /// Get this device's unique 96-bit ID.
-pub fn uid() -> &'static [u8; 12] {
-    unsafe { &*crate::pac::UID.uid(0).as_ptr().cast::<[u8; 12]>() }
+pub fn uid() -> [u8; 12] {
+    unsafe { *crate::pac::UID.uid(0).as_ptr().cast::<[u8; 12]>() }
 }
 
 /// Get this device's unique 96-bit ID, encoded into a string of 24 hexadecimal ASCII digits.
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 10dc02334..26d2b8991 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -5,16 +5,16 @@ use core::sync::atomic::{AtomicBool, AtomicU8, AtomicUsize, Ordering};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use embassy_hal_internal::Peri;
+use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
 use embassy_sync::waitqueue::AtomicWaker;
 
 #[cfg(not(any(usart_v1, usart_v2)))]
 use super::DePin;
 use super::{
+    Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin, TxPin,
     clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate,
-    sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin,
-    TxPin,
+    sr, tdr,
 };
 use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::{self, InterruptExt};
@@ -87,7 +87,7 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
     // With `usart_v4` hardware FIFO is enabled and Transmission complete (TC)
     // indicates that all bytes are pushed out from the FIFO.
     // For other usart variants it shows that last byte from the buffer was just sent.
-    if sr_val.tc() {
+    if sr_val.tc() && r.cr1().read().tcie() {
         // For others it is cleared above with `clear_interrupt_flags`.
         #[cfg(any(usart_v1, usart_v2))]
         sr(r).modify(|w| w.set_tc(false));
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 0d2d86aca..0e7da634d 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -4,15 +4,16 @@
 
 use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::sync::atomic::{compiler_fence, AtomicU8, AtomicUsize, Ordering};
+use core::sync::atomic::{AtomicU8, AtomicUsize, Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::drop::OnDrop;
 use embassy_hal_internal::PeripheralType;
+use embassy_hal_internal::drop::OnDrop;
 use embassy_sync::waitqueue::AtomicWaker;
-use futures_util::future::{select, Either};
+use futures_util::future::{Either, select};
 
+use crate::Peri;
 use crate::dma::ChannelAndRequest;
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt as _;
@@ -25,7 +26,6 @@ use crate::pac::usart::Usart as Regs;
 use crate::pac::usart::{regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peri;
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 27071fb31..bac570d27 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -1,19 +1,21 @@
 use core::future::poll_fn;
 use core::mem;
-use core::sync::atomic::{compiler_fence, Ordering};
+use core::sync::atomic::{Ordering, compiler_fence};
 use core::task::Poll;
 
 use embassy_embedded_hal::SetConfig;
 use embedded_io_async::ReadReady;
-use futures_util::future::{select, Either};
+use futures_util::future::{Either, select};
 
-use super::{rdr, reconfigure, set_baudrate, sr, Config, ConfigError, Error, Info, State, UartRx};
+use super::{
+    Config, ConfigError, Error, Info, State, UartRx, clear_interrupt_flags, rdr, reconfigure, set_baudrate, sr,
+};
+use crate::Peri;
 use crate::dma::ReadableRingBuffer;
 use crate::gpio::{AnyPin, SealedPin as _};
 use crate::mode::Async;
 use crate::time::Hertz;
 use crate::usart::Regs;
-use crate::Peri;
 
 /// Rx-only Ring-buffered UART Driver
 ///
@@ -338,26 +340,16 @@ impl Drop for RingBufferedUartRx<'_> {
 /// For usart_v1 and usart_v2, all status flags must be handled together anyway because all flags
 /// are cleared by a single read to the RDR register.
 fn check_idle_and_errors(r: Regs) -> Result<bool, Error> {
-    // Critical section is required so that the flags aren't set after read and before clear
-    let sr = critical_section::with(|_| {
-        // SAFETY: read only and we only use Rx related flags
-        let sr = sr(r).read();
-
-        #[cfg(any(usart_v3, usart_v4))]
-        r.icr().write(|w| {
-            w.set_idle(true);
-            w.set_pe(true);
-            w.set_fe(true);
-            w.set_ne(true);
-            w.set_ore(true);
-        });
-        #[cfg(not(any(usart_v3, usart_v4)))]
-        unsafe {
-            // This read also clears the error and idle interrupt flags on v1 (TODO and v2?)
-            rdr(r).read_volatile()
-        };
-        sr
-    });
+    // SAFETY: read only and we only use Rx related flags
+    let sr = sr(r).read();
+
+    #[cfg(not(any(usart_v3, usart_v4)))]
+    unsafe {
+        // This read also clears the error and idle interrupt flags on v1 (TODO and v2?)
+        rdr(r).read_volatile()
+    };
+    clear_interrupt_flags(r, sr);
+
     if sr.pe() {
         Err(Error::Parity)
     } else if sr.fe() {
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 5ce81b131..f6b1a81db 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -2,18 +2,18 @@ use core::marker::PhantomData;
 
 use embassy_hal_internal::PeripheralType;
 use embassy_usb_driver::{EndpointAddress, EndpointAllocError, EndpointType, Event, Unsupported};
-use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
-use embassy_usb_synopsys_otg::otg_v1::Otg;
 pub use embassy_usb_synopsys_otg::Config;
+use embassy_usb_synopsys_otg::otg_v1::Otg;
+use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
 use embassy_usb_synopsys_otg::{
-    on_interrupt as on_interrupt_impl, Bus as OtgBus, ControlPipe, Driver as OtgDriver, Endpoint, In, OtgInstance, Out,
-    PhyType, State,
+    Bus as OtgBus, ControlPipe, Driver as OtgDriver, Endpoint, In, OtgInstance, Out, PhyType, State,
+    on_interrupt as on_interrupt_impl,
 };
 
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 const MAX_EP_COUNT: usize = 9;
 
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 9e08d99b3..d405e4802 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -12,11 +12,11 @@ use embassy_usb_driver::{
     Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
 };
 
+use crate::pac::USBRAM;
 use crate::pac::usb::regs;
 use crate::pac::usb::vals::{EpType, Stat};
-use crate::pac::USBRAM;
 use crate::rcc::RccPeripheral;
-use crate::{interrupt, Peri};
+use crate::{Peri, interrupt};
 
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
diff --git a/embassy-stm32/src/vrefbuf/mod.rs b/embassy-stm32/src/vrefbuf/mod.rs
index ccbd748d5..43dd9c800 100644
--- a/embassy-stm32/src/vrefbuf/mod.rs
+++ b/embassy-stm32/src/vrefbuf/mod.rs
@@ -14,10 +14,10 @@ pub struct VoltageReferenceBuffer<'d, T: Instance> {
 #[cfg(rcc_wba)]
 fn get_refbuf_trim(voltage_scale: Vrs) -> usize {
     match voltage_scale {
-        Vrs::VREF0 => 0x0BFA_07A8usize,
-        Vrs::VREF1 => 0x0BFA_07A9usize,
-        Vrs::VREF2 => 0x0BFA_07AAusize,
-        Vrs::VREF3 => 0x0BFA_07ABusize,
+        Vrs::VREF0 => 0x0BFA_07ABusize,
+        Vrs::VREF1 => 0x0BFA_07AAusize,
+        Vrs::VREF2 => 0x0BFA_07A9usize,
+        Vrs::VREF3 => 0x0BFA_07A8usize,
         _ => panic!("Incorrect Vrs setting!"),
     }
 }
@@ -62,8 +62,7 @@ impl<'d, T: Instance> VoltageReferenceBuffer<'d, T> {
         }
         trace!(
             "Vrefbuf configured with voltage scale {} and impedance mode {}",
-            voltage_scale as u8,
-            impedance_mode as u8,
+            voltage_scale as u8, impedance_mode as u8,
         );
         VoltageReferenceBuffer { vrefbuf: PhantomData }
     }
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index fb5c3d930..1164739ff 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -4,8 +4,8 @@ use core::marker::PhantomData;
 use embassy_hal_internal::PeripheralType;
 use stm32_metapac::iwdg::vals::{Key, Pr};
 
-use crate::rcc::LSI_FREQ;
 use crate::Peri;
+use crate::rcc::LSI_FREQ;
 
 /// Independent watchdog (IWDG) driver.
 pub struct IndependentWatchdog<'d, T: Instance> {
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
index 6f224ab99..466e1a9b4 100644
--- a/embassy-stm32/src/xspi/mod.rs
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -11,15 +11,15 @@ use embassy_embedded_hal::{GetConfig, SetConfig};
 use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 
-use crate::dma::{word, ChannelAndRequest};
+use crate::dma::{ChannelAndRequest, word};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::pac::xspi::vals::*;
 use crate::pac::xspi::Xspi as Regs;
+use crate::pac::xspi::vals::*;
 #[cfg(xspim_v1)]
 use crate::pac::xspim::Xspim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peri};
+use crate::{Peri, peripherals};
 
 /// XPSI driver config.
 #[derive(Clone, Copy)]