diff options
| author | seth <[email protected]> | 2024-07-01 06:44:47 -0700 |
|---|---|---|
| committer | seth <[email protected]> | 2024-07-01 06:44:47 -0700 |
| commit | 27652798c72d16cbcf2245ae7d4bd4574001ef1f (patch) | |
| tree | 6642069eb7e2855f32a02fcf292edb132c703918 /embassy-stm32 | |
| parent | 6926e9e07154c72d68ef099d5f28178274f86032 (diff) | |
fix typo, add spaces after //
Diffstat (limited to 'embassy-stm32')
| -rw-r--r-- | embassy-stm32/src/adc/ringbuffered_v2.rs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs index 8c5eb9672..fb29d9a8c 100644 --- a/embassy-stm32/src/adc/ringbuffered_v2.rs +++ b/embassy-stm32/src/adc/ringbuffered_v2.rs | |||
| @@ -170,7 +170,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> { | |||
| 170 | Self::start_adc(); | 170 | Self::start_adc(); |
| 171 | } | 171 | } |
| 172 | 172 | ||
| 173 | //Check the sequence is long enough | 173 | // Check the sequence is long enough |
| 174 | T::regs().sqr1().modify(|r| { | 174 | T::regs().sqr1().modify(|r| { |
| 175 | let prev: Sequence = r.l().into(); | 175 | let prev: Sequence = r.l().into(); |
| 176 | if prev < sequence { | 176 | if prev < sequence { |
| @@ -182,10 +182,10 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> { | |||
| 182 | } | 182 | } |
| 183 | }); | 183 | }); |
| 184 | 184 | ||
| 185 | //Set this GPIO as an analog input. | 185 | // Set this GPIO as an analog input. |
| 186 | channel.setup(); | 186 | channel.setup(); |
| 187 | 187 | ||
| 188 | //Set the channel in the right sequence field. | 188 | // Set the channel in the right sequence field. |
| 189 | match sequence { | 189 | match sequence { |
| 190 | Sequence::One => T::regs().sqr3().modify(|w| w.set_sq(0, channel.channel())), | 190 | Sequence::One => T::regs().sqr3().modify(|w| w.set_sq(0, channel.channel())), |
| 191 | Sequence::Two => T::regs().sqr3().modify(|w| w.set_sq(1, channel.channel())), | 191 | Sequence::Two => T::regs().sqr3().modify(|w| w.set_sq(1, channel.channel())), |
| @@ -260,7 +260,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> { | |||
| 260 | 260 | ||
| 261 | let r = T::regs(); | 261 | let r = T::regs(); |
| 262 | 262 | ||
| 263 | //Enable ADC | 263 | // Enable ADC |
| 264 | let was_on = Self::is_on(); | 264 | let was_on = Self::is_on(); |
| 265 | if !was_on { | 265 | if !was_on { |
| 266 | r.cr2().modify(|reg| { | 266 | r.cr2().modify(|reg| { |
| @@ -298,7 +298,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> { | |||
| 298 | w.set_eocs(vals::Eocs::EACHCONVERSION); | 298 | w.set_eocs(vals::Eocs::EACHCONVERSION); |
| 299 | }); | 299 | }); |
| 300 | 300 | ||
| 301 | //Being ADC conversions | 301 | // Begin ADC conversions |
| 302 | T::regs().cr2().modify(|reg| { | 302 | T::regs().cr2().modify(|reg| { |
| 303 | reg.set_adon(true); | 303 | reg.set_adon(true); |
| 304 | reg.set_swstart(true); | 304 | reg.set_swstart(true); |
