diff options
| author | xoviat <[email protected]> | 2023-08-08 19:58:03 -0500 |
|---|---|---|
| committer | xoviat <[email protected]> | 2023-08-08 19:58:03 -0500 |
| commit | 6a73ab1afa76944c413cb91932881c35ddfbcbcd (patch) | |
| tree | 28f2d62dc4d9ab554da1da414db1820e4cd53b90 /embassy-stm32 | |
| parent | 6fc5c608f8a99e0275916b7c86116ac6eb14c97a (diff) | |
stm32/l4: set rtc clock source in rcc
Diffstat (limited to 'embassy-stm32')
| -rw-r--r-- | embassy-stm32/src/rcc/l4.rs | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/embassy-stm32/src/rcc/l4.rs b/embassy-stm32/src/rcc/l4.rs index 36c9eb2f5..b2828e58e 100644 --- a/embassy-stm32/src/rcc/l4.rs +++ b/embassy-stm32/src/rcc/l4.rs | |||
| @@ -10,6 +10,7 @@ use crate::gpio::Speed; | |||
| 10 | use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; | 10 | use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw}; |
| 11 | use crate::pac::{FLASH, PWR, RCC}; | 11 | use crate::pac::{FLASH, PWR, RCC}; |
| 12 | use crate::rcc::{set_freqs, Clocks}; | 12 | use crate::rcc::{set_freqs, Clocks}; |
| 13 | use crate::rtc::{Rtc, RtcClockSource as RCS}; | ||
| 13 | use crate::time::Hertz; | 14 | use crate::time::Hertz; |
| 14 | use crate::{peripherals, Peripheral}; | 15 | use crate::{peripherals, Peripheral}; |
| 15 | 16 | ||
| @@ -426,6 +427,8 @@ pub(crate) unsafe fn init(config: Config) { | |||
| 426 | 427 | ||
| 427 | // Wait until LSE is running | 428 | // Wait until LSE is running |
| 428 | while !RCC.bdcr().read().lserdy() {} | 429 | while !RCC.bdcr().read().lserdy() {} |
| 430 | |||
| 431 | Rtc::set_clock_source(RCS::LSE); | ||
| 429 | } | 432 | } |
| 430 | RtcClockSource::LSI32 => { | 433 | RtcClockSource::LSI32 => { |
| 431 | // Turn on the internal 32 kHz LSI oscillator | 434 | // Turn on the internal 32 kHz LSI oscillator |
| @@ -433,6 +436,8 @@ pub(crate) unsafe fn init(config: Config) { | |||
| 433 | 436 | ||
| 434 | // Wait until LSI is running | 437 | // Wait until LSI is running |
| 435 | while !RCC.csr().read().lsirdy() {} | 438 | while !RCC.csr().read().lsirdy() {} |
| 439 | |||
| 440 | Rtc::set_clock_source(RCS::LSI); | ||
| 436 | } | 441 | } |
| 437 | } | 442 | } |
| 438 | 443 | ||
