implement PWM waveform generating with DMA

3 files changed, 113 insertions, 16 deletions

diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index 058b8a0fc..de03827e9 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -1008,6 +1008,7 @@ fn main() {
         (("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
         (("dac", "CH1"), quote!(crate::dac::DacDma1)),
         (("dac", "CH2"), quote!(crate::dac::DacDma2)),
+        (("timer", "UP"), quote!(crate::timer::UpDma)),
     ]
     .into();
 
@@ -1023,6 +1024,16 @@ fn main() {
                 }
 
                 if let Some(tr) = signals.get(&(regs.kind, ch.signal)) {
+                    // TIM6 of stm32f334 is special, DMA channel for TIM6 depending on SYSCFG state
+                    if chip_name.starts_with("stm32f334") && p.name == "TIM6" {
+                        continue;
+                    }
+
+                    // TIM6 of stm32f378 is special, DMA channel for TIM6 depending on SYSCFG state
+                    if chip_name.starts_with("stm32f378") && p.name == "TIM6" {
+                        continue;
+                    }
+
                     let peri = format_ident!("{}", p.name);
 
                     let channel = if let Some(channel) = &ch.channel {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 74120adad..05a0564a3 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -91,7 +91,12 @@ pub(crate) mod sealed {
 
         /// Enable/disable the update interrupt.
         fn enable_update_interrupt(&mut self, enable: bool) {
-            Self::regs().dier().write(|r| r.set_uie(enable));
+            Self::regs().dier().modify(|r| r.set_uie(enable));
+        }
+
+        /// Enable/disable the update dma.
+        fn enable_update_dma(&mut self, enable: bool) {
+            Self::regs().dier().modify(|r| r.set_ude(enable));
         }
 
         /// Enable/disable autoreload preload.
@@ -288,6 +293,14 @@ pub(crate) mod sealed {
         fn get_compare_value(&self, channel: Channel) -> u16 {
             Self::regs_gp16().ccr(channel.index()).read().ccr()
         }
+
+        /// Set output compare preload.
+        fn set_output_compare_preload(&mut self, channel: Channel, preload: bool) {
+            let channel_index = channel.index();
+            Self::regs_gp16()
+                .ccmr_output(channel_index / 2)
+                .modify(|w| w.set_ocpe(channel_index % 2, preload));
+        }
     }
 
     /// Capture/Compare 16-bit timer instance with complementary pin support.
@@ -676,3 +689,6 @@ foreach_interrupt! {
         }
     };
 }
+
+// Update Event trigger DMA for every timer
+dma_trait!(UpDma, Basic16bitInstance);
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index e6072aa15..1819c7c55 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -55,11 +55,12 @@ channel_impl!(new_ch3, Ch3, Channel3Pin);
 channel_impl!(new_ch4, Ch4, Channel4Pin);
 
 /// Simple PWM driver.
-pub struct SimplePwm<'d, T> {
+pub struct SimplePwm<'d, T, Dma> {
     inner: PeripheralRef<'d, T>,
+    dma: PeripheralRef<'d, Dma>,
 }
 
-impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
+impl<'d, T: CaptureCompare16bitInstance, Dma> SimplePwm<'d, T, Dma> {
     /// Create a new simple PWM driver.
     pub fn new(
         tim: impl Peripheral<P = T> + 'd,
@@ -69,16 +70,22 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
         _ch4: Option<PwmPin<'d, T, Ch4>>,
         freq: Hertz,
         counting_mode: CountingMode,
+        dma: impl Peripheral<P = Dma> + 'd,
     ) -> Self {
-        Self::new_inner(tim, freq, counting_mode)
+        Self::new_inner(tim, freq, counting_mode, dma)
     }
 
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
-        into_ref!(tim);
+    fn new_inner(
+        tim: impl Peripheral<P = T> + 'd,
+        freq: Hertz,
+        counting_mode: CountingMode,
+        dma: impl Peripheral<P = Dma> + 'd,
+    ) -> Self {
+        into_ref!(tim, dma);
 
         T::enable_and_reset();
 
-        let mut this = Self { inner: tim };
+        let mut this = Self { inner: tim, dma };
 
         this.inner.set_counting_mode(counting_mode);
         this.set_frequency(freq);
@@ -86,14 +93,13 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
 
         this.inner.enable_outputs();
 
-        this.inner
-            .set_output_compare_mode(Channel::Ch1, OutputCompareMode::PwmMode1);
-        this.inner
-            .set_output_compare_mode(Channel::Ch2, OutputCompareMode::PwmMode1);
-        this.inner
-            .set_output_compare_mode(Channel::Ch3, OutputCompareMode::PwmMode1);
-        this.inner
-            .set_output_compare_mode(Channel::Ch4, OutputCompareMode::PwmMode1);
+        [Channel::Ch1, Channel::Ch2, Channel::Ch3, Channel::Ch4]
+            .iter()
+            .for_each(|&channel| {
+                this.inner.set_output_compare_mode(channel, OutputCompareMode::PwmMode1);
+                this.inner.set_output_compare_preload(channel, true)
+            });
+
         this
     }
 
@@ -141,7 +147,71 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
     }
 }
 
-impl<'d, T: CaptureCompare16bitInstance> embedded_hal_02::Pwm for SimplePwm<'d, T> {
+impl<'d, T: CaptureCompare16bitInstance + Basic16bitInstance, Dma> SimplePwm<'d, T, Dma>
+where
+    Dma: super::UpDma<T>,
+{
+    /// Generate a sequence of PWM waveform
+    pub async fn gen_waveform(&mut self, channel: Channel, duty: &[u16]) {
+        duty.iter().all(|v| v.le(&self.get_max_duty()));
+
+        self.inner.enable_update_dma(true);
+
+        #[cfg_attr(any(stm32f334, stm32f378), allow(clippy::let_unit_value))]
+        let req = self.dma.request();
+
+        self.enable(channel);
+
+        #[cfg(not(any(bdma, gpdma)))]
+        let dma_regs = self.dma.regs();
+        #[cfg(not(any(bdma, gpdma)))]
+        let isr_num = self.dma.num() / 4;
+        #[cfg(not(any(bdma, gpdma)))]
+        let isr_bit = self.dma.num() % 4;
+
+        #[cfg(not(any(bdma, gpdma)))]
+        // clean DMA FIFO error before a transfer
+        if dma_regs.isr(isr_num).read().feif(isr_bit) {
+            dma_regs.ifcr(isr_num).write(|v| v.set_feif(isr_bit, true));
+        }
+
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr8,
+                ..Default::default()
+            };
+
+            Transfer::new_write(
+                &mut self.dma,
+                req,
+                duty,
+                T::regs_gp16().ccr(channel.index()).as_ptr() as *mut _,
+                dma_transfer_option,
+            )
+            .await
+        };
+
+        self.disable(channel);
+
+        self.inner.enable_update_dma(false);
+
+        #[cfg(not(any(bdma, gpdma)))]
+        // Since DMA is closed before timer update event trigger DMA is turn off, it will almost always trigger a DMA FIFO error.
+        // Thus, we will always clean DMA FEIF after each transfer
+        if dma_regs.isr(isr_num).read().feif(isr_bit) {
+            dma_regs.ifcr(isr_num).write(|v| v.set_feif(isr_bit, true));
+        }
+    }
+}
+
+impl<'d, T: CaptureCompare16bitInstance, Dma> embedded_hal_02::Pwm for SimplePwm<'d, T, Dma> {
     type Channel = Channel;
     type Time = Hertz;
     type Duty = u16;