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| author | Chen Yuheng <[email protected]> | 2024-06-27 17:04:26 +0800 |
|---|---|---|
| committer | Chen Yuheng <[email protected]> | 2024-06-27 17:04:26 +0800 |
| commit | a0799bf270010f4e91b0c3eebe487d8bc6fb54fc (patch) | |
| tree | 23e2090e0e53118a71e3d57417503104cc07e1cc /embassy-stm32 | |
| parent | a2acb3e3dceddb4752f8fb1c17aa65e1959a2180 (diff) | |
Add adc oversampling support
Diffstat (limited to 'embassy-stm32')
| -rw-r--r-- | embassy-stm32/src/adc/v3.rs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs index 398c57a92..bf7ad242b 100644 --- a/embassy-stm32/src/adc/v3.rs +++ b/embassy-stm32/src/adc/v3.rs | |||
| @@ -277,6 +277,21 @@ impl<'d, T: Instance> Adc<'d, T> { | |||
| 277 | val | 277 | val |
| 278 | } | 278 | } |
| 279 | 279 | ||
| 280 | #[cfg(any(adc_g0, adc_u0))] | ||
| 281 | pub fn set_oversampling_shift(&mut self, shift: u8) { | ||
| 282 | T::regs().cfgr2().modify(|reg| reg.set_ovss(shift)); | ||
| 283 | } | ||
| 284 | |||
| 285 | #[cfg(any(adc_g0, adc_u0))] | ||
| 286 | pub fn set_oversampling_ratio(&mut self, ratio: u8) { | ||
| 287 | T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio)); | ||
| 288 | } | ||
| 289 | |||
| 290 | #[cfg(any(adc_g0, adc_u0))] | ||
| 291 | pub fn oversampling_enable(&mut self, enable: bool) { | ||
| 292 | T::regs().cfgr2().modify(|reg| reg.set_ovse(enable)); | ||
| 293 | } | ||
| 294 | |||
| 280 | fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) { | 295 | fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) { |
| 281 | cfg_if! { | 296 | cfg_if! { |
| 282 | if #[cfg(any(adc_g0, adc_u0))] { | 297 | if #[cfg(any(adc_g0, adc_u0))] { |
