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authorxoviat <[email protected]>2023-08-06 12:06:29 -0500
committerxoviat <[email protected]>2023-08-06 12:06:29 -0500
commitae608cf2fa009556953b72f18683496c17b8dca0 (patch)
tree3253eccf6784fbd38e2a1fcdce9d03aad6497c35 /embassy-stm32
parent28618d12a11a73a5c0c4e2b176b7096796f79cdb (diff)
stm32: fix rtc and examples
Diffstat (limited to 'embassy-stm32')
-rw-r--r--embassy-stm32/src/rtc/v3.rs7
1 files changed, 4 insertions, 3 deletions
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 64ecf4fbd..9f04c9b69 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -22,10 +22,11 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
22 let reg = crate::pac::RCC.bdcr().read(); 22 let reg = crate::pac::RCC.bdcr().read();
23 assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet."); 23 assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
24 24
25 let clock_source = clock_source as u8;
25 #[cfg(not(any(rcc_wl5, rcc_wle)))] 26 #[cfg(not(any(rcc_wl5, rcc_wle)))]
26 let config_rtcsel = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source as u8); 27 let clock_source = crate::pac::rcc::vals::Rtcsel::from_bits(clock_source);
27 28
28 if !reg.rtcen() || reg.rtcsel() != clock_source as u8 { 29 if !reg.rtcen() || reg.rtcsel() != clock_source {
29 crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); 30 crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
30 31
31 crate::pac::RCC.bdcr().modify(|w| { 32 crate::pac::RCC.bdcr().modify(|w| {
@@ -33,7 +34,7 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
33 w.set_bdrst(false); 34 w.set_bdrst(false);
34 35
35 // Select RTC source 36 // Select RTC source
36 w.set_rtcsel(clock_source as u8); 37 w.set_rtcsel(clock_source);
37 38
38 w.set_rtcen(true); 39 w.set_rtcen(true);
39 40