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authorxoviat <[email protected]>2023-10-03 15:53:22 -0500
committerxoviat <[email protected]>2023-10-03 15:53:22 -0500
commitbb8a1b7f1f8728e09435a8ee89b393533f813e85 (patch)
tree303f04f0bbfda2799a9614fd3a3f8f63051f9f69 /embassy-stm32
parentb012a67df7b5c95cce0e09eb66e3952bbc021bcc (diff)
wpan: re-enable HIL tests
Diffstat (limited to 'embassy-stm32')
-rw-r--r--embassy-stm32/src/rcc/bd.rs4
1 files changed, 4 insertions, 0 deletions
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 026c89d6a..cec2ea010 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -88,6 +88,8 @@ impl BackupDomain {
88 ))] 88 ))]
89 #[allow(dead_code, unused_variables)] 89 #[allow(dead_code, unused_variables)]
90 pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) { 90 pub fn configure_ls(clock_source: RtcClockSource, lsi: bool, lse: Option<LseDrive>) {
91 use atomic_polyfill::{compiler_fence, Ordering};
92
91 match clock_source { 93 match clock_source {
92 RtcClockSource::LSI => assert!(lsi), 94 RtcClockSource::LSI => assert!(lsi),
93 RtcClockSource::LSE => assert!(&lse.is_some()), 95 RtcClockSource::LSE => assert!(&lse.is_some()),
@@ -173,5 +175,7 @@ impl BackupDomain {
173 } 175 }
174 176
175 trace!("BDCR configured: {:08x}", Self::read().0); 177 trace!("BDCR configured: {:08x}", Self::read().0);
178
179 compiler_fence(Ordering::SeqCst);
176 } 180 }
177} 181}