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authorMarco Pastrello <[email protected]>2023-05-05 00:12:32 +0200
committerMarco Pastrello <[email protected]>2023-05-05 00:12:32 +0200
commitc37f86ff1c507cc036b9754a00dea85d439a8369 (patch)
tree861c4a88a9130be470fa0623b937588807427f3e /embassy-stm32
parent2dcbe75cca84cc44fc2357091aec20d2d9d5be00 (diff)
removes unecessary braces
Diffstat (limited to 'embassy-stm32')
-rw-r--r--embassy-stm32/src/rcc/f1.rs6
1 files changed, 2 insertions, 4 deletions
diff --git a/embassy-stm32/src/rcc/f1.rs b/embassy-stm32/src/rcc/f1.rs
index 106acb097..3c374adf4 100644
--- a/embassy-stm32/src/rcc/f1.rs
+++ b/embassy-stm32/src/rcc/f1.rs
@@ -148,10 +148,8 @@ pub(crate) unsafe fn init(config: Config) {
148 } 148 }
149 149
150 if let Some(pllmul_bits) = pllmul_bits { 150 if let Some(pllmul_bits) = pllmul_bits {
151 { 151 let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 };
152 let pllctpre_flag: u8 = if config.pllxtpre { 1 } else { 0 }; 152 RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
153 RCC.cfgr().modify(|w| w.set_pllxtpre(Pllxtpre(pllctpre_flag)));
154 }
155 153
156 // enable PLL and wait for it to be ready 154 // enable PLL and wait for it to be ready
157 RCC.cfgr().modify(|w| { 155 RCC.cfgr().modify(|w| {