merge new embassy changes

author: jrmoulton <[email protected]> 2025-06-10 15:47:54 -0600
committer: jrmoulton <[email protected]> 2025-06-10 15:48:36 -0600
commit: cfad9798ff99d4de0571a512d156b5fe1ef1d427 (patch)
tree: fc3bf670f82d139de19466cddad1e909db7f3d2e /embassy-stm32
parent: fc342915e6155dec7bafa3e135da7f37a9a07f5c (diff)
parent: 6186d111a5c150946ee5b7e9e68d987a38c1a463 (diff)
144 files changed, 18198 insertions, 6602 deletions
diff --git a/embassy-stm32/CHANGELOG.md b/embassy-stm32/CHANGELOG.md
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+++ b/embassy-stm32/CHANGELOG.md
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+# Changelog for embassy-stm32
+All notable changes to this project will be documented in this file.
+The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
+and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
+## Unreleased
+- Modify BufferedUart initialization to take pins before interrupts ([#3983](https://github.com/embassy-rs/embassy/pull/3983))
+- Added a 'single-bank' and a 'dual-bank' feature so chips with configurable flash bank setups are be supported in embassy ([#4125](https://github.com/embassy-rs/embassy/pull/4125))
+## 0.2.0 - 2025-01-10
+Starting 2025 strong with a release packed with new, exciting good stuff! 🚀
+### New chips
+This release adds support for many newly-released STM32 chips.
+- STM32H7[RS] "bootflash line" ([#2898](https://github.com/embassy-rs/embassy/pull/2898))
+- STM32U0 ([#2809](https://github.com/embassy-rs/embassy/pull/2809) [#2813](https://github.com/embassy-rs/embassy/pull/2813))
+- STM32H5[23] ([#2892](https://github.com/embassy-rs/embassy/pull/2892))
+- STM32U5[FG] ([#2892](https://github.com/embassy-rs/embassy/pull/2892))
+- STM32WBA5[045] ([#2892](https://github.com/embassy-rs/embassy/pull/2892))
+### Simpler APIs with less generics
+Many HAL APIs have been simplified thanks to reducing the amount of generic parameters. This helps with creating arrays of pins or peripherals, and for calling the same code with different pins/peripherals without incurring in code size penalties d
+For GPIO, the pins have been eliminated. `Output<'_, PA4>` is now `Output<'_>`.
+For peripherals, both pins and DMA channels have been eliminated. Peripherals now have a "mode" generic param that specifies whether it's capable of async operation. For example, `I2c<'_, I2C2, NoDma, NoDma>` is now `I2c<'_, Blocking>` and `I2c<'_, I2C2, DMA2_CH1, DMA2_CH2>` is now `I2c<'_, Async>`.
+- Removed DMA channel generic params for UART ([#2821](https://github.com/embassy-rs/embassy/pull/2821)), I2C ([#2820](https://github.com/embassy-rs/embassy/pull/2820)), SPI ([#2819](https://github.com/embassy-rs/embassy/pull/2819)), QSPI ([#2982](https://github.com/embassy-rs/embassy/pull/2982)), OSPI ([#2941](https://github.com/embassy-rs/embassy/pull/2941)).
+- Removed peripheral generic params for GPIO ([#2471](https://github.com/embassy-rs/embassy/pull/2471)), UART ([#2836](https://github.com/embassy-rs/embassy/pull/2836)), I2C ([#2974](https://github.com/embassy-rs/embassy/pull/2974)), SPI ([#2835](https://github.com/embassy-rs/embassy/pull/2835))
+- Remove generics in CAN ([#3012](https://github.com/embassy-rs/embassy/pull/3012), [#3020](https://github.com/embassy-rs/embassy/pull/3020), [#3032](https://github.com/embassy-rs/embassy/pull/3032), [#3033](https://github.com/embassy-rs/embassy/pull/3033))
+### More complete and consistent RCC
+RCC support has been vastly expanded and improved.
+- The API is now consistent across all STM32 families. Previously in some families you'd configure the desired target frequencies for `sysclk` and the buses and `embassy-stm32` would try to calculate dividers and muxes to hit them as close as possible. This has proved to be intractable in the general case and hard to extend to more exotic RCC configurations. So, we have standardized on an API where the user specifies the settings for dividers and muxes directly. It's lower level but gices more control to the user, supports all edge case exotic configurations, and makes it easier to translate a configuration from the STM32CubeMX tool. ([Tracking issue](https://github.com/embassy-rs/embassy/issues/2515). [#2624](https://github.com/embassy-rs/embassy/pull/2624). F0, F1 [#2564](https://github.com/embassy-rs/embassy/pull/2564), F3 [#2560](https://github.com/embassy-rs/embassy/pull/2560), U5 [#2617](https://github.com/embassy-rs/embassy/pull/2617), [#3514](https://github.com/embassy-rs/embassy/pull/3514), [#3513](https://github.com/embassy-rs/embassy/pull/3513), G4 [#2579](https://github.com/embassy-rs/embassy/pull/2579), [#2618](https://github.com/embassy-rs/embassy/pull/2618), WBA [#2520](https://github.com/embassy-rs/embassy/pull/2520), G0, C0 ([#2656](https://github.com/embassy-rs/embassy/pull/2656)).
+- Added support for configuring all per-peripheral clock muxes (CCIPRx, DCKCFGRx registers) in `config.rcc.mux`. This was previously handled in an ad-hoc way in some drivers (e.g. USB) and not at all in others (causing e.g. wrong SPI frequency) ([#2521](https://github.com/embassy-rs/embassy/pull/2521), [#2583](https://github.com/embassy-rs/embassy/pull/2583), [#2634](https://github.com/embassy-rs/embassy/pull/2634), [#2626](https://github.com/embassy-rs/embassy/pull/2626), [#2815](https://github.com/embassy-rs/embassy/pull/2815), [#2517](https://github.com/embassy-rs/embassy/pull/2517)).
+- Switch to a safe configuration before configuring RCC. This helps avoid crashes when RCC has been already configured previously (for example by a bootloader). (F2, F4, F7 [#2829](https://github.com/embassy-rs/embassy/pull/2829), C0, F0, F1, F3, G0, G4, H5, H7[#3008](https://github.com/embassy-rs/embassy/pull/3008))
+- Some new nice features:
+    - Expose RCC enable and disable in public API. ([#2807](https://github.com/embassy-rs/embassy/pull/2807))
+    - Add `unchecked-overclocking` feature that disables all asserts, allowing running RCC out of spec. ([#3574](https://github.com/embassy-rs/embassy/pull/3574))
+- Many fixes:
+    - Workaround H5 errata that accidentally clears RAM on backup domain reset. ([#2616](https://github.com/embassy-rs/embassy/pull/2616))
+    - Reset RTC on L0 ([#2597](https://github.com/embassy-rs/embassy/pull/2597))
+    - Fix H7 to use correct unit in vco clock check ([#2537](https://github.com/embassy-rs/embassy/pull/2537))
+    - Fix incorrect D1CPRE max for STM32H7 RM0468 ([#2518](https://github.com/embassy-rs/embassy/pull/2518))
+    - WBA's high speed external clock has to run at 32 MHz ([#2511](https://github.com/embassy-rs/embassy/pull/2511))
+    - Take into account clock propagation delay to peripherals after enabling a clock. ([#2677](https://github.com/embassy-rs/embassy/pull/2677))
+    - Fix crash caused by using higher MSI range as sysclk on STM32WL ([#2786](https://github.com/embassy-rs/embassy/pull/2786))
+    - fix using HSI48 as SYSCLK on F0 devices with CRS ([#3652](https://github.com/embassy-rs/embassy/pull/3652))
+    - compute LSE and LSI frequency for STM32L and STM32U0 series ([#3554](https://github.com/embassy-rs/embassy/pull/3554))
+    - Add support for LSESYS, used to pass LSE clock to peripherals ([#3518](https://github.com/embassy-rs/embassy/pull/3518))
+    - H5: LSE low drive mode is not functional ([#2738](https://github.com/embassy-rs/embassy/pull/2738))
+### New peripheral drivers
+- Dual-core support. First core initializes RCC and writes a struct into shared memory that the second core uses, ensuring no conflicts. ([#3158](https://github.com/embassy-rs/embassy/pull/3158), [#3263](https://github.com/embassy-rs/embassy/pull/3263), [#3687](https://github.com/embassy-rs/embassy/pull/3687))
+- USB Type-C/USB Power Delivery Interface (UCPD) ([#2652](https://github.com/embassy-rs/embassy/pull/2652), [#2683](https://github.com/embassy-rs/embassy/pull/2683), [#2701](https://github.com/embassy-rs/embassy/pull/2701), [#2925](https://github.com/embassy-rs/embassy/pull/2925), [#3084](https://github.com/embassy-rs/embassy/pull/3084), [#3271](https://github.com/embassy-rs/embassy/pull/3271), [#3678](https://github.com/embassy-rs/embassy/pull/3678), [#3714](https://github.com/embassy-rs/embassy/pull/3714))
+- Touch sensing controller (TSC) ([#2853](https://github.com/embassy-rs/embassy/pull/2853), [#3111](https://github.com/embassy-rs/embassy/pull/3111), [#3163](https://github.com/embassy-rs/embassy/pull/3163), [#3274](https://github.com/embassy-rs/embassy/pull/3274))
+- Display Serial Interface (DSI) [#2903](https://github.com/embassy-rs/embassy/pull/2903), ([#3082](https://github.com/embassy-rs/embassy/pull/3082))
+- LCD/TFT Display Controller (LTDC) ([#3126](https://github.com/embassy-rs/embassy/pull/3126), [#3458](https://github.com/embassy-rs/embassy/pull/3458))
+- SPDIF receiver (SPDIFRX) ([#3280](https://github.com/embassy-rs/embassy/pull/3280))
+- CORDIC math accelerator ([#2697](https://github.com/embassy-rs/embassy/pull/2697))
+- Digital Temperature Sensor (DTS) ([#3717](https://github.com/embassy-rs/embassy/pull/3717))
+- HMAC accelerator ([#2565](https://github.com/embassy-rs/embassy/pull/2565))
+- Hash accelerator ([#2528](https://github.com/embassy-rs/embassy/pull/2528))
+- Crypto accelerator ([#2619](https://github.com/embassy-rs/embassy/pull/2619), [#2691](https://github.com/embassy-rs/embassy/pull/2691))
+- Semaphore (HSEM) ([#2777](https://github.com/embassy-rs/embassy/pull/2777), [#3161](https://github.com/embassy-rs/embassy/pull/3161))
+### Improvements to existing drivers
+GPIO:
+- Generate singletons only for pins that actually exist. ([#3738](https://github.com/embassy-rs/embassy/pull/3738))
+- Add `set_as_analog` to Flex ([#3017](https://github.com/embassy-rs/embassy/pull/3017))
+- Add `embedded-hal` v0.2 `InputPin` impls for `OutputOpenDrain`. ([#2716](https://github.com/embassy-rs/embassy/pull/2716))
+- Add a config option to make the VDDIO2 supply line valid ([#2737](https://github.com/embassy-rs/embassy/pull/2737))
+- Refactor AfType ([#3031](https://github.com/embassy-rs/embassy/pull/3031))
+- Gpiov1: Do not call set_speed for AFType::Input ([#2996](https://github.com/embassy-rs/embassy/pull/2996))
+UART: 
+- Add embedded-io impls ([#2739](https://github.com/embassy-rs/embassy/pull/2739))
+- Add support for changing baud rate ([#3512](https://github.com/embassy-rs/embassy/pull/3512))
+- Add split_ref ([#3500](https://github.com/embassy-rs/embassy/pull/3500))
+- Add data bit selection ([#3595](https://github.com/embassy-rs/embassy/pull/3595))
+- Add RX Pull configuration option ([#3415](https://github.com/embassy-rs/embassy/pull/3415))
+- Add async flush ([#3379](https://github.com/embassy-rs/embassy/pull/3379))
+- Add support for sending breaks ([#3286](https://github.com/embassy-rs/embassy/pull/3286))
+- Disconnect pins on drop ([#3006](https://github.com/embassy-rs/embassy/pull/3006))
+- Half-duplex improvements
+    - Add half-duplex for all USART versions ([#2833](https://github.com/embassy-rs/embassy/pull/2833))
+    - configurable readback for half-duplex. ([#3679](https://github.com/embassy-rs/embassy/pull/3679))
+    - Convert uart half_duplex to use user configurable IO ([#3233](https://github.com/embassy-rs/embassy/pull/3233))
+    - Fix uart::flush with FIFO at Half-Duplex mode ([#2895](https://github.com/embassy-rs/embassy/pull/2895))
+    - Fix Half-Duplex sequential reads and writes ([#3089](https://github.com/embassy-rs/embassy/pull/3089))
+    - disable transmitter during during half-duplex flush ([#3299](https://github.com/embassy-rs/embassy/pull/3299))
+- Buffered UART improvements
+    - Add embedded-io ReadReady impls ([#3179](https://github.com/embassy-rs/embassy/pull/3179), [#3451](https://github.com/embassy-rs/embassy/pull/3451))
+    - Add constructors for RS485 ([#3441](https://github.com/embassy-rs/embassy/pull/3441))
+    - Fix RingBufferedUartRx hard-resetting DMA after initial error ([#3356](https://github.com/embassy-rs/embassy/pull/3356))
+    - Don't teardown during reconfigure ([#2989](https://github.com/embassy-rs/embassy/pull/2989))
+    - Wake receive task for each received byte ([#2722](https://github.com/embassy-rs/embassy/pull/2722))
+    - Fix dma and idle line detection in ringbuffereduartrx ([#3319](https://github.com/embassy-rs/embassy/pull/3319))
+SPI: 
+- Add MISO pullup configuration option ([#2943](https://github.com/embassy-rs/embassy/pull/2943))
+- Add slew rate configuration options ([#3669](https://github.com/embassy-rs/embassy/pull/3669))
+- Fix blocking_write on nosck spi. ([#3035](https://github.com/embassy-rs/embassy/pull/3035))
+- Restrict txonly_nosck to SPIv1, it hangs in other versions. ([#3028](https://github.com/embassy-rs/embassy/pull/3028))
+- Fix non-u8 word sizes. ([#3363](https://github.com/embassy-rs/embassy/pull/3363))
+- Issue correct DMA word length when reading to prevent hang. ([#3362](https://github.com/embassy-rs/embassy/pull/3362))
+- Add proper rxonly support for spi_v3 and force tx dma stream requirements. ([#3007](https://github.com/embassy-rs/embassy/pull/3007))
+I2C:
+- Implement asynchronous transactions ([#2742](https://github.com/embassy-rs/embassy/pull/2742))
+- Implement blocking transactions ([#2713](https://github.com/embassy-rs/embassy/pull/2713))
+- Disconnect pins on drop ([#3006](https://github.com/embassy-rs/embassy/pull/3006))
+- Ensure bus is free before master-write operation ([#3104](https://github.com/embassy-rs/embassy/pull/3104))
+- Add workaround for STM32 i2cv1 errata ([#2887](https://github.com/embassy-rs/embassy/pull/2887))
+- Fix disabling pullup accidentally enabling pulldown ([#3410](https://github.com/embassy-rs/embassy/pull/3410))
+Flash:
+- Add L5 support ([#3423](https://github.com/embassy-rs/embassy/pull/3423))
+- Add H5 support ([#3305](https://github.com/embassy-rs/embassy/pull/3305))
+- add F2 support ([#3303](https://github.com/embassy-rs/embassy/pull/3303))
+- Add U5 support ([#2591](https://github.com/embassy-rs/embassy/pull/2591), [#2792](https://github.com/embassy-rs/embassy/pull/2792))
+- Add H50x support ([#2600](https://github.com/embassy-rs/embassy/pull/2600), [#2808](https://github.com/embassy-rs/embassy/pull/2808))
+- Fix flash erase on F3 ([#3744](https://github.com/embassy-rs/embassy/pull/3744))
+- Support G0 second flash bank ([#3711](https://github.com/embassy-rs/embassy/pull/3711))
+- F1, F3: wait for BSY flag to clear before flashing ([#3217](https://github.com/embassy-rs/embassy/pull/3217))
+- H7: enhance resilience to program sequence errors (pgserr) ([#2539](https://github.com/embassy-rs/embassy/pull/2539))
+ADC:
+- Add `AnyAdcChannel` type. You can obtain it from a pin with `.degrade_adc()`. Useful for making arrays of ADC pins. ([#2985](https://github.com/embassy-rs/embassy/pull/2985))
+- Add L0 support ([#2544](https://github.com/embassy-rs/embassy/pull/2544))
+- Add U5 support ([#3688](https://github.com/embassy-rs/embassy/pull/3688))
+- Add H5 support ([#2613](https://github.com/embassy-rs/embassy/pull/2613), [#3557](https://github.com/embassy-rs/embassy/pull/3557))
+- Add G4 async support ([#3566](https://github.com/embassy-rs/embassy/pull/3566))
+- Add G4 support for calibrating differential inputs ([#3735](https://github.com/embassy-rs/embassy/pull/3735))
+- Add oversampling and differential support for G4 ([#3169](https://github.com/embassy-rs/embassy/pull/3169))
+- Add DMA support for ADC v2 ([#3116](https://github.com/embassy-rs/embassy/pull/3116))
+- Add DMA support for ADC v3 and v4 ([#3128](https://github.com/embassy-rs/embassy/pull/3128))
+- Unify naming `blocking_read` for blocking, `read` for async. ([#3148](https://github.com/embassy-rs/embassy/pull/3148))
+- Fix channel count for the STM32G4 ADCs. ([#2828](https://github.com/embassy-rs/embassy/pull/2828))
+- Fix blocking_delay_us() overflowing when sys freq is high ([#2825](https://github.com/embassy-rs/embassy/pull/2825))
+- Remove need for taking a `Delay` impl. ([#2797](https://github.com/embassy-rs/embassy/pull/2797))
+- H5: set OR.OP0 to 1 when ADCx_INP0 is selected, per RM ([#2776](https://github.com/embassy-rs/embassy/pull/2776))
+- Add oversampling support ([#3124](https://github.com/embassy-rs/embassy/pull/3124))
+- Adc averaging support for ADC v4. ([#3110](https://github.com/embassy-rs/embassy/pull/3110))
+- F2 ADC fixes ([#2513](https://github.com/embassy-rs/embassy/pull/2513))
+DAC:
+- Fix new_internal not setting mode as documented ([#2886](https://github.com/embassy-rs/embassy/pull/2886))
+OPAMP:
+- Add missing opamp external outputs for STM32G4 ([#3636](https://github.com/embassy-rs/embassy/pull/3636))
+- Add extra lifetime to opamp-using structs ([#3207](https://github.com/embassy-rs/embassy/pull/3207))
+- Make OpAmp usable in follower configuration for internal DAC channel ([#3021](https://github.com/embassy-rs/embassy/pull/3021))
+CAN:
+- Add FDCAN support. ([#2475](https://github.com/embassy-rs/embassy/pull/2475), [#2571](https://github.com/embassy-rs/embassy/pull/2571), [#2623](https://github.com/embassy-rs/embassy/pull/2623), [#2631](https://github.com/embassy-rs/embassy/pull/2631), [#2635](https://github.com/embassy-rs/embassy/pull/2635), [#2637](https://github.com/embassy-rs/embassy/pull/2637), [#2645](https://github.com/embassy-rs/embassy/pull/2645), [#2647](https://github.com/embassy-rs/embassy/pull/2647), [#2658](https://github.com/embassy-rs/embassy/pull/2658), [#2703](https://github.com/embassy-rs/embassy/pull/2703), [#3364](https://github.com/embassy-rs/embassy/pull/3364))
+- Simplify BXCAN API, make BXCAN and FDCAN APIs consistent. ([#2760](https://github.com/embassy-rs/embassy/pull/2760), [#2693](https://github.com/embassy-rs/embassy/pull/2693), [#2744](https://github.com/embassy-rs/embassy/pull/2744))
+- Add buffered mode support ([#2588](https://github.com/embassy-rs/embassy/pull/2588))
+- Add support for modifying the receiver filters from `BufferedCan`, `CanRx`, and `BufferedCanRx` ([#3733](https://github.com/embassy-rs/embassy/pull/3733))
+- Add support for optional FIFO scheduling for outgoing frames ([#2988](https://github.com/embassy-rs/embassy/pull/2988))
+- fdcan: Properties for common runtime get/set operations ([#2840](https://github.com/embassy-rs/embassy/pull/2840))
+- fdcan: implement bus-off recovery ([#2832](https://github.com/embassy-rs/embassy/pull/2832))
+- Add BXCAN sleep/wakeup functionality ([#2854](https://github.com/embassy-rs/embassy/pull/2854))
+- Fix BXCAN hangs ([#3468](https://github.com/embassy-rs/embassy/pull/3468))
+- add RTR flag if it is remote frame ([#3421](https://github.com/embassy-rs/embassy/pull/3421))
+- Fix log storm when no CAN is connected ([#3284](https://github.com/embassy-rs/embassy/pull/3284))
+- Fix error handling ([#2850](https://github.com/embassy-rs/embassy/pull/2850))
+- Give CAN a kick when writing into TX buffer via sender. ([#2646](https://github.com/embassy-rs/embassy/pull/2646))
+- Preseve the RTR flag in messages. ([#2745](https://github.com/embassy-rs/embassy/pull/2745))
+FMC:
+- Add 13bit address sdram constructors ([#3189](https://github.com/embassy-rs/embassy/pull/3189))
+xSPI:
+- Add OCTOSPI support ([#2672](https://github.com/embassy-rs/embassy/pull/2672))
+- Add OCTOSPIM support ([#3102](https://github.com/embassy-rs/embassy/pull/3102))
+- Add HEXADECASPI support ([#3667](https://github.com/embassy-rs/embassy/pull/3667))
+- Add memory mapping support for QSPI ([#3725](https://github.com/embassy-rs/embassy/pull/3725))
+- Add memory mapping support for OCTOSPI ([#3456](https://github.com/embassy-rs/embassy/pull/3456))
+- Add async support for QSPI ([#3475](https://github.com/embassy-rs/embassy/pull/3475))
+- Fix QSPI synchronous read operation hangs when FIFO is not full ([#3724](https://github.com/embassy-rs/embassy/pull/3724))
+- Stick to `blocking_*` naming convention for QSPI, OSPI ([#3661](https://github.com/embassy-rs/embassy/pull/3661))
+SDMMC:
+- Add `block-device-driver` impl for use with `embedded-fatfs` ([#2607](https://github.com/embassy-rs/embassy/pull/2607))
+- Allow cmd block to be passed in for sdmmc dma transfers ([#3188](https://github.com/embassy-rs/embassy/pull/3188))
+ETH:
+- Fix reception of multicast packets ([#3488](https://github.com/embassy-rs/embassy/pull/3488), [#3707](https://github.com/embassy-rs/embassy/pull/3707))
+- Add support for executing custom SMI commands ([#3355](https://github.com/embassy-rs/embassy/pull/3355))
+- Add support for MII interface ([#2465](https://github.com/embassy-rs/embassy/pull/2465))
+USB:
+- Assert correct clock on init. ([#2711](https://github.com/embassy-rs/embassy/pull/2711))
+- Set PWR_CR2 USV on STM32L4 ([#2605](https://github.com/embassy-rs/embassy/pull/2605))
+- USBD driver improvements:
+    - Add ISO endpoint support ([#3314](https://github.com/embassy-rs/embassy/pull/3314))
+    - Add support for L1. ([#2452](https://github.com/embassy-rs/embassy/pull/2452))
+    - set USB initialization delay to 1µs ([#3700](https://github.com/embassy-rs/embassy/pull/3700))
+- OTG driver improvements:
+    - Add ISO endpoint support ([#3314](https://github.com/embassy-rs/embassy/pull/3314))
+    - Add support for U595, U5A5 ([#3613](https://github.com/embassy-rs/embassy/pull/3613))
+    - Add support for STM32H7R/S ([#3337](https://github.com/embassy-rs/embassy/pull/3337))
+    - Add support for full-speed ULPI mode ([#3281](https://github.com/embassy-rs/embassy/pull/3281))
+    - Make max EP count configurable ([#2881](https://github.com/embassy-rs/embassy/pull/2881))
+    - fix corruption in CONTROL OUT transfers in stm32f4. ([#3565](https://github.com/embassy-rs/embassy/pull/3565))
+    - Extract Synopsys USB OTG driver to a separate crate ([#2871](https://github.com/embassy-rs/embassy/pull/2871))
+    - Add critical sections to avoid USB OTG corruption Errata ([#2823](https://github.com/embassy-rs/embassy/pull/2823))
+    - Fix support for OTG_HS in FS mode. ([#2805](https://github.com/embassy-rs/embassy/pull/2805))
+I2S:
+- Add SPIv3 support. ([#2992](https://github.com/embassy-rs/embassy/pull/2992))
+- Add full-duplex support. ([#2992](https://github.com/embassy-rs/embassy/pull/2992))
+- Add I2S ringbuffered DMA support ([#3023](https://github.com/embassy-rs/embassy/pull/3023))
+- Fix STM32F4 I2S clock calculations ([#3716](https://github.com/embassy-rs/embassy/pull/3716))
+SAI:
+- Add a function that waits for any SAI/ringbuffer write error ([#3545](https://github.com/embassy-rs/embassy/pull/3545))
+- Disallow start without an initial write ([#3541](https://github.com/embassy-rs/embassy/pull/3541))
+- Flush FIFO on init and disable ([#3538](https://github.com/embassy-rs/embassy/pull/3538))
+- Fix MCKDIV for SAI v3/v4 ([#2710](https://github.com/embassy-rs/embassy/pull/2710))
+- Pull down clock and data lines in receive mode ([#3326](https://github.com/embassy-rs/embassy/pull/3326))
+- Add function to check if SAI is muted ([#3282](https://github.com/embassy-rs/embassy/pull/3282))
+Low-power support:
+- Update `embassy-executor` to v0.7.
+- Add support for U0 ([#3556](https://github.com/embassy-rs/embassy/pull/3556))
+- Add support for U5 ([#3496](https://github.com/embassy-rs/embassy/pull/3496))
+- Add support for H5 ([#2877](https://github.com/embassy-rs/embassy/pull/2877))
+- Add support for L4 ([#3213](https://github.com/embassy-rs/embassy/pull/3213))
+- Fix low-power EXTI IRQ handler dropped edges ([#3404](https://github.com/embassy-rs/embassy/pull/3404))
+- Fix alarms not triggering in some cases ([#3592](https://github.com/embassy-rs/embassy/pull/3592))
+Timer:
+- Add Input Capture high-level driver ([#2912](https://github.com/embassy-rs/embassy/pull/2912))
+- Add PWM Input high-level driver ([#3014](https://github.com/embassy-rs/embassy/pull/3014))
+- Add support for splitting `SimplePwm` into channels ([#3317](https://github.com/embassy-rs/embassy/pull/3317))
+- Fix `SimplePwm` not enabling output pin in some stm32 families ([#2670](https://github.com/embassy-rs/embassy/pull/2670))
+- Add LPTIM low-level driver. ([#3310](https://github.com/embassy-rs/embassy/pull/3310))
+- Low-level TIM driver improvements:
+    - Simplify traits, convert from trait methods to struct. ([#2728](https://github.com/embassy-rs/embassy/pull/2728))
+    - Add `low_level::Timer::get_clock_frequency()` ([#2908](https://github.com/embassy-rs/embassy/pull/2908))
+    - Fix 32bit timer off by one ARR error ([#2876](https://github.com/embassy-rs/embassy/pull/2876))
+    - Avoid max_compare_value >= u16::MAX ([#3549](https://github.com/embassy-rs/embassy/pull/3549))
+DMA:
+- Add `AnyChannel` type. Similar to `AnyPin`, it allows representing any DMA channel at runtime without needing generics. ([#2606](https://github.com/embassy-rs/embassy/pull/2606))
+, Add support for BDMA on H7 ([#2606](https://github.com/embassy-rs/embassy/pull/2606))
+- Add async `stop()` function to BDMA, DMA ([#2757](https://github.com/embassy-rs/embassy/pull/2757))
+- Add configuration option for DMA Request Priority ([#2680](https://github.com/embassy-rs/embassy/pull/2680))
+- Rewrite DMA ringbuffers ([#3336](https://github.com/embassy-rs/embassy/pull/3336))
+- Enable half transfer IRQ when constructing a ReadableDmaRingBuffer ([#3093](https://github.com/embassy-rs/embassy/pull/3093))
+- Right-align `write_immediate()` in ring buffers ([#3588](https://github.com/embassy-rs/embassy/pull/3588))
+`embassy-time` driver:
+- Update to `embassy-time` v0.4, `embassy-time-driver` v0.2. ([#3593](https://github.com/embassy-rs/embassy/pull/3593))
+- Change preference order of `time-driver-any` to pick less-featureful timers first. ([#2570](https://github.com/embassy-rs/embassy/pull/2570))
+- Allow using more TIMx timers for the time driver  of TIM1 ([#2570](https://github.com/embassy-rs/embassy/pull/2570), [#2614](https://github.com/embassy-rs/embassy/pull/2614))
+- Correctly gate `time` feature of embassy-embedded-hal in embassy-stm32 ([#3359](https://github.com/embassy-rs/embassy/pull/3359))
+- adds timer-driver for tim21 and tim22 (on L0) ([#2450](https://github.com/embassy-rs/embassy/pull/2450))
+WDG:
+- Allow higher PSC value for iwdg_v3 ... ([#2628](https://github.com/embassy-rs/embassy/pull/2628))
+Misc:
+- Allow `bind_interrupts!` to accept conditional compilation attrs ([#3444](https://github.com/embassy-rs/embassy/pull/3444))
+## 0.1.0 - 2024-01-12
+First release.
diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index ac9e9644c..034f51df9 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "embassy-stm32"
-version = "0.1.0"
+version = "0.2.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "Embassy Hardware Abstraction Layer (HAL) for ST STM32 series microcontrollers"
@@ -19,16 +19,22 @@ flavors = [
    { regex_feature = "stm32f1.*", target = "thumbv7m-none-eabi" },
    { regex_feature = "stm32f2.*", target = "thumbv7m-none-eabi" },
    { regex_feature = "stm32f3.*", target = "thumbv7em-none-eabi" },
-    { regex_feature = "stm32f4.*", target = "thumbv7em-none-eabi", features = ["low-power"] },
+    { regex_feature = "stm32f4[2367]..[ig]", target = "thumbv7em-none-eabi", features = ["low-power", "dual-bank"] },
+    { regex_feature = "stm32f4.*", target = "thumbv7em-none-eabi", features = ["low-power", "single-bank"] },
+    { regex_feature = "stm32f7[67]..[ig]", target = "thumbv7em-none-eabi", features = ["dual-bank"] },
    { regex_feature = "stm32f7.*", target = "thumbv7em-none-eabi" },
    { regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" },
+    { regex_feature = "stm32g0...c", target = "thumbv6m-none-eabi", features = ["dual-bank"] },
    { regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" },
+    { regex_feature = "stm32g4[78].*", target = "thumbv7em-none-eabi", features = ["low-power", "dual-bank"] },
    { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi", features = ["low-power"] },
    { regex_feature = "stm32h5.*", target = "thumbv8m.main-none-eabihf", features = ["low-power"] },
    { regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" },
    { regex_feature = "stm32l0.*", target = "thumbv6m-none-eabi", features = ["low-power"] },
    { regex_feature = "stm32l1.*", target = "thumbv7m-none-eabi" },
+    { regex_feature = "stm32l4[pqrs].*", target = "thumbv7em-none-eabi", features = ["dual-bank"] },
    { regex_feature = "stm32l4.*", target = "thumbv7em-none-eabi" },
+    { regex_feature = "stm32l5...e", target = "thumbv8m.main-none-eabihf", features = ["low-power", "dual-bank"] },
    { regex_feature = "stm32l5.*", target = "thumbv8m.main-none-eabihf", features = ["low-power"] },
    { regex_feature = "stm32u0.*", target = "thumbv6m-none-eabi" },
    { regex_feature = "stm32u5.*", target = "thumbv8m.main-none-eabihf" },
@@ -38,20 +44,21 @@ flavors = [
 ]
 [package.metadata.docs.rs]
-features = ["defmt", "unstable-pac", "exti", "time-driver-any", "time", "stm32h755zi-cm7"]
+features = ["defmt", "unstable-pac", "exti", "time-driver-any", "time", "stm32h755zi-cm7", "single-bank"]
 rustdoc-args = ["--cfg", "docsrs"]
 [dependencies]
-embassy-sync = { version = "0.6.0", path = "../embassy-sync" }
+embassy-sync = { version = "0.7.0", path = "../embassy-sync" }
-embassy-time = { version = "0.3.2", path = "../embassy-time", optional = true }
+embassy-time = { version = "0.4.0", path = "../embassy-time", optional = true }
-embassy-time-driver = { version = "0.1", path = "../embassy-time-driver", optional = true }
+embassy-time-driver = { version = "0.2", path = "../embassy-time-driver", optional = true }
+embassy-time-queue-utils = { version = "0.1", path = "../embassy-time-queue-utils", optional = true }
 embassy-futures = { version = "0.1.0", path = "../embassy-futures" }
-embassy-hal-internal = {version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
+embassy-hal-internal = { version = "0.2.0", path = "../embassy-hal-internal", features = ["cortex-m", "prio-bits-4"] }
-embassy-embedded-hal = {version = "0.2.0", path = "../embassy-embedded-hal" }
+embassy-embedded-hal = { version = "0.3.0", path = "../embassy-embedded-hal", default-features = false }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
-embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver" }
+embassy-usb-driver = { version = "0.1.0", path = "../embassy-usb-driver" }
-embassy-usb-synopsys-otg = {version = "0.1.0", path = "../embassy-usb-synopsys-otg" }
+embassy-usb-synopsys-otg = { version = "0.2.0", path = "../embassy-usb-synopsys-otg" }
-embassy-executor = { version = "0.6.0", path = "../embassy-executor", optional = true }
+embassy-executor = { version = "0.7.0", path = "../embassy-executor", optional = true }
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 embedded-hal-1 = { package = "embedded-hal", version = "1.0" }
@@ -62,17 +69,19 @@ embedded-can = "0.4"
 embedded-storage = "0.3.1"
 embedded-storage-async = { version = "0.4.1" }
+rand-core-06 = { package = "rand_core", version = "0.6" }
+rand-core-09 = { package = "rand_core", version = "0.9" }
-defmt = { version = "0.3", optional = true }
+defmt = { version = "1.0.1", optional = true }
 log = { version = "0.4.14", optional = true }
 cortex-m-rt = ">=0.6.15,<0.8"
 cortex-m = "0.7.6"
 futures-util = { version = "0.3.30", default-features = false }
-rand_core = "0.6.3"
+sdio-host = "0.9.0"
-sdio-host = "0.5.0"
 critical-section = "1.1"
-#stm32-metapac = { version = "15" }
+#stm32-metapac = { version = "16" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e0cfd165fd8fffaa0df66a35eeca83b228496645" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec" }
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -88,16 +97,20 @@ static_assertions = { version = "1.1" }
 volatile-register = { version = "0.2.1" }
 bitflags = "2.4.2"
+block-device-driver = { version = "0.2" }
+aligned = "0.4.1"
 [dev-dependencies]
 critical-section = { version = "1.1", features = ["std"] }
+proptest = "1.5.0"
+proptest-state-machine = "0.3.0"
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-#stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
+#stm32-metapac = { version = "16", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-e0cfd165fd8fffaa0df66a35eeca83b228496645", default-features = false, features = ["metadata"] }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-27ef8fba3483187e852eaf3796d827259f61e8ec", default-features = false, features = ["metadata"] }
 [features]
 default = ["rt"]
@@ -106,14 +119,24 @@ default = ["rt"]
 rt = ["stm32-metapac/rt"]
 ## Use [`defmt`](https://docs.rs/defmt/latest/defmt/) for logging
-defmt = ["dep:defmt", "embassy-sync/defmt", "embassy-embedded-hal/defmt", "embassy-hal-internal/defmt", "embedded-io-async/defmt-03", "embassy-usb-driver/defmt", "embassy-net-driver/defmt", "embassy-time?/defmt"]
+defmt = [
+    "dep:defmt",
+    "embassy-sync/defmt",
+    "embassy-embedded-hal/defmt",
+    "embassy-hal-internal/defmt",
+    "embedded-io-async/defmt-03",
+    "embassy-usb-driver/defmt",
+    "embassy-net-driver/defmt",
+    "embassy-time?/defmt",
+    "embassy-usb-synopsys-otg/defmt",
+]
 exti = []
 low-power = [ "dep:embassy-executor", "embassy-executor?/arch-cortex-m", "time" ]
 low-power-debug-with-sleep = []
-## Automatically generate `memory.x` file using [`stm32-metapac`](https://docs.rs/stm32-metapac/)
+## Automatically generate `memory.x` file based on the memory map from [`stm32-metapac`](https://docs.rs/stm32-metapac/)
-memory-x = ["stm32-metapac/memory-x"]
+memory-x = []
 ## Use secure registers when TrustZone is enabled
 trustzone-secure = []
@@ -124,14 +147,18 @@ trustzone-secure = []
 ## There are no plans to make this stable.
 unstable-pac = []
+## Enable this feature to disable the overclocking check.
+## DO NOT ENABLE THIS FEATURE UNLESS YOU KNOW WHAT YOU'RE DOING.
+unchecked-overclocking = []
 #! ## Time
 ## Enables additional driver features that depend on embassy-time
-time = ["dep:embassy-time"]
+time = ["dep:embassy-time", "embassy-embedded-hal/time"]
 # Features starting with `_` are for internal use only. They're not intended
 # to be enabled by other crates, and are not covered by semver guarantees.
-_time-driver = ["dep:embassy-time-driver", "time"]
+_time-driver = ["dep:embassy-time-driver", "time", "dep:embassy-time-queue-utils"]
 ## Use any time driver
 time-driver-any = ["_time-driver"]
@@ -178,11 +205,17 @@ split-pc2 = ["_split-pins-enabled"]
 ## Split PC3
 split-pc3 = ["_split-pins-enabled"]
+dual-bank = []
+single-bank = []
 ## internal use only
 _split-pins-enabled = []
 ## internal use only
 _dual-core = []
+_core-cm0p = []
+_core-cm4 = []
+_core-cm7 = []
 #! ## Chip-selection features
 #! Select your chip by specifying the model as a feature, e.g. `stm32c011d6`.
@@ -1007,40 +1040,40 @@ stm32h743xg = [ "stm32-metapac/stm32h743xg" ]
 stm32h743xi = [ "stm32-metapac/stm32h743xi" ]
 stm32h743zg = [ "stm32-metapac/stm32h743zg" ]
 stm32h743zi = [ "stm32-metapac/stm32h743zi" ]
-stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "_dual-core" ]
+stm32h745bg-cm7 = [ "stm32-metapac/stm32h745bg-cm7", "_dual-core", "_core-cm7" ]
-stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "_dual-core" ]
+stm32h745bg-cm4 = [ "stm32-metapac/stm32h745bg-cm4", "_dual-core", "_core-cm4" ]
-stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "_dual-core" ]
+stm32h745bi-cm7 = [ "stm32-metapac/stm32h745bi-cm7", "_dual-core", "_core-cm7" ]
-stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "_dual-core" ]
+stm32h745bi-cm4 = [ "stm32-metapac/stm32h745bi-cm4", "_dual-core", "_core-cm4" ]
-stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "_dual-core" ]
+stm32h745ig-cm7 = [ "stm32-metapac/stm32h745ig-cm7", "_dual-core", "_core-cm7" ]
-stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "_dual-core" ]
+stm32h745ig-cm4 = [ "stm32-metapac/stm32h745ig-cm4", "_dual-core", "_core-cm4" ]
-stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "_dual-core" ]
+stm32h745ii-cm7 = [ "stm32-metapac/stm32h745ii-cm7", "_dual-core", "_core-cm7" ]
-stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "_dual-core" ]
+stm32h745ii-cm4 = [ "stm32-metapac/stm32h745ii-cm4", "_dual-core", "_core-cm4" ]
-stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "_dual-core" ]
+stm32h745xg-cm7 = [ "stm32-metapac/stm32h745xg-cm7", "_dual-core", "_core-cm7" ]
-stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "_dual-core" ]
+stm32h745xg-cm4 = [ "stm32-metapac/stm32h745xg-cm4", "_dual-core", "_core-cm4" ]
-stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "_dual-core" ]
+stm32h745xi-cm7 = [ "stm32-metapac/stm32h745xi-cm7", "_dual-core", "_core-cm7" ]
-stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "_dual-core" ]
+stm32h745xi-cm4 = [ "stm32-metapac/stm32h745xi-cm4", "_dual-core", "_core-cm4" ]
-stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "_dual-core" ]
+stm32h745zg-cm7 = [ "stm32-metapac/stm32h745zg-cm7", "_dual-core", "_core-cm7" ]
-stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "_dual-core" ]
+stm32h745zg-cm4 = [ "stm32-metapac/stm32h745zg-cm4", "_dual-core", "_core-cm4" ]
-stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "_dual-core" ]
+stm32h745zi-cm7 = [ "stm32-metapac/stm32h745zi-cm7", "_dual-core", "_core-cm7" ]
-stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "_dual-core" ]
+stm32h745zi-cm4 = [ "stm32-metapac/stm32h745zi-cm4", "_dual-core", "_core-cm4" ]
-stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "_dual-core" ]
+stm32h747ag-cm7 = [ "stm32-metapac/stm32h747ag-cm7", "_dual-core", "_core-cm7" ]
-stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "_dual-core" ]
+stm32h747ag-cm4 = [ "stm32-metapac/stm32h747ag-cm4", "_dual-core", "_core-cm4" ]
-stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "_dual-core" ]
+stm32h747ai-cm7 = [ "stm32-metapac/stm32h747ai-cm7", "_dual-core", "_core-cm7" ]
-stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "_dual-core" ]
+stm32h747ai-cm4 = [ "stm32-metapac/stm32h747ai-cm4", "_dual-core", "_core-cm4" ]
-stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "_dual-core" ]
+stm32h747bg-cm7 = [ "stm32-metapac/stm32h747bg-cm7", "_dual-core", "_core-cm7" ]
-stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "_dual-core" ]
+stm32h747bg-cm4 = [ "stm32-metapac/stm32h747bg-cm4", "_dual-core", "_core-cm4" ]
-stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "_dual-core" ]
+stm32h747bi-cm7 = [ "stm32-metapac/stm32h747bi-cm7", "_dual-core", "_core-cm7" ]
-stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "_dual-core" ]
+stm32h747bi-cm4 = [ "stm32-metapac/stm32h747bi-cm4", "_dual-core", "_core-cm4" ]
-stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "_dual-core" ]
+stm32h747ig-cm7 = [ "stm32-metapac/stm32h747ig-cm7", "_dual-core", "_core-cm7" ]
-stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "_dual-core" ]
+stm32h747ig-cm4 = [ "stm32-metapac/stm32h747ig-cm4", "_dual-core", "_core-cm4" ]
-stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "_dual-core" ]
+stm32h747ii-cm7 = [ "stm32-metapac/stm32h747ii-cm7", "_dual-core", "_core-cm7" ]
-stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "_dual-core" ]
+stm32h747ii-cm4 = [ "stm32-metapac/stm32h747ii-cm4", "_dual-core", "_core-cm4" ]
-stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "_dual-core" ]
+stm32h747xg-cm7 = [ "stm32-metapac/stm32h747xg-cm7", "_dual-core", "_core-cm7" ]
-stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "_dual-core" ]
+stm32h747xg-cm4 = [ "stm32-metapac/stm32h747xg-cm4", "_dual-core", "_core-cm4" ]
-stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "_dual-core" ]
+stm32h747xi-cm7 = [ "stm32-metapac/stm32h747xi-cm7", "_dual-core", "_core-cm7" ]
-stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "_dual-core" ]
+stm32h747xi-cm4 = [ "stm32-metapac/stm32h747xi-cm4", "_dual-core", "_core-cm4" ]
-stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "_dual-core" ]
+stm32h747zi-cm7 = [ "stm32-metapac/stm32h747zi-cm7", "_dual-core", "_core-cm7" ]
-stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "_dual-core" ]
+stm32h747zi-cm4 = [ "stm32-metapac/stm32h747zi-cm4", "_dual-core", "_core-cm4" ]
 stm32h750ib = [ "stm32-metapac/stm32h750ib" ]
 stm32h750vb = [ "stm32-metapac/stm32h750vb" ]
 stm32h750xb = [ "stm32-metapac/stm32h750xb" ]
@@ -1051,24 +1084,24 @@ stm32h753ii = [ "stm32-metapac/stm32h753ii" ]
 stm32h753vi = [ "stm32-metapac/stm32h753vi" ]
 stm32h753xi = [ "stm32-metapac/stm32h753xi" ]
 stm32h753zi = [ "stm32-metapac/stm32h753zi" ]
-stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "_dual-core" ]
+stm32h755bi-cm7 = [ "stm32-metapac/stm32h755bi-cm7", "_dual-core", "_core-cm7" ]
-stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "_dual-core" ]
+stm32h755bi-cm4 = [ "stm32-metapac/stm32h755bi-cm4", "_dual-core", "_core-cm4" ]
-stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "_dual-core" ]
+stm32h755ii-cm7 = [ "stm32-metapac/stm32h755ii-cm7", "_dual-core", "_core-cm7" ]
-stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "_dual-core" ]
+stm32h755ii-cm4 = [ "stm32-metapac/stm32h755ii-cm4", "_dual-core", "_core-cm4" ]
-stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "_dual-core" ]
+stm32h755xi-cm7 = [ "stm32-metapac/stm32h755xi-cm7", "_dual-core", "_core-cm7" ]
-stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "_dual-core" ]
+stm32h755xi-cm4 = [ "stm32-metapac/stm32h755xi-cm4", "_dual-core", "_core-cm4" ]
-stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "_dual-core" ]
+stm32h755zi-cm7 = [ "stm32-metapac/stm32h755zi-cm7", "_dual-core", "_core-cm7" ]
-stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "_dual-core" ]
+stm32h755zi-cm4 = [ "stm32-metapac/stm32h755zi-cm4", "_dual-core", "_core-cm4" ]
-stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "_dual-core" ]
+stm32h757ai-cm7 = [ "stm32-metapac/stm32h757ai-cm7", "_dual-core", "_core-cm7" ]
-stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "_dual-core" ]
+stm32h757ai-cm4 = [ "stm32-metapac/stm32h757ai-cm4", "_dual-core", "_core-cm4" ]
-stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "_dual-core" ]
+stm32h757bi-cm7 = [ "stm32-metapac/stm32h757bi-cm7", "_dual-core", "_core-cm7" ]
-stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "_dual-core" ]
+stm32h757bi-cm4 = [ "stm32-metapac/stm32h757bi-cm4", "_dual-core", "_core-cm4" ]
-stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "_dual-core" ]
+stm32h757ii-cm7 = [ "stm32-metapac/stm32h757ii-cm7", "_dual-core", "_core-cm7" ]
-stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "_dual-core" ]
+stm32h757ii-cm4 = [ "stm32-metapac/stm32h757ii-cm4", "_dual-core", "_core-cm4" ]
-stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "_dual-core" ]
+stm32h757xi-cm7 = [ "stm32-metapac/stm32h757xi-cm7", "_dual-core", "_core-cm7" ]
-stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "_dual-core" ]
+stm32h757xi-cm4 = [ "stm32-metapac/stm32h757xi-cm4", "_dual-core", "_core-cm4" ]
-stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "_dual-core" ]
+stm32h757zi-cm7 = [ "stm32-metapac/stm32h757zi-cm7", "_dual-core", "_core-cm7" ]
-stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "_dual-core" ]
+stm32h757zi-cm4 = [ "stm32-metapac/stm32h757zi-cm4", "_dual-core", "_core-cm4" ]
 stm32h7a3ag = [ "stm32-metapac/stm32h7a3ag" ]
 stm32h7a3ai = [ "stm32-metapac/stm32h7a3ai" ]
 stm32h7a3ig = [ "stm32-metapac/stm32h7a3ig" ]
@@ -1601,14 +1634,14 @@ stm32wba55he = [ "stm32-metapac/stm32wba55he" ]
 stm32wba55hg = [ "stm32-metapac/stm32wba55hg" ]
 stm32wba55ue = [ "stm32-metapac/stm32wba55ue" ]
 stm32wba55ug = [ "stm32-metapac/stm32wba55ug" ]
-stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core" ]
+stm32wl54cc-cm4 = [ "stm32-metapac/stm32wl54cc-cm4", "_dual-core", "_core-cm4" ]
-stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core" ]
+stm32wl54cc-cm0p = [ "stm32-metapac/stm32wl54cc-cm0p", "_dual-core", "_core-cm0p" ]
-stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core" ]
+stm32wl54jc-cm4 = [ "stm32-metapac/stm32wl54jc-cm4", "_dual-core", "_core-cm4" ]
-stm32wl54jc-cm0p = [ "stm32-metapac/stm32wl54jc-cm0p", "_dual-core" ]
+stm32wl54jc-cm0p = [ "stm32-metapac/stm32wl54jc-cm0p", "_dual-core", "_core-cm0p" ]
-stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4", "_dual-core" ]
+stm32wl55cc-cm4 = [ "stm32-metapac/stm32wl55cc-cm4", "_dual-core", "_core-cm4" ]
-stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p", "_dual-core" ]
+stm32wl55cc-cm0p = [ "stm32-metapac/stm32wl55cc-cm0p", "_dual-core", "_core-cm0p" ]
-stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4", "_dual-core" ]
+stm32wl55jc-cm4 = [ "stm32-metapac/stm32wl55jc-cm4", "_dual-core", "_core-cm4" ]
-stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p", "_dual-core" ]
+stm32wl55jc-cm0p = [ "stm32-metapac/stm32wl55jc-cm0p", "_dual-core", "_core-cm0p" ]
 stm32wle4c8 = [ "stm32-metapac/stm32wle4c8" ]
 stm32wle4cb = [ "stm32-metapac/stm32wle4cb" ]
 stm32wle4cc = [ "stm32-metapac/stm32wle4cc" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index d8a7ea0e6..bb5ef53d7 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -9,8 +9,8 @@ use proc_macro2::{Ident, TokenStream};
 use quote::{format_ident, quote};
 use stm32_metapac::metadata::ir::BitOffset;
 use stm32_metapac::metadata::{
-    MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode, ALL_CHIPS,
+    MemoryRegion, MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode,
-    ALL_PERIPHERAL_VERSIONS, METADATA,
+    ALL_CHIPS, ALL_PERIPHERAL_VERSIONS, METADATA,
 };
 #[path = "./build_common.rs"]
@@ -50,12 +50,63 @@ fn main() {
    }
    // ========
+    // Select the memory variant to use
+    let memory = {
+        let single_bank_selected = env::var("CARGO_FEATURE_SINGLE_BANK").is_ok();
+        let dual_bank_selected = env::var("CARGO_FEATURE_DUAL_BANK").is_ok();
+        let single_bank_memory = METADATA.memory.iter().find(|mem| {
+            mem.iter().any(|region| region.name.contains("BANK_1"))
+                && !mem.iter().any(|region| region.name.contains("BANK_2"))
+        });
+        let dual_bank_memory = METADATA.memory.iter().find(|mem| {
+            mem.iter().any(|region| region.name.contains("BANK_1"))
+                && mem.iter().any(|region| region.name.contains("BANK_2"))
+        });
+        cfgs.set(
+            "bank_setup_configurable",
+            single_bank_memory.is_some() && dual_bank_memory.is_some(),
+        );
+        match (single_bank_selected, dual_bank_selected) {
+            (true, true) => panic!("Both 'single-bank' and 'dual-bank' features enabled"),
+            (true, false) => {
+                single_bank_memory.expect("The 'single-bank' feature is not supported on this dual bank chip")
+            }
+            (false, true) => {
+                dual_bank_memory.expect("The 'dual-bank' feature is not supported on this single bank chip")
+            }
+            (false, false) => {
+                if METADATA.memory.len() != 1 {
+                    panic!("Chip supports single and dual bank configuration. No Cargo feature to select one is enabled. Use the 'single-bank' or 'dual-bank' feature to make your selection")
+                }
+                METADATA.memory[0]
+            }
+        }
+    };
+    // ========
    // Generate singletons
    let mut singletons: Vec<String> = Vec::new();
+    // Generate one singleton per pin
+    for p in METADATA.pins {
+        singletons.push(p.name.to_string());
+    }
+    // generate one singleton per peripheral (with many exceptions...)
    for p in METADATA.peripherals {
        if let Some(r) = &p.registers {
-            if r.kind == "adccommon" || r.kind == "sai" || r.kind == "ucpd" {
+            if r.kind == "adccommon"
+                || r.kind == "sai"
+                || r.kind == "ucpd"
+                || r.kind == "otg"
+                || r.kind == "octospi"
+                || r.kind == "xspi"
+            {
                // TODO: should we emit this for all peripherals? if so, we will need a list of all
                // possible peripherals across all chips, so that we can declare the configs
                // (replacing the hard-coded list of `peri_*` cfgs below)
@@ -63,13 +114,8 @@ fn main() {
            }
            match r.kind {
-                // Generate singletons per pin, not per port
+                // handled above
-                "gpio" => {
+                "gpio" => {}
-                    let port_letter = p.name.strip_prefix("GPIO").unwrap();
-                    for pin_num in 0..16 {
-                        singletons.push(format!("P{}{}", port_letter, pin_num));
-                    }
-                }
                // No singleton for these, the HAL handles them specially.
                "exti" => {}
@@ -111,6 +157,10 @@ fn main() {
        "peri_sai4",
        "peri_ucpd1",
        "peri_ucpd2",
+        "peri_usb_otg_fs",
+        "peri_usb_otg_hs",
+        "peri_octospi2",
+        "peri_xspi2",
    ]);
    cfgs.declare_all(&["mco", "mco1", "mco2"]);
@@ -192,7 +242,7 @@ fn main() {
                .to_ascii_lowercase(),
        ),
        Err(GetOneError::None) => None,
-        Err(GetOneError::Multiple) => panic!("Multiple stm32xx Cargo features enabled"),
+        Err(GetOneError::Multiple) => panic!("Multiple time-driver-xxx Cargo features enabled"),
    };
    let time_driver_singleton = match time_driver.as_ref().map(|x| x.as_ref()) {
@@ -278,8 +328,7 @@ fn main() {
    // ========
    // Generate FLASH regions
    let mut flash_regions = TokenStream::new();
-    let flash_memory_regions: Vec<_> = METADATA
+    let flash_memory_regions: Vec<_> = memory
-        .memory
        .iter()
        .filter(|x| x.kind == MemoryRegionKind::Flash && x.settings.is_some())
        .collect();
@@ -291,6 +340,8 @@ fn main() {
                "Bank1"
            } else if region.name.starts_with("BANK_2") {
                "Bank2"
+            } else if region.name == "OTP" {
+                "Otp"
            } else {
                continue;
            }
@@ -317,7 +368,7 @@ fn main() {
        let region_type = format_ident!("{}", get_flash_region_type_name(region.name));
        flash_regions.extend(quote! {
            #[cfg(flash)]
-            pub struct #region_type<'d, MODE = crate::flash::Async>(pub &'static crate::flash::FlashRegion, pub(crate) embassy_hal_internal::PeripheralRef<'d, crate::peripherals::FLASH>, pub(crate) core::marker::PhantomData<MODE>);
+            pub struct #region_type<'d, MODE = crate::flash::Async>(pub &'static crate::flash::FlashRegion, pub(crate) embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>, pub(crate) core::marker::PhantomData<MODE>);
        });
    }
@@ -349,7 +400,7 @@ fn main() {
        #[cfg(flash)]
        impl<'d, MODE> FlashLayout<'d, MODE> {
-            pub(crate) fn new(p: embassy_hal_internal::PeripheralRef<'d, crate::peripherals::FLASH>) -> Self {
+            pub(crate) fn new(p: embassy_hal_internal::Peri<'d, crate::peripherals::FLASH>) -> Self {
                Self {
                    #(#inits),*,
                    _mode: core::marker::PhantomData,
@@ -475,9 +526,39 @@ fn main() {
    }
    impl<'a> ClockGen<'a> {
+        fn parse_mul_div(name: &str) -> (&str, Frac) {
+            if name == "hse_div_rtcpre" {
+                return (name, Frac { num: 1, denom: 1 });
+            }
+            if let Some(i) = name.find("_div_") {
+                let n = &name[..i];
+                let val: u32 = name[i + 5..].parse().unwrap();
+                (n, Frac { num: 1, denom: val })
+            } else if let Some(i) = name.find("_mul_") {
+                let n = &name[..i];
+                let val: u32 = name[i + 5..].parse().unwrap();
+                (n, Frac { num: val, denom: 1 })
+            } else {
+                (name, Frac { num: 1, denom: 1 })
+            }
+        }
        fn gen_clock(&mut self, peripheral: &str, name: &str) -> TokenStream {
-            let clock_name = format_ident!("{}", name.to_ascii_lowercase());
+            let name = name.to_ascii_lowercase();
-            self.clock_names.insert(name.to_ascii_lowercase());
+            let (name, frac) = Self::parse_mul_div(&name);
+            let clock_name = format_ident!("{}", name);
+            self.clock_names.insert(name.to_string());
+            let mut muldiv = quote!();
+            if frac.num != 1 {
+                let val = frac.num;
+                muldiv.extend(quote!(* #val));
+            }
+            if frac.denom != 1 {
+                let val = frac.denom;
+                muldiv.extend(quote!(/ #val));
+            }
            quote!(unsafe {
                unwrap!(
                    crate::rcc::get_freqs().#clock_name.to_hertz(),
@@ -486,6 +567,7 @@ fn main() {
                    #peripheral,
                    #name
                )
+                #muldiv
            })
        }
@@ -527,7 +609,11 @@ fn main() {
                match crate::pac::RCC.#fieldset_name().read().#field_name() {
                    #match_arms
                    #[allow(unreachable_patterns)]
-                    _ => unreachable!(),
+                    _ => panic!(
+                        "attempted to use peripheral '{}' but its clock mux is not set to a valid \
+                         clock. Change 'config.rcc.mux' to another clock.",
+                        #peripheral
+                    )
                }
            }
        }
@@ -598,6 +684,8 @@ fn main() {
                PeripheralRccKernelClock::Clock(clock) => clock_gen.gen_clock(p.name, clock),
            };
+            let bus_clock_frequency = clock_gen.gen_clock(p.name, &rcc.bus_clock);
            // A refcount leak can result if the same field is shared by peripherals with different stop modes
            // This condition should be checked in stm32-data
            let stop_mode = match rcc.stop_mode {
@@ -611,6 +699,9 @@ fn main() {
                    fn frequency() -> crate::time::Hertz {
                        #clock_frequency
                    }
+                    fn bus_frequency() -> crate::time::Hertz {
+                        #bus_clock_frequency
+                    }
                    const RCC_INFO: crate::rcc::RccInfo = unsafe {
                        crate::rcc::RccInfo::new(
@@ -709,6 +800,16 @@ fn main() {
    // Generate RCC
    clock_gen.clock_names.insert("sys".to_string());
    clock_gen.clock_names.insert("rtc".to_string());
+    // STM32F4 SPI in I2S mode receives a clock input from the dedicated I2S PLL.
+    // For this, there is an additional clock MUX, which is not present in other
+    // peripherals and does not fit the current RCC structure of stm32-data.
+    if chip_name.starts_with("stm32f4") && !chip_name.starts_with("stm32f410") {
+        clock_gen.clock_names.insert("plli2s1_p".to_string());
+        clock_gen.clock_names.insert("plli2s1_q".to_string());
+        clock_gen.clock_names.insert("plli2s1_r".to_string());
+    }
    let clock_idents: Vec<_> = clock_gen.clock_names.iter().map(|n| format_ident!("{}", n)).collect();
    g.extend(quote! {
        #[derive(Clone, Copy, Debug)]
@@ -857,6 +958,7 @@ fn main() {
        (("ltdc", "B7"), quote!(crate::ltdc::B7Pin)),
        (("usb", "DP"), quote!(crate::usb::DpPin)),
        (("usb", "DM"), quote!(crate::usb::DmPin)),
+        (("usb", "SOF"), quote!(crate::usb::SofPin)),
        (("otg", "DP"), quote!(crate::usb::DpPin)),
        (("otg", "DM"), quote!(crate::usb::DmPin)),
        (("otg", "ULPI_CK"), quote!(crate::usb::UlpiClkPin)),
@@ -1015,6 +1117,9 @@ fn main() {
        (("hrtim", "CHE2"), quote!(crate::hrtim::ChannelEComplementaryPin)),
        (("hrtim", "CHF1"), quote!(crate::hrtim::ChannelFPin)),
        (("hrtim", "CHF2"), quote!(crate::hrtim::ChannelFComplementaryPin)),
+        (("lptim", "CH1"), quote!(crate::lptim::Channel1Pin)),
+        (("lptim", "CH2"), quote!(crate::lptim::Channel2Pin)),
+        (("lptim", "OUT"), quote!(crate::lptim::OutputPin)),
        (("sdmmc", "CK"), quote!(crate::sdmmc::CkPin)),
        (("sdmmc", "CMD"), quote!(crate::sdmmc::CmdPin)),
        (("sdmmc", "D0"), quote!(crate::sdmmc::D0Pin)),
@@ -1024,7 +1129,7 @@ fn main() {
        (("sdmmc", "D4"), quote!(crate::sdmmc::D4Pin)),
        (("sdmmc", "D5"), quote!(crate::sdmmc::D5Pin)),
        (("sdmmc", "D6"), quote!(crate::sdmmc::D6Pin)),
-        (("sdmmc", "D6"), quote!(crate::sdmmc::D7Pin)),
+        (("sdmmc", "D7"), quote!(crate::sdmmc::D7Pin)),
        (("sdmmc", "D8"), quote!(crate::sdmmc::D8Pin)),
        (("quadspi", "BK1_IO0"), quote!(crate::qspi::BK1D0Pin)),
        (("quadspi", "BK1_IO1"), quote!(crate::qspi::BK1D1Pin)),
@@ -1049,6 +1154,117 @@ fn main() {
        (("octospi", "NCS"), quote!(crate::ospi::NSSPin)),
        (("octospi", "CLK"), quote!(crate::ospi::SckPin)),
        (("octospi", "NCLK"), quote!(crate::ospi::NckPin)),
+        (("octospim", "P1_IO0"), quote!(crate::ospi::D0Pin)),
+        (("octospim", "P1_IO1"), quote!(crate::ospi::D1Pin)),
+        (("octospim", "P1_IO2"), quote!(crate::ospi::D2Pin)),
+        (("octospim", "P1_IO3"), quote!(crate::ospi::D3Pin)),
+        (("octospim", "P1_IO4"), quote!(crate::ospi::D4Pin)),
+        (("octospim", "P1_IO5"), quote!(crate::ospi::D5Pin)),
+        (("octospim", "P1_IO6"), quote!(crate::ospi::D6Pin)),
+        (("octospim", "P1_IO7"), quote!(crate::ospi::D7Pin)),
+        (("octospim", "P1_DQS"), quote!(crate::ospi::DQSPin)),
+        (("octospim", "P1_NCS"), quote!(crate::ospi::NSSPin)),
+        (("octospim", "P1_CLK"), quote!(crate::ospi::SckPin)),
+        (("octospim", "P1_NCLK"), quote!(crate::ospi::NckPin)),
+        (("octospim", "P2_IO0"), quote!(crate::ospi::D0Pin)),
+        (("octospim", "P2_IO1"), quote!(crate::ospi::D1Pin)),
+        (("octospim", "P2_IO2"), quote!(crate::ospi::D2Pin)),
+        (("octospim", "P2_IO3"), quote!(crate::ospi::D3Pin)),
+        (("octospim", "P2_IO4"), quote!(crate::ospi::D4Pin)),
+        (("octospim", "P2_IO5"), quote!(crate::ospi::D5Pin)),
+        (("octospim", "P2_IO6"), quote!(crate::ospi::D6Pin)),
+        (("octospim", "P2_IO7"), quote!(crate::ospi::D7Pin)),
+        (("octospim", "P2_DQS"), quote!(crate::ospi::DQSPin)),
+        (("octospim", "P2_NCS"), quote!(crate::ospi::NSSPin)),
+        (("octospim", "P2_CLK"), quote!(crate::ospi::SckPin)),
+        (("octospim", "P2_NCLK"), quote!(crate::ospi::NckPin)),
+        (("xspi", "IO0"), quote!(crate::xspi::D0Pin)),
+        (("xspi", "IO1"), quote!(crate::xspi::D1Pin)),
+        (("xspi", "IO2"), quote!(crate::xspi::D2Pin)),
+        (("xspi", "IO3"), quote!(crate::xspi::D3Pin)),
+        (("xspi", "IO4"), quote!(crate::xspi::D4Pin)),
+        (("xspi", "IO5"), quote!(crate::xspi::D5Pin)),
+        (("xspi", "IO6"), quote!(crate::xspi::D6Pin)),
+        (("xspi", "IO7"), quote!(crate::xspi::D7Pin)),
+        (("xspi", "IO8"), quote!(crate::xspi::D8Pin)),
+        (("xspi", "IO9"), quote!(crate::xspi::D9Pin)),
+        (("xspi", "IO10"), quote!(crate::xspi::D10Pin)),
+        (("xspi", "IO11"), quote!(crate::xspi::D11Pin)),
+        (("xspi", "IO12"), quote!(crate::xspi::D12Pin)),
+        (("xspi", "IO13"), quote!(crate::xspi::D13Pin)),
+        (("xspi", "IO14"), quote!(crate::xspi::D14Pin)),
+        (("xspi", "IO15"), quote!(crate::xspi::D15Pin)),
+        (("xspi", "DQS0"), quote!(crate::xspi::DQS0Pin)),
+        (("xspi", "DQS1"), quote!(crate::xspi::DQS1Pin)),
+        (("xspi", "NCS1"), quote!(crate::xspi::NCSPin)),
+        (("xspi", "NCS2"), quote!(crate::xspi::NCSPin)),
+        (("xspi", "CLK"), quote!(crate::xspi::CLKPin)),
+        (("xspi", "NCLK"), quote!(crate::xspi::NCLKPin)),
+        (("xspim", "P1_IO0"), quote!(crate::xspi::D0Pin)),
+        (("xspim", "P1_IO1"), quote!(crate::xspi::D1Pin)),
+        (("xspim", "P1_IO2"), quote!(crate::xspi::D2Pin)),
+        (("xspim", "P1_IO3"), quote!(crate::xspi::D3Pin)),
+        (("xspim", "P1_IO4"), quote!(crate::xspi::D4Pin)),
+        (("xspim", "P1_IO5"), quote!(crate::xspi::D5Pin)),
+        (("xspim", "P1_IO6"), quote!(crate::xspi::D6Pin)),
+        (("xspim", "P1_IO7"), quote!(crate::xspi::D7Pin)),
+        (("xspim", "P1_IO8"), quote!(crate::xspi::D8Pin)),
+        (("xspim", "P1_IO9"), quote!(crate::xspi::D9Pin)),
+        (("xspim", "P1_IO10"), quote!(crate::xspi::D10Pin)),
+        (("xspim", "P1_IO11"), quote!(crate::xspi::D11Pin)),
+        (("xspim", "P1_IO12"), quote!(crate::xspi::D12Pin)),
+        (("xspim", "P1_IO13"), quote!(crate::xspi::D13Pin)),
+        (("xspim", "P1_IO14"), quote!(crate::xspi::D14Pin)),
+        (("xspim", "P1_IO15"), quote!(crate::xspi::D15Pin)),
+        (("xspim", "P1_DQS0"), quote!(crate::xspi::DQS0Pin)),
+        (("xspim", "P1_DQS1"), quote!(crate::xspi::DQS1Pin)),
+        (("xspim", "P1_NCS1"), quote!(crate::xspi::NCSPin)),
+        (("xspim", "P1_NCS2"), quote!(crate::xspi::NCSPin)),
+        (("xspim", "P1_CLK"), quote!(crate::xspi::CLKPin)),
+        (("xspim", "P1_NCLK"), quote!(crate::xspi::NCLKPin)),
+        (("xspim", "P2_IO0"), quote!(crate::xspi::D0Pin)),
+        (("xspim", "P2_IO1"), quote!(crate::xspi::D1Pin)),
+        (("xspim", "P2_IO2"), quote!(crate::xspi::D2Pin)),
+        (("xspim", "P2_IO3"), quote!(crate::xspi::D3Pin)),
+        (("xspim", "P2_IO4"), quote!(crate::xspi::D4Pin)),
+        (("xspim", "P2_IO5"), quote!(crate::xspi::D5Pin)),
+        (("xspim", "P2_IO6"), quote!(crate::xspi::D6Pin)),
+        (("xspim", "P2_IO7"), quote!(crate::xspi::D7Pin)),
+        (("xspim", "P2_IO8"), quote!(crate::xspi::D8Pin)),
+        (("xspim", "P2_IO9"), quote!(crate::xspi::D9Pin)),
+        (("xspim", "P2_IO10"), quote!(crate::xspi::D10Pin)),
+        (("xspim", "P2_IO11"), quote!(crate::xspi::D11Pin)),
+        (("xspim", "P2_IO12"), quote!(crate::xspi::D12Pin)),
+        (("xspim", "P2_IO13"), quote!(crate::xspi::D13Pin)),
+        (("xspim", "P2_IO14"), quote!(crate::xspi::D14Pin)),
+        (("xspim", "P2_IO15"), quote!(crate::xspi::D15Pin)),
+        (("xspim", "P2_DQS0"), quote!(crate::xspi::DQS0Pin)),
+        (("xspim", "P2_DQS1"), quote!(crate::xspi::DQS1Pin)),
+        (("xspim", "P2_NCS1"), quote!(crate::xspi::NCSPin)),
+        (("xspim", "P2_NCS2"), quote!(crate::xspi::NCSPin)),
+        (("xspim", "P2_CLK"), quote!(crate::xspi::CLKPin)),
+        (("xspim", "P2_NCLK"), quote!(crate::xspi::NCLKPin)),
+        (("hspi", "IO0"), quote!(crate::hspi::D0Pin)),
+        (("hspi", "IO1"), quote!(crate::hspi::D1Pin)),
+        (("hspi", "IO2"), quote!(crate::hspi::D2Pin)),
+        (("hspi", "IO3"), quote!(crate::hspi::D3Pin)),
+        (("hspi", "IO4"), quote!(crate::hspi::D4Pin)),
+        (("hspi", "IO5"), quote!(crate::hspi::D5Pin)),
+        (("hspi", "IO6"), quote!(crate::hspi::D6Pin)),
+        (("hspi", "IO7"), quote!(crate::hspi::D7Pin)),
+        (("hspi", "IO8"), quote!(crate::hspi::D8Pin)),
+        (("hspi", "IO9"), quote!(crate::hspi::D9Pin)),
+        (("hspi", "IO10"), quote!(crate::hspi::D10Pin)),
+        (("hspi", "IO11"), quote!(crate::hspi::D11Pin)),
+        (("hspi", "IO12"), quote!(crate::hspi::D12Pin)),
+        (("hspi", "IO13"), quote!(crate::hspi::D13Pin)),
+        (("hspi", "IO14"), quote!(crate::hspi::D14Pin)),
+        (("hspi", "IO15"), quote!(crate::hspi::D15Pin)),
+        (("hspi", "DQS0"), quote!(crate::hspi::DQS0Pin)),
+        (("hspi", "DQS1"), quote!(crate::hspi::DQS1Pin)),
+        (("hspi", "NCS"), quote!(crate::hspi::NSSPin)),
+        (("hspi", "CLK"), quote!(crate::hspi::SckPin)),
+        (("hspi", "NCLK"), quote!(crate::hspi::NckPin)),
        (("tsc", "G1_IO1"), quote!(crate::tsc::G1IO1Pin)),
        (("tsc", "G1_IO2"), quote!(crate::tsc::G1IO2Pin)),
        (("tsc", "G1_IO3"), quote!(crate::tsc::G1IO3Pin)),
@@ -1081,6 +1297,8 @@ fn main() {
        (("tsc", "G8_IO2"), quote!(crate::tsc::G8IO2Pin)),
        (("tsc", "G8_IO3"), quote!(crate::tsc::G8IO3Pin)),
        (("tsc", "G8_IO4"), quote!(crate::tsc::G8IO4Pin)),
+        (("dac", "OUT1"), quote!(crate::dac::DacPin<Ch1>)),
+        (("dac", "OUT2"), quote!(crate::dac::DacPin<Ch2>)),
    ].into();
    for p in METADATA.peripherals {
@@ -1106,6 +1324,41 @@ fn main() {
                        peri = format_ident!("{}", pin.signal.replace('_', ""));
                    }
+                    // OCTOSPIM is special
+                    if p.name == "OCTOSPIM" {
+                        // Some chips have OCTOSPIM but not OCTOSPI2.
+                        if METADATA.peripherals.iter().any(|p| p.name == "OCTOSPI2") {
+                            peri = format_ident!("{}", "OCTOSPI2");
+                            g.extend(quote! {
+                                pin_trait_impl!(#tr, #peri, #pin_name, #af);
+                            });
+                        }
+                        peri = format_ident!("{}", "OCTOSPI1");
+                    }
+                    // XSPIM  is special
+                    if p.name == "XSPIM" {
+                        if pin.signal.starts_with("P1") {
+                            peri = format_ident!("{}", "XSPI1");
+                        } else if pin.signal.starts_with("P2") {
+                            peri = format_ident!("{}", "XSPI2");
+                        } else {
+                            panic! {"malformed XSPIM pin: {:?}", pin}
+                        }
+                    }
+                    // XSPI NCS pin to CSSEL mapping
+                    if pin.signal.ends_with("NCS1") {
+                        g.extend(quote! {
+                            sel_trait_impl!(crate::xspi::NCSEither, #peri, #pin_name, 0);
+                        })
+                    }
+                    if pin.signal.ends_with("NCS2") {
+                        g.extend(quote! {
+                            sel_trait_impl!(crate::xspi::NCSEither, #peri, #pin_name, 1);
+                        })
+                    }
                    g.extend(quote! {
                        pin_trait_impl!(#tr, #peri, #pin_name, #af);
                    })
@@ -1158,6 +1411,18 @@ fn main() {
                        g.extend(quote! {
                            impl_opamp_vp_pin!( #peri, #pin_name, #ch);
                        })
+                    } else if pin.signal.starts_with("VINM") {
+                        // Impl NonInvertingPin for the VINM* signals ( VINM0, VINM1, etc)
+                        // STM32G4
+                        let peri = format_ident!("{}", p.name);
+                        let pin_name = format_ident!("{}", pin.pin);
+                        let ch: Result<u8, _> = pin.signal.strip_prefix("VINM").unwrap().parse();
+                        if let Ok(ch) = ch {
+                            g.extend(quote! {
+                                impl_opamp_vn_pin!( #peri, #pin_name, #ch);
+                            })
+                        }
                    } else if pin.signal == "VOUT" {
                        // Impl OutputPin for the VOUT pin
                        let peri = format_ident!("{}", p.name);
@@ -1168,14 +1433,14 @@ fn main() {
                    }
                }
-                // DAC is special
+                if regs.kind == "spdifrx" {
-                if regs.kind == "dac" {
                    let peri = format_ident!("{}", p.name);
                    let pin_name = format_ident!("{}", pin.pin);
-                    let ch: u8 = pin.signal.strip_prefix("OUT").unwrap().parse().unwrap();
+                    let af = pin.af.unwrap_or(0);
+                    let sel: u8 = pin.signal.strip_prefix("IN").unwrap().parse().unwrap();
                    g.extend(quote! {
-                    impl_dac_pin!( #peri, #pin_name, #ch);
+                    impl_spdifrx_pin!( #peri, #pin_name, #af, #sel);
                    })
                }
            }
@@ -1185,13 +1450,12 @@ fn main() {
    // ========
    // Generate dma_trait_impl!
-    let signals: HashMap<_, _> = [
+    let mut signals: HashMap<_, _> = [
        // (kind, signal) => trait
        (("adc", "ADC"), quote!(crate::adc::RxDma)),
        (("adc", "ADC1"), quote!(crate::adc::RxDma)),
        (("adc", "ADC2"), quote!(crate::adc::RxDma)),
        (("adc", "ADC3"), quote!(crate::adc::RxDma)),
-        (("adc", "ADC4"), quote!(crate::adc::RxDma)),
        (("ucpd", "RX"), quote!(crate::ucpd::RxDma)),
        (("ucpd", "TX"), quote!(crate::ucpd::TxDma)),
        (("usart", "RX"), quote!(crate::usart::RxDma)),
@@ -1202,6 +1466,7 @@ fn main() {
        (("sai", "B"), quote!(crate::sai::Dma<B>)),
        (("spi", "RX"), quote!(crate::spi::RxDma)),
        (("spi", "TX"), quote!(crate::spi::TxDma)),
+        (("spdifrx", "RX"), quote!(crate::spdifrx::Dma)),
        (("i2c", "RX"), quote!(crate::i2c::RxDma)),
        (("i2c", "TX"), quote!(crate::i2c::TxDma)),
        (("dcmi", "DCMI"), quote!(crate::dcmi::FrameDma)),
@@ -1210,8 +1475,9 @@ fn main() {
        (("sdmmc", "RX"), quote!(crate::sdmmc::SdmmcDma)),
        (("quadspi", "QUADSPI"), quote!(crate::qspi::QuadDma)),
        (("octospi", "OCTOSPI1"), quote!(crate::ospi::OctoDma)),
-        (("dac", "CH1"), quote!(crate::dac::DacDma1)),
+        (("hspi", "HSPI1"), quote!(crate::hspi::HspiDma)),
-        (("dac", "CH2"), quote!(crate::dac::DacDma2)),
+        (("dac", "CH1"), quote!(crate::dac::Dma<Ch1>)),
+        (("dac", "CH2"), quote!(crate::dac::Dma<Ch2>)),
        (("timer", "UP"), quote!(crate::timer::UpDma)),
        (("hash", "IN"), quote!(crate::hash::Dma)),
        (("cryp", "IN"), quote!(crate::cryp::DmaIn)),
@@ -1225,6 +1491,19 @@ fn main() {
    ]
    .into();
+    if chip_name.starts_with("stm32u5") {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma4));
+    } else {
+        signals.insert(("adc", "ADC4"), quote!(crate::adc::RxDma));
+    }
+    if chip_name.starts_with("stm32g4") {
+        let line_number = chip_name.chars().skip(8).next().unwrap();
+        if line_number == '3' || line_number == '4' {
+            signals.insert(("adc", "ADC5"), quote!(crate::adc::RxDma));
+        }
+    }
    for p in METADATA.peripherals {
        if let Some(regs) = &p.registers {
            // FIXME: stm32u5a crash on Cordic driver
@@ -1290,36 +1569,13 @@ fn main() {
    for e in rcc_registers.ir.enums {
        fn is_rcc_name(e: &str) -> bool {
            match e {
-                "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" => true,
+                "Pllp" | "Pllq" | "Pllr" | "Pllm" | "Plln" | "Prediv1" | "Prediv2" => true,
                "Timpre" | "Pllrclkpre" => false,
                e if e.ends_with("pre") || e.ends_with("pres") || e.ends_with("div") || e.ends_with("mul") => true,
                _ => false,
            }
        }
-        #[derive(Copy, Clone, Debug)]
-        struct Frac {
-            num: u32,
-            denom: u32,
-        }
-        impl Frac {
-            fn simplify(self) -> Self {
-                let d = gcd(self.num, self.denom);
-                Self {
-                    num: self.num / d,
-                    denom: self.denom / d,
-                }
-            }
-        }
-        fn gcd(a: u32, b: u32) -> u32 {
-            if b == 0 {
-                return a;
-            }
-            gcd(b, a % b)
-        }
        fn parse_num(n: &str) -> Result<Frac, ()> {
            for prefix in ["DIV", "MUL"] {
                if let Some(n) = n.strip_prefix(prefix) {
@@ -1402,8 +1658,7 @@ fn main() {
    let mut pins_table: Vec<Vec<String>> = Vec::new();
    let mut adc_table: Vec<Vec<String>> = Vec::new();
-    for m in METADATA
+    for m in memory
-        .memory
        .iter()
        .filter(|m| m.kind == MemoryRegionKind::Flash && m.settings.is_some())
    {
@@ -1419,43 +1674,42 @@ fn main() {
    let gpio_base = METADATA.peripherals.iter().find(|p| p.name == "GPIOA").unwrap().address as u32;
    let gpio_stride = 0x400;
-    for p in METADATA.peripherals {
+    for pin in METADATA.pins {
-        if let Some(regs) = &p.registers {
+        let port_letter = pin.name.chars().nth(1).unwrap();
-            if regs.kind == "gpio" {
+        let pname = format!("GPIO{}", port_letter);
-                let port_letter = p.name.chars().nth(4).unwrap();
+        let p = METADATA.peripherals.iter().find(|p| p.name == pname).unwrap();
-                assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
+        assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
-                let port_num = (p.address as u32 - gpio_base) / gpio_stride;
+        let port_num = (p.address as u32 - gpio_base) / gpio_stride;
+        let pin_num: u32 = pin.name[2..].parse().unwrap();
-                for pin_num in 0u32..16 {
-                    let pin_name = format!("P{}{}", port_letter, pin_num);
+        pins_table.push(vec![
+            pin.name.to_string(),
-                    pins_table.push(vec![
+            p.name.to_string(),
-                        pin_name.clone(),
+            port_num.to_string(),
-                        p.name.to_string(),
+            pin_num.to_string(),
-                        port_num.to_string(),
+            format!("EXTI{}", pin_num),
-                        pin_num.to_string(),
+        ]);
-                        format!("EXTI{}", pin_num),
-                    ]);
+        // If we have the split pins, we need to do a little extra work:
+        // Add the "_C" variant to the table. The solution is not optimal, though.
-                    // If we have the split pins, we need to do a little extra work:
+        // Adding them only when the corresponding GPIOx also appears.
-                    // Add the "_C" variant to the table. The solution is not optimal, though.
+        // This should avoid unintended side-effects as much as possible.
-                    // Adding them only when the corresponding GPIOx also appears.
+        #[cfg(feature = "_split-pins-enabled")]
-                    // This should avoid unintended side-effects as much as possible.
+        for split_feature in &split_features {
-                    #[cfg(feature = "_split-pins-enabled")]
+            if split_feature.pin_name_without_c == pin.name {
-                    for split_feature in &split_features {
+                pins_table.push(vec![
-                        if split_feature.pin_name_without_c == pin_name {
+                    split_feature.pin_name_with_c.to_string(),
-                            pins_table.push(vec![
+                    p.name.to_string(),
-                                split_feature.pin_name_with_c.to_string(),
+                    port_num.to_string(),
-                                p.name.to_string(),
+                    pin_num.to_string(),
-                                port_num.to_string(),
+                    format!("EXTI{}", pin_num),
-                                pin_num.to_string(),
+                ]);
-                                format!("EXTI{}", pin_num),
-                            ]);
-                        }
-                    }
-                }
            }
+        }
+    }
+    for p in METADATA.peripherals {
+        if let Some(regs) = &p.registers {
            if regs.kind == "adc" {
                let adc_num = p.name.strip_prefix("ADC").unwrap();
                let mut adc_common = None;
@@ -1494,6 +1748,36 @@ fn main() {
        .flat_map(|p| &p.registers)
        .any(|p| p.kind == "dmamux");
+    let mut dma_irqs: BTreeMap<&str, Vec<String>> = BTreeMap::new();
+    for p in METADATA.peripherals {
+        if let Some(r) = &p.registers {
+            if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" || r.kind == "lpdma" {
+                for irq in p.interrupts {
+                    let ch_name = format!("{}_{}", p.name, irq.signal);
+                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name).unwrap();
+                    // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
+                    if has_dmamux && ch.dmamux.is_none() {
+                        continue;
+                    }
+                    dma_irqs.entry(irq.interrupt).or_default().push(ch_name);
+                }
+            }
+        }
+    }
+    #[cfg(feature = "_dual-core")]
+    let mut dma_ch_to_irq: BTreeMap<&str, Vec<String>> = BTreeMap::new();
+    #[cfg(feature = "_dual-core")]
+    for (irq, channels) in &dma_irqs {
+        for channel in channels {
+            dma_ch_to_irq.entry(channel).or_default().push(irq.to_string());
+        }
+    }
    for (ch_idx, ch) in METADATA.dma_channels.iter().enumerate() {
        // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
        if has_dmamux && ch.dmamux.is_none() {
@@ -1502,6 +1786,16 @@ fn main() {
        let name = format_ident!("{}", ch.name);
        let idx = ch_idx as u8;
+        #[cfg(feature = "_dual-core")]
+        let irq = {
+            let irq_name = if let Some(x) = &dma_ch_to_irq.get(ch.name) {
+                format_ident!("{}", x.get(0).unwrap())
+            } else {
+                panic!("failed to find dma interrupt")
+            };
+            quote!(crate::pac::Interrupt::#irq_name)
+        };
        g.extend(quote!(dma_channel_impl!(#name, #idx);));
        let dma = format_ident!("{}", ch.dma);
@@ -1532,10 +1826,20 @@ fn main() {
            None => quote!(),
        };
+        #[cfg(not(feature = "_dual-core"))]
+        dmas.extend(quote! {
+            crate::dma::ChannelInfo {
+                dma: #dma_info,
+                num: #ch_num,
+                #dmamux
+            },
+        });
+        #[cfg(feature = "_dual-core")]
        dmas.extend(quote! {
            crate::dma::ChannelInfo {
                dma: #dma_info,
                num: #ch_num,
+                irq: #irq,
                #dmamux
            },
        });
@@ -1544,26 +1848,6 @@ fn main() {
    // ========
    // Generate DMA IRQs.
-    let mut dma_irqs: BTreeMap<&str, Vec<String>> = BTreeMap::new();
-    for p in METADATA.peripherals {
-        if let Some(r) = &p.registers {
-            if r.kind == "dma" || r.kind == "bdma" || r.kind == "gpdma" {
-                for irq in p.interrupts {
-                    let ch_name = format!("{}_{}", p.name, irq.signal);
-                    let ch = METADATA.dma_channels.iter().find(|c| c.name == ch_name).unwrap();
-                    // Some H7 chips have BDMA1 hardcoded for DFSDM, ie no DMAMUX. It's unsupported, skip it.
-                    if has_dmamux && ch.dmamux.is_none() {
-                        continue;
-                    }
-                    dma_irqs.entry(irq.interrupt).or_default().push(ch_name);
-                }
-            }
-        }
-    }
    let dma_irqs: TokenStream = dma_irqs
        .iter()
        .map(|(irq, channels)| {
@@ -1589,6 +1873,100 @@ fn main() {
        pub(crate) const DMA_CHANNELS: &[crate::dma::ChannelInfo] = &[#dmas];
    });
+    // ========
+    // Generate gpio_block() function
+    let gpio_base = METADATA.peripherals.iter().find(|p| p.name == "GPIOA").unwrap().address as usize;
+    let gpio_stride = 0x400 as usize;
+    for p in METADATA.peripherals {
+        if let Some(bi) = &p.registers {
+            if bi.kind == "gpio" {
+                assert_eq!(0, (p.address as usize - gpio_base) % gpio_stride);
+            }
+        }
+    }
+    g.extend(quote!(
+        pub fn gpio_block(n: usize) -> crate::pac::gpio::Gpio {{
+            unsafe {{ crate::pac::gpio::Gpio::from_ptr((#gpio_base + #gpio_stride*n) as _) }}
+        }}
+    ));
+    // ========
+    // Generate flash constants
+    let flash_regions: Vec<&MemoryRegion> = memory
+        .iter()
+        .filter(|x| x.kind == MemoryRegionKind::Flash && x.name.starts_with("BANK_"))
+        .collect();
+    let first_flash = flash_regions.first().unwrap();
+    let total_flash_size = flash_regions
+        .iter()
+        .map(|x| x.size)
+        .reduce(|acc, item| acc + item)
+        .unwrap();
+    let write_sizes: HashSet<_> = flash_regions
+        .iter()
+        .map(|r| r.settings.as_ref().unwrap().write_size)
+        .collect();
+    assert_eq!(1, write_sizes.len());
+    let flash_base = first_flash.address as usize;
+    let total_flash_size = total_flash_size as usize;
+    let write_size = (*write_sizes.iter().next().unwrap()) as usize;
+    g.extend(quote!(
+        pub const FLASH_BASE: usize = #flash_base;
+        pub const FLASH_SIZE: usize = #total_flash_size;
+        pub const WRITE_SIZE: usize = #write_size;
+    ));
+    // ========
+    // Generate EEPROM constants
+    cfgs.declare("eeprom");
+    let eeprom_memory_regions: Vec<&MemoryRegion> =
+        memory.iter().filter(|x| x.kind == MemoryRegionKind::Eeprom).collect();
+    if !eeprom_memory_regions.is_empty() {
+        cfgs.enable("eeprom");
+        let mut sorted_eeprom_regions = eeprom_memory_regions.clone();
+        sorted_eeprom_regions.sort_by_key(|r| r.address);
+        let first_eeprom_address = sorted_eeprom_regions[0].address;
+        let mut total_eeprom_size = 0;
+        let mut current_expected_address = first_eeprom_address;
+        for region in sorted_eeprom_regions.iter() {
+            if region.address != current_expected_address {
+                // For STM32L0 and STM32L1, EEPROM regions (if multiple) are expected to be contiguous.
+                // If they are not, this indicates an issue with the chip metadata or an unsupported configuration.
+                panic!(
+                    "EEPROM regions for chip {} are not contiguous, which is unexpected for L0/L1 series. \
+                    First region: '{}' at {:#X}. Found next non-contiguous region: '{}' at {:#X}. \
+                    Please verify chip metadata. Embassy currently assumes contiguous EEPROM for these series.",
+                    chip_name, sorted_eeprom_regions[0].name, first_eeprom_address, region.name, region.address
+                );
+            }
+            total_eeprom_size += region.size;
+            current_expected_address += region.size;
+        }
+        let eeprom_base_usize = first_eeprom_address as usize;
+        let total_eeprom_size_usize = total_eeprom_size as usize;
+        g.extend(quote! {
+            pub const EEPROM_BASE: usize = #eeprom_base_usize;
+            pub const EEPROM_SIZE: usize = #total_eeprom_size_usize;
+        });
+    }
+    // ========
+    // Generate macro-tables
    for irq in METADATA.interrupts {
        let name = irq.name.to_ascii_uppercase();
        interrupts_table.push(vec![name.clone()]);
@@ -1683,6 +2061,11 @@ fn main() {
    }
    println!("cargo:rerun-if-changed=build.rs");
+    if cfg!(feature = "memory-x") {
+        gen_memory_x(memory, out_dir);
+        println!("cargo:rustc-link-search={}", out_dir.display());
+    }
 }
 enum GetOneError {
@@ -1768,3 +2151,97 @@ fn rustfmt(path: impl AsRef<Path>) {
        }
    }
 }
+fn gen_memory_x(memory: &[MemoryRegion], out_dir: &Path) {
+    let mut memory_x = String::new();
+    let flash = get_memory_range(memory, MemoryRegionKind::Flash);
+    let ram = get_memory_range(memory, MemoryRegionKind::Ram);
+    write!(memory_x, "MEMORY\n{{\n").unwrap();
+    writeln!(
+        memory_x,
+        "    FLASH : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */",
+        flash.0,
+        flash.1 / 1024,
+        flash.2
+    )
+    .unwrap();
+    writeln!(
+        memory_x,
+        "    RAM   : ORIGIN = 0x{:08x}, LENGTH = {:>4}K /* {} */",
+        ram.0,
+        ram.1 / 1024,
+        ram.2
+    )
+    .unwrap();
+    write!(memory_x, "}}").unwrap();
+    std::fs::write(out_dir.join("memory.x"), memory_x.as_bytes()).unwrap();
+}
+fn get_memory_range(memory: &[MemoryRegion], kind: MemoryRegionKind) -> (u32, u32, String) {
+    let mut mems: Vec<_> = memory.iter().filter(|m| m.kind == kind && m.size != 0).collect();
+    mems.sort_by_key(|m| m.address);
+    let mut start = u32::MAX;
+    let mut end = u32::MAX;
+    let mut names = Vec::new();
+    let mut best: Option<(u32, u32, String)> = None;
+    for m in mems {
+        if !mem_filter(&METADATA.name, &m.name) {
+            continue;
+        }
+        if m.address != end {
+            names = Vec::new();
+            start = m.address;
+            end = m.address;
+        }
+        end += m.size;
+        names.push(m.name.to_string());
+        if best.is_none() || end - start > best.as_ref().unwrap().1 {
+            best = Some((start, end - start, names.join(" + ")));
+        }
+    }
+    best.unwrap()
+}
+fn mem_filter(chip: &str, region: &str) -> bool {
+    // in STM32WB, SRAM2a/SRAM2b are reserved for the radio core.
+    if chip.starts_with("STM32WB")
+        && !chip.starts_with("STM32WBA")
+        && !chip.starts_with("STM32WB0")
+        && region.starts_with("SRAM2")
+    {
+        return false;
+    }
+    true
+}
+#[derive(Copy, Clone, Debug)]
+struct Frac {
+    num: u32,
+    denom: u32,
+}
+impl Frac {
+    fn simplify(self) -> Self {
+        let d = gcd(self.num, self.denom);
+        Self {
+            num: self.num / d,
+            denom: self.denom / d,
+        }
+    }
+}
+fn gcd(a: u32, b: u32) -> u32 {
+    if b == 0 {
+        return a;
+    }
+    gcd(b, a % b)
+}
diff --git a/embassy-stm32/src/adc/c0.rs b/embassy-stm32/src/adc/c0.rs
new file mode 100644
index 000000000..936ad7413
--- /dev/null
+++ b/embassy-stm32/src/adc/c0.rs
@@ -0,0 +1,467 @@
+use pac::adc::vals::Scandir;
+#[allow(unused)]
+use pac::adc::vals::{Adstp, Align, Ckmode, Dmacfg, Exten, Ovrmod, Ovsr};
+use pac::adccommon::vals::Presc;
+use super::{
+    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
+};
+use crate::dma::Transfer;
+use crate::time::Hertz;
+use crate::{pac, rcc, Peri};
+/// Default VREF voltage used for sample conversion to millivolts.
+pub const VREF_DEFAULT_MV: u32 = 3300;
+/// VREF voltage used for factory calibration of VREFINTCAL register.
+pub const VREF_CALIB_MV: u32 = 3300;
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(25);
+const TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US: u32 = 20;
+const TEMP_CHANNEL: u8 = 9;
+const VREF_CHANNEL: u8 = 10;
+const NUM_HW_CHANNELS: u8 = 22;
+const CHSELR_SQ_SIZE: usize = 8;
+const CHSELR_SQ_MAX_CHANNEL: u8 = 14;
+const CHSELR_SQ_SEQUENCE_END_MARKER: u8 = 0b1111;
+// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs,
+// this currently cannot be modeled with stm32-data,
+// so these are available from the software on all ADCs.
+/// Internal voltage reference channel.
+pub struct VrefInt;
+impl<T: Instance> AdcChannel<T> for VrefInt {}
+impl<T: Instance> SealedAdcChannel<T> for VrefInt {
+    fn channel(&self) -> u8 {
+        VREF_CHANNEL
+    }
+}
+/// Internal temperature channel.
+pub struct Temperature;
+impl<T: Instance> AdcChannel<T> for Temperature {}
+impl<T: Instance> SealedAdcChannel<T> for Temperature {
+    fn channel(&self) -> u8 {
+        TEMP_CHANNEL
+    }
+}
+#[derive(Debug)]
+pub enum Prescaler {
+    NotDivided,
+    DividedBy2,
+    DividedBy4,
+    DividedBy6,
+    DividedBy8,
+    DividedBy10,
+    DividedBy12,
+    DividedBy16,
+    DividedBy32,
+    DividedBy64,
+    DividedBy128,
+    DividedBy256,
+}
+impl Prescaler {
+    fn from_ker_ck(frequency: Hertz) -> Self {
+        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        match raw_prescaler {
+            0 => Self::NotDivided,
+            1 => Self::DividedBy2,
+            2..=3 => Self::DividedBy4,
+            4..=5 => Self::DividedBy6,
+            6..=7 => Self::DividedBy8,
+            8..=9 => Self::DividedBy10,
+            10..=11 => Self::DividedBy12,
+            _ => unimplemented!(),
+        }
+    }
+    #[allow(unused)]
+    fn divisor(&self) -> u32 {
+        match self {
+            Prescaler::NotDivided => 1,
+            Prescaler::DividedBy2 => 2,
+            Prescaler::DividedBy4 => 4,
+            Prescaler::DividedBy6 => 6,
+            Prescaler::DividedBy8 => 8,
+            Prescaler::DividedBy10 => 10,
+            Prescaler::DividedBy12 => 12,
+            Prescaler::DividedBy16 => 16,
+            Prescaler::DividedBy32 => 32,
+            Prescaler::DividedBy64 => 64,
+            Prescaler::DividedBy128 => 128,
+            Prescaler::DividedBy256 => 256,
+        }
+    }
+    fn presc(&self) -> Presc {
+        match self {
+            Prescaler::NotDivided => Presc::DIV1,
+            Prescaler::DividedBy2 => Presc::DIV2,
+            Prescaler::DividedBy4 => Presc::DIV4,
+            Prescaler::DividedBy6 => Presc::DIV6,
+            Prescaler::DividedBy8 => Presc::DIV8,
+            Prescaler::DividedBy10 => Presc::DIV10,
+            Prescaler::DividedBy12 => Presc::DIV12,
+            Prescaler::DividedBy16 => Presc::DIV16,
+            Prescaler::DividedBy32 => Presc::DIV32,
+            Prescaler::DividedBy64 => Presc::DIV64,
+            Prescaler::DividedBy128 => Presc::DIV128,
+            Prescaler::DividedBy256 => Presc::DIV256,
+        }
+    }
+}
+#[cfg(feature = "defmt")]
+impl<'a> defmt::Format for Prescaler {
+    fn format(&self, fmt: defmt::Formatter) {
+        match self {
+            Prescaler::NotDivided => defmt::write!(fmt, "Prescaler::NotDivided"),
+            Prescaler::DividedBy2 => defmt::write!(fmt, "Prescaler::DividedBy2"),
+            Prescaler::DividedBy4 => defmt::write!(fmt, "Prescaler::DividedBy4"),
+            Prescaler::DividedBy6 => defmt::write!(fmt, "Prescaler::DividedBy6"),
+            Prescaler::DividedBy8 => defmt::write!(fmt, "Prescaler::DividedBy8"),
+            Prescaler::DividedBy10 => defmt::write!(fmt, "Prescaler::DividedBy10"),
+            Prescaler::DividedBy12 => defmt::write!(fmt, "Prescaler::DividedBy12"),
+            Prescaler::DividedBy16 => defmt::write!(fmt, "Prescaler::DividedBy16"),
+            Prescaler::DividedBy32 => defmt::write!(fmt, "Prescaler::DividedBy32"),
+            Prescaler::DividedBy64 => defmt::write!(fmt, "Prescaler::DividedBy64"),
+            Prescaler::DividedBy128 => defmt::write!(fmt, "Prescaler::DividedBy128"),
+            Prescaler::DividedBy256 => defmt::write!(fmt, "Prescaler::DividedBy256"),
+        }
+    }
+}
+/// Number of samples used for averaging.
+/// TODO: Implement hardware averaging setting.
+#[allow(unused)]
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+    Samples512,
+    Samples1024,
+}
+impl<'d, T: Instance> Adc<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: Peri<'d, T>, sample_time: SampleTime, resolution: Resolution) -> Self {
+        rcc::enable_and_reset::<T>();
+        T::regs().cfgr2().modify(|w| w.set_ckmode(Ckmode::SYSCLK));
+        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        debug!("ADC frequency set to {}", frequency);
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+        }
+        let mut s = Self {
+            adc,
+            sample_time: SampleTime::from_bits(0),
+        };
+        s.power_up();
+        s.set_resolution(resolution);
+        s.calibrate();
+        s.enable();
+        s.configure_default();
+        s.set_sample_time_all_channels(sample_time);
+        s
+    }
+    fn power_up(&mut self) {
+        T::regs().cr().modify(|reg| {
+            reg.set_advregen(true);
+        });
+        // "The software must wait for the ADC voltage regulator startup time."
+        // See datasheet for the value.
+        blocking_delay_us(TIME_ADC_VOLTAGE_REGUALTOR_STARTUP_US + 1);
+    }
+    fn calibrate(&mut self) {
+        // We have to make sure AUTOFF is OFF, but keep its value after calibration.
+        let autoff_value = T::regs().cfgr1().read().autoff();
+        T::regs().cfgr1().modify(|w| w.set_autoff(false));
+        T::regs().cr().modify(|w| w.set_adcal(true));
+        // "ADCAL bit stays at 1 during all the calibration sequence."
+        // "It is then cleared by hardware as soon the calibration completes."
+        while T::regs().cr().read().adcal() {}
+        debug!("ADC calibration value: {}.", T::regs().dr().read().data());
+        T::regs().cfgr1().modify(|w| w.set_autoff(autoff_value));
+    }
+    fn enable(&mut self) {
+        T::regs().isr().modify(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        // ADRDY is "ADC ready". Wait until it will be True.
+        while !T::regs().isr().read().adrdy() {}
+    }
+    fn configure_default(&mut self) {
+        // single conversion mode, software trigger
+        T::regs().cfgr1().modify(|w| {
+            w.set_cont(false);
+            w.set_exten(Exten::DISABLED);
+            w.set_align(Align::RIGHT);
+        });
+    }
+    /// Enable reading the voltage reference internal channel.
+    pub fn enable_vrefint(&self) -> VrefInt {
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_vrefen(true);
+        });
+        VrefInt {}
+    }
+    /// Enable reading the temperature internal channel.
+    pub fn enable_temperature(&self) -> Temperature {
+        debug!("Ensure that sample time is set to more than temperature sensor T_start from the datasheet!");
+        T::common_regs().ccr().modify(|reg| {
+            reg.set_tsen(true);
+        });
+        Temperature {}
+    }
+    /// Set the ADC sample time.
+    /// Shall only be called when ADC is not converting.
+    pub fn set_sample_time_all_channels(&mut self, sample_time: SampleTime) {
+        self.sample_time = sample_time;
+        // Set all channels to use SMP1 field as source.
+        T::regs().smpr().modify(|w| {
+            w.smpsel(0);
+            w.set_smp1(sample_time);
+        });
+    }
+    /// Set the ADC resolution.
+    pub fn set_resolution(&mut self, resolution: Resolution) {
+        T::regs().cfgr1().modify(|reg| reg.set_res(resolution));
+    }
+    /// Perform a single conversion.
+    fn convert(&mut self) -> u16 {
+        // Set single conversion mode.
+        T::regs().cfgr1().modify(|w| w.set_cont(false));
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+        // Waiting for End Of Conversion (EOC).
+        while !T::regs().isr().read().eoc() {}
+        T::regs().dr().read().data() as u16
+    }
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        Self::configure_channel(channel);
+        T::regs().cfgr1().write(|reg| {
+            reg.set_chselrmod(false);
+            reg.set_align(Align::RIGHT);
+        });
+        self.convert()
+    }
+    fn setup_channel_sequencer<'a>(channel_sequence: impl ExactSizeIterator<Item = &'a mut AnyAdcChannel<T>>) {
+        assert!(
+            channel_sequence.len() <= CHSELR_SQ_SIZE,
+            "Seqenced read set cannot be more than {} in size.",
+            CHSELR_SQ_SIZE
+        );
+        let mut last_sq_set: usize = 0;
+        T::regs().chselr_sq().write(|w| {
+            for (i, channel) in channel_sequence.enumerate() {
+                assert!(
+                    channel.channel() <= CHSELR_SQ_MAX_CHANNEL,
+                    "Sequencer only support HW channels smaller than {}.",
+                    CHSELR_SQ_MAX_CHANNEL
+                );
+                w.set_sq(i, channel.channel());
+                last_sq_set = i;
+            }
+            for i in (last_sq_set + 1)..CHSELR_SQ_SIZE {
+                w.set_sq(i, CHSELR_SQ_SEQUENCE_END_MARKER);
+            }
+        });
+        Self::apply_channel_conf()
+    }
+    async fn dma_convert(&mut self, rx_dma: Peri<'_, impl RxDma<T>>, readings: &mut [u16]) {
+        // Enable overrun control, so no new DMA requests will be generated until
+        // previous DR values is read.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+        // Set continuous mode with oneshot dma.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::DMA_ONE_SHOT);
+            reg.set_dmaen(true);
+            reg.set_ovrmod(Ovrmod::PRESERVE);
+        });
+        let request = rx_dma.request();
+        let transfer = unsafe {
+            Transfer::new_read(
+                rx_dma,
+                request,
+                T::regs().dr().as_ptr() as *mut u16,
+                readings,
+                Default::default(),
+            )
+        };
+        // Start conversion.
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+        // Wait for conversion sequence to finish.
+        transfer.await;
+        // Ensure conversions are finished.
+        Self::cancel_conversions();
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_cont(false);
+            reg.set_dmacfg(Dmacfg::from_bits(0));
+            reg.set_dmaen(false);
+        });
+    }
+    /// Read one or multiple ADC channels using DMA in hardware order.
+    /// Readings will be ordered based on **hardware** ADC channel number and `scandir` setting.
+    /// Readings won't be in the same order as in the `set`!
+    ///
+    /// In STM32C0, channels bigger than 14 cannot be read using sequencer, so you have to use
+    /// either blocking reads or use the mechanism to read in HW order (CHSELRMOD=0).
+    /// TODO(chudsaviet): externalize generic code and merge with read().
+    pub async fn read_in_hw_order(
+        &mut self,
+        rx_dma: Peri<'_, impl RxDma<T>>,
+        hw_channel_selection: u32,
+        scandir: Scandir,
+        readings: &mut [u16],
+    ) {
+        assert!(
+            hw_channel_selection != 0,
+            "Some bits in `hw_channel_selection` shall be set."
+        );
+        assert!(
+            (hw_channel_selection >> NUM_HW_CHANNELS) == 0,
+            "STM32C0 only have {} ADC channels. `hw_channel_selection` cannot have bits higher than this number set.",
+            NUM_HW_CHANNELS
+        );
+        // To check for correct readings slice size, we shall solve Hamming weight problem,
+        // which is either slow or memory consuming.
+        // Since we have limited resources, we don't do it here.
+        // Not doing this have a great potential for a bug through.
+        // Ensure no conversions are ongoing.
+        Self::cancel_conversions();
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_chselrmod(false);
+            reg.set_scandir(scandir);
+            reg.set_align(Align::RIGHT);
+        });
+        // Set required channels for multi-convert.
+        unsafe { (T::regs().chselr().as_ptr() as *mut u32).write_volatile(hw_channel_selection) }
+        Self::apply_channel_conf();
+        self.dma_convert(rx_dma, readings).await
+    }
+    // Read ADC channels in specified order using DMA (CHSELRMOD = 1).
+    // In STM32C0, only lower 14 ADC channels can be read this way.
+    // For other channels, use `read_in_hw_order()` or blocking read.
+    pub async fn read(
+        &mut self,
+        rx_dma: Peri<'_, impl RxDma<T>>,
+        channel_sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
+        readings: &mut [u16],
+    ) {
+        assert!(
+            channel_sequence.len() != 0,
+            "Asynchronous read channel sequence cannot be empty."
+        );
+        assert!(
+            channel_sequence.len() == readings.len(),
+            "Channel sequence length must be equal to readings length."
+        );
+        // Ensure no conversions are ongoing.
+        Self::cancel_conversions();
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_chselrmod(true);
+            reg.set_align(Align::RIGHT);
+        });
+        Self::setup_channel_sequencer(channel_sequence);
+        self.dma_convert(rx_dma, readings).await
+    }
+    fn configure_channel(channel: &mut impl AdcChannel<T>) {
+        channel.setup();
+        // write() because we want all other bits to be set to 0.
+        T::regs()
+            .chselr()
+            .write(|w| w.set_chsel(channel.channel().into(), true));
+        Self::apply_channel_conf();
+    }
+    fn apply_channel_conf() {
+        // Trigger and wait for the channel selection procedure to complete.
+        T::regs().isr().modify(|w| w.set_ccrdy(false));
+        while !T::regs().isr().read().ccrdy() {}
+    }
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+}
diff --git a/embassy-stm32/src/adc/f1.rs b/embassy-stm32/src/adc/f1.rs
index b37ec260f..3cdc9d8fb 100644
--- a/embassy-stm32/src/adc/f1.rs
+++ b/embassy-stm32/src/adc/f1.rs
@@ -2,12 +2,12 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::into_ref;
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
+use crate::interrupt::typelevel::Interrupt;
+use crate::interrupt::{self};
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{rcc, Peri};
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -22,12 +22,9 @@ pub struct InterruptHandler<T: Instance> {
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
    unsafe fn on_interrupt() {
        if T::regs().sr().read().eoc() {
-            T::regs().cr1().modify(|w| w.set_eocie(false));
+            T::regs().cr1().modify(|w| w.set_eocie(false)); // End of Convert interrupt disable
-        } else {
+            T::state().waker.wake();
-            return;
        }
-        T::state().waker.wake();
    }
 }
@@ -48,8 +45,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
 }
 impl<'d, T: Instance> Adc<'d, T> {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(adc: Peri<'d, T>) -> Self {
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        T::regs().cr2().modify(|reg| reg.set_adon(true));
@@ -72,6 +68,9 @@ impl<'d, T: Instance> Adc<'d, T> {
        // One cycle after calibration
        blocking_delay_us((1_000_000 * 1) / Self::freq().0 + 1);
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
        Self {
            adc,
            sample_time: SampleTime::from_bits(0),
diff --git a/embassy-stm32/src/adc/f3.rs b/embassy-stm32/src/adc/f3.rs
index ac88c9742..3aeb6f2c7 100644
--- a/embassy-stm32/src/adc/f3.rs
+++ b/embassy-stm32/src/adc/f3.rs
@@ -2,13 +2,11 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::into_ref;
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const ADC_MAX: u32 = (1 << 12) - 1;
@@ -42,7 +40,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for Vref {
 impl Vref {
    /// The value that vref would be if vdda was at 3300mv
    pub fn value(&self) -> u16 {
-        crate::pac::VREFINTCAL.data().read().value()
+        crate::pac::VREFINTCAL.data().read()
    }
 }
@@ -56,13 +54,11 @@ impl<T: Instance> super::SealedAdcChannel<T> for Temperature {
 impl<'d, T: Instance> Adc<'d, T> {
    pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
        use crate::pac::adc::vals;
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        // Enable the adc regulator
diff --git a/embassy-stm32/src/adc/f3_v1_1.rs b/embassy-stm32/src/adc/f3_v1_1.rs
index 689c2871d..944e971bb 100644
--- a/embassy-stm32/src/adc/f3_v1_1.rs
+++ b/embassy-stm32/src/adc/f3_v1_1.rs
@@ -3,14 +3,13 @@ use core::marker::PhantomData;
 use core::task::Poll;
 use embassy_futures::yield_now;
-use embassy_hal_internal::into_ref;
 use embassy_time::Instant;
 use super::Resolution;
 use crate::adc::{Adc, AdcChannel, Instance, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::time::Hertz;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 const ADC_FREQ: Hertz = crate::rcc::HSI_FREQ;
@@ -74,7 +73,7 @@ impl<T: Instance> super::SealedAdcChannel<T> for Vref<T> {
 impl<T: Instance> Vref<T> {
    /// The value that vref would be if vdda was at 3000mv
    pub fn calibrated_value(&self) -> u16 {
-        crate::pac::VREFINTCAL.data().read().value()
+        crate::pac::VREFINTCAL.data().read()
    }
    pub async fn calibrate(&mut self, adc: &mut Adc<'_, T>) -> Calibration {
@@ -138,11 +137,9 @@ impl<T: Instance> Drop for Temperature<T> {
 impl<'d, T: Instance> Adc<'d, T> {
    pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        //let r = T::regs();
diff --git a/embassy-stm32/src/adc/g4.rs b/embassy-stm32/src/adc/g4.rs
index c1e584f59..1fce3085a 100644
--- a/embassy-stm32/src/adc/g4.rs
+++ b/embassy-stm32/src/adc/g4.rs
@@ -1,10 +1,17 @@
 #[allow(unused)]
+#[cfg(stm32h7)]
 use pac::adc::vals::{Adcaldif, Difsel, Exten};
+#[allow(unused)]
+#[cfg(stm32g4)]
+use pac::adc::vals::{Adcaldif, Difsel, Exten, Rovsm, Trovs};
 use pac::adccommon::vals::Presc;
+use stm32_metapac::adc::vals::{Adstp, Dmacfg, Dmaen};
-use super::{blocking_delay_us, Adc, AdcChannel, Instance, Resolution, SampleTime};
+use super::{blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime};
+use crate::adc::SealedAdcChannel;
+use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -128,8 +135,7 @@ impl Prescaler {
 impl<'d, T: Instance> Adc<'d, T> {
    /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(adc: Peri<'d, T>) -> Self {
-        embassy_hal_internal::into_ref!(adc);
        rcc::enable_and_reset::<T>();
        let prescaler = Prescaler::from_ker_ck(T::frequency());
@@ -137,7 +143,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
-        info!("ADC frequency set to {} Hz", frequency.0);
+        trace!("ADC frequency set to {}", frequency);
        if frequency > MAX_ADC_CLK_FREQ {
            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
@@ -165,32 +171,58 @@ impl<'d, T: Instance> Adc<'d, T> {
            reg.set_advregen(true);
        });
-        blocking_delay_us(10);
+        blocking_delay_us(20);
    }
    fn configure_differential_inputs(&mut self) {
        T::regs().difsel().modify(|w| {
            for n in 0..18 {
-                w.set_difsel(n, Difsel::SINGLEENDED);
+                w.set_difsel(n, Difsel::SINGLE_ENDED);
            }
        });
    }
    fn calibrate(&mut self) {
        T::regs().cr().modify(|w| {
-            w.set_adcaldif(Adcaldif::SINGLEENDED);
+            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
        });
        T::regs().cr().modify(|w| w.set_adcal(true));
        while T::regs().cr().read().adcal() {}
+        blocking_delay_us(20);
+        T::regs().cr().modify(|w| {
+            w.set_adcaldif(Adcaldif::DIFFERENTIAL);
+        });
+        T::regs().cr().modify(|w| w.set_adcal(true));
+        while T::regs().cr().read().adcal() {}
+        blocking_delay_us(20);
    }
    fn enable(&mut self) {
-        T::regs().isr().write(|w| w.set_adrdy(true));
+        // Make sure bits are off
-        T::regs().cr().modify(|w| w.set_aden(true));
+        while T::regs().cr().read().addis() {
-        while !T::regs().isr().read().adrdy() {}
+            // spin
-        T::regs().isr().write(|w| w.set_adrdy(true));
+        }
+        if !T::regs().cr().read().aden() {
+            // Enable ADC
+            T::regs().isr().modify(|reg| {
+                reg.set_adrdy(true);
+            });
+            T::regs().cr().modify(|reg| {
+                reg.set_aden(true);
+            });
+            while !T::regs().isr().read().adrdy() {
+                // spin
+            }
+        }
    }
    fn configure(&mut self) {
@@ -228,6 +260,68 @@ impl<'d, T: Instance> Adc<'d, T> {
        Vbat {}
    }
+    /// Enable differential channel.
+    /// Caution:
+    /// : When configuring the channel “i” in differential input mode, its negative input voltage VINN[i]
+    /// is connected to another channel. As a consequence, this channel is no longer usable in
+    /// single-ended mode or in differential mode and must never be configured to be converted.
+    /// Some channels are shared between ADC1/ADC2/ADC3/ADC4/ADC5: this can make the
+    /// channel on the other ADC unusable. The only exception is when ADC master and the slave
+    /// operate in interleaved mode.
+    #[cfg(stm32g4)]
+    pub fn set_differential_channel(&mut self, ch: usize, enable: bool) {
+        T::regs().cr().modify(|w| w.set_aden(false)); // disable adc
+        T::regs().difsel().modify(|w| {
+            w.set_difsel(
+                ch,
+                if enable {
+                    Difsel::DIFFERENTIAL
+                } else {
+                    Difsel::SINGLE_ENDED
+                },
+            );
+        });
+        T::regs().cr().modify(|w| w.set_aden(true));
+    }
+    #[cfg(stm32g4)]
+    pub fn set_differential(&mut self, channel: &mut impl AdcChannel<T>, enable: bool) {
+        self.set_differential_channel(channel.channel() as usize, enable);
+    }
+    /// Set oversampling shift.
+    #[cfg(stm32g4)]
+    pub fn set_oversampling_shift(&mut self, shift: u8) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovss(shift));
+    }
+    /// Set oversampling ratio.
+    #[cfg(stm32g4)]
+    pub fn set_oversampling_ratio(&mut self, ratio: u8) {
+        T::regs().cfgr2().modify(|reg| reg.set_ovsr(ratio));
+    }
+    /// Enable oversampling in regular mode.
+    #[cfg(stm32g4)]
+    pub fn enable_regular_oversampling_mode(&mut self, mode: Rovsm, trig_mode: Trovs, enable: bool) {
+        T::regs().cfgr2().modify(|reg| reg.set_trovs(trig_mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovsm(mode));
+        T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+    }
+    // Reads that are not implemented as INJECTED in "blocking_read"
+    // #[cfg(stm32g4)]
+    // pub fn enalble_injected_oversampling_mode(&mut self, enable: bool) {
+    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
+    // }
+    // #[cfg(stm32g4)]
+    // pub fn enable_oversampling_regular_injected_mode(&mut self, enable: bool) {
+    //     // the regularoversampling mode is forced to resumed mode (ROVSM bit ignored),
+    //     T::regs().cfgr2().modify(|reg| reg.set_rovse(enable));
+    //     T::regs().cfgr2().modify(|reg| reg.set_jovse(enable));
+    // }
    /// Set the ADC sample time.
    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
        self.sample_time = sample_time;
@@ -261,23 +355,146 @@ impl<'d, T: Instance> Adc<'d, T> {
    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
        channel.setup();
-        self.read_channel(channel.channel())
+        self.read_channel(channel)
    }
-    fn read_channel(&mut self, channel: u8) -> u16 {
+    /// Read one or multiple ADC channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::{Adc, AdcChannel}
+    ///
+    /// let mut adc = Adc::new(p.ADC1);
+    /// let mut adc_pin0 = p.PA0.into();
+    /// let mut adc_pin1 = p.PA1.into();
+    /// let mut measurements = [0u16; 2];
+    ///
+    /// adc.read(
+    ///     p.DMA1_CH2.reborrow(),
+    ///     [
+    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
+    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
+    ///     ]
+    ///     .into_iter(),
+    ///     &mut measurements,
+    /// )
+    /// .await;
+    /// defmt::info!("measurements: {}", measurements);
+    /// ```
+    pub async fn read(
+        &mut self,
+        rx_dma: Peri<'_, impl RxDma<T>>,
+        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
+        readings: &mut [u16],
+    ) {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        assert!(
+            sequence.len() <= 16,
+            "Asynchronous read sequence cannot be more than 16 in length"
+        );
+        // Ensure no conversions are ongoing and ADC is enabled.
+        Self::cancel_conversions();
+        self.enable();
+        // Set sequence length
+        T::regs().sqr1().modify(|w| {
+            w.set_l(sequence.len() as u8 - 1);
+        });
+        // Configure channels and ranks
+        for (_i, (channel, sample_time)) in sequence.enumerate() {
+            Self::configure_channel(channel, sample_time);
+            match _i {
+                0..=3 => {
+                    T::regs().sqr1().modify(|w| {
+                        w.set_sq(_i, channel.channel());
+                    });
+                }
+                4..=8 => {
+                    T::regs().sqr2().modify(|w| {
+                        w.set_sq(_i - 4, channel.channel());
+                    });
+                }
+                9..=13 => {
+                    T::regs().sqr3().modify(|w| {
+                        w.set_sq(_i - 9, channel.channel());
+                    });
+                }
+                14..=15 => {
+                    T::regs().sqr4().modify(|w| {
+                        w.set_sq(_i - 14, channel.channel());
+                    });
+                }
+                _ => unreachable!(),
+            }
+        }
+        // Set continuous mode with oneshot dma.
+        // Clear overrun flag before starting transfer.
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+        });
+        T::regs().cfgr().modify(|reg| {
+            reg.set_discen(false);
+            reg.set_cont(true);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
+            reg.set_dmaen(Dmaen::ENABLE);
+        });
+        let request = rx_dma.request();
+        let transfer = unsafe {
+            Transfer::new_read(
+                rx_dma,
+                request,
+                T::regs().dr().as_ptr() as *mut u16,
+                readings,
+                Default::default(),
+            )
+        };
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+        // Wait for conversion sequence to finish.
+        transfer.await;
+        // Ensure conversions are finished.
+        Self::cancel_conversions();
+        // Reset configuration.
+        T::regs().cfgr().modify(|reg| {
+            reg.set_cont(false);
+        });
+    }
+    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
        // Configure channel
-        Self::set_channel_sample_time(channel, self.sample_time);
+        Self::set_channel_sample_time(channel.channel(), sample_time);
+    }
+    fn read_channel(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        Self::configure_channel(channel, self.sample_time);
        #[cfg(stm32h7)]
        {
            T::regs().cfgr2().modify(|w| w.set_lshift(0));
            T::regs()
                .pcsel()
-                .write(|w| w.set_pcsel(channel as _, Pcsel::PRESELECTED));
+                .write(|w| w.set_pcsel(channel.channel() as _, Pcsel::PRESELECTED));
        }
        T::regs().sqr1().write(|reg| {
-            reg.set_sq(0, channel);
+            reg.set_sq(0, channel.channel());
            reg.set_l(0);
        });
@@ -292,4 +509,13 @@ impl<'d, T: Instance> Adc<'d, T> {
            T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
        }
    }
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(Adstp::STOP);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
 }
diff --git a/embassy-stm32/src/adc/mod.rs b/embassy-stm32/src/adc/mod.rs
index 2f36df240..f46e87f38 100644
--- a/embassy-stm32/src/adc/mod.rs
+++ b/embassy-stm32/src/adc/mod.rs
@@ -4,37 +4,46 @@
 #![allow(missing_docs)] // TODO
 #![cfg_attr(adc_f3_v2, allow(unused))]
-#[cfg(not(adc_f3_v2))]
+#[cfg(not(any(adc_f3_v2)))]
 #[cfg_attr(adc_f1, path = "f1.rs")]
 #[cfg_attr(adc_f3, path = "f3.rs")]
 #[cfg_attr(adc_f3_v1_1, path = "f3_v1_1.rs")]
 #[cfg_attr(adc_v1, path = "v1.rs")]
 #[cfg_attr(adc_l0, path = "v1.rs")]
 #[cfg_attr(adc_v2, path = "v2.rs")]
-#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_u0), path = "v3.rs")]
+#[cfg_attr(any(adc_v3, adc_g0, adc_h5, adc_h7rs, adc_u0), path = "v3.rs")]
-#[cfg_attr(adc_v4, path = "v4.rs")]
+#[cfg_attr(any(adc_v4, adc_u5), path = "v4.rs")]
 #[cfg_attr(adc_g4, path = "g4.rs")]
+#[cfg_attr(adc_c0, path = "c0.rs")]
 mod _version;
 use core::marker::PhantomData;
 #[allow(unused)]
-#[cfg(not(adc_f3_v2))]
+#[cfg(not(any(adc_f3_v2)))]
 pub use _version::*;
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 #[cfg(any(adc_f1, adc_f3, adc_v1, adc_l0, adc_f3_v1_1))]
 use embassy_sync::waitqueue::AtomicWaker;
+#[cfg(adc_u5)]
+#[path = "u5_adc4.rs"]
+pub mod adc4;
+pub use crate::pac::adc::vals;
 #[cfg(not(any(adc_f1, adc_f3_v2)))]
 pub use crate::pac::adc::vals::Res as Resolution;
 pub use crate::pac::adc::vals::SampleTime;
 use crate::peripherals;
 dma_trait!(RxDma, Instance);
+#[cfg(adc_u5)]
+dma_trait!(RxDma4, adc4::Instance);
 /// Analog to Digital driver.
 pub struct Adc<'d, T: Instance> {
    #[allow(unused)]
-    adc: crate::PeripheralRef<'d, T>,
+    adc: crate::Peri<'d, T>,
    #[cfg(not(any(adc_f3_v2, adc_f3_v1_1)))]
    sample_time: SampleTime,
 }
@@ -64,7 +73,7 @@ trait SealedInstance {
 }
 pub(crate) trait SealedAdcChannel<T> {
-    #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+    #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
    fn setup(&mut self) {}
    #[allow(unused)]
@@ -98,10 +107,13 @@ pub(crate) fn blocking_delay_us(us: u32) {
    adc_f3_v1_1,
    adc_g0,
    adc_u0,
-    adc_h5
+    adc_h5,
+    adc_h7rs,
+    adc_u5,
+    adc_c0
 )))]
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
+pub trait Instance: SealedInstance + crate::PeripheralType {
    type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
 /// ADC instance.
@@ -117,10 +129,13 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> {
    adc_f3_v1_1,
    adc_g0,
    adc_u0,
-    adc_h5
+    adc_h5,
+    adc_h7rs,
+    adc_u5,
+    adc_c0
 ))]
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::RccPeripheral {
+pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
    type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
@@ -129,7 +144,7 @@ pub trait Instance: SealedInstance + crate::Peripheral<P = Self> + crate::rcc::R
 pub trait AdcChannel<T>: SealedAdcChannel<T> + Sized {
    #[allow(unused_mut)]
    fn degrade_adc(mut self) -> AnyAdcChannel<T> {
-        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+        #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
        self.setup();
        AnyAdcChannel {
@@ -147,7 +162,7 @@ pub struct AnyAdcChannel<T> {
    channel: u8,
    _phantom: PhantomData<T>,
 }
+impl_peripheral!(AnyAdcChannel<T: Instance>);
 impl<T: Instance> AdcChannel<T> for AnyAdcChannel<T> {}
 impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
    fn channel(&self) -> u8 {
@@ -155,6 +170,45 @@ impl<T: Instance> SealedAdcChannel<T> for AnyAdcChannel<T> {
    }
 }
+impl<T> AnyAdcChannel<T> {
+    #[allow(unused)]
+    pub fn get_hw_channel(&self) -> u8 {
+        self.channel
+    }
+}
+#[cfg(adc_u5)]
+foreach_adc!(
+    (ADC4, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::adc4::SealedInstance for peripherals::ADC4 {
+            fn regs() -> crate::pac::adc::Adc4 {
+                crate::pac::ADC4
+            }
+        }
+        impl crate::adc::adc4::Instance for peripherals::ADC4 {
+            type Interrupt = crate::_generated::peripheral_interrupts::ADC4::GLOBAL;
+        }
+    };
+    ($inst:ident, $common_inst:ident, $clock:ident) => {
+        impl crate::adc::SealedInstance for peripherals::$inst {
+            fn regs() -> crate::pac::adc::Adc {
+                crate::pac::$inst
+            }
+            fn common_regs() -> crate::pac::adccommon::AdcCommon {
+                return crate::pac::$common_inst
+            }
+        }
+        impl crate::adc::Instance for peripherals::$inst {
+            type Interrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
+#[cfg(not(adc_u5))]
 foreach_adc!(
    ($inst:ident, $common_inst:ident, $clock:ident) => {
        impl crate::adc::SealedInstance for peripherals::$inst {
@@ -182,11 +236,11 @@ foreach_adc!(
 macro_rules! impl_adc_pin {
    ($inst:ident, $pin:ident, $ch:expr) => {
-        impl crate::adc::AdcChannel<peripherals::$inst> for crate::peripherals::$pin {}
+        impl crate::adc::AdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {}
-        impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::peripherals::$pin {
+        impl crate::adc::SealedAdcChannel<peripherals::$inst> for crate::Peri<'_, crate::peripherals::$pin> {
-            #[cfg(any(adc_v1, adc_l0, adc_v2, adc_g4, adc_v4))]
+            #[cfg(any(adc_v1, adc_c0, adc_l0, adc_v2, adc_g4, adc_v4, adc_u5))]
            fn setup(&mut self) {
-                <Self as crate::gpio::SealedPin>::set_as_analog(self);
+                <crate::peripherals::$pin as crate::gpio::SealedPin>::set_as_analog(self);
            }
            fn channel(&self) -> u8 {
@@ -204,7 +258,7 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
    match res {
        #[cfg(adc_v4)]
        Resolution::BITS16 => (1 << 16) - 1,
-        #[cfg(adc_v4)]
+        #[cfg(any(adc_v4, adc_u5))]
        Resolution::BITS14 => (1 << 14) - 1,
        #[cfg(adc_v4)]
        Resolution::BITS14V => (1 << 14) - 1,
@@ -213,7 +267,7 @@ pub const fn resolution_to_max_count(res: Resolution) -> u32 {
        Resolution::BITS12 => (1 << 12) - 1,
        Resolution::BITS10 => (1 << 10) - 1,
        Resolution::BITS8 => (1 << 8) - 1,
-        #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
+        #[cfg(any(adc_v1, adc_v2, adc_v3, adc_l0, adc_c0, adc_g0, adc_f3, adc_f3_v1_1, adc_h5))]
        Resolution::BITS6 => (1 << 6) - 1,
        #[allow(unreachable_patterns)]
        _ => core::unreachable!(),
diff --git a/embassy-stm32/src/adc/ringbuffered_v2.rs b/embassy-stm32/src/adc/ringbuffered_v2.rs
index 3b064044e..6f69e8486 100644
--- a/embassy-stm32/src/adc/ringbuffered_v2.rs
+++ b/embassy-stm32/src/adc/ringbuffered_v2.rs
@@ -2,14 +2,15 @@ use core::marker::PhantomData;
 use core::mem;
 use core::sync::atomic::{compiler_fence, Ordering};
-use embassy_hal_internal::{into_ref, Peripheral};
 use stm32_metapac::adc::vals::SampleTime;
 use crate::adc::{Adc, AdcChannel, Instance, RxDma};
-use crate::dma::ringbuffer::OverrunError;
 use crate::dma::{Priority, ReadableRingBuffer, TransferOptions};
 use crate::pac::adc::vals;
-use crate::rcc;
+use crate::{rcc, Peri};
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct OverrunError;
 fn clear_interrupt_flags(r: crate::pac::adc::Adc) {
    r.sr().modify(|regs| {
@@ -101,13 +102,8 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// It is critical to call `read` frequently to prevent DMA buffer overrun.
    ///
    /// [`read`]: #method.read
-    pub fn into_ring_buffered(
+    pub fn into_ring_buffered(self, dma: Peri<'d, impl RxDma<T>>, dma_buf: &'d mut [u16]) -> RingBufferedAdc<'d, T> {
-        self,
-        dma: impl Peripheral<P = impl RxDma<T>> + 'd,
-        dma_buf: &'d mut [u16],
-    ) -> RingBufferedAdc<'d, T> {
        assert!(!dma_buf.is_empty() && dma_buf.len() <= 0xFFFF);
-        into_ref!(dma);
        let opts: crate::dma::TransferOptions = TransferOptions {
            half_transfer_ir: true,
@@ -203,16 +199,16 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
            Sequence::Four => T::regs().sqr3().modify(|w| w.set_sq(3, channel.channel())),
            Sequence::Five => T::regs().sqr3().modify(|w| w.set_sq(4, channel.channel())),
            Sequence::Six => T::regs().sqr3().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Seven => T::regs().sqr2().modify(|w| w.set_sq(6, channel.channel())),
+            Sequence::Seven => T::regs().sqr2().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Eight => T::regs().sqr2().modify(|w| w.set_sq(7, channel.channel())),
+            Sequence::Eight => T::regs().sqr2().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Nine => T::regs().sqr2().modify(|w| w.set_sq(8, channel.channel())),
+            Sequence::Nine => T::regs().sqr2().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Ten => T::regs().sqr2().modify(|w| w.set_sq(9, channel.channel())),
+            Sequence::Ten => T::regs().sqr2().modify(|w| w.set_sq(3, channel.channel())),
-            Sequence::Eleven => T::regs().sqr2().modify(|w| w.set_sq(10, channel.channel())),
+            Sequence::Eleven => T::regs().sqr2().modify(|w| w.set_sq(4, channel.channel())),
-            Sequence::Twelve => T::regs().sqr2().modify(|w| w.set_sq(11, channel.channel())),
+            Sequence::Twelve => T::regs().sqr2().modify(|w| w.set_sq(5, channel.channel())),
-            Sequence::Thirteen => T::regs().sqr1().modify(|w| w.set_sq(12, channel.channel())),
+            Sequence::Thirteen => T::regs().sqr1().modify(|w| w.set_sq(0, channel.channel())),
-            Sequence::Fourteen => T::regs().sqr1().modify(|w| w.set_sq(13, channel.channel())),
+            Sequence::Fourteen => T::regs().sqr1().modify(|w| w.set_sq(1, channel.channel())),
-            Sequence::Fifteen => T::regs().sqr1().modify(|w| w.set_sq(14, channel.channel())),
+            Sequence::Fifteen => T::regs().sqr1().modify(|w| w.set_sq(2, channel.channel())),
-            Sequence::Sixteen => T::regs().sqr1().modify(|w| w.set_sq(15, channel.channel())),
+            Sequence::Sixteen => T::regs().sqr1().modify(|w| w.set_sq(3, channel.channel())),
        };
        if !was_on {
@@ -226,9 +222,8 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
    /// Turns on ADC if it is not already turned on and starts continuous DMA transfer.
    pub fn start(&mut self) -> Result<(), OverrunError> {
-        self.ring_buf.clear();
        self.setup_adc();
+        self.ring_buf.clear();
        Ok(())
    }
@@ -245,7 +240,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
    /// [`start`]: #method.start
    pub fn teardown_adc(&mut self) {
        // Stop the DMA transfer
-        self.ring_buf.request_stop();
+        self.ring_buf.request_pause();
        let r = T::regs();
@@ -311,7 +306,7 @@ impl<'d, T: Instance> RingBufferedAdc<'d, T> {
            // DMA requests are issues as long as DMA=1 and data are converted.
            w.set_dds(vals::Dds::CONTINUOUS);
            // EOC flag is set at the end of each conversion.
-            w.set_eocs(vals::Eocs::EACHCONVERSION);
+            w.set_eocs(vals::Eocs::EACH_CONVERSION);
        });
        // Begin ADC conversions
diff --git a/embassy-stm32/src/adc/u5_adc4.rs b/embassy-stm32/src/adc/u5_adc4.rs
new file mode 100644
index 000000000..1dd664366
--- /dev/null
+++ b/embassy-stm32/src/adc/u5_adc4.rs
@@ -0,0 +1,478 @@
+#[allow(unused)]
+use pac::adc::vals::{Adc4Dmacfg, Adc4Exten, Adc4OversamplingRatio};
+use super::{blocking_delay_us, AdcChannel, AnyAdcChannel, RxDma4, SealedAdcChannel};
+use crate::dma::Transfer;
+pub use crate::pac::adc::regs::Adc4Chselrmod0;
+pub use crate::pac::adc::vals::{Adc4Presc as Presc, Adc4Res as Resolution, Adc4SampleTime as SampleTime};
+use crate::time::Hertz;
+use crate::{pac, rcc, Peri};
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
+/// Default VREF voltage used for sample conversion to millivolts.
+pub const VREF_DEFAULT_MV: u32 = 3300;
+/// VREF voltage used for factory calibration of VREFINTCAL register.
+pub const VREF_CALIB_MV: u32 = 3300;
+const VREF_CHANNEL: u8 = 0;
+const VCORE_CHANNEL: u8 = 12;
+const TEMP_CHANNEL: u8 = 13;
+const VBAT_CHANNEL: u8 = 14;
+const DAC_CHANNEL: u8 = 21;
+// NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
+/// Internal voltage reference channel.
+pub struct VrefInt;
+impl<T: Instance> AdcChannel<T> for VrefInt {}
+impl<T: Instance> SealedAdcChannel<T> for VrefInt {
+    fn channel(&self) -> u8 {
+        VREF_CHANNEL
+    }
+}
+/// Internal temperature channel.
+pub struct Temperature;
+impl<T: Instance> AdcChannel<T> for Temperature {}
+impl<T: Instance> SealedAdcChannel<T> for Temperature {
+    fn channel(&self) -> u8 {
+        TEMP_CHANNEL
+    }
+}
+/// Internal battery voltage channel.
+pub struct Vbat;
+impl<T: Instance> AdcChannel<T> for Vbat {}
+impl<T: Instance> SealedAdcChannel<T> for Vbat {
+    fn channel(&self) -> u8 {
+        VBAT_CHANNEL
+    }
+}
+/// Internal DAC channel.
+pub struct Dac;
+impl<T: Instance> AdcChannel<T> for Dac {}
+impl<T: Instance> SealedAdcChannel<T> for Dac {
+    fn channel(&self) -> u8 {
+        DAC_CHANNEL
+    }
+}
+/// Internal Vcore channel.
+pub struct Vcore;
+impl<T: Instance> AdcChannel<T> for Vcore {}
+impl<T: Instance> SealedAdcChannel<T> for Vcore {
+    fn channel(&self) -> u8 {
+        VCORE_CHANNEL
+    }
+}
+pub enum DacChannel {
+    OUT1,
+    OUT2,
+}
+/// Number of samples used for averaging.
+pub enum Averaging {
+    Disabled,
+    Samples2,
+    Samples4,
+    Samples8,
+    Samples16,
+    Samples32,
+    Samples64,
+    Samples128,
+    Samples256,
+}
+pub const fn resolution_to_max_count(res: Resolution) -> u32 {
+    match res {
+        Resolution::BITS12 => (1 << 12) - 1,
+        Resolution::BITS10 => (1 << 10) - 1,
+        Resolution::BITS8 => (1 << 8) - 1,
+        Resolution::BITS6 => (1 << 6) - 1,
+        #[allow(unreachable_patterns)]
+        _ => core::unreachable!(),
+    }
+}
+// NOTE (unused): The prescaler enum closely copies the hardware capabilities,
+// but high prescaling doesn't make a lot of sense in the current implementation and is ommited.
+#[allow(unused)]
+enum Prescaler {
+    NotDivided,
+    DividedBy2,
+    DividedBy4,
+    DividedBy6,
+    DividedBy8,
+    DividedBy10,
+    DividedBy12,
+    DividedBy16,
+    DividedBy32,
+    DividedBy64,
+    DividedBy128,
+    DividedBy256,
+}
+impl Prescaler {
+    fn from_ker_ck(frequency: Hertz) -> Self {
+        let raw_prescaler = frequency.0 / MAX_ADC_CLK_FREQ.0;
+        match raw_prescaler {
+            0 => Self::NotDivided,
+            1 => Self::DividedBy2,
+            2..=3 => Self::DividedBy4,
+            4..=5 => Self::DividedBy6,
+            6..=7 => Self::DividedBy8,
+            8..=9 => Self::DividedBy10,
+            10..=11 => Self::DividedBy12,
+            _ => unimplemented!(),
+        }
+    }
+    fn divisor(&self) -> u32 {
+        match self {
+            Prescaler::NotDivided => 1,
+            Prescaler::DividedBy2 => 2,
+            Prescaler::DividedBy4 => 4,
+            Prescaler::DividedBy6 => 6,
+            Prescaler::DividedBy8 => 8,
+            Prescaler::DividedBy10 => 10,
+            Prescaler::DividedBy12 => 12,
+            Prescaler::DividedBy16 => 16,
+            Prescaler::DividedBy32 => 32,
+            Prescaler::DividedBy64 => 64,
+            Prescaler::DividedBy128 => 128,
+            Prescaler::DividedBy256 => 256,
+        }
+    }
+    fn presc(&self) -> Presc {
+        match self {
+            Prescaler::NotDivided => Presc::DIV1,
+            Prescaler::DividedBy2 => Presc::DIV2,
+            Prescaler::DividedBy4 => Presc::DIV4,
+            Prescaler::DividedBy6 => Presc::DIV6,
+            Prescaler::DividedBy8 => Presc::DIV8,
+            Prescaler::DividedBy10 => Presc::DIV10,
+            Prescaler::DividedBy12 => Presc::DIV12,
+            Prescaler::DividedBy16 => Presc::DIV16,
+            Prescaler::DividedBy32 => Presc::DIV32,
+            Prescaler::DividedBy64 => Presc::DIV64,
+            Prescaler::DividedBy128 => Presc::DIV128,
+            Prescaler::DividedBy256 => Presc::DIV256,
+        }
+    }
+}
+pub trait SealedInstance {
+    #[allow(unused)]
+    fn regs() -> crate::pac::adc::Adc4;
+}
+pub trait Instance: SealedInstance + crate::PeripheralType + crate::rcc::RccPeripheral {
+    type Interrupt: crate::interrupt::typelevel::Interrupt;
+}
+pub struct Adc4<'d, T: Instance> {
+    #[allow(unused)]
+    adc: crate::Peri<'d, T>,
+}
+#[derive(Debug)]
+pub enum Adc4Error {
+    InvalidSequence,
+    DMAError,
+}
+impl<'d, T: Instance> Adc4<'d, T> {
+    /// Create a new ADC driver.
+    pub fn new(adc: Peri<'d, T>) -> Self {
+        rcc::enable_and_reset::<T>();
+        let prescaler = Prescaler::from_ker_ck(T::frequency());
+        T::regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
+        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
+        info!("ADC4 frequency set to {}", frequency);
+        if frequency > MAX_ADC_CLK_FREQ {
+            panic!("Maximal allowed frequency for ADC4 is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
+        }
+        let mut s = Self { adc };
+        s.power_up();
+        s.calibrate();
+        blocking_delay_us(1);
+        s.enable();
+        s.configure();
+        s
+    }
+    fn power_up(&mut self) {
+        T::regs().isr().modify(|w| {
+            w.set_ldordy(true);
+        });
+        T::regs().cr().modify(|w| {
+            w.set_advregen(true);
+        });
+        while !T::regs().isr().read().ldordy() {}
+        T::regs().isr().modify(|w| {
+            w.set_ldordy(true);
+        });
+    }
+    fn calibrate(&mut self) {
+        T::regs().cr().modify(|w| w.set_adcal(true));
+        while T::regs().cr().read().adcal() {}
+        T::regs().isr().modify(|w| w.set_eocal(true));
+    }
+    fn enable(&mut self) {
+        T::regs().isr().write(|w| w.set_adrdy(true));
+        T::regs().cr().modify(|w| w.set_aden(true));
+        while !T::regs().isr().read().adrdy() {}
+        T::regs().isr().write(|w| w.set_adrdy(true));
+    }
+    fn configure(&mut self) {
+        // single conversion mode, software trigger
+        T::regs().cfgr1().modify(|w| {
+            w.set_cont(false);
+            w.set_discen(false);
+            w.set_exten(Adc4Exten::DISABLED);
+            w.set_chselrmod(false);
+        });
+        // only use one channel at the moment
+        T::regs().smpr().modify(|w| {
+            for i in 0..24 {
+                w.set_smpsel(i, false);
+            }
+        });
+    }
+    /// Enable reading the voltage reference internal channel.
+    pub fn enable_vrefint(&self) -> VrefInt {
+        T::regs().ccr().modify(|w| {
+            w.set_vrefen(true);
+        });
+        VrefInt {}
+    }
+    /// Enable reading the temperature internal channel.
+    pub fn enable_temperature(&self) -> Temperature {
+        T::regs().ccr().modify(|w| {
+            w.set_vsensesel(true);
+        });
+        Temperature {}
+    }
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vbat(&self) -> Vbat {
+        T::regs().ccr().modify(|w| {
+            w.set_vbaten(true);
+        });
+        Vbat {}
+    }
+    /// Enable reading the vbat internal channel.
+    pub fn enable_vcore(&self) -> Vcore {
+        Vcore {}
+    }
+    /// Enable reading the vbat internal channel.
+    pub fn enable_dac_channel(&self, dac: DacChannel) -> Dac {
+        let mux;
+        match dac {
+            DacChannel::OUT1 => mux = false,
+            DacChannel::OUT2 => mux = true,
+        }
+        T::regs().or().modify(|w| w.set_chn21sel(mux));
+        Dac {}
+    }
+    /// Set the ADC sample time.
+    pub fn set_sample_time(&mut self, sample_time: SampleTime) {
+        T::regs().smpr().modify(|w| {
+            w.set_smp(0, sample_time);
+        });
+    }
+    /// Get the ADC sample time.
+    pub fn sample_time(&self) -> SampleTime {
+        T::regs().smpr().read().smp(0)
+    }
+    /// Set the ADC resolution.
+    pub fn set_resolution(&mut self, resolution: Resolution) {
+        T::regs().cfgr1().modify(|w| w.set_res(resolution.into()));
+    }
+    /// Set hardware averaging.
+    pub fn set_averaging(&mut self, averaging: Averaging) {
+        let (enable, samples, right_shift) = match averaging {
+            Averaging::Disabled => (false, Adc4OversamplingRatio::OVERSAMPLE2X, 0),
+            Averaging::Samples2 => (true, Adc4OversamplingRatio::OVERSAMPLE2X, 1),
+            Averaging::Samples4 => (true, Adc4OversamplingRatio::OVERSAMPLE4X, 2),
+            Averaging::Samples8 => (true, Adc4OversamplingRatio::OVERSAMPLE8X, 3),
+            Averaging::Samples16 => (true, Adc4OversamplingRatio::OVERSAMPLE16X, 4),
+            Averaging::Samples32 => (true, Adc4OversamplingRatio::OVERSAMPLE32X, 5),
+            Averaging::Samples64 => (true, Adc4OversamplingRatio::OVERSAMPLE64X, 6),
+            Averaging::Samples128 => (true, Adc4OversamplingRatio::OVERSAMPLE128X, 7),
+            Averaging::Samples256 => (true, Adc4OversamplingRatio::OVERSAMPLE256X, 8),
+        };
+        T::regs().cfgr2().modify(|w| {
+            w.set_ovsr(samples);
+            w.set_ovss(right_shift);
+            w.set_ovse(enable)
+        })
+    }
+    /// Read an ADC channel.
+    pub fn blocking_read(&mut self, channel: &mut impl AdcChannel<T>) -> u16 {
+        channel.setup();
+        // Select channel
+        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        T::regs().chselrmod0().modify(|w| {
+            w.set_chsel(channel.channel() as usize, true);
+        });
+        // Reset interrupts
+        T::regs().isr().modify(|reg| {
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+        while !T::regs().isr().read().eos() {
+            // spin
+        }
+        T::regs().dr().read().0 as u16
+    }
+    /// Read one or multiple ADC channels using DMA.
+    ///
+    /// `sequence` iterator and `readings` must have the same length.
+    /// The channels in `sequence` must be in ascending order.
+    ///
+    /// Example
+    /// ```rust,ignore
+    /// use embassy_stm32::adc::adc4;
+    /// use embassy_stm32::adc::AdcChannel;
+    ///
+    /// let mut adc4 = adc4::Adc4::new(p.ADC4);
+    /// let mut adc4_pin1 = p.PC1;
+    /// let mut adc4_pin2 = p.PC0;
+    /// let mut.into()d41 = adc4_pin1.into();
+    /// let mut.into()d42 = adc4_pin2.into();
+    /// let mut measurements = [0u16; 2];
+    /// // not that the channels must be in ascending order
+    /// adc4.read(
+    ///     &mut p.GPDMA1_CH1,
+    ///    [
+    ///        &mut.into()d42,
+    ///        &mut.into()d41,
+    ///    ]
+    ///    .into_iter(),
+    ///    &mut measurements,
+    /// ).await.unwrap();
+    /// ```
+    pub async fn read(
+        &mut self,
+        rx_dma: Peri<'_, impl RxDma4<T>>,
+        sequence: impl ExactSizeIterator<Item = &mut AnyAdcChannel<T>>,
+        readings: &mut [u16],
+    ) -> Result<(), Adc4Error> {
+        assert!(sequence.len() != 0, "Asynchronous read sequence cannot be empty");
+        assert!(
+            sequence.len() == readings.len(),
+            "Sequence length must be equal to readings length"
+        );
+        // Ensure no conversions are ongoing
+        Self::cancel_conversions();
+        T::regs().isr().modify(|reg| {
+            reg.set_ovr(true);
+            reg.set_eos(true);
+            reg.set_eoc(true);
+        });
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(true);
+            reg.set_dmacfg(Adc4Dmacfg::ONE_SHOT);
+            reg.set_chselrmod(false);
+        });
+        // Verify and activate sequence
+        let mut prev_channel: i16 = -1;
+        T::regs().chselrmod0().write_value(Adc4Chselrmod0(0_u32));
+        for channel in sequence {
+            let channel_num = channel.channel;
+            if channel_num as i16 <= prev_channel {
+                return Err(Adc4Error::InvalidSequence);
+            };
+            prev_channel = channel_num as i16;
+            T::regs().chselrmod0().modify(|w| {
+                w.set_chsel(channel.channel as usize, true);
+            });
+        }
+        let request = rx_dma.request();
+        let transfer = unsafe {
+            Transfer::new_read(
+                rx_dma,
+                request,
+                T::regs().dr().as_ptr() as *mut u16,
+                readings,
+                Default::default(),
+            )
+        };
+        // Start conversion
+        T::regs().cr().modify(|reg| {
+            reg.set_adstart(true);
+        });
+        transfer.await;
+        // Ensure conversions are finished.
+        Self::cancel_conversions();
+        // Reset configuration.
+        T::regs().cfgr1().modify(|reg| {
+            reg.set_dmaen(false);
+        });
+        if T::regs().isr().read().ovr() {
+            Err(Adc4Error::DMAError)
+        } else {
+            Ok(())
+        }
+    }
+    fn cancel_conversions() {
+        if T::regs().cr().read().adstart() && !T::regs().cr().read().addis() {
+            T::regs().cr().modify(|reg| {
+                reg.set_adstp(true);
+            });
+            while T::regs().cr().read().adstart() {}
+        }
+    }
+}
diff --git a/embassy-stm32/src/adc/v1.rs b/embassy-stm32/src/adc/v1.rs
index 9bec2e13b..fb6f5b7d0 100644
--- a/embassy-stm32/src/adc/v1.rs
+++ b/embassy-stm32/src/adc/v1.rs
@@ -2,7 +2,6 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::into_ref;
 #[cfg(adc_l0)]
 use stm32_metapac::adc::vals::Ckmode;
@@ -10,7 +9,7 @@ use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::interrupt::typelevel::Interrupt;
 use crate::peripherals::ADC1;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 pub const VDDA_CALIB_MV: u32 = 3300;
 pub const VREF_INT: u32 = 1230;
@@ -63,10 +62,9 @@ impl super::SealedAdcChannel<ADC1> for Temperature {
 impl<'d, T: Instance> Adc<'d, T> {
    pub fn new(
-        adc: impl Peripheral<P = T> + 'd,
+        adc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        // Delay 1μs when using HSI14 as the ADC clock.
@@ -160,7 +158,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        channel.setup();
        // A.7.5 Single conversion sequence code example - Software trigger
-        T::regs().chselr().write(|reg| reg.set_chselx(ch_num as usize, true));
+        T::regs().chselr().write(|reg| reg.set_chsel_x(ch_num as usize, true));
        self.convert().await
    }
diff --git a/embassy-stm32/src/adc/v2.rs b/embassy-stm32/src/adc/v2.rs
index 842a5ee6d..e94a25b24 100644
--- a/embassy-stm32/src/adc/v2.rs
+++ b/embassy-stm32/src/adc/v2.rs
@@ -1,10 +1,8 @@
-use embassy_hal_internal::into_ref;
 use super::blocking_delay_us;
 use crate::adc::{Adc, AdcChannel, Instance, Resolution, SampleTime};
 use crate::peripherals::ADC1;
 use crate::time::Hertz;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 mod ringbuffered_v2;
 pub use ringbuffered_v2::{RingBufferedAdc, Sequence};
@@ -97,8 +95,7 @@ impl<'d, T> Adc<'d, T>
 where
    T: Instance,
 {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(adc: Peri<'d, T>) -> Self {
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        let presc = Prescaler::from_pclk2(T::frequency());
diff --git a/embassy-stm32/src/adc/v3.rs b/embassy-stm32/src/adc/v3.rs
index 9441e42ff..313244e19 100644
--- a/embassy-stm32/src/adc/v3.rs
+++ b/embassy-stm32/src/adc/v3.rs
@@ -1,12 +1,11 @@
 use cfg_if::cfg_if;
-use embassy_hal_internal::into_ref;
 use pac::adc::vals::Dmacfg;
 use super::{
    blocking_delay_us, Adc, AdcChannel, AnyAdcChannel, Instance, Resolution, RxDma, SampleTime, SealedAdcChannel,
 };
 use crate::dma::Transfer;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -20,7 +19,7 @@ impl<T: Instance> SealedAdcChannel<T> for VrefInt {
        cfg_if! {
            if #[cfg(adc_g0)] {
                let val = 13;
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                let val = 17;
            } else if #[cfg(adc_u0)] {
                let val = 12;
@@ -39,7 +38,7 @@ impl<T: Instance> SealedAdcChannel<T> for Temperature {
        cfg_if! {
            if #[cfg(adc_g0)] {
                let val = 12;
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                let val = 16;
            } else if #[cfg(adc_u0)] {
                let val = 11;
@@ -58,9 +57,9 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
        cfg_if! {
            if #[cfg(adc_g0)] {
                let val = 14;
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                let val = 2;
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                let val = 13;
            } else {
                let val = 18;
@@ -71,7 +70,7 @@ impl<T: Instance> SealedAdcChannel<T> for Vbat {
 }
 cfg_if! {
-    if #[cfg(adc_h5)] {
+    if #[cfg(any(adc_h5, adc_h7rs))] {
        pub struct VddCore;
        impl<T: Instance> AdcChannel<T> for VddCore {}
        impl<T: Instance> super::SealedAdcChannel<T> for VddCore {
@@ -95,8 +94,7 @@ cfg_if! {
 }
 impl<'d, T: Instance> Adc<'d, T> {
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(adc: Peri<'d, T>) -> Self {
-        into_ref!(adc);
        rcc::enable_and_reset::<T>();
        T::regs().cr().modify(|reg| {
            #[cfg(not(any(adc_g0, adc_u0)))]
@@ -173,7 +171,7 @@ impl<'d, T: Instance> Adc<'d, T> {
                T::regs().ccr().modify(|reg| {
                    reg.set_tsen(true);
                });
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                T::common_regs().ccr().modify(|reg| {
                    reg.set_tsen(true);
                });
@@ -193,7 +191,7 @@ impl<'d, T: Instance> Adc<'d, T> {
                T::regs().ccr().modify(|reg| {
                    reg.set_vbaten(true);
                });
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                T::common_regs().ccr().modify(|reg| {
                    reg.set_vbaten(true);
                });
@@ -262,6 +260,9 @@ impl<'d, T: Instance> Adc<'d, T> {
    ///
    /// `sequence` iterator and `readings` must have the same length.
    ///
+    /// Note: The order of values in `readings` is defined by the pin ADC
+    /// channel number and not the pin order in `sequence`.
+    ///
    /// Example
    /// ```rust,ignore
    /// use embassy_stm32::adc::{Adc, AdcChannel}
@@ -271,8 +272,8 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// let mut adc_pin1 = p.PA1.degrade_adc();
    /// let mut measurements = [0u16; 2];
    ///
-    /// adc.read_async(
+    /// adc.read(
-    ///     p.DMA1_CH2,
+    ///     p.DMA1_CH2.reborrow(),
    ///     [
    ///         (&mut *adc_pin0, SampleTime::CYCLES160_5),
    ///         (&mut *adc_pin1, SampleTime::CYCLES160_5),
@@ -285,7 +286,7 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// ```
    pub async fn read(
        &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
        readings: &mut [u16],
    ) {
@@ -366,14 +367,14 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().cfgr().modify(|reg| {
            reg.set_discen(false);
            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONESHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
            reg.set_dmaen(true);
        });
        #[cfg(any(adc_g0, adc_u0))]
        T::regs().cfgr1().modify(|reg| {
            reg.set_discen(false);
            reg.set_cont(true);
-            reg.set_dmacfg(Dmacfg::ONESHOT);
+            reg.set_dmacfg(Dmacfg::ONE_SHOT);
            reg.set_dmaen(true);
        });
@@ -413,7 +414,7 @@ impl<'d, T: Instance> Adc<'d, T> {
    fn configure_channel(channel: &mut impl AdcChannel<T>, sample_time: SampleTime) {
        // RM0492, RM0481, etc.
        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(adc_h5)]
+        #[cfg(any(adc_h5, adc_h7rs))]
        if channel.channel() == 0 {
            T::regs().or().modify(|reg| reg.set_op0(true));
        }
@@ -446,7 +447,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        // RM0492, RM0481, etc.
        // "This option bit must be set to 1 when ADCx_INP0 or ADCx_INN1 channel is selected."
-        #[cfg(adc_h5)]
+        #[cfg(any(adc_h5, adc_h7rs))]
        if channel.channel() == 0 {
            T::regs().or().modify(|reg| reg.set_op0(false));
        }
@@ -474,7 +475,7 @@ impl<'d, T: Instance> Adc<'d, T> {
            if #[cfg(any(adc_g0, adc_u0))] {
                // On G0 and U6 all channels use the same sampling time.
                T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
-            } else if #[cfg(adc_h5)] {
+            } else if #[cfg(any(adc_h5, adc_h7rs))] {
                match _ch {
                    0..=9 => T::regs().smpr1().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
                    _ => T::regs().smpr2().modify(|w| w.set_smp(_ch as usize % 10, sample_time.into())),
diff --git a/embassy-stm32/src/adc/v4.rs b/embassy-stm32/src/adc/v4.rs
index 63b5b58ea..39e0d51b9 100644
--- a/embassy-stm32/src/adc/v4.rs
+++ b/embassy-stm32/src/adc/v4.rs
@@ -1,5 +1,7 @@
+#[cfg(not(stm32u5))]
+use pac::adc::vals::{Adcaldif, Boost};
 #[allow(unused)]
-use pac::adc::vals::{Adcaldif, Adstp, Boost, Difsel, Dmngt, Exten, Pcsel};
+use pac::adc::vals::{Adstp, Difsel, Dmngt, Exten, Pcsel};
 use pac::adccommon::vals::Presc;
 use super::{
@@ -7,7 +9,7 @@ use super::{
 };
 use crate::dma::Transfer;
 use crate::time::Hertz;
-use crate::{pac, rcc, Peripheral};
+use crate::{pac, rcc, Peri};
 /// Default VREF voltage used for sample conversion to millivolts.
 pub const VREF_DEFAULT_MV: u32 = 3300;
@@ -19,6 +21,8 @@ pub const VREF_CALIB_MV: u32 = 3300;
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(60);
 #[cfg(stm32h7)]
 const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(50);
+#[cfg(stm32u5)]
+const MAX_ADC_CLK_FREQ: Hertz = Hertz::mhz(55);
 #[cfg(stm32g4)]
 const VREF_CHANNEL: u8 = 18;
@@ -31,8 +35,16 @@ const VREF_CHANNEL: u8 = 19;
 const TEMP_CHANNEL: u8 = 18;
 // TODO this should be 14 for H7a/b/35
+#[cfg(not(stm32u5))]
 const VBAT_CHANNEL: u8 = 17;
+#[cfg(stm32u5)]
+const VREF_CHANNEL: u8 = 0;
+#[cfg(stm32u5)]
+const TEMP_CHANNEL: u8 = 19;
+#[cfg(stm32u5)]
+const VBAT_CHANNEL: u8 = 18;
 // NOTE: Vrefint/Temperature/Vbat are not available on all ADCs, this currently cannot be modeled with stm32-data, so these are available from the software on all ADCs
 /// Internal voltage reference channel.
 pub struct VrefInt;
@@ -146,8 +158,7 @@ pub enum Averaging {
 impl<'d, T: Instance> Adc<'d, T> {
    /// Create a new ADC driver.
-    pub fn new(adc: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(adc: Peri<'d, T>) -> Self {
-        embassy_hal_internal::into_ref!(adc);
        rcc::enable_and_reset::<T>();
        let prescaler = Prescaler::from_ker_ck(T::frequency());
@@ -155,7 +166,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::common_regs().ccr().modify(|w| w.set_presc(prescaler.presc()));
        let frequency = Hertz(T::frequency().0 / prescaler.divisor());
-        info!("ADC frequency set to {} Hz", frequency.0);
+        info!("ADC frequency set to {}", frequency);
        if frequency > MAX_ADC_CLK_FREQ {
            panic!("Maximal allowed frequency for the ADC is {} MHz and it varies with different packages, refer to ST docs for more information.", MAX_ADC_CLK_FREQ.0 /  1_000_000 );
@@ -202,14 +213,15 @@ impl<'d, T: Instance> Adc<'d, T> {
    fn configure_differential_inputs(&mut self) {
        T::regs().difsel().modify(|w| {
            for n in 0..20 {
-                w.set_difsel(n, Difsel::SINGLEENDED);
+                w.set_difsel(n, Difsel::SINGLE_ENDED);
            }
        });
    }
    fn calibrate(&mut self) {
        T::regs().cr().modify(|w| {
-            w.set_adcaldif(Adcaldif::SINGLEENDED);
+            #[cfg(not(adc_u5))]
+            w.set_adcaldif(Adcaldif::SINGLE_ENDED);
            w.set_adcallin(true);
        });
@@ -293,7 +305,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        T::regs().cfgr2().modify(|reg| {
            reg.set_rovse(enable);
-            reg.set_osvr(samples);
+            reg.set_ovsr(samples);
            reg.set_ovss(right_shift);
        })
    }
@@ -331,12 +343,12 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// use embassy_stm32::adc::{Adc, AdcChannel}
    ///
    /// let mut adc = Adc::new(p.ADC1);
-    /// let mut adc_pin0 = p.PA0.degrade_adc();
+    /// let mut adc_pin0 = p.PA0.into();
-    /// let mut adc_pin2 = p.PA2.degrade_adc();
+    /// let mut adc_pin2 = p.PA2.into();
    /// let mut measurements = [0u16; 2];
    ///
-    /// adc.read_async(
+    /// adc.read(
-    ///     p.DMA2_CH0,
+    ///     p.DMA2_CH0.reborrow(),
    ///     [
    ///         (&mut *adc_pin0, SampleTime::CYCLES112),
    ///         (&mut *adc_pin2, SampleTime::CYCLES112),
@@ -349,7 +361,7 @@ impl<'d, T: Instance> Adc<'d, T> {
    /// ```
    pub async fn read(
        &mut self,
-        rx_dma: &mut impl RxDma<T>,
+        rx_dma: Peri<'_, impl RxDma<T>>,
        sequence: impl ExactSizeIterator<Item = (&mut AnyAdcChannel<T>, SampleTime)>,
        readings: &mut [u16],
    ) {
@@ -407,7 +419,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        });
        T::regs().cfgr().modify(|reg| {
            reg.set_cont(true);
-            reg.set_dmngt(Dmngt::DMA_ONESHOT);
+            reg.set_dmngt(Dmngt::DMA_ONE_SHOT);
        });
        let request = rx_dma.request();
@@ -446,7 +458,7 @@ impl<'d, T: Instance> Adc<'d, T> {
        Self::set_channel_sample_time(channel, sample_time);
-        #[cfg(stm32h7)]
+        #[cfg(any(stm32h7, stm32u5))]
        {
            T::regs().cfgr2().modify(|w| w.set_lshift(0));
            T::regs()
diff --git a/embassy-stm32/src/can/bxcan/mod.rs b/embassy-stm32/src/can/bxcan/mod.rs
index 278c93ff4..305666d5b 100644
--- a/embassy-stm32/src/can/bxcan/mod.rs
+++ b/embassy-stm32/src/can/bxcan/mod.rs
@@ -6,7 +6,7 @@ use core::marker::PhantomData;
 use core::task::Poll;
 use embassy_hal_internal::interrupt::InterruptExt;
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
@@ -17,11 +17,11 @@ use self::registers::{Registers, RxFifo};
 pub use super::common::{BufferedCanReceiver, BufferedCanSender};
 use super::frame::{Envelope, Frame};
 use super::util;
-use crate::can::enums::{BusError, TryReadError};
+use crate::can::enums::{BusError, InternalOperation, TryReadError};
 use crate::gpio::{AfType, OutputType, Pull, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals, Peri};
 /// Interrupt handler.
 pub struct TxInterruptHandler<T: Instance> {
@@ -68,7 +68,6 @@ pub struct SceInterruptHandler<T: Instance> {
 impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterruptHandler<T> {
    unsafe fn on_interrupt() {
-        info!("sce irq");
        let msr = T::regs().msr();
        let msr_val = msr.read();
@@ -76,9 +75,8 @@ impl<T: Instance> interrupt::typelevel::Handler<T::SCEInterrupt> for SceInterrup
            msr.modify(|m| m.set_slaki(true));
            T::state().err_waker.wake();
        } else if msr_val.erri() {
-            info!("Error interrupt");
            // Disable the interrupt, but don't acknowledge the error, so that it can be
-            // forwarded off the the bus message consumer. If we don't provide some way for
+            // forwarded off the bus message consumer. If we don't provide some way for
            // downstream code to determine that it has already provided this bus error instance
            // to the bus message consumer, we are doomed to re-provide a single error instance for
            // an indefinite amount of time.
@@ -175,16 +173,15 @@ impl<'d> Can<'d> {
    /// Creates a new Bxcan instance, keeping the peripheral in sleep mode.
    /// You must call [Can::enable_non_blocking] to use the peripheral.
    pub fn new<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irqs: impl interrupt::typelevel::Binding<T::TXInterrupt, TxInterruptHandler<T>>
            + interrupt::typelevel::Binding<T::RX0Interrupt, Rx0InterruptHandler<T>>
            + interrupt::typelevel::Binding<T::RX1Interrupt, Rx1InterruptHandler<T>>
            + interrupt::typelevel::Binding<T::SCEInterrupt, SceInterruptHandler<T>>
            + 'd,
    ) -> Self {
-        into_ref!(_peri, rx, tx);
        let info = T::info();
        let regs = &T::info().regs;
@@ -504,6 +501,14 @@ impl<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_
    pub fn reader(&self) -> BufferedCanReceiver {
        self.rx.reader()
    }
+    /// Accesses the filter banks owned by this CAN peripheral.
+    ///
+    /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
+    /// peripheral instead.
+    pub fn modify_filters(&mut self) -> MasterFilters<'_> {
+        self.rx.modify_filters()
+    }
 }
 /// CAN driver, transmit half.
@@ -679,22 +684,18 @@ impl<'d, const TX_BUF_SIZE: usize> BufferedCanTx<'d, TX_BUF_SIZE> {
    /// Returns a sender that can be used for sending CAN frames.
    pub fn writer(&self) -> BufferedCanSender {
+        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
        BufferedCanSender {
            tx_buf: self.tx_buf.sender().into(),
            waker: self.info.tx_waker,
+            internal_operation: self.info.internal_operation,
        }
    }
 }
 impl<'d, const TX_BUF_SIZE: usize> Drop for BufferedCanTx<'d, TX_BUF_SIZE> {
    fn drop(&mut self) {
-        critical_section::with(|_| {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-            }
-        });
    }
 }
@@ -735,6 +736,14 @@ impl<'d> CanRx<'d> {
    ) -> BufferedCanRx<'d, RX_BUF_SIZE> {
        BufferedCanRx::new(self.info, self.state, self, rxb)
    }
+    /// Accesses the filter banks owned by this CAN peripheral.
+    ///
+    /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
+    /// peripheral instead.
+    pub fn modify_filters(&mut self) -> MasterFilters<'_> {
+        unsafe { MasterFilters::new(self.info) }
+    }
 }
 /// User supplied buffer for RX Buffering
@@ -744,16 +753,16 @@ pub type RxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Result<
 pub struct BufferedCanRx<'d, const RX_BUF_SIZE: usize> {
    info: &'static Info,
    state: &'static State,
-    _rx: CanRx<'d>,
+    rx: CanRx<'d>,
    rx_buf: &'static RxBuf<RX_BUF_SIZE>,
 }
 impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
-    fn new(info: &'static Info, state: &'static State, _rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
+    fn new(info: &'static Info, state: &'static State, rx: CanRx<'d>, rx_buf: &'static RxBuf<RX_BUF_SIZE>) -> Self {
        BufferedCanRx {
            info,
            state,
-            _rx,
+            rx,
            rx_buf,
        }
        .setup()
@@ -811,19 +820,25 @@ impl<'d, const RX_BUF_SIZE: usize> BufferedCanRx<'d, RX_BUF_SIZE> {
    /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
    pub fn reader(&self) -> BufferedCanReceiver {
-        self.rx_buf.receiver().into()
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
+        BufferedCanReceiver {
+            rx_buf: self.rx_buf.receiver().into(),
+            internal_operation: self.info.internal_operation,
+        }
+    }
+    /// Accesses the filter banks owned by this CAN peripheral.
+    ///
+    /// To modify filters of a slave peripheral, `modify_filters` has to be called on the master
+    /// peripheral instead.
+    pub fn modify_filters(&mut self) -> MasterFilters<'_> {
+        self.rx.modify_filters()
    }
 }
 impl<'d, const RX_BUF_SIZE: usize> Drop for BufferedCanRx<'d, RX_BUF_SIZE> {
    fn drop(&mut self) {
-        critical_section::with(|_| {
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-            let state = self.state as *const State;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-            }
-        });
    }
 }
@@ -895,7 +910,7 @@ impl RxMode {
                    RxFifo::Fifo0 => 0usize,
                    RxFifo::Fifo1 => 1usize,
                };
-                T::regs().ier().write(|w| {
+                T::regs().ier().modify(|w| {
                    w.set_fmpie(fifo_idx, false);
                });
                waker.wake();
@@ -938,18 +953,22 @@ impl RxMode {
            Self::NonBuffered(_) => {
                let registers = &info.regs;
                if let Some(msg) = registers.receive_fifo(RxFifo::Fifo0) {
-                    registers.0.ier().write(|w| {
+                    registers.0.ier().modify(|w| {
                        w.set_fmpie(0, true);
                    });
                    Ok(msg)
                } else if let Some(msg) = registers.receive_fifo(RxFifo::Fifo1) {
-                    registers.0.ier().write(|w| {
+                    registers.0.ier().modify(|w| {
                        w.set_fmpie(1, true);
                    });
                    Ok(msg)
                } else if let Some(err) = registers.curr_error() {
                    Err(TryReadError::BusError(err))
                } else {
+                    registers.0.ier().modify(|w| {
+                        w.set_fmpie(0, true);
+                        w.set_fmpie(1, true);
+                    });
                    Err(TryReadError::Empty)
                }
            }
@@ -1022,6 +1041,8 @@ pub(crate) struct State {
    pub(crate) rx_mode: RxMode,
    pub(crate) tx_mode: TxMode,
    pub err_waker: AtomicWaker,
+    receiver_instance_count: usize,
+    sender_instance_count: usize,
 }
 impl State {
@@ -1030,6 +1051,8 @@ impl State {
            rx_mode: RxMode::NonBuffered(AtomicWaker::new()),
            tx_mode: TxMode::NonBuffered(AtomicWaker::new()),
            err_waker: AtomicWaker::new(),
+            receiver_instance_count: 1,
+            sender_instance_count: 1,
        }
    }
 }
@@ -1041,6 +1064,7 @@ pub(crate) struct Info {
    rx1_interrupt: crate::interrupt::Interrupt,
    sce_interrupt: crate::interrupt::Interrupt,
    tx_waker: fn(),
+    internal_operation: fn(InternalOperation),
    /// The total number of filter banks available to the instance.
    ///
@@ -1053,11 +1077,12 @@ trait SealedInstance {
    fn regs() -> crate::pac::can::Can;
    fn state() -> &'static State;
    unsafe fn mut_state() -> &'static mut State;
+    fn internal_operation(val: InternalOperation);
 }
 /// CAN instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
    /// TX interrupt for this instance.
    type TXInterrupt: crate::interrupt::typelevel::Interrupt;
    /// RX0 interrupt for this instance.
@@ -1110,6 +1135,7 @@ foreach_peripheral!(
                    rx1_interrupt: crate::_generated::peripheral_interrupts::$inst::RX1::IRQ,
                    sce_interrupt: crate::_generated::peripheral_interrupts::$inst::SCE::IRQ,
                    tx_waker: crate::_generated::peripheral_interrupts::$inst::TX::pend,
+                    internal_operation: peripherals::$inst::internal_operation,
                    num_filter_banks: peripherals::$inst::NUM_FILTER_BANKS,
                };
                &INFO
@@ -1125,6 +1151,37 @@ foreach_peripheral!(
            fn state() -> &'static State {
                unsafe { peripherals::$inst::mut_state() }
            }
+            fn internal_operation(val: InternalOperation) {
+                critical_section::with(|_| {
+                    //let state = self.state as *const State;
+                    unsafe {
+                        //let mut_state = state as *mut State;
+                        let mut_state = peripherals::$inst::mut_state();
+                        match val {
+                            InternalOperation::NotifySenderCreated => {
+                                mut_state.sender_instance_count += 1;
+                            }
+                            InternalOperation::NotifySenderDestroyed => {
+                                mut_state.sender_instance_count -= 1;
+                                if ( 0 == mut_state.sender_instance_count) {
+                                    (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                                }
+                            }
+                            InternalOperation::NotifyReceiverCreated => {
+                                mut_state.receiver_instance_count += 1;
+                            }
+                            InternalOperation::NotifyReceiverDestroyed => {
+                                mut_state.receiver_instance_count -= 1;
+                                if ( 0 == mut_state.receiver_instance_count) {
+                                    (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                                }
+                            }
+                        }
+                    }
+                });
+            }
        }
        impl Instance for peripherals::$inst {
diff --git a/embassy-stm32/src/can/bxcan/registers.rs b/embassy-stm32/src/can/bxcan/registers.rs
index c5de1c683..c295b0f50 100644
--- a/embassy-stm32/src/can/bxcan/registers.rs
+++ b/embassy-stm32/src/can/bxcan/registers.rs
@@ -2,7 +2,7 @@ use core::cmp::Ordering;
 use core::convert::Infallible;
 pub use embedded_can::{ExtendedId, Id, StandardId};
-use stm32_metapac::can::vals::Lec;
+use stm32_metapac::can::vals::{Lec, Rtr};
 use super::{Mailbox, TransmitStatus};
 use crate::can::enums::BusError;
@@ -166,16 +166,16 @@ impl Registers {
            return Some(BusError::BusPassive);
        } else if err.ewgf() {
            return Some(BusError::BusWarning);
-        } else if err.lec() != Lec::NOERROR {
+        } else if err.lec() != Lec::NO_ERROR {
            return Some(match err.lec() {
                Lec::STUFF => BusError::Stuff,
                Lec::FORM => BusError::Form,
                Lec::ACK => BusError::Acknowledge,
-                Lec::BITRECESSIVE => BusError::BitRecessive,
+                Lec::BIT_RECESSIVE => BusError::BitRecessive,
-                Lec::BITDOMINANT => BusError::BitDominant,
+                Lec::BIT_DOMINANT => BusError::BitDominant,
                Lec::CRC => BusError::Crc,
                Lec::CUSTOM => BusError::Software,
-                Lec::NOERROR => unreachable!(),
+                Lec::NO_ERROR => unreachable!(),
            });
        }
        None
@@ -299,13 +299,16 @@ impl Registers {
        mb.tdtr().write(|w| w.set_dlc(frame.header().len() as u8));
        mb.tdlr()
-            .write(|w| w.0 = u32::from_ne_bytes(unwrap!(frame.data()[0..4].try_into())));
+            .write(|w| w.0 = u32::from_ne_bytes(unwrap!(frame.raw_data()[0..4].try_into())));
        mb.tdhr()
-            .write(|w| w.0 = u32::from_ne_bytes(unwrap!(frame.data()[4..8].try_into())));
+            .write(|w| w.0 = u32::from_ne_bytes(unwrap!(frame.raw_data()[4..8].try_into())));
        let id: IdReg = frame.id().into();
        mb.tir().write(|w| {
            w.0 = id.0;
            w.set_txrq(true);
+            if frame.header().rtr() {
+                w.set_rtr(Rtr::REMOTE);
+            }
        });
    }
diff --git a/embassy-stm32/src/can/common.rs b/embassy-stm32/src/can/common.rs
index a54b54f6e..386d4467c 100644
--- a/embassy-stm32/src/can/common.rs
+++ b/embassy-stm32/src/can/common.rs
@@ -1,43 +1,43 @@
-use embassy_sync::channel::{DynamicReceiver, DynamicSender};
+use embassy_sync::channel::{SendDynamicReceiver, SendDynamicSender};
 use super::enums::*;
 use super::frame::*;
 pub(crate) struct ClassicBufferedRxInner {
-    pub rx_sender: DynamicSender<'static, Result<Envelope, BusError>>,
+    pub rx_sender: SendDynamicSender<'static, Result<Envelope, BusError>>,
 }
 pub(crate) struct ClassicBufferedTxInner {
-    pub tx_receiver: DynamicReceiver<'static, Frame>,
+    pub tx_receiver: SendDynamicReceiver<'static, Frame>,
 }
 #[cfg(any(can_fdcan_v1, can_fdcan_h7))]
 pub(crate) struct FdBufferedRxInner {
-    pub rx_sender: DynamicSender<'static, Result<FdEnvelope, BusError>>,
+    pub rx_sender: SendDynamicSender<'static, Result<FdEnvelope, BusError>>,
 }
 #[cfg(any(can_fdcan_v1, can_fdcan_h7))]
 pub(crate) struct FdBufferedTxInner {
-    pub tx_receiver: DynamicReceiver<'static, FdFrame>,
+    pub tx_receiver: SendDynamicReceiver<'static, FdFrame>,
 }
 /// Sender that can be used for sending CAN frames.
-#[derive(Copy, Clone)]
+pub struct BufferedSender<'ch, FRAME> {
-pub struct BufferedCanSender {
+    pub(crate) tx_buf: embassy_sync::channel::SendDynamicSender<'ch, FRAME>,
-    pub(crate) tx_buf: embassy_sync::channel::DynamicSender<'static, Frame>,
    pub(crate) waker: fn(),
+    pub(crate) internal_operation: fn(InternalOperation),
 }
-impl BufferedCanSender {
+impl<'ch, FRAME> BufferedSender<'ch, FRAME> {
    /// Async write frame to TX buffer.
-    pub fn try_write(&mut self, frame: Frame) -> Result<(), embassy_sync::channel::TrySendError<Frame>> {
+    pub fn try_write(&mut self, frame: FRAME) -> Result<(), embassy_sync::channel::TrySendError<FRAME>> {
        self.tx_buf.try_send(frame)?;
        (self.waker)();
        Ok(())
    }
    /// Async write frame to TX buffer.
-    pub async fn write(&mut self, frame: Frame) {
+    pub async fn write(&mut self, frame: FRAME) {
        self.tx_buf.send(frame).await;
        (self.waker)();
    }
@@ -48,5 +48,77 @@ impl BufferedCanSender {
    }
 }
+impl<'ch, FRAME> Clone for BufferedSender<'ch, FRAME> {
+    fn clone(&self) -> Self {
+        (self.internal_operation)(InternalOperation::NotifySenderCreated);
+        Self {
+            tx_buf: self.tx_buf,
+            waker: self.waker,
+            internal_operation: self.internal_operation,
+        }
+    }
+}
+impl<'ch, FRAME> Drop for BufferedSender<'ch, FRAME> {
+    fn drop(&mut self) {
+        (self.internal_operation)(InternalOperation::NotifySenderDestroyed);
+    }
+}
+/// Sender that can be used for sending Classic CAN frames.
+pub type BufferedCanSender = BufferedSender<'static, Frame>;
 /// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
-pub type BufferedCanReceiver = embassy_sync::channel::DynamicReceiver<'static, Result<Envelope, BusError>>;
+pub struct BufferedReceiver<'ch, ENVELOPE> {
+    pub(crate) rx_buf: embassy_sync::channel::SendDynamicReceiver<'ch, Result<ENVELOPE, BusError>>,
+    pub(crate) internal_operation: fn(InternalOperation),
+}
+impl<'ch, ENVELOPE> BufferedReceiver<'ch, ENVELOPE> {
+    /// Receive the next frame.
+    ///
+    /// See [`Channel::receive()`].
+    pub fn receive(&self) -> embassy_sync::channel::DynamicReceiveFuture<'_, Result<ENVELOPE, BusError>> {
+        self.rx_buf.receive()
+    }
+    /// Attempt to immediately receive the next frame.
+    ///
+    /// See [`Channel::try_receive()`]
+    pub fn try_receive(&self) -> Result<Result<ENVELOPE, BusError>, embassy_sync::channel::TryReceiveError> {
+        self.rx_buf.try_receive()
+    }
+    /// Allows a poll_fn to poll until the channel is ready to receive
+    ///
+    /// See [`Channel::poll_ready_to_receive()`]
+    pub fn poll_ready_to_receive(&self, cx: &mut core::task::Context<'_>) -> core::task::Poll<()> {
+        self.rx_buf.poll_ready_to_receive(cx)
+    }
+    /// Poll the channel for the next frame
+    ///
+    /// See [`Channel::poll_receive()`]
+    pub fn poll_receive(&self, cx: &mut core::task::Context<'_>) -> core::task::Poll<Result<ENVELOPE, BusError>> {
+        self.rx_buf.poll_receive(cx)
+    }
+}
+impl<'ch, ENVELOPE> Clone for BufferedReceiver<'ch, ENVELOPE> {
+    fn clone(&self) -> Self {
+        (self.internal_operation)(InternalOperation::NotifyReceiverCreated);
+        Self {
+            rx_buf: self.rx_buf,
+            internal_operation: self.internal_operation,
+        }
+    }
+}
+impl<'ch, ENVELOPE> Drop for BufferedReceiver<'ch, ENVELOPE> {
+    fn drop(&mut self) {
+        (self.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+    }
+}
+/// A BufferedCanReceiver for Classic CAN frames.
+pub type BufferedCanReceiver = BufferedReceiver<'static, Envelope>;
diff --git a/embassy-stm32/src/can/enums.rs b/embassy-stm32/src/can/enums.rs
index a5cca424d..97cb47640 100644
--- a/embassy-stm32/src/can/enums.rs
+++ b/embassy-stm32/src/can/enums.rs
@@ -68,3 +68,17 @@ pub enum TryReadError {
    /// Receive buffer is empty
    Empty,
 }
+/// Internal Operation
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum InternalOperation {
+    /// Notify receiver created
+    NotifyReceiverCreated,
+    /// Notify receiver destroyed
+    NotifyReceiverDestroyed,
+    /// Notify sender created
+    NotifySenderCreated,
+    /// Notify sender destroyed
+    NotifySenderDestroyed,
+}
diff --git a/embassy-stm32/src/can/fd/config.rs b/embassy-stm32/src/can/fd/config.rs
index 68161ca50..c6a66b469 100644
--- a/embassy-stm32/src/can/fd/config.rs
+++ b/embassy-stm32/src/can/fd/config.rs
@@ -328,11 +328,15 @@ pub struct FdCanConfig {
    ///
    /// Automatic retransmission is enabled by default.
    pub automatic_retransmit: bool,
-    /// Enabled or disables the pausing between transmissions
+    /// The transmit pause feature is intended for use in CAN systems where the CAN message
+    /// identifiers are permanently specified to specific values and cannot easily be changed.
    ///
-    /// This feature looses up burst transmissions coming from a single node and it protects against
+    /// These message identifiers can have a higher CAN arbitration priority than other defined
-    /// "babbling idiot" scenarios where the application program erroneously requests too many
+    /// messages, while in a specific application their relative arbitration priority must be inverse.
-    /// transmissions.
+    ///
+    /// This may lead to a case where one ECU sends a burst of CAN messages that cause
+    /// another ECU CAN messages to be delayed because that other messages have a lower
+    /// CAN arbitration priority.
    pub transmit_pause: bool,
    /// Enabled or disables the pausing between transmissions
    ///
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index 07e3dddad..0a22f2c91 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -71,11 +71,28 @@ impl Registers {
        }
    }
+    #[cfg(feature = "time")]
+    pub fn calc_timestamp(&self, ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+        let now_embassy = embassy_time::Instant::now();
+        if ns_per_timer_tick == 0 {
+            return now_embassy;
+        }
+        let cantime = { self.regs.tscv().read().tsc() };
+        let delta = cantime.overflowing_sub(ts_val).0 as u64;
+        let ns = ns_per_timer_tick * delta as u64;
+        now_embassy - embassy_time::Duration::from_nanos(ns)
+    }
+    #[cfg(not(feature = "time"))]
+    pub fn calc_timestamp(&self, _ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
+        ts_val
+    }
    pub fn put_tx_frame(&self, bufidx: usize, header: &Header, buffer: &[u8]) {
        let mailbox = self.tx_buffer_element(bufidx);
        mailbox.reset();
        put_tx_header(mailbox, header);
-        put_tx_data(mailbox, &buffer[..header.len() as usize]);
+        put_tx_data(mailbox, buffer);
        // Set <idx as Mailbox> as ready to transmit
        self.regs.txbar().modify(|w| w.set_ar(bufidx, true));
@@ -190,7 +207,7 @@ impl Registers {
                DataLength::Fdcan(len) => len,
                DataLength::Classic(len) => len,
            };
-            if len as usize > ClassicData::MAX_DATA_LEN {
+            if len as usize > 8 {
                return None;
            }
@@ -200,7 +217,7 @@ impl Registers {
            if header_reg.rtr().bit() {
                F::new_remote(id, len as usize)
            } else {
-                F::new(id, &data)
+                F::new(id, &data[0..(len as usize)])
            }
        } else {
            // Abort request failed because the frame was already sent (or being sent) on
@@ -458,7 +475,7 @@ impl Registers {
    /// [`FdCanConfig::set_transmit_pause`]
    #[inline]
    pub fn set_transmit_pause(&self, enabled: bool) {
-        self.regs.cccr().modify(|w| w.set_txp(!enabled));
+        self.regs.cccr().modify(|w| w.set_txp(enabled));
    }
    /// Configures non-iso mode. See [`FdCanConfig::set_non_iso_mode`]
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index c549313f3..97d22315a 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -4,16 +4,16 @@ use core::marker::PhantomData;
 use core::task::Poll;
 use embassy_hal_internal::interrupt::InterruptExt;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
-use embassy_sync::channel::{Channel, DynamicReceiver, DynamicSender};
+use embassy_sync::channel::Channel;
 use embassy_sync::waitqueue::AtomicWaker;
 use crate::can::fd::peripheral::Registers;
-use crate::gpio::{AfType, OutputType, Pull, Speed};
+use crate::gpio::{AfType, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals, Peri};
 pub(crate) mod fd;
@@ -52,36 +52,39 @@ impl<T: Instance> interrupt::typelevel::Handler<T::IT0Interrupt> for IT0Interrup
            regs.ir().write(|w| w.set_tefn(true));
        }
-        match &T::state().tx_mode {
+        T::info().state.lock(|s| {
-            TxMode::NonBuffered(waker) => waker.wake(),
+            let state = s.borrow_mut();
-            TxMode::ClassicBuffered(buf) => {
+            match &state.tx_mode {
-                if !T::registers().tx_queue_is_full() {
+                TxMode::NonBuffered(waker) => waker.wake(),
-                    match buf.tx_receiver.try_receive() {
+                TxMode::ClassicBuffered(buf) => {
-                        Ok(frame) => {
+                    if !T::registers().tx_queue_is_full() {
-                            _ = T::registers().write(&frame);
+                        match buf.tx_receiver.try_receive() {
+                            Ok(frame) => {
+                                _ = T::registers().write(&frame);
+                            }
+                            Err(_) => {}
                        }
-                        Err(_) => {}
                    }
                }
-            }
+                TxMode::FdBuffered(buf) => {
-            TxMode::FdBuffered(buf) => {
+                    if !T::registers().tx_queue_is_full() {
-                if !T::registers().tx_queue_is_full() {
+                        match buf.tx_receiver.try_receive() {
-                    match buf.tx_receiver.try_receive() {
+                            Ok(frame) => {
-                        Ok(frame) => {
+                                _ = T::registers().write(&frame);
-                            _ = T::registers().write(&frame);
+                            }
+                            Err(_) => {}
                        }
-                        Err(_) => {}
                    }
                }
            }
-        }
-        if ir.rfn(0) {
+            if ir.rfn(0) {
-            T::state().rx_mode.on_interrupt::<T>(0);
+                state.rx_mode.on_interrupt::<T>(0, state.ns_per_timer_tick);
-        }
+            }
-        if ir.rfn(1) {
+            if ir.rfn(1) {
-            T::state().rx_mode.on_interrupt::<T>(1);
+                state.rx_mode.on_interrupt::<T>(1, state.ns_per_timer_tick);
-        }
+            }
+        });
        if ir.bo() {
            regs.ir().write(|w| w.set_bo(true));
@@ -165,7 +168,6 @@ pub struct CanConfigurator<'d> {
    _phantom: PhantomData<&'d ()>,
    config: crate::can::fd::config::FdCanConfig,
    info: &'static Info,
-    state: &'static State,
    /// Reference to internals.
    properties: Properties,
    periph_clock: crate::time::Hertz,
@@ -175,27 +177,30 @@ impl<'d> CanConfigurator<'d> {
    /// Creates a new Fdcan instance, keeping the peripheral in sleep mode.
    /// You must call [Fdcan::enable_non_blocking] to use the peripheral.
    pub fn new<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irqs: impl interrupt::typelevel::Binding<T::IT0Interrupt, IT0InterruptHandler<T>>
            + interrupt::typelevel::Binding<T::IT1Interrupt, IT1InterruptHandler<T>>
            + 'd,
    ) -> CanConfigurator<'d> {
-        into_ref!(_peri, rx, tx);
        rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
        tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
        rcc::enable_and_reset::<T>();
+        let info = T::info();
+        T::info().state.lock(|s| {
+            s.borrow_mut().tx_pin_port = Some(tx.pin_port());
+            s.borrow_mut().rx_pin_port = Some(rx.pin_port());
+        });
+        (info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        let mut config = crate::can::fd::config::FdCanConfig::default();
        config.timestamp_source = TimestampSource::Prescaler(TimestampPrescaler::_1);
        T::registers().into_config_mode(config);
-        rx.set_as_af(rx.af_num(), AfType::input(Pull::None));
-        tx.set_as_af(tx.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
        unsafe {
            T::IT0Interrupt::unpend(); // Not unsafe
            T::IT0Interrupt::enable();
@@ -206,8 +211,7 @@ impl<'d> CanConfigurator<'d> {
        Self {
            _phantom: PhantomData,
            config,
-            info: T::info(),
+            info,
-            state: T::state(),
            properties: Properties::new(T::info()),
            periph_clock: T::frequency(),
        }
@@ -259,19 +263,16 @@ impl<'d> CanConfigurator<'d> {
    /// Start in mode.
    pub fn start(self, mode: OperatingMode) -> Can<'d> {
        let ns_per_timer_tick = calc_ns_per_timer_tick(self.info, self.periph_clock, self.config.frame_transmit);
-        critical_section::with(|_| {
+        self.info.state.lock(|s| {
-            let state = self.state as *const State;
+            s.borrow_mut().ns_per_timer_tick = ns_per_timer_tick;
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).ns_per_timer_tick = ns_per_timer_tick;
-            }
        });
        self.info.regs.into_mode(self.config, mode);
+        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        Can {
            _phantom: PhantomData,
            config: self.config,
            info: self.info,
-            state: self.state,
            _mode: mode,
            properties: Properties::new(self.info),
        }
@@ -293,12 +294,18 @@ impl<'d> CanConfigurator<'d> {
    }
 }
+impl<'d> Drop for CanConfigurator<'d> {
+    fn drop(&mut self) {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
+    }
+}
 /// FDCAN Instance
 pub struct Can<'d> {
    _phantom: PhantomData<&'d ()>,
    config: crate::can::fd::config::FdCanConfig,
    info: &'static Info,
-    state: &'static State,
    _mode: OperatingMode,
    properties: Properties,
 }
@@ -312,7 +319,9 @@ impl<'d> Can<'d> {
    /// Flush one of the TX mailboxes.
    pub async fn flush(&self, idx: usize) {
        poll_fn(|cx| {
-            self.state.tx_mode.register(cx.waker());
+            self.info.state.lock(|s| {
+                s.borrow_mut().tx_mode.register(cx.waker());
+            });
            if idx > 3 {
                panic!("Bad mailbox");
@@ -332,12 +341,12 @@ impl<'d> Can<'d> {
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
    pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        self.state.tx_mode.write(self.info, frame).await
+        TxMode::write(self.info, frame).await
    }
    /// Returns the next received message frame
    pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read_classic(self.info, self.state).await
+        RxMode::read_classic(self.info).await
    }
    /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -345,40 +354,43 @@ impl<'d> Can<'d> {
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
    pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        self.state.tx_mode.write_fd(self.info, frame).await
+        TxMode::write_fd(self.info, frame).await
    }
    /// Returns the next received message frame
    pub async fn read_fd(&mut self) -> Result<FdEnvelope, BusError> {
-        self.state.rx_mode.read_fd(self.info, self.state).await
+        RxMode::read_fd(self.info).await
    }
    /// Split instance into separate portions: Tx(write), Rx(read), common properties
    pub fn split(self) -> (CanTx<'d>, CanRx<'d>, Properties) {
+        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        (
            CanTx {
                _phantom: PhantomData,
                info: self.info,
-                state: self.state,
                config: self.config,
                _mode: self._mode,
            },
            CanRx {
                _phantom: PhantomData,
                info: self.info,
-                state: self.state,
                _mode: self._mode,
            },
-            self.properties,
+            Properties {
+                info: self.properties.info,
+            },
        )
    }
    /// Join split rx and tx portions back together
    pub fn join(tx: CanTx<'d>, rx: CanRx<'d>) -> Self {
+        (tx.info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (tx.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        Can {
            _phantom: PhantomData,
            config: tx.config,
            info: tx.info,
-            state: tx.state,
            _mode: rx._mode,
            properties: Properties::new(tx.info),
        }
@@ -390,7 +402,7 @@ impl<'d> Can<'d> {
        tx_buf: &'static mut TxBuf<TX_BUF_SIZE>,
        rxb: &'static mut RxBuf<RX_BUF_SIZE>,
    ) -> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCan::new(self.info, self.state, self._mode, tx_buf, rxb)
+        BufferedCan::new(self.info, self._mode, tx_buf, rxb)
    }
    /// Return a buffered instance of driver with CAN FD support. User must supply Buffers
@@ -399,7 +411,14 @@ impl<'d> Can<'d> {
        tx_buf: &'static mut TxFdBuf<TX_BUF_SIZE>,
        rxb: &'static mut RxFdBuf<RX_BUF_SIZE>,
    ) -> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
-        BufferedCanFd::new(self.info, self.state, self._mode, tx_buf, rxb)
+        BufferedCanFd::new(self.info, self._mode, tx_buf, rxb)
+    }
+}
+impl<'d> Drop for Can<'d> {
+    fn drop(&mut self) {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
    }
 }
@@ -413,7 +432,6 @@ pub type TxBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Frame,
 pub struct BufferedCan<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
    _phantom: PhantomData<&'d ()>,
    info: &'static Info,
-    state: &'static State,
    _mode: OperatingMode,
    tx_buf: &'static TxBuf<TX_BUF_SIZE>,
    rx_buf: &'static RxBuf<RX_BUF_SIZE>,
@@ -423,15 +441,15 @@ pub struct BufferedCan<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
    fn new(
        info: &'static Info,
-        state: &'static State,
        _mode: OperatingMode,
        tx_buf: &'static TxBuf<TX_BUF_SIZE>,
        rx_buf: &'static RxBuf<RX_BUF_SIZE>,
    ) -> Self {
+        (info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        BufferedCan {
            _phantom: PhantomData,
            info,
-            state,
            _mode,
            tx_buf,
            rx_buf,
@@ -447,19 +465,15 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
    fn setup(self) -> Self {
        // We don't want interrupts being processed while we change modes.
-        critical_section::with(|_| {
+        self.info.state.lock(|s| {
            let rx_inner = super::common::ClassicBufferedRxInner {
                rx_sender: self.rx_buf.sender().into(),
            };
            let tx_inner = super::common::ClassicBufferedTxInner {
                tx_receiver: self.tx_buf.receiver().into(),
            };
-            let state = self.state as *const State;
+            s.borrow_mut().rx_mode = RxMode::ClassicBuffered(rx_inner);
-            unsafe {
+            s.borrow_mut().tx_mode = TxMode::ClassicBuffered(tx_inner);
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::ClassicBuffered(rx_inner);
-                (*mut_state).tx_mode = TxMode::ClassicBuffered(tx_inner);
-            }
        });
        self
    }
@@ -478,28 +492,28 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCan<'d,
    /// Returns a sender that can be used for sending CAN frames.
    pub fn writer(&self) -> BufferedCanSender {
+        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
        BufferedCanSender {
            tx_buf: self.tx_buf.sender().into(),
            waker: self.info.tx_waker,
+            internal_operation: self.info.internal_operation,
        }
    }
    /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
    pub fn reader(&self) -> BufferedCanReceiver {
-        self.rx_buf.receiver().into()
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
+        BufferedCanReceiver {
+            rx_buf: self.rx_buf.receiver().into(),
+            internal_operation: self.info.internal_operation,
+        }
    }
 }
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCan<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
    fn drop(&mut self) {
-        critical_section::with(|_| {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-            let state = self.state as *const State;
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-            }
-        });
    }
 }
@@ -509,41 +523,16 @@ pub type RxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, Resul
 /// User supplied buffer for TX buffering
 pub type TxFdBuf<const BUF_SIZE: usize> = Channel<CriticalSectionRawMutex, FdFrame, BUF_SIZE>;
-/// Sender that can be used for sending CAN frames.
+/// Sender that can be used for sending Classic CAN frames.
-#[derive(Copy, Clone)]
+pub type BufferedFdCanSender = super::common::BufferedSender<'static, FdFrame>;
-pub struct BufferedFdCanSender {
-    tx_buf: DynamicSender<'static, FdFrame>,
-    waker: fn(),
-}
-impl BufferedFdCanSender {
-    /// Async write frame to TX buffer.
-    pub fn try_write(&mut self, frame: FdFrame) -> Result<(), embassy_sync::channel::TrySendError<FdFrame>> {
-        self.tx_buf.try_send(frame)?;
-        (self.waker)();
-        Ok(())
-    }
-    /// Async write frame to TX buffer.
-    pub async fn write(&mut self, frame: FdFrame) {
-        self.tx_buf.send(frame).await;
-        (self.waker)();
-    }
-    /// Allows a poll_fn to poll until the channel is ready to write
-    pub fn poll_ready_to_send(&self, cx: &mut core::task::Context<'_>) -> core::task::Poll<()> {
-        self.tx_buf.poll_ready_to_send(cx)
-    }
-}
 /// Receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
-pub type BufferedFdCanReceiver = DynamicReceiver<'static, Result<FdEnvelope, BusError>>;
+pub type BufferedFdCanReceiver = super::common::BufferedReceiver<'static, FdEnvelope>;
 /// Buffered FDCAN Instance
 pub struct BufferedCanFd<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> {
    _phantom: PhantomData<&'d ()>,
    info: &'static Info,
-    state: &'static State,
    _mode: OperatingMode,
    tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
    rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
@@ -553,15 +542,15 @@ pub struct BufferedCanFd<'d, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize>
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
    fn new(
        info: &'static Info,
-        state: &'static State,
        _mode: OperatingMode,
        tx_buf: &'static TxFdBuf<TX_BUF_SIZE>,
        rx_buf: &'static RxFdBuf<RX_BUF_SIZE>,
    ) -> Self {
+        (info.internal_operation)(InternalOperation::NotifySenderCreated);
+        (info.internal_operation)(InternalOperation::NotifyReceiverCreated);
        BufferedCanFd {
            _phantom: PhantomData,
            info,
-            state,
            _mode,
            tx_buf,
            rx_buf,
@@ -577,19 +566,15 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
    fn setup(self) -> Self {
        // We don't want interrupts being processed while we change modes.
-        critical_section::with(|_| {
+        self.info.state.lock(|s| {
            let rx_inner = super::common::FdBufferedRxInner {
                rx_sender: self.rx_buf.sender().into(),
            };
            let tx_inner = super::common::FdBufferedTxInner {
                tx_receiver: self.tx_buf.receiver().into(),
            };
-            let state = self.state as *const State;
+            s.borrow_mut().rx_mode = RxMode::FdBuffered(rx_inner);
-            unsafe {
+            s.borrow_mut().tx_mode = TxMode::FdBuffered(tx_inner);
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::FdBuffered(rx_inner);
-                (*mut_state).tx_mode = TxMode::FdBuffered(tx_inner);
-            }
        });
        self
    }
@@ -608,28 +593,28 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> BufferedCanFd<'
    /// Returns a sender that can be used for sending CAN frames.
    pub fn writer(&self) -> BufferedFdCanSender {
+        (self.info.internal_operation)(InternalOperation::NotifySenderCreated);
        BufferedFdCanSender {
            tx_buf: self.tx_buf.sender().into(),
            waker: self.info.tx_waker,
+            internal_operation: self.info.internal_operation,
        }
    }
    /// Returns a receiver that can be used for receiving CAN frames. Note, each CAN frame will only be received by one receiver.
    pub fn reader(&self) -> BufferedFdCanReceiver {
-        self.rx_buf.receiver().into()
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverCreated);
+        BufferedFdCanReceiver {
+            rx_buf: self.rx_buf.receiver().into(),
+            internal_operation: self.info.internal_operation,
+        }
    }
 }
 impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for BufferedCanFd<'d, TX_BUF_SIZE, RX_BUF_SIZE> {
    fn drop(&mut self) {
-        critical_section::with(|_| {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
-            let state = self.state as *const State;
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
-            unsafe {
-                let mut_state = state as *mut State;
-                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
-            }
-        });
    }
 }
@@ -637,19 +622,24 @@ impl<'c, 'd, const TX_BUF_SIZE: usize, const RX_BUF_SIZE: usize> Drop for Buffer
 pub struct CanRx<'d> {
    _phantom: PhantomData<&'d ()>,
    info: &'static Info,
-    state: &'static State,
    _mode: OperatingMode,
 }
 impl<'d> CanRx<'d> {
    /// Returns the next received message frame
    pub async fn read(&mut self) -> Result<Envelope, BusError> {
-        self.state.rx_mode.read_classic(&self.info, &self.state).await
+        RxMode::read_classic(&self.info).await
    }
    /// Returns the next received message frame
    pub async fn read_fd(&mut self) -> Result<FdEnvelope, BusError> {
-        self.state.rx_mode.read_fd(&self.info, &self.state).await
+        RxMode::read_fd(&self.info).await
+    }
+}
+impl<'d> Drop for CanRx<'d> {
+    fn drop(&mut self) {
+        (self.info.internal_operation)(InternalOperation::NotifyReceiverDestroyed);
    }
 }
@@ -657,7 +647,6 @@ impl<'d> CanRx<'d> {
 pub struct CanTx<'d> {
    _phantom: PhantomData<&'d ()>,
    info: &'static Info,
-    state: &'static State,
    config: crate::can::fd::config::FdCanConfig,
    _mode: OperatingMode,
 }
@@ -668,7 +657,7 @@ impl<'c, 'd> CanTx<'d> {
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
    pub async fn write(&mut self, frame: &Frame) -> Option<Frame> {
-        self.state.tx_mode.write(self.info, frame).await
+        TxMode::write(self.info, frame).await
    }
    /// Queues the message to be sent but exerts backpressure.  If a lower-priority
@@ -676,7 +665,13 @@ impl<'c, 'd> CanTx<'d> {
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
    pub async fn write_fd(&mut self, frame: &FdFrame) -> Option<FdFrame> {
-        self.state.tx_mode.write_fd(self.info, frame).await
+        TxMode::write_fd(self.info, frame).await
+    }
+}
+impl<'d> Drop for CanTx<'d> {
+    fn drop(&mut self) {
+        (self.info.internal_operation)(InternalOperation::NotifySenderDestroyed);
    }
 }
@@ -696,19 +691,19 @@ impl RxMode {
        }
    }
-    fn on_interrupt<T: Instance>(&self, fifonr: usize) {
+    fn on_interrupt<T: Instance>(&self, fifonr: usize, ns_per_timer_tick: u64) {
        T::registers().regs.ir().write(|w| w.set_rfn(fifonr, true));
        match self {
            RxMode::NonBuffered(waker) => {
                waker.wake();
            }
            RxMode::ClassicBuffered(buf) => {
-                if let Some(result) = self.try_read::<T>() {
+                if let Some(result) = self.try_read::<T>(ns_per_timer_tick) {
                    let _ = buf.rx_sender.try_send(result);
                }
            }
            RxMode::FdBuffered(buf) => {
-                if let Some(result) = self.try_read_fd::<T>() {
+                if let Some(result) = self.try_read_fd::<T>(ns_per_timer_tick) {
                    let _ = buf.rx_sender.try_send(result);
                }
            }
@@ -716,12 +711,12 @@ impl RxMode {
    }
    //async fn read_classic<T: Instance>(&self) -> Result<Envelope, BusError> {
-    fn try_read<T: Instance>(&self) -> Option<Result<Envelope, BusError>> {
+    fn try_read<T: Instance>(&self, ns_per_timer_tick: u64) -> Option<Result<Envelope, BusError>> {
        if let Some((frame, ts)) = T::registers().read(0) {
-            let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+            let ts = T::registers().calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok(Envelope { ts, frame }))
        } else if let Some((frame, ts)) = T::registers().read(1) {
-            let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+            let ts = T::registers().calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok(Envelope { ts, frame }))
        } else if let Some(err) = T::registers().curr_error() {
            // TODO: this is probably wrong
@@ -731,12 +726,12 @@ impl RxMode {
        }
    }
-    fn try_read_fd<T: Instance>(&self) -> Option<Result<FdEnvelope, BusError>> {
+    fn try_read_fd<T: Instance>(&self, ns_per_timer_tick: u64) -> Option<Result<FdEnvelope, BusError>> {
        if let Some((frame, ts)) = T::registers().read(0) {
-            let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+            let ts = T::registers().calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok(FdEnvelope { ts, frame }))
        } else if let Some((frame, ts)) = T::registers().read(1) {
-            let ts = T::calc_timestamp(T::state().ns_per_timer_tick, ts);
+            let ts = T::registers().calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok(FdEnvelope { ts, frame }))
        } else if let Some(err) = T::registers().curr_error() {
            // TODO: this is probably wrong
@@ -746,16 +741,12 @@ impl RxMode {
        }
    }
-    fn read<F: CanHeader>(
+    fn read<F: CanHeader>(info: &'static Info, ns_per_timer_tick: u64) -> Option<Result<(F, Timestamp), BusError>> {
-        &self,
-        info: &'static Info,
-        state: &'static State,
-    ) -> Option<Result<(F, Timestamp), BusError>> {
        if let Some((msg, ts)) = info.regs.read(0) {
-            let ts = info.calc_timestamp(state.ns_per_timer_tick, ts);
+            let ts = info.regs.calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok((msg, ts)))
        } else if let Some((msg, ts)) = info.regs.read(1) {
-            let ts = info.calc_timestamp(state.ns_per_timer_tick, ts);
+            let ts = info.regs.calc_timestamp(ns_per_timer_tick, ts);
            Some(Ok((msg, ts)))
        } else if let Some(err) = info.regs.curr_error() {
            // TODO: this is probably wrong
@@ -765,16 +756,15 @@ impl RxMode {
        }
    }
-    async fn read_async<F: CanHeader>(
+    async fn read_async<F: CanHeader>(info: &'static Info) -> Result<(F, Timestamp), BusError> {
-        &self,
-        info: &'static Info,
-        state: &'static State,
-    ) -> Result<(F, Timestamp), BusError> {
-        //let _ = self.read::<F>(info, state);
        poll_fn(move |cx| {
-            state.err_waker.register(cx.waker());
+            let ns_per_timer_tick = info.state.lock(|s| {
-            self.register(cx.waker());
+                let state = s.borrow_mut();
-            match self.read::<_>(info, state) {
+                state.err_waker.register(cx.waker());
+                state.rx_mode.register(cx.waker());
+                state.ns_per_timer_tick
+            });
+            match RxMode::read::<_>(info, ns_per_timer_tick) {
                Some(result) => Poll::Ready(result),
                None => Poll::Pending,
            }
@@ -782,15 +772,15 @@ impl RxMode {
        .await
    }
-    async fn read_classic(&self, info: &'static Info, state: &'static State) -> Result<Envelope, BusError> {
+    async fn read_classic(info: &'static Info) -> Result<Envelope, BusError> {
-        match self.read_async::<_>(info, state).await {
+        match RxMode::read_async::<_>(info).await {
            Ok((frame, ts)) => Ok(Envelope { ts, frame }),
            Err(e) => Err(e),
        }
    }
-    async fn read_fd(&self, info: &'static Info, state: &'static State) -> Result<FdEnvelope, BusError> {
+    async fn read_fd(info: &'static Info) -> Result<FdEnvelope, BusError> {
-        match self.read_async::<_>(info, state).await {
+        match RxMode::read_async::<_>(info).await {
            Ok((frame, ts)) => Ok(FdEnvelope { ts, frame }),
            Err(e) => Err(e),
        }
@@ -819,9 +809,11 @@ impl TxMode {
    /// frame is dropped from the mailbox, it is returned.  If no lower-priority frames
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
-    async fn write_generic<F: embedded_can::Frame + CanHeader>(&self, info: &'static Info, frame: &F) -> Option<F> {
+    async fn write_generic<F: embedded_can::Frame + CanHeader>(info: &'static Info, frame: &F) -> Option<F> {
        poll_fn(|cx| {
-            self.register(cx.waker());
+            info.state.lock(|s| {
+                s.borrow_mut().tx_mode.register(cx.waker());
+            });
            if let Ok(dropped) = info.regs.write(frame) {
                return Poll::Ready(dropped);
@@ -838,16 +830,16 @@ impl TxMode {
    /// frame is dropped from the mailbox, it is returned.  If no lower-priority frames
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
-    async fn write(&self, info: &'static Info, frame: &Frame) -> Option<Frame> {
+    async fn write(info: &'static Info, frame: &Frame) -> Option<Frame> {
-        self.write_generic::<_>(info, frame).await
+        TxMode::write_generic::<_>(info, frame).await
    }
    /// Queues the message to be sent but exerts backpressure.  If a lower-priority
    /// frame is dropped from the mailbox, it is returned.  If no lower-priority frames
    /// can be replaced, this call asynchronously waits for a frame to be successfully
    /// transmitted, then tries again.
-    async fn write_fd(&self, info: &'static Info, frame: &FdFrame) -> Option<FdFrame> {
+    async fn write_fd(info: &'static Info, frame: &FdFrame) -> Option<FdFrame> {
-        self.write_generic::<_>(info, frame).await
+        TxMode::write_generic::<_>(info, frame).await
    }
 }
@@ -922,6 +914,10 @@ struct State {
    pub rx_mode: RxMode,
    pub tx_mode: TxMode,
    pub ns_per_timer_tick: u64,
+    receiver_instance_count: usize,
+    sender_instance_count: usize,
+    tx_pin_port: Option<u8>,
+    rx_pin_port: Option<u8>,
    pub err_waker: AtomicWaker,
 }
@@ -933,34 +929,22 @@ impl State {
            tx_mode: TxMode::NonBuffered(AtomicWaker::new()),
            ns_per_timer_tick: 0,
            err_waker: AtomicWaker::new(),
+            receiver_instance_count: 0,
+            sender_instance_count: 0,
+            tx_pin_port: None,
+            rx_pin_port: None,
        }
    }
 }
+type SharedState = embassy_sync::blocking_mutex::Mutex<CriticalSectionRawMutex, core::cell::RefCell<State>>;
 struct Info {
    regs: Registers,
    interrupt0: crate::interrupt::Interrupt,
    _interrupt1: crate::interrupt::Interrupt,
    tx_waker: fn(),
-}
+    internal_operation: fn(InternalOperation),
+    state: SharedState,
-impl Info {
-    #[cfg(feature = "time")]
-    fn calc_timestamp(&self, ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
-        let now_embassy = embassy_time::Instant::now();
-        if ns_per_timer_tick == 0 {
-            return now_embassy;
-        }
-        let cantime = { self.regs.regs.tscv().read().tsc() };
-        let delta = cantime.overflowing_sub(ts_val).0 as u64;
-        let ns = ns_per_timer_tick * delta as u64;
-        now_embassy - embassy_time::Duration::from_nanos(ns)
-    }
-    #[cfg(not(feature = "time"))]
-    fn calc_timestamp(&self, _ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
-        ts_val
-    }
 }
 trait SealedInstance {
@@ -968,14 +952,12 @@ trait SealedInstance {
    fn info() -> &'static Info;
    fn registers() -> crate::can::fd::peripheral::Registers;
-    fn state() -> &'static State;
+    fn internal_operation(val: InternalOperation);
-    unsafe fn mut_state() -> &'static mut State;
-    fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp;
 }
 /// Instance trait
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
    /// Interrupt 0
    type IT0Interrupt: crate::interrupt::typelevel::Interrupt;
    /// Interrupt 1
@@ -983,7 +965,7 @@ pub trait Instance: SealedInstance + RccPeripheral + 'static {
 }
 /// Fdcan Instance struct
-pub struct FdcanInstance<'a, T>(PeripheralRef<'a, T>);
+pub struct FdcanInstance<'a, T: Instance>(Peri<'a, T>);
 macro_rules! impl_fdcan {
    ($inst:ident,
@@ -992,42 +974,56 @@ macro_rules! impl_fdcan {
        impl SealedInstance for peripherals::$inst {
            const MSG_RAM_OFFSET: usize = $msg_ram_offset;
+            fn internal_operation(val: InternalOperation) {
+                peripherals::$inst::info().state.lock(|s| {
+                    let mut mut_state = s.borrow_mut();
+                    match val {
+                        InternalOperation::NotifySenderCreated => {
+                            mut_state.sender_instance_count += 1;
+                        }
+                        InternalOperation::NotifySenderDestroyed => {
+                            mut_state.sender_instance_count -= 1;
+                            if ( 0 == mut_state.sender_instance_count) {
+                                (*mut_state).tx_mode = TxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                            }
+                        }
+                        InternalOperation::NotifyReceiverCreated => {
+                            mut_state.receiver_instance_count += 1;
+                        }
+                        InternalOperation::NotifyReceiverDestroyed => {
+                            mut_state.receiver_instance_count -= 1;
+                            if ( 0 == mut_state.receiver_instance_count) {
+                                (*mut_state).rx_mode = RxMode::NonBuffered(embassy_sync::waitqueue::AtomicWaker::new());
+                            }
+                        }
+                    }
+                    if mut_state.sender_instance_count == 0 && mut_state.receiver_instance_count == 0 {
+                        unsafe {
+                            let tx_pin = crate::gpio::AnyPin::steal(mut_state.tx_pin_port.unwrap());
+                            tx_pin.set_as_disconnected();
+                            let rx_pin = crate::gpio::AnyPin::steal(mut_state.rx_pin_port.unwrap());
+                            rx_pin.set_as_disconnected();
+                            rcc::disable::<peripherals::$inst>();
+                        }
+                    }
+                });
+            }
            fn info() -> &'static Info {
                static INFO: Info = Info {
                    regs: Registers{regs: crate::pac::$inst, msgram: crate::pac::$msg_ram_inst, msg_ram_offset: $msg_ram_offset},
                    interrupt0: crate::_generated::peripheral_interrupts::$inst::IT0::IRQ,
                    _interrupt1: crate::_generated::peripheral_interrupts::$inst::IT1::IRQ,
                    tx_waker: crate::_generated::peripheral_interrupts::$inst::IT0::pend,
+                    internal_operation: peripherals::$inst::internal_operation,
+                    state: embassy_sync::blocking_mutex::Mutex::new(core::cell::RefCell::new(State::new())),
                };
                &INFO
            }
            fn registers() -> Registers {
                Registers{regs: crate::pac::$inst, msgram: crate::pac::$msg_ram_inst, msg_ram_offset: Self::MSG_RAM_OFFSET}
            }
-            unsafe fn mut_state() -> &'static mut State {
-                static mut STATE: State = State::new();
-                &mut *core::ptr::addr_of_mut!(STATE)
-            }
-            fn state() -> &'static State {
-                unsafe { peripherals::$inst::mut_state() }
-            }
-            #[cfg(feature = "time")]
-            fn calc_timestamp(ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
-                let now_embassy = embassy_time::Instant::now();
-                if ns_per_timer_tick == 0 {
-                    return now_embassy;
-                }
-                let cantime = { Self::registers().regs.tscv().read().tsc() };
-                let delta = cantime.overflowing_sub(ts_val).0 as u64;
-                let ns = ns_per_timer_tick * delta as u64;
-                now_embassy - embassy_time::Duration::from_nanos(ns)
-            }
-            #[cfg(not(feature = "time"))]
-            fn calc_timestamp(_ns_per_timer_tick: u64, ts_val: u16) -> Timestamp {
-                ts_val
-            }
        }
diff --git a/embassy-stm32/src/can/frame.rs b/embassy-stm32/src/can/frame.rs
index d2d1f7aa6..0fbab053b 100644
--- a/embassy-stm32/src/can/frame.rs
+++ b/embassy-stm32/src/can/frame.rs
@@ -104,15 +104,13 @@ pub trait CanHeader: Sized {
 #[derive(Debug, Copy, Clone)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct ClassicData {
-    pub(crate) bytes: [u8; Self::MAX_DATA_LEN],
+    pub(crate) bytes: [u8; 8],
 }
 impl ClassicData {
-    pub(crate) const MAX_DATA_LEN: usize = 8;
    /// Creates a data payload from a raw byte slice.
    ///
-    /// Returns `None` if `data` is more than 64 bytes (which is the maximum) or
+    /// Returns `FrameCreateError` if `data` is more than 8 bytes (which is the maximum).
-    /// cannot be represented with an FDCAN DLC.
    pub fn new(data: &[u8]) -> Result<Self, FrameCreateError> {
        if data.len() > 8 {
            return Err(FrameCreateError::InvalidDataLength);
@@ -129,6 +127,11 @@ impl ClassicData {
        &self.bytes
    }
+    /// Raw mutable read access to data.
+    pub fn raw_mut(&mut self) -> &mut [u8] {
+        &mut self.bytes
+    }
    /// Checks if the length can be encoded in FDCAN DLC field.
    pub const fn is_valid_len(len: usize) -> bool {
        match len {
@@ -206,7 +209,17 @@ impl Frame {
    /// Get reference to data
    pub fn data(&self) -> &[u8] {
-        &self.data.raw()
+        &self.data.raw()[..self.can_header.len as usize]
+    }
+    /// Get reference to underlying 8-byte raw data buffer, some bytes on the tail might be undefined.
+    pub fn raw_data(&self) -> &[u8] {
+        self.data.raw()
+    }
+    /// Get mutable reference to data
+    pub fn data_mut(&mut self) -> &mut [u8] {
+        &mut self.data.raw_mut()[..self.can_header.len as usize]
    }
    /// Get priority of frame
@@ -250,7 +263,7 @@ impl embedded_can::Frame for Frame {
        self.can_header.len as usize
    }
    fn data(&self) -> &[u8] {
-        &self.data.raw()
+        &self.data()
    }
 }
@@ -314,6 +327,11 @@ impl FdData {
        &self.bytes
    }
+    /// Raw mutable read access to data.
+    pub fn raw_mut(&mut self) -> &mut [u8] {
+        &mut self.bytes
+    }
    /// Checks if the length can be encoded in FDCAN DLC field.
    pub const fn is_valid_len(len: usize) -> bool {
        match len {
@@ -390,7 +408,12 @@ impl FdFrame {
    /// Get reference to data
    pub fn data(&self) -> &[u8] {
-        &self.data.raw()
+        &self.data.raw()[..self.can_header.len as usize]
+    }
+    /// Get mutable reference to data
+    pub fn data_mut(&mut self) -> &mut [u8] {
+        &mut self.data.raw_mut()[..self.can_header.len as usize]
    }
 }
@@ -428,7 +451,7 @@ impl embedded_can::Frame for FdFrame {
        self.can_header.len as usize
    }
    fn data(&self) -> &[u8] {
-        &self.data.raw()
+        &self.data()
    }
 }
diff --git a/embassy-stm32/src/cordic/mod.rs b/embassy-stm32/src/cordic/mod.rs
index fb342d2e7..320774857 100644
--- a/embassy-stm32/src/cordic/mod.rs
+++ b/embassy-stm32/src/cordic/mod.rs
@@ -1,7 +1,7 @@
 //! coordinate rotation digital computer (CORDIC)
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 use crate::pac::cordic::vals;
 use crate::{dma, peripherals, rcc};
@@ -16,7 +16,7 @@ pub mod utils;
 /// CORDIC driver
 pub struct Cordic<'d, T: Instance> {
-    peri: PeripheralRef<'d, T>,
+    peri: Peri<'d, T>,
    config: Config,
 }
@@ -137,7 +137,7 @@ trait SealedInstance {
 /// CORDIC instance trait
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral {}
 /// CORDIC configuration
 #[derive(Debug)]
@@ -198,11 +198,9 @@ impl<'d, T: Instance> Cordic<'d, T> {
    /// Note:  
    /// If you need a peripheral -> CORDIC -> peripheral mode,  
    /// you may want to set Cordic into [Mode::ZeroOverhead] mode, and add extra arguments with [Self::extra_config]
-    pub fn new(peri: impl Peripheral<P = T> + 'd, config: Config) -> Self {
+    pub fn new(peri: Peri<'d, T>, config: Config) -> Self {
        rcc::enable_and_reset::<T>();
-        into_ref!(peri);
        let mut instance = Self { peri, config };
        instance.reconfigure();
@@ -378,8 +376,8 @@ impl<'d, T: Instance> Cordic<'d, T> {
    /// If you want to make sure ARG2 is set to +1, consider run [.reconfigure()](Self::reconfigure).
    pub async fn async_calc_32bit(
        &mut self,
-        write_dma: impl Peripheral<P = impl WriteDma<T>>,
+        mut write_dma: Peri<'_, impl WriteDma<T>>,
-        read_dma: impl Peripheral<P = impl ReadDma<T>>,
+        mut read_dma: Peri<'_, impl ReadDma<T>>,
        arg: &[u32],
        res: &mut [u32],
        arg1_only: bool,
@@ -393,8 +391,6 @@ impl<'d, T: Instance> Cordic<'d, T> {
        let active_res_buf = &mut res[..res_cnt];
-        into_ref!(write_dma, read_dma);
        self.peri
            .set_argument_count(if arg1_only { AccessCount::One } else { AccessCount::Two });
@@ -416,7 +412,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
        unsafe {
            let write_transfer = dma::Transfer::new_write(
-                &mut write_dma,
+                write_dma.reborrow(),
                write_req,
                arg,
                T::regs().wdata().as_ptr() as *mut _,
@@ -424,7 +420,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
            );
            let read_transfer = dma::Transfer::new_read(
-                &mut read_dma,
+                read_dma.reborrow(),
                read_req,
                T::regs().rdata().as_ptr() as *mut _,
                active_res_buf,
@@ -519,8 +515,8 @@ impl<'d, T: Instance> Cordic<'d, T> {
    /// User will take respond to merge two u16 arguments into one u32 data, and/or split one u32 data into two u16 results.
    pub async fn async_calc_16bit(
        &mut self,
-        write_dma: impl Peripheral<P = impl WriteDma<T>>,
+        mut write_dma: Peri<'_, impl WriteDma<T>>,
-        read_dma: impl Peripheral<P = impl ReadDma<T>>,
+        mut read_dma: Peri<'_, impl ReadDma<T>>,
        arg: &[u32],
        res: &mut [u32],
    ) -> Result<usize, CordicError> {
@@ -536,8 +532,6 @@ impl<'d, T: Instance> Cordic<'d, T> {
        let active_res_buf = &mut res[..res_cnt];
-        into_ref!(write_dma, read_dma);
        // In q1.15 mode, 1 write/read to access 2 arguments/results
        self.peri.set_argument_count(AccessCount::One);
        self.peri.set_result_count(AccessCount::One);
@@ -557,7 +551,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
        unsafe {
            let write_transfer = dma::Transfer::new_write(
-                &mut write_dma,
+                write_dma.reborrow(),
                write_req,
                arg,
                T::regs().wdata().as_ptr() as *mut _,
@@ -565,7 +559,7 @@ impl<'d, T: Instance> Cordic<'d, T> {
            );
            let read_transfer = dma::Transfer::new_read(
-                &mut read_dma,
+                read_dma.reborrow(),
                read_req,
                T::regs().rdata().as_ptr() as *mut _,
                active_res_buf,
diff --git a/embassy-stm32/src/crc/v1.rs b/embassy-stm32/src/crc/v1.rs
index f3d13de7c..13e5263de 100644
--- a/embassy-stm32/src/crc/v1.rs
+++ b/embassy-stm32/src/crc/v1.rs
@@ -1,23 +1,18 @@
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 /// CRC driver.
 pub struct Crc<'d> {
-    _peri: PeripheralRef<'d, CRC>,
+    _peri: Peri<'d, CRC>,
 }
 impl<'d> Crc<'d> {
    /// Instantiates the CRC32 peripheral and initializes it to default values.
-    pub fn new(peripheral: impl Peripheral<P = CRC> + 'd) -> Self {
+    pub fn new(peripheral: Peri<'d, CRC>) -> Self {
-        into_ref!(peripheral);
        // Note: enable and reset come from RccPeripheral.
        // enable CRC clock in RCC.
        rcc::enable_and_reset::<CRC>();
-        // Peripheral the peripheral
        let mut instance = Self { _peri: peripheral };
        instance.reset();
        instance
@@ -28,22 +23,16 @@ impl<'d> Crc<'d> {
        PAC_CRC.cr().write(|w| w.set_reset(true));
    }
-    /// Feeds a word to the peripheral and returns the current CRC value
+    /// Feeds a word into the CRC peripheral. Returns the computed CRC.
    pub fn feed_word(&mut self, word: u32) -> u32 {
        // write a single byte to the device, and return the result
-        #[cfg(not(crc_v1))]
-        PAC_CRC.dr32().write_value(word);
-        #[cfg(crc_v1)]
        PAC_CRC.dr().write_value(word);
        self.read()
    }
-    /// Feed a slice of words to the peripheral and return the result.
+    /// Feeds a slice of words into the CRC peripheral. Returns the computed CRC.
    pub fn feed_words(&mut self, words: &[u32]) -> u32 {
        for word in words {
-            #[cfg(not(crc_v1))]
-            PAC_CRC.dr32().write_value(*word);
-            #[cfg(crc_v1)]
            PAC_CRC.dr().write_value(*word);
        }
@@ -51,12 +40,6 @@ impl<'d> Crc<'d> {
    }
    /// Read the CRC result value.
-    #[cfg(not(crc_v1))]
-    pub fn read(&self) -> u32 {
-        PAC_CRC.dr32().read()
-    }
-    /// Read the CRC result value.
-    #[cfg(crc_v1)]
    pub fn read(&self) -> u32 {
        PAC_CRC.dr().read()
    }
diff --git a/embassy-stm32/src/crc/v2v3.rs b/embassy-stm32/src/crc/v2v3.rs
index 09d956d7c..d834d0971 100644
--- a/embassy-stm32/src/crc/v2v3.rs
+++ b/embassy-stm32/src/crc/v2v3.rs
@@ -1,17 +1,15 @@
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use crate::pac::crc::vals;
 use crate::pac::CRC as PAC_CRC;
 use crate::peripherals::CRC;
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 /// CRC driver.
 pub struct Crc<'d> {
-    _peripheral: PeripheralRef<'d, CRC>,
+    _peripheral: Peri<'d, CRC>,
    _config: Config,
 }
-/// CRC configuration errlr
+/// CRC configuration error
 #[derive(Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum ConfigError {
@@ -36,9 +34,9 @@ pub enum InputReverseConfig {
    None,
    /// Reverse bytes
    Byte,
-    /// Reverse 16-bit halfwords.
+    /// Reverse 16-bit halfwords
    Halfword,
-    /// Reverse 32-bit words.
+    /// Reverse 32-bit words
    Word,
 }
@@ -80,11 +78,10 @@ pub enum PolySize {
 impl<'d> Crc<'d> {
    /// Instantiates the CRC32 peripheral and initializes it to default values.
-    pub fn new(peripheral: impl Peripheral<P = CRC> + 'd, config: Config) -> Self {
+    pub fn new(peripheral: Peri<'d, CRC>, config: Config) -> Self {
        // Note: enable and reset come from RccPeripheral.
        // reset to default values and enable CRC clock in RCC.
        rcc::enable_and_reset::<CRC>();
-        into_ref!(peripheral);
        let mut instance = Self {
            _peripheral: peripheral,
            _config: config,
@@ -118,7 +115,7 @@ impl<'d> Crc<'d> {
            w.set_rev_in(match self._config.reverse_in {
                InputReverseConfig::None => vals::RevIn::NORMAL,
                InputReverseConfig::Byte => vals::RevIn::BYTE,
-                InputReverseConfig::Halfword => vals::RevIn::HALFWORD,
+                InputReverseConfig::Halfword => vals::RevIn::HALF_WORD,
                InputReverseConfig::Word => vals::RevIn::WORD,
            });
            // configure the polynomial.
@@ -130,45 +127,52 @@ impl<'d> Crc<'d> {
                PolySize::Width32 => vals::Polysize::POLYSIZE32,
            });
        });
+    }
-        self.reset();
+    /// Read the CRC result value.
+    pub fn read(&self) -> u32 {
+        PAC_CRC.dr32().read()
    }
-    /// Feeds a byte into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a byte into the CRC peripheral. Returns the computed CRC.
    pub fn feed_byte(&mut self, byte: u8) -> u32 {
        PAC_CRC.dr8().write_value(byte);
-        PAC_CRC.dr32().read()
+        self.read()
    }
-    /// Feeds an slice of bytes into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a slice of bytes into the CRC peripheral. Returns the computed CRC.
    pub fn feed_bytes(&mut self, bytes: &[u8]) -> u32 {
        for byte in bytes {
            PAC_CRC.dr8().write_value(*byte);
        }
-        PAC_CRC.dr32().read()
+        self.read()
    }
-    /// Feeds a halfword into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a halfword into the CRC peripheral. Returns the computed CRC.
    pub fn feed_halfword(&mut self, halfword: u16) -> u32 {
        PAC_CRC.dr16().write_value(halfword);
-        PAC_CRC.dr32().read()
+        self.read()
    }
-    /// Feeds an slice of halfwords into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a slice of halfwords into the CRC peripheral. Returns the computed CRC.
    pub fn feed_halfwords(&mut self, halfwords: &[u16]) -> u32 {
        for halfword in halfwords {
            PAC_CRC.dr16().write_value(*halfword);
        }
-        PAC_CRC.dr32().read()
+        self.read()
    }
-    /// Feeds a words into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a word into the CRC peripheral. Returns the computed CRC.
    pub fn feed_word(&mut self, word: u32) -> u32 {
        PAC_CRC.dr32().write_value(word as u32);
-        PAC_CRC.dr32().read()
+        self.read()
    }
-    /// Feeds an slice of words into the CRC peripheral. Returns the computed checksum.
+    /// Feeds a slice of words into the CRC peripheral. Returns the computed CRC.
    pub fn feed_words(&mut self, words: &[u32]) -> u32 {
        for word in words {
            PAC_CRC.dr32().write_value(*word as u32);
        }
-        PAC_CRC.dr32().read()
+        self.read()
    }
 }
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 8d600c73c..fba3c0fd7 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -4,12 +4,13 @@ use core::cmp::min;
 use core::marker::PhantomData;
 use core::ptr;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
-use crate::dma::{NoDma, Transfer, TransferOptions};
+use crate::dma::{ChannelAndRequest, TransferOptions};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::mode::{Async, Blocking, Mode};
+use crate::{interrupt, pac, peripherals, rcc};
 const DES_BLOCK_SIZE: usize = 8; // 64 bits
 const AES_BLOCK_SIZE: usize = 16; // 128 bits
@@ -57,15 +58,10 @@ pub trait Cipher<'c> {
    fn prepare_key(&self, _p: pac::cryp::Cryp) {}
    /// Performs any cipher-specific initialization.
-    fn init_phase_blocking<T: Instance, DmaIn, DmaOut>(&self, _p: pac::cryp::Cryp, _cryp: &Cryp<T, DmaIn, DmaOut>) {}
+    fn init_phase_blocking<T: Instance, M: Mode>(&self, _p: pac::cryp::Cryp, _cryp: &Cryp<T, M>) {}
    /// Performs any cipher-specific initialization.
-    async fn init_phase<T: Instance, DmaIn, DmaOut>(&self, _p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, DmaIn, DmaOut>)
+    async fn init_phase<T: Instance>(&self, _p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, Async>) {}
-    where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
-    }
    /// Called prior to processing the last data block for cipher-specific operations.
    fn pre_final(&self, _p: pac::cryp::Cryp, _dir: Direction, _padding_len: usize) -> [u32; 4] {
@@ -73,10 +69,10 @@ pub trait Cipher<'c> {
    }
    /// Called after processing the last data block for cipher-specific operations.
-    fn post_final_blocking<T: Instance, DmaIn, DmaOut>(
+    fn post_final_blocking<T: Instance, M: Mode>(
        &self,
        _p: pac::cryp::Cryp,
-        _cryp: &Cryp<T, DmaIn, DmaOut>,
+        _cryp: &Cryp<T, M>,
        _dir: Direction,
        _int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
@@ -85,18 +81,15 @@ pub trait Cipher<'c> {
    }
    /// Called after processing the last data block for cipher-specific operations.
-    async fn post_final<T: Instance, DmaIn, DmaOut>(
+    async fn post_final<T: Instance>(
        &self,
        _p: pac::cryp::Cryp,
-        _cryp: &mut Cryp<'_, T, DmaIn, DmaOut>,
+        _cryp: &mut Cryp<'_, T, Async>,
        _dir: Direction,
        _int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
        _padding_mask: [u8; 16],
-    ) where
+    ) {
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
    }
    /// Returns the AAD header block as required by the cipher.
@@ -474,13 +467,13 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
        p.cr().modify(|w| w.set_algomode3(true));
    }
-    fn init_phase_blocking<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, _cryp: &Cryp<T, DmaIn, DmaOut>) {
+    fn init_phase_blocking<T: Instance, M: Mode>(&self, p: pac::cryp::Cryp, _cryp: &Cryp<T, M>) {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
        p.cr().modify(|w| w.set_crypen(true));
        while p.cr().read().crypen() {}
    }
-    async fn init_phase<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, DmaIn, DmaOut>) {
+    async fn init_phase<T: Instance>(&self, p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, Async>) {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
        p.cr().modify(|w| w.set_crypen(true));
        while p.cr().read().crypen() {}
@@ -508,10 +501,10 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
    }
    #[cfg(cryp_v2)]
-    fn post_final_blocking<T: Instance, DmaIn, DmaOut>(
+    fn post_final_blocking<T: Instance, M: Mode>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &Cryp<T, DmaIn, DmaOut>,
+        cryp: &Cryp<T, M>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
@@ -534,18 +527,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
    }
    #[cfg(cryp_v2)]
-    async fn post_final<T: Instance, DmaIn, DmaOut>(
+    async fn post_final<T: Instance>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &mut Cryp<'_, T, DmaIn, DmaOut>,
+        cryp: &mut Cryp<'_, T, Async>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
        padding_mask: [u8; AES_BLOCK_SIZE],
-    ) where
+    ) {
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
        if dir == Direction::Encrypt {
            // Handle special GCM partial block process.
            p.cr().modify(|w| w.set_crypen(false));
@@ -559,8 +549,8 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
            let mut out_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
-            let read = Cryp::<T, DmaIn, DmaOut>::read_bytes(&mut cryp.outdma, Self::BLOCK_SIZE, &mut out_data);
+            let read = Cryp::<T, Async>::read_bytes(cryp.outdma.as_mut().unwrap(), Self::BLOCK_SIZE, &mut out_data);
-            let write = Cryp::<T, DmaIn, DmaOut>::write_bytes(&mut cryp.indma, Self::BLOCK_SIZE, int_data);
+            let write = Cryp::<T, Async>::write_bytes(cryp.indma.as_mut().unwrap(), Self::BLOCK_SIZE, int_data);
            embassy_futures::join::join(read, write).await;
@@ -615,13 +605,13 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
        p.cr().modify(|w| w.set_algomode3(true));
    }
-    fn init_phase_blocking<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, _cryp: &Cryp<T, DmaIn, DmaOut>) {
+    fn init_phase_blocking<T: Instance, M: Mode>(&self, p: pac::cryp::Cryp, _cryp: &Cryp<T, M>) {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
        p.cr().modify(|w| w.set_crypen(true));
        while p.cr().read().crypen() {}
    }
-    async fn init_phase<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, DmaIn, DmaOut>) {
+    async fn init_phase<T: Instance>(&self, p: pac::cryp::Cryp, _cryp: &mut Cryp<'_, T, Async>) {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
        p.cr().modify(|w| w.set_crypen(true));
        while p.cr().read().crypen() {}
@@ -649,10 +639,10 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
    }
    #[cfg(cryp_v2)]
-    fn post_final_blocking<T: Instance, DmaIn, DmaOut>(
+    fn post_final_blocking<T: Instance, M: Mode>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &Cryp<T, DmaIn, DmaOut>,
+        cryp: &Cryp<T, M>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
@@ -675,18 +665,15 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
    }
    #[cfg(cryp_v2)]
-    async fn post_final<T: Instance, DmaIn, DmaOut>(
+    async fn post_final<T: Instance>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &mut Cryp<'_, T, DmaIn, DmaOut>,
+        cryp: &mut Cryp<'_, T, Async>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        _temp1: [u32; 4],
        padding_mask: [u8; AES_BLOCK_SIZE],
-    ) where
+    ) {
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
        if dir == Direction::Encrypt {
            // Handle special GCM partial block process.
            p.cr().modify(|w| w.set_crypen(false));
@@ -700,8 +687,8 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
            let mut out_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
-            let read = Cryp::<T, DmaIn, DmaOut>::read_bytes(&mut cryp.outdma, Self::BLOCK_SIZE, &mut out_data);
+            let read = Cryp::<T, Async>::read_bytes(cryp.outdma.as_mut().unwrap(), Self::BLOCK_SIZE, &mut out_data);
-            let write = Cryp::<T, DmaIn, DmaOut>::write_bytes(&mut cryp.indma, Self::BLOCK_SIZE, int_data);
+            let write = Cryp::<T, Async>::write_bytes(cryp.indma.as_mut().unwrap(), Self::BLOCK_SIZE, int_data);
            embassy_futures::join::join(read, write).await;
        }
@@ -812,7 +799,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
        p.cr().modify(|w| w.set_algomode3(true));
    }
-    fn init_phase_blocking<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, cryp: &Cryp<T, DmaIn, DmaOut>) {
+    fn init_phase_blocking<T: Instance, M: Mode>(&self, p: pac::cryp::Cryp, cryp: &Cryp<T, M>) {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
        cryp.write_bytes_blocking(Self::BLOCK_SIZE, &self.block0);
@@ -821,14 +808,10 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
        while p.cr().read().crypen() {}
    }
-    async fn init_phase<T: Instance, DmaIn, DmaOut>(&self, p: pac::cryp::Cryp, cryp: &mut Cryp<'_, T, DmaIn, DmaOut>)
+    async fn init_phase<T: Instance>(&self, p: pac::cryp::Cryp, cryp: &mut Cryp<'_, T, Async>) {
-    where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
        p.cr().modify(|w| w.set_gcm_ccmph(0));
-        Cryp::<T, DmaIn, DmaOut>::write_bytes(&mut cryp.indma, Self::BLOCK_SIZE, &self.block0).await;
+        Cryp::<T, Async>::write_bytes(cryp.indma.as_mut().unwrap(), Self::BLOCK_SIZE, &self.block0).await;
        p.cr().modify(|w| w.set_crypen(true));
        while p.cr().read().crypen() {}
@@ -865,10 +848,10 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
    }
    #[cfg(cryp_v2)]
-    fn post_final_blocking<T: Instance, DmaIn, DmaOut>(
+    fn post_final_blocking<T: Instance, M: Mode>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &Cryp<T, DmaIn, DmaOut>,
+        cryp: &Cryp<T, M>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        temp1: [u32; 4],
@@ -902,18 +885,15 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
    }
    #[cfg(cryp_v2)]
-    async fn post_final<T: Instance, DmaIn, DmaOut>(
+    async fn post_final<T: Instance>(
        &self,
        p: pac::cryp::Cryp,
-        cryp: &mut Cryp<'_, T, DmaIn, DmaOut>,
+        cryp: &mut Cryp<'_, T, Async>,
        dir: Direction,
        int_data: &mut [u8; AES_BLOCK_SIZE],
        temp1: [u32; 4],
        padding_mask: [u8; 16],
-    ) where
+    ) {
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
        if dir == Direction::Decrypt {
            //Handle special CCM partial block process.
            let mut temp2 = [0; 4];
@@ -937,7 +917,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
                in_data[i] = int_word;
                in_data[i] = in_data[i] ^ temp1[i] ^ temp2[i];
            }
-            Cryp::<T, DmaIn, DmaOut>::write_words(&mut cryp.indma, Self::BLOCK_SIZE, &in_data).await;
+            Cryp::<T, Async>::write_words(cryp.indma.as_mut().unwrap(), Self::BLOCK_SIZE, &in_data).await;
        }
    }
 }
@@ -1007,26 +987,25 @@ pub enum Direction {
 }
 /// Crypto Accelerator Driver
-pub struct Cryp<'d, T: Instance, DmaIn = NoDma, DmaOut = NoDma> {
+pub struct Cryp<'d, T: Instance, M: Mode> {
-    _peripheral: PeripheralRef<'d, T>,
+    _peripheral: Peri<'d, T>,
-    indma: PeripheralRef<'d, DmaIn>,
+    _phantom: PhantomData<M>,
-    outdma: PeripheralRef<'d, DmaOut>,
+    indma: Option<ChannelAndRequest<'d>>,
+    outdma: Option<ChannelAndRequest<'d>>,
 }
-impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
+impl<'d, T: Instance> Cryp<'d, T, Blocking> {
-    /// Create a new CRYP driver.
+    /// Create a new CRYP driver in blocking mode.
-    pub fn new(
+    pub fn new_blocking(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        indma: impl Peripheral<P = DmaIn> + 'd,
-        outdma: impl Peripheral<P = DmaOut> + 'd,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
        rcc::enable_and_reset::<T>();
-        into_ref!(peri, indma, outdma);
        let instance = Self {
            _peripheral: peri,
-            indma: indma,
+            _phantom: PhantomData,
-            outdma: outdma,
+            indma: None,
+            outdma: None,
        };
        T::Interrupt::unpend();
@@ -1034,7 +1013,9 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        instance
    }
+}
+impl<'d, T: Instance, M: Mode> Cryp<'d, T, M> {
    /// Start a new encrypt or decrypt operation for the given cipher.
    pub fn start_blocking<'c, C: Cipher<'c> + CipherSized + IVSized>(
        &self,
@@ -1114,89 +1095,6 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        ctx
    }
-    /// Start a new encrypt or decrypt operation for the given cipher.
-    pub async fn start<'c, C: Cipher<'c> + CipherSized + IVSized>(
-        &mut self,
-        cipher: &'c C,
-        dir: Direction,
-    ) -> Context<'c, C>
-    where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
-        let mut ctx: Context<'c, C> = Context {
-            dir,
-            last_block_processed: false,
-            cr: 0,
-            iv: [0; 4],
-            csgcmccm: [0; 8],
-            csgcm: [0; 8],
-            aad_complete: false,
-            header_len: 0,
-            payload_len: 0,
-            cipher: cipher,
-            phantom_data: PhantomData,
-            header_processed: false,
-            aad_buffer: [0; 16],
-            aad_buffer_len: 0,
-        };
-        T::regs().cr().modify(|w| w.set_crypen(false));
-        let key = ctx.cipher.key();
-        if key.len() == (128 / 8) {
-            T::regs().cr().modify(|w| w.set_keysize(0));
-        } else if key.len() == (192 / 8) {
-            T::regs().cr().modify(|w| w.set_keysize(1));
-        } else if key.len() == (256 / 8) {
-            T::regs().cr().modify(|w| w.set_keysize(2));
-        }
-        self.load_key(key);
-        // Set data type to 8-bit. This will match software implementations.
-        T::regs().cr().modify(|w| w.set_datatype(2));
-        ctx.cipher.prepare_key(T::regs());
-        ctx.cipher.set_algomode(T::regs());
-        // Set encrypt/decrypt
-        if dir == Direction::Encrypt {
-            T::regs().cr().modify(|w| w.set_algodir(false));
-        } else {
-            T::regs().cr().modify(|w| w.set_algodir(true));
-        }
-        // Load the IV into the registers.
-        let iv = ctx.cipher.iv();
-        let mut full_iv: [u8; 16] = [0; 16];
-        full_iv[0..iv.len()].copy_from_slice(iv);
-        let mut iv_idx = 0;
-        let mut iv_word: [u8; 4] = [0; 4];
-        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
-        iv_idx += 4;
-        T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
-        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
-        iv_idx += 4;
-        T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
-        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
-        iv_idx += 4;
-        T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
-        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
-        T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
-        // Flush in/out FIFOs
-        T::regs().cr().modify(|w| w.fflush());
-        ctx.cipher.init_phase(T::regs(), self).await;
-        self.store_context(&mut ctx);
-        ctx
-    }
    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
    /// Controls the header phase of cipher processing.
    /// This function is only valid for authenticated ciphers including GCM, CCM, and GMAC.
@@ -1294,101 +1192,6 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        self.store_context(ctx);
    }
-    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-    /// Controls the header phase of cipher processing.
-    /// This function is only valid for authenticated ciphers including GCM, CCM, and GMAC.
-    /// All additional associated data (AAD) must be supplied to this function prior to starting the payload phase with `payload`.
-    /// The AAD must be supplied in multiples of the block size (128-bits for AES, 64-bits for DES), except when supplying the last block.
-    /// When supplying the last block of AAD, `last_aad_block` must be `true`.
-    pub async fn aad<'c, const TAG_SIZE: usize, C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>>(
-        &mut self,
-        ctx: &mut Context<'c, C>,
-        aad: &[u8],
-        last_aad_block: bool,
-    ) where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
-        self.load_context(ctx);
-        // Perform checks for correctness.
-        if ctx.aad_complete {
-            panic!("Cannot update AAD after starting payload!")
-        }
-        ctx.header_len += aad.len() as u64;
-        // Header phase
-        T::regs().cr().modify(|w| w.set_crypen(false));
-        T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
-        T::regs().cr().modify(|w| w.set_crypen(true));
-        // First write the header B1 block if not yet written.
-        if !ctx.header_processed {
-            ctx.header_processed = true;
-            let header = ctx.cipher.get_header_block();
-            ctx.aad_buffer[0..header.len()].copy_from_slice(header);
-            ctx.aad_buffer_len += header.len();
-        }
-        // Fill the header block to make a full block.
-        let len_to_copy = min(aad.len(), C::BLOCK_SIZE - ctx.aad_buffer_len);
-        ctx.aad_buffer[ctx.aad_buffer_len..ctx.aad_buffer_len + len_to_copy].copy_from_slice(&aad[..len_to_copy]);
-        ctx.aad_buffer_len += len_to_copy;
-        ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
-        let mut aad_len_remaining = aad.len() - len_to_copy;
-        if ctx.aad_buffer_len < C::BLOCK_SIZE {
-            // The buffer isn't full and this is the last buffer, so process it as is (already padded).
-            if last_aad_block {
-                Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &ctx.aad_buffer).await;
-                assert_eq!(T::regs().sr().read().ifem(), true);
-                // Switch to payload phase.
-                ctx.aad_complete = true;
-                T::regs().cr().modify(|w| w.set_crypen(false));
-                T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
-                T::regs().cr().modify(|w| w.fflush());
-            } else {
-                // Just return because we don't yet have a full block to process.
-                return;
-            }
-        } else {
-            // Load the full block from the buffer.
-            Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &ctx.aad_buffer).await;
-            assert_eq!(T::regs().sr().read().ifem(), true);
-        }
-        // Handle a partial block that is passed in.
-        ctx.aad_buffer_len = 0;
-        let leftovers = aad_len_remaining % C::BLOCK_SIZE;
-        ctx.aad_buffer[..leftovers].copy_from_slice(&aad[aad.len() - leftovers..aad.len()]);
-        ctx.aad_buffer_len += leftovers;
-        ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
-        aad_len_remaining -= leftovers;
-        assert_eq!(aad_len_remaining % C::BLOCK_SIZE, 0);
-        // Load full data blocks into core.
-        let num_full_blocks = aad_len_remaining / C::BLOCK_SIZE;
-        let start_index = len_to_copy;
-        let end_index = start_index + (C::BLOCK_SIZE * num_full_blocks);
-        Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &aad[start_index..end_index]).await;
-        if last_aad_block {
-            if leftovers > 0 {
-                Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &ctx.aad_buffer).await;
-                assert_eq!(T::regs().sr().read().ifem(), true);
-            }
-            // Switch to payload phase.
-            ctx.aad_complete = true;
-            T::regs().cr().modify(|w| w.set_crypen(false));
-            T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
-            T::regs().cr().modify(|w| w.fflush());
-        }
-        self.store_context(ctx);
-    }
    /// Performs encryption/decryption on the provided context.
    /// The context determines algorithm, mode, and state of the crypto accelerator.
    /// When the last piece of data is supplied, `last_block` should be `true`.
@@ -1478,105 +1281,6 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        self.store_context(ctx);
    }
-    /// Performs encryption/decryption on the provided context.
-    /// The context determines algorithm, mode, and state of the crypto accelerator.
-    /// When the last piece of data is supplied, `last_block` should be `true`.
-    /// This function panics under various mismatches of parameters.
-    /// Output buffer must be at least as long as the input buffer.
-    /// Data must be a multiple of block size (128-bits for AES, 64-bits for DES) for CBC and ECB modes.
-    /// Padding or ciphertext stealing must be managed by the application for these modes.
-    /// Data must also be a multiple of block size unless `last_block` is `true`.
-    pub async fn payload<'c, C: Cipher<'c> + CipherSized + IVSized>(
-        &mut self,
-        ctx: &mut Context<'c, C>,
-        input: &[u8],
-        output: &mut [u8],
-        last_block: bool,
-    ) where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
-        self.load_context(ctx);
-        let last_block_remainder = input.len() % C::BLOCK_SIZE;
-        // Perform checks for correctness.
-        if !ctx.aad_complete && ctx.header_len > 0 {
-            panic!("Additional associated data must be processed first!");
-        } else if !ctx.aad_complete {
-            #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-            {
-                ctx.aad_complete = true;
-                T::regs().cr().modify(|w| w.set_crypen(false));
-                T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
-                T::regs().cr().modify(|w| w.fflush());
-                T::regs().cr().modify(|w| w.set_crypen(true));
-            }
-        }
-        if ctx.last_block_processed {
-            panic!("The last block has already been processed!");
-        }
-        if input.len() > output.len() {
-            panic!("Output buffer length must match input length.");
-        }
-        if !last_block {
-            if last_block_remainder != 0 {
-                panic!("Input length must be a multiple of {} bytes.", C::BLOCK_SIZE);
-            }
-        }
-        if C::REQUIRES_PADDING {
-            if last_block_remainder != 0 {
-                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
-            }
-        }
-        if last_block {
-            ctx.last_block_processed = true;
-        }
-        // Load data into core, block by block.
-        let num_full_blocks = input.len() / C::BLOCK_SIZE;
-        for block in 0..num_full_blocks {
-            let index = block * C::BLOCK_SIZE;
-            // Read block out
-            let read = Self::read_bytes(
-                &mut self.outdma,
-                C::BLOCK_SIZE,
-                &mut output[index..index + C::BLOCK_SIZE],
-            );
-            // Write block in
-            let write = Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &input[index..index + C::BLOCK_SIZE]);
-            embassy_futures::join::join(read, write).await;
-        }
-        // Handle the final block, which is incomplete.
-        if last_block_remainder > 0 {
-            let padding_len = C::BLOCK_SIZE - last_block_remainder;
-            let temp1 = ctx.cipher.pre_final(T::regs(), ctx.dir, padding_len);
-            let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
-            let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
-            last_block[..last_block_remainder].copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
-            let read = Self::read_bytes(&mut self.outdma, C::BLOCK_SIZE, &mut intermediate_data);
-            let write = Self::write_bytes(&mut self.indma, C::BLOCK_SIZE, &last_block);
-            embassy_futures::join::join(read, write).await;
-            // Handle the last block depending on mode.
-            let output_len = output.len();
-            output[output_len - last_block_remainder..output_len]
-                .copy_from_slice(&intermediate_data[0..last_block_remainder]);
-            let mut mask: [u8; 16] = [0; 16];
-            mask[..last_block_remainder].fill(0xFF);
-            ctx.cipher
-                .post_final(T::regs(), self, ctx.dir, &mut intermediate_data, temp1, mask)
-                .await;
-        }
-        ctx.payload_len += input.len() as u64;
-        self.store_context(ctx);
-    }
    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
    /// Generates an authentication tag for authenticated ciphers including GCM, CCM, and GMAC.
    /// Called after the all data has been encrypted/decrypted by `payload`.
@@ -1623,57 +1327,6 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        tag
    }
-    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-    // Generates an authentication tag for authenticated ciphers including GCM, CCM, and GMAC.
-    /// Called after the all data has been encrypted/decrypted by `payload`.
-    pub async fn finish<
-        'c,
-        const TAG_SIZE: usize,
-        C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>,
-    >(
-        &mut self,
-        mut ctx: Context<'c, C>,
-    ) -> [u8; TAG_SIZE]
-    where
-        DmaIn: crate::cryp::DmaIn<T>,
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
-        self.load_context(&mut ctx);
-        T::regs().cr().modify(|w| w.set_crypen(false));
-        T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
-        T::regs().cr().modify(|w| w.set_crypen(true));
-        let headerlen1: u32 = ((ctx.header_len * 8) >> 32) as u32;
-        let headerlen2: u32 = (ctx.header_len * 8) as u32;
-        let payloadlen1: u32 = ((ctx.payload_len * 8) >> 32) as u32;
-        let payloadlen2: u32 = (ctx.payload_len * 8) as u32;
-        #[cfg(cryp_v2)]
-        let footer: [u32; 4] = [
-            headerlen1.swap_bytes(),
-            headerlen2.swap_bytes(),
-            payloadlen1.swap_bytes(),
-            payloadlen2.swap_bytes(),
-        ];
-        #[cfg(any(cryp_v3, cryp_v4))]
-        let footer: [u32; 4] = [headerlen1, headerlen2, payloadlen1, payloadlen2];
-        let write = Self::write_words(&mut self.indma, C::BLOCK_SIZE, &footer);
-        let mut full_tag: [u8; 16] = [0; 16];
-        let read = Self::read_bytes(&mut self.outdma, C::BLOCK_SIZE, &mut full_tag);
-        embassy_futures::join::join(read, write).await;
-        let mut tag: [u8; TAG_SIZE] = [0; TAG_SIZE];
-        tag.copy_from_slice(&full_tag[0..TAG_SIZE]);
-        T::regs().cr().modify(|w| w.set_crypen(false));
-        tag
-    }
    fn load_key(&self, key: &[u8]) {
        // Load the key into the registers.
        let mut keyidx = 0;
@@ -1774,97 +1427,435 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
        }
    }
-    async fn write_bytes(dma: &mut PeripheralRef<'_, DmaIn>, block_size: usize, blocks: &[u8])
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-    where
+    fn write_words_blocking(&self, block_size: usize, blocks: &[u32]) {
-        DmaIn: crate::cryp::DmaIn<T>,
+        assert_eq!((blocks.len() * 4) % block_size, 0);
-    {
+        let mut byte_counter: usize = 0;
+        for word in blocks {
+            T::regs().din().write_value(*word);
+            byte_counter += 4;
+            if byte_counter % block_size == 0 {
+                // Block until input FIFO is empty.
+                while !T::regs().sr().read().ifem() {}
+            }
+        }
+    }
+    fn read_bytes_blocking(&self, block_size: usize, blocks: &mut [u8]) {
+        // Block until there is output to read.
+        while !T::regs().sr().read().ofne() {}
+        // Ensure input is a multiple of block size.
+        assert_eq!(blocks.len() % block_size, 0);
+        // Read block out
+        let mut index = 0;
+        let end_index = blocks.len();
+        while index < end_index {
+            let out_word: u32 = T::regs().dout().read();
+            blocks[index..index + 4].copy_from_slice(u32::to_ne_bytes(out_word).as_slice());
+            index += 4;
+        }
+    }
+}
+impl<'d, T: Instance> Cryp<'d, T, Async> {
+    /// Create a new CRYP driver.
+    pub fn new(
+        peri: Peri<'d, T>,
+        indma: Peri<'d, impl DmaIn<T>>,
+        outdma: Peri<'d, impl DmaOut<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+    ) -> Self {
+        rcc::enable_and_reset::<T>();
+        let instance = Self {
+            _peripheral: peri,
+            _phantom: PhantomData,
+            indma: new_dma!(indma),
+            outdma: new_dma!(outdma),
+        };
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+        instance
+    }
+    /// Start a new encrypt or decrypt operation for the given cipher.
+    pub async fn start<'c, C: Cipher<'c> + CipherSized + IVSized>(
+        &mut self,
+        cipher: &'c C,
+        dir: Direction,
+    ) -> Context<'c, C> {
+        let mut ctx: Context<'c, C> = Context {
+            dir,
+            last_block_processed: false,
+            cr: 0,
+            iv: [0; 4],
+            csgcmccm: [0; 8],
+            csgcm: [0; 8],
+            aad_complete: false,
+            header_len: 0,
+            payload_len: 0,
+            cipher: cipher,
+            phantom_data: PhantomData,
+            header_processed: false,
+            aad_buffer: [0; 16],
+            aad_buffer_len: 0,
+        };
+        T::regs().cr().modify(|w| w.set_crypen(false));
+        let key = ctx.cipher.key();
+        if key.len() == (128 / 8) {
+            T::regs().cr().modify(|w| w.set_keysize(0));
+        } else if key.len() == (192 / 8) {
+            T::regs().cr().modify(|w| w.set_keysize(1));
+        } else if key.len() == (256 / 8) {
+            T::regs().cr().modify(|w| w.set_keysize(2));
+        }
+        self.load_key(key);
+        // Set data type to 8-bit. This will match software implementations.
+        T::regs().cr().modify(|w| w.set_datatype(2));
+        ctx.cipher.prepare_key(T::regs());
+        ctx.cipher.set_algomode(T::regs());
+        // Set encrypt/decrypt
+        if dir == Direction::Encrypt {
+            T::regs().cr().modify(|w| w.set_algodir(false));
+        } else {
+            T::regs().cr().modify(|w| w.set_algodir(true));
+        }
+        // Load the IV into the registers.
+        let iv = ctx.cipher.iv();
+        let mut full_iv: [u8; 16] = [0; 16];
+        full_iv[0..iv.len()].copy_from_slice(iv);
+        let mut iv_idx = 0;
+        let mut iv_word: [u8; 4] = [0; 4];
+        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+        iv_idx += 4;
+        T::regs().init(0).ivlr().write_value(u32::from_be_bytes(iv_word));
+        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+        iv_idx += 4;
+        T::regs().init(0).ivrr().write_value(u32::from_be_bytes(iv_word));
+        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+        iv_idx += 4;
+        T::regs().init(1).ivlr().write_value(u32::from_be_bytes(iv_word));
+        iv_word.copy_from_slice(&full_iv[iv_idx..iv_idx + 4]);
+        T::regs().init(1).ivrr().write_value(u32::from_be_bytes(iv_word));
+        // Flush in/out FIFOs
+        T::regs().cr().modify(|w| w.fflush());
+        ctx.cipher.init_phase(T::regs(), self).await;
+        self.store_context(&mut ctx);
+        ctx
+    }
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
+    /// Controls the header phase of cipher processing.
+    /// This function is only valid for authenticated ciphers including GCM, CCM, and GMAC.
+    /// All additional associated data (AAD) must be supplied to this function prior to starting the payload phase with `payload`.
+    /// The AAD must be supplied in multiples of the block size (128-bits for AES, 64-bits for DES), except when supplying the last block.
+    /// When supplying the last block of AAD, `last_aad_block` must be `true`.
+    pub async fn aad<
+        'c,
+        const TAG_SIZE: usize,
+        C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>,
+    >(
+        &mut self,
+        ctx: &mut Context<'c, C>,
+        aad: &[u8],
+        last_aad_block: bool,
+    ) {
+        self.load_context(ctx);
+        // Perform checks for correctness.
+        if ctx.aad_complete {
+            panic!("Cannot update AAD after starting payload!")
+        }
+        ctx.header_len += aad.len() as u64;
+        // Header phase
+        T::regs().cr().modify(|w| w.set_crypen(false));
+        T::regs().cr().modify(|w| w.set_gcm_ccmph(1));
+        T::regs().cr().modify(|w| w.set_crypen(true));
+        // First write the header B1 block if not yet written.
+        if !ctx.header_processed {
+            ctx.header_processed = true;
+            let header = ctx.cipher.get_header_block();
+            ctx.aad_buffer[0..header.len()].copy_from_slice(header);
+            ctx.aad_buffer_len += header.len();
+        }
+        // Fill the header block to make a full block.
+        let len_to_copy = min(aad.len(), C::BLOCK_SIZE - ctx.aad_buffer_len);
+        ctx.aad_buffer[ctx.aad_buffer_len..ctx.aad_buffer_len + len_to_copy].copy_from_slice(&aad[..len_to_copy]);
+        ctx.aad_buffer_len += len_to_copy;
+        ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
+        let mut aad_len_remaining = aad.len() - len_to_copy;
+        if ctx.aad_buffer_len < C::BLOCK_SIZE {
+            // The buffer isn't full and this is the last buffer, so process it as is (already padded).
+            if last_aad_block {
+                Self::write_bytes(self.indma.as_mut().unwrap(), C::BLOCK_SIZE, &ctx.aad_buffer).await;
+                assert_eq!(T::regs().sr().read().ifem(), true);
+                // Switch to payload phase.
+                ctx.aad_complete = true;
+                T::regs().cr().modify(|w| w.set_crypen(false));
+                T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+                T::regs().cr().modify(|w| w.fflush());
+            } else {
+                // Just return because we don't yet have a full block to process.
+                return;
+            }
+        } else {
+            // Load the full block from the buffer.
+            Self::write_bytes(self.indma.as_mut().unwrap(), C::BLOCK_SIZE, &ctx.aad_buffer).await;
+            assert_eq!(T::regs().sr().read().ifem(), true);
+        }
+        // Handle a partial block that is passed in.
+        ctx.aad_buffer_len = 0;
+        let leftovers = aad_len_remaining % C::BLOCK_SIZE;
+        ctx.aad_buffer[..leftovers].copy_from_slice(&aad[aad.len() - leftovers..aad.len()]);
+        ctx.aad_buffer_len += leftovers;
+        ctx.aad_buffer[ctx.aad_buffer_len..].fill(0);
+        aad_len_remaining -= leftovers;
+        assert_eq!(aad_len_remaining % C::BLOCK_SIZE, 0);
+        // Load full data blocks into core.
+        let num_full_blocks = aad_len_remaining / C::BLOCK_SIZE;
+        let start_index = len_to_copy;
+        let end_index = start_index + (C::BLOCK_SIZE * num_full_blocks);
+        Self::write_bytes(
+            self.indma.as_mut().unwrap(),
+            C::BLOCK_SIZE,
+            &aad[start_index..end_index],
+        )
+        .await;
+        if last_aad_block {
+            if leftovers > 0 {
+                Self::write_bytes(self.indma.as_mut().unwrap(), C::BLOCK_SIZE, &ctx.aad_buffer).await;
+                assert_eq!(T::regs().sr().read().ifem(), true);
+            }
+            // Switch to payload phase.
+            ctx.aad_complete = true;
+            T::regs().cr().modify(|w| w.set_crypen(false));
+            T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+            T::regs().cr().modify(|w| w.fflush());
+        }
+        self.store_context(ctx);
+    }
+    /// Performs encryption/decryption on the provided context.
+    /// The context determines algorithm, mode, and state of the crypto accelerator.
+    /// When the last piece of data is supplied, `last_block` should be `true`.
+    /// This function panics under various mismatches of parameters.
+    /// Output buffer must be at least as long as the input buffer.
+    /// Data must be a multiple of block size (128-bits for AES, 64-bits for DES) for CBC and ECB modes.
+    /// Padding or ciphertext stealing must be managed by the application for these modes.
+    /// Data must also be a multiple of block size unless `last_block` is `true`.
+    pub async fn payload<'c, C: Cipher<'c> + CipherSized + IVSized>(
+        &mut self,
+        ctx: &mut Context<'c, C>,
+        input: &[u8],
+        output: &mut [u8],
+        last_block: bool,
+    ) {
+        self.load_context(ctx);
+        let last_block_remainder = input.len() % C::BLOCK_SIZE;
+        // Perform checks for correctness.
+        if !ctx.aad_complete && ctx.header_len > 0 {
+            panic!("Additional associated data must be processed first!");
+        } else if !ctx.aad_complete {
+            #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
+            {
+                ctx.aad_complete = true;
+                T::regs().cr().modify(|w| w.set_crypen(false));
+                T::regs().cr().modify(|w| w.set_gcm_ccmph(2));
+                T::regs().cr().modify(|w| w.fflush());
+                T::regs().cr().modify(|w| w.set_crypen(true));
+            }
+        }
+        if ctx.last_block_processed {
+            panic!("The last block has already been processed!");
+        }
+        if input.len() > output.len() {
+            panic!("Output buffer length must match input length.");
+        }
+        if !last_block {
+            if last_block_remainder != 0 {
+                panic!("Input length must be a multiple of {} bytes.", C::BLOCK_SIZE);
+            }
+        }
+        if C::REQUIRES_PADDING {
+            if last_block_remainder != 0 {
+                panic!("Input must be a multiple of {} bytes in ECB and CBC modes. Consider padding or ciphertext stealing.", C::BLOCK_SIZE);
+            }
+        }
+        if last_block {
+            ctx.last_block_processed = true;
+        }
+        // Load data into core, block by block.
+        let num_full_blocks = input.len() / C::BLOCK_SIZE;
+        for block in 0..num_full_blocks {
+            let index = block * C::BLOCK_SIZE;
+            // Read block out
+            let read = Self::read_bytes(
+                self.outdma.as_mut().unwrap(),
+                C::BLOCK_SIZE,
+                &mut output[index..index + C::BLOCK_SIZE],
+            );
+            // Write block in
+            let write = Self::write_bytes(
+                self.indma.as_mut().unwrap(),
+                C::BLOCK_SIZE,
+                &input[index..index + C::BLOCK_SIZE],
+            );
+            embassy_futures::join::join(read, write).await;
+        }
+        // Handle the final block, which is incomplete.
+        if last_block_remainder > 0 {
+            let padding_len = C::BLOCK_SIZE - last_block_remainder;
+            let temp1 = ctx.cipher.pre_final(T::regs(), ctx.dir, padding_len);
+            let mut intermediate_data: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
+            let mut last_block: [u8; AES_BLOCK_SIZE] = [0; AES_BLOCK_SIZE];
+            last_block[..last_block_remainder].copy_from_slice(&input[input.len() - last_block_remainder..input.len()]);
+            let read = Self::read_bytes(self.outdma.as_mut().unwrap(), C::BLOCK_SIZE, &mut intermediate_data);
+            let write = Self::write_bytes(self.indma.as_mut().unwrap(), C::BLOCK_SIZE, &last_block);
+            embassy_futures::join::join(read, write).await;
+            // Handle the last block depending on mode.
+            let output_len = output.len();
+            output[output_len - last_block_remainder..output_len]
+                .copy_from_slice(&intermediate_data[0..last_block_remainder]);
+            let mut mask: [u8; 16] = [0; 16];
+            mask[..last_block_remainder].fill(0xFF);
+            ctx.cipher
+                .post_final(T::regs(), self, ctx.dir, &mut intermediate_data, temp1, mask)
+                .await;
+        }
+        ctx.payload_len += input.len() as u64;
+        self.store_context(ctx);
+    }
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
+    // Generates an authentication tag for authenticated ciphers including GCM, CCM, and GMAC.
+    /// Called after the all data has been encrypted/decrypted by `payload`.
+    pub async fn finish<
+        'c,
+        const TAG_SIZE: usize,
+        C: Cipher<'c> + CipherSized + IVSized + CipherAuthenticated<TAG_SIZE>,
+    >(
+        &mut self,
+        mut ctx: Context<'c, C>,
+    ) -> [u8; TAG_SIZE] {
+        self.load_context(&mut ctx);
+        T::regs().cr().modify(|w| w.set_crypen(false));
+        T::regs().cr().modify(|w| w.set_gcm_ccmph(3));
+        T::regs().cr().modify(|w| w.set_crypen(true));
+        let headerlen1: u32 = ((ctx.header_len * 8) >> 32) as u32;
+        let headerlen2: u32 = (ctx.header_len * 8) as u32;
+        let payloadlen1: u32 = ((ctx.payload_len * 8) >> 32) as u32;
+        let payloadlen2: u32 = (ctx.payload_len * 8) as u32;
+        #[cfg(cryp_v2)]
+        let footer: [u32; 4] = [
+            headerlen1.swap_bytes(),
+            headerlen2.swap_bytes(),
+            payloadlen1.swap_bytes(),
+            payloadlen2.swap_bytes(),
+        ];
+        #[cfg(any(cryp_v3, cryp_v4))]
+        let footer: [u32; 4] = [headerlen1, headerlen2, payloadlen1, payloadlen2];
+        let write = Self::write_words(self.indma.as_mut().unwrap(), C::BLOCK_SIZE, &footer);
+        let mut full_tag: [u8; 16] = [0; 16];
+        let read = Self::read_bytes(self.outdma.as_mut().unwrap(), C::BLOCK_SIZE, &mut full_tag);
+        embassy_futures::join::join(read, write).await;
+        let mut tag: [u8; TAG_SIZE] = [0; TAG_SIZE];
+        tag.copy_from_slice(&full_tag[0..TAG_SIZE]);
+        T::regs().cr().modify(|w| w.set_crypen(false));
+        tag
+    }
+    async fn write_bytes(dma: &mut ChannelAndRequest<'d>, block_size: usize, blocks: &[u8]) {
        if blocks.len() == 0 {
            return;
        }
        // Ensure input is a multiple of block size.
        assert_eq!(blocks.len() % block_size, 0);
        // Configure DMA to transfer input to crypto core.
-        let dma_request = dma.request();
+        let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let dst_ptr = T::regs().din().as_ptr();
        let num_words = blocks.len() / 4;
-        let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
+        let src_ptr: *const [u8] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
        let options = TransferOptions {
            #[cfg(not(gpdma))]
            priority: crate::dma::Priority::High,
            ..Default::default()
        };
-        let dma_transfer = unsafe { Transfer::new_write_raw(dma, dma_request, src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
        T::regs().dmacr().modify(|w| w.set_dien(true));
        // Wait for the transfer to complete.
        dma_transfer.await;
    }
    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-    fn write_words_blocking(&self, block_size: usize, blocks: &[u32]) {
+    async fn write_words(dma: &mut ChannelAndRequest<'d>, block_size: usize, blocks: &[u32]) {
-        assert_eq!((blocks.len() * 4) % block_size, 0);
-        let mut byte_counter: usize = 0;
-        for word in blocks {
-            T::regs().din().write_value(*word);
-            byte_counter += 4;
-            if byte_counter % block_size == 0 {
-                // Block until input FIFO is empty.
-                while !T::regs().sr().read().ifem() {}
-            }
-        }
-    }
-    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
-    async fn write_words(dma: &mut PeripheralRef<'_, DmaIn>, block_size: usize, blocks: &[u32])
-    where
-        DmaIn: crate::cryp::DmaIn<T>,
-    {
        if blocks.len() == 0 {
            return;
        }
        // Ensure input is a multiple of block size.
        assert_eq!((blocks.len() * 4) % block_size, 0);
        // Configure DMA to transfer input to crypto core.
-        let dma_request = dma.request();
+        let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let dst_ptr = T::regs().din().as_ptr();
        let num_words = blocks.len();
-        let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
+        let src_ptr: *const [u32] = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
        let options = TransferOptions {
            #[cfg(not(gpdma))]
            priority: crate::dma::Priority::High,
            ..Default::default()
        };
-        let dma_transfer = unsafe { Transfer::new_write_raw(dma, dma_request, src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr, options) };
        T::regs().dmacr().modify(|w| w.set_dien(true));
        // Wait for the transfer to complete.
        dma_transfer.await;
    }
-    fn read_bytes_blocking(&self, block_size: usize, blocks: &mut [u8]) {
+    async fn read_bytes(dma: &mut ChannelAndRequest<'d>, block_size: usize, blocks: &mut [u8]) {
-        // Block until there is output to read.
-        while !T::regs().sr().read().ofne() {}
-        // Ensure input is a multiple of block size.
-        assert_eq!(blocks.len() % block_size, 0);
-        // Read block out
-        let mut index = 0;
-        let end_index = blocks.len();
-        while index < end_index {
-            let out_word: u32 = T::regs().dout().read();
-            blocks[index..index + 4].copy_from_slice(u32::to_ne_bytes(out_word).as_slice());
-            index += 4;
-        }
-    }
-    async fn read_bytes(dma: &mut PeripheralRef<'_, DmaOut>, block_size: usize, blocks: &mut [u8])
-    where
-        DmaOut: crate::cryp::DmaOut<T>,
-    {
        if blocks.len() == 0 {
            return;
        }
        // Ensure input is a multiple of block size.
        assert_eq!(blocks.len() % block_size, 0);
        // Configure DMA to get output from crypto core.
-        let dma_request = dma.request();
        let src_ptr = T::regs().dout().as_ptr();
        let num_words = blocks.len() / 4;
        let dst_ptr = ptr::slice_from_raw_parts_mut(blocks.as_mut_ptr().cast(), num_words);
@@ -1873,7 +1864,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
            priority: crate::dma::Priority::VeryHigh,
            ..Default::default()
        };
-        let dma_transfer = unsafe { Transfer::new_read_raw(dma, dma_request, src_ptr, dst_ptr, options) };
+        let dma_transfer = unsafe { dma.read_raw(src_ptr, dst_ptr, options) };
        T::regs().dmacr().modify(|w| w.set_doen(true));
        // Wait for the transfer to complete.
        dma_transfer.await;
@@ -1886,7 +1877,7 @@ trait SealedInstance {
 /// CRYP instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
    /// Interrupt for this CRYP instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/dac/mod.rs b/embassy-stm32/src/dac/mod.rs
index 8bba5ded0..30046849b 100644
--- a/embassy-stm32/src/dac/mod.rs
+++ b/embassy-stm32/src/dac/mod.rs
@@ -3,15 +3,15 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use crate::dma::ChannelAndRequest;
+use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::dma::NoDma;
 #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
 use crate::pac::dac;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 mod tsel;
+use embassy_hal_internal::PeripheralType;
 pub use tsel::TriggerSel;
 /// Operating mode for DAC channel
@@ -100,46 +100,34 @@ pub enum ValueArray<'a> {
 ///
 /// If you want to use both channels, either together or independently,
 /// create a [`Dac`] first and use it to access each channel.
-pub struct DacChannel<'d, T: Instance, const N: u8, DMA = NoDma> {
+pub struct DacChannel<'d, T: Instance, C: Channel, M: PeriMode> {
-    phantom: PhantomData<&'d mut T>,
+    phantom: PhantomData<&'d mut (T, C, M)>,
    #[allow(unused)]
-    dma: PeripheralRef<'d, DMA>,
+    dma: Option<ChannelAndRequest<'d>>,
 }
 /// DAC channel 1 type alias.
-pub type DacCh1<'d, T, DMA = NoDma> = DacChannel<'d, T, 1, DMA>;
+pub type DacCh1<'d, T, M> = DacChannel<'d, T, Ch1, M>;
 /// DAC channel 2 type alias.
-pub type DacCh2<'d, T, DMA = NoDma> = DacChannel<'d, T, 2, DMA>;
+pub type DacCh2<'d, T, M> = DacChannel<'d, T, Ch2, M>;
-impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
-    const IDX: usize = (N - 1) as usize;
+impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Async> {
    /// Create a new `DacChannel` instance, consuming the underlying DAC peripheral.
    ///
-    /// If you're not using DMA, pass [`dma::NoDma`] for the `dma` argument.
-    ///
    /// The channel is enabled on creation and begin to drive the output pin.
    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will
    /// disable the channel; you must re-enable it with `enable()`.
    ///
    /// By default, triggering is disabled, but it can be enabled using
    /// [`DacChannel::set_trigger()`].
-    pub fn new(
+    pub fn new(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
-        _peri: impl Peripheral<P = T> + 'd,
-        dma: impl Peripheral<P = DMA> + 'd,
-        pin: impl Peripheral<P = impl DacPin<T, N> + crate::gpio::Pin> + 'd,
-    ) -> Self {
-        into_ref!(dma, pin);
        pin.set_as_analog();
-        rcc::enable_and_reset::<T>();
+        Self::new_inner(
-        let mut dac = Self {
+            peri,
-            phantom: PhantomData,
+            new_dma!(dma),
-            dma,
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
-        };
+            Mode::NormalExternalBuffered,
-        #[cfg(any(dac_v5, dac_v6, dac_v7))]
+        )
-        dac.set_hfsel();
-        dac.enable();
-        dac
    }
    /// Create a new `DacChannel` instance where the external output pin is not used,
@@ -150,13 +138,97 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will disable the
    /// channel; you must re-enable it with `enable()`.
    ///
-    /// If you're not using DMA, pass [`dma::NoDma`] for the `dma` argument.
+    /// By default, triggering is disabled, but it can be enabled using
+    /// [`DacChannel::set_trigger()`].
+    #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
+    pub fn new_internal(peri: Peri<'d, T>, dma: Peri<'d, impl Dma<T, C>>) -> Self {
+        Self::new_inner(peri, new_dma!(dma), Mode::NormalInternalUnbuffered)
+    }
+    /// Write `data` to this channel via DMA.
+    ///
+    /// To prevent delays or glitches when outputing a periodic waveform, the `circular`
+    /// flag can be set. This configures a circular DMA transfer that continually outputs
+    /// `data`. Note that for performance reasons in circular mode the transfer-complete
+    /// interrupt is disabled.
+    #[cfg(not(gpdma))]
+    pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) {
+        // Enable DAC and DMA
+        T::regs().cr().modify(|w| {
+            w.set_en(C::IDX, true);
+            w.set_dmaen(C::IDX, true);
+        });
+        let dma = self.dma.as_mut().unwrap();
+        let tx_options = crate::dma::TransferOptions {
+            circular,
+            half_transfer_ir: false,
+            complete_transfer_ir: !circular,
+            ..Default::default()
+        };
+        // Initiate the correct type of DMA transfer depending on what data is passed
+        let tx_f = match data {
+            ValueArray::Bit8(buf) => unsafe { dma.write(buf, T::regs().dhr8r(C::IDX).as_ptr() as *mut u8, tx_options) },
+            ValueArray::Bit12Left(buf) => unsafe {
+                dma.write(buf, T::regs().dhr12l(C::IDX).as_ptr() as *mut u16, tx_options)
+            },
+            ValueArray::Bit12Right(buf) => unsafe {
+                dma.write(buf, T::regs().dhr12r(C::IDX).as_ptr() as *mut u16, tx_options)
+            },
+        };
+        tx_f.await;
+        T::regs().cr().modify(|w| {
+            w.set_en(C::IDX, false);
+            w.set_dmaen(C::IDX, false);
+        });
+    }
+}
+impl<'d, T: Instance, C: Channel> DacChannel<'d, T, C, Blocking> {
+    /// Create a new `DacChannel` instance, consuming the underlying DAC peripheral.
+    ///
+    /// The channel is enabled on creation and begin to drive the output pin.
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will
+    /// disable the channel; you must re-enable it with `enable()`.
+    ///
+    /// By default, triggering is disabled, but it can be enabled using
+    /// [`DacChannel::set_trigger()`].
+    pub fn new_blocking(peri: Peri<'d, T>, pin: Peri<'d, impl DacPin<T, C>>) -> Self {
+        pin.set_as_analog();
+        Self::new_inner(
+            peri,
+            None,
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+            Mode::NormalExternalBuffered,
+        )
+    }
+    /// Create a new `DacChannel` instance where the external output pin is not used,
+    /// so the DAC can only be used to generate internal signals.
+    /// The GPIO pin is therefore available to be used for other functions.
+    ///
+    /// The channel is set to [`Mode::NormalInternalUnbuffered`] and enabled on creation.
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will disable the
+    /// channel; you must re-enable it with `enable()`.
    ///
    /// By default, triggering is disabled, but it can be enabled using
    /// [`DacChannel::set_trigger()`].
    #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-    pub fn new_internal(_peri: impl Peripheral<P = T> + 'd, dma: impl Peripheral<P = DMA> + 'd) -> Self {
+    pub fn new_internal_blocking(peri: Peri<'d, T>) -> Self {
-        into_ref!(dma);
+        Self::new_inner(peri, None, Mode::NormalInternalUnbuffered)
+    }
+}
+impl<'d, T: Instance, C: Channel, M: PeriMode> DacChannel<'d, T, C, M> {
+    fn new_inner(
+        _peri: Peri<'d, T>,
+        dma: Option<ChannelAndRequest<'d>>,
+        #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
+    ) -> Self {
        rcc::enable_and_reset::<T>();
        let mut dac = Self {
            phantom: PhantomData,
@@ -164,7 +236,8 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
        };
        #[cfg(any(dac_v5, dac_v6, dac_v7))]
        dac.set_hfsel();
-        dac.set_mode(Mode::NormalInternalUnbuffered);
+        #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+        dac.set_mode(mode);
        dac.enable();
        dac
    }
@@ -173,7 +246,7 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    pub fn set_enable(&mut self, on: bool) {
        critical_section::with(|_| {
            T::regs().cr().modify(|reg| {
-                reg.set_en(Self::IDX, on);
+                reg.set_en(C::IDX, on);
            });
        });
    }
@@ -194,8 +267,8 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    pub fn set_trigger(&mut self, source: TriggerSel) {
        critical_section::with(|_| {
            T::regs().cr().modify(|reg| {
-                reg.set_en(Self::IDX, false);
+                reg.set_en(C::IDX, false);
-                reg.set_tsel(Self::IDX, source as u8);
+                reg.set_tsel(C::IDX, source as u8);
            });
        });
    }
@@ -204,7 +277,7 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    pub fn set_triggering(&mut self, on: bool) {
        critical_section::with(|_| {
            T::regs().cr().modify(|reg| {
-                reg.set_ten(Self::IDX, on);
+                reg.set_ten(C::IDX, on);
            });
        });
    }
@@ -212,7 +285,7 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    /// Software trigger this channel.
    pub fn trigger(&mut self) {
        T::regs().swtrigr().write(|reg| {
-            reg.set_swtrig(Self::IDX, true);
+            reg.set_swtrig(C::IDX, true);
        });
    }
@@ -223,10 +296,10 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    pub fn set_mode(&mut self, mode: Mode) {
        critical_section::with(|_| {
            T::regs().cr().modify(|reg| {
-                reg.set_en(Self::IDX, false);
+                reg.set_en(C::IDX, false);
            });
            T::regs().mcr().modify(|reg| {
-                reg.set_mode(Self::IDX, mode.mode());
+                reg.set_mode(C::IDX, mode.mode());
            });
        });
    }
@@ -237,15 +310,15 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    /// it will be output after the next trigger.
    pub fn set(&mut self, value: Value) {
        match value {
-            Value::Bit8(v) => T::regs().dhr8r(Self::IDX).write(|reg| reg.set_dhr(v)),
+            Value::Bit8(v) => T::regs().dhr8r(C::IDX).write(|reg| reg.set_dhr(v)),
-            Value::Bit12Left(v) => T::regs().dhr12l(Self::IDX).write(|reg| reg.set_dhr(v)),
+            Value::Bit12Left(v) => T::regs().dhr12l(C::IDX).write(|reg| reg.set_dhr(v)),
-            Value::Bit12Right(v) => T::regs().dhr12r(Self::IDX).write(|reg| reg.set_dhr(v)),
+            Value::Bit12Right(v) => T::regs().dhr12r(C::IDX).write(|reg| reg.set_dhr(v)),
        }
    }
    /// Read the current output value of the DAC.
    pub fn read(&self) -> u16 {
-        T::regs().dor(Self::IDX).read().dor()
+        T::regs().dor(C::IDX).read().dor()
    }
    /// Set HFSEL as appropriate for the current peripheral clock frequency.
@@ -279,82 +352,7 @@ impl<'d, T: Instance, const N: u8, DMA> DacChannel<'d, T, N, DMA> {
    }
 }
-macro_rules! impl_dma_methods {
+impl<'d, T: Instance, C: Channel, M: PeriMode> Drop for DacChannel<'d, T, C, M> {
-    ($n:literal, $trait:ident) => {
-        impl<'d, T: Instance, DMA> DacChannel<'d, T, $n, DMA>
-        where
-            DMA: $trait<T>,
-        {
-            /// Write `data` to this channel via DMA.
-            ///
-            /// To prevent delays or glitches when outputing a periodic waveform, the `circular`
-            /// flag can be set. This configures a circular DMA transfer that continually outputs
-            /// `data`. Note that for performance reasons in circular mode the transfer-complete
-            /// interrupt is disabled.
-            #[cfg(not(gpdma))]
-            pub async fn write(&mut self, data: ValueArray<'_>, circular: bool) {
-                // Enable DAC and DMA
-                T::regs().cr().modify(|w| {
-                    w.set_en(Self::IDX, true);
-                    w.set_dmaen(Self::IDX, true);
-                });
-                let tx_request = self.dma.request();
-                let dma_channel = &mut self.dma;
-                let tx_options = crate::dma::TransferOptions {
-                    circular,
-                    half_transfer_ir: false,
-                    complete_transfer_ir: !circular,
-                    ..Default::default()
-                };
-                // Initiate the correct type of DMA transfer depending on what data is passed
-                let tx_f = match data {
-                    ValueArray::Bit8(buf) => unsafe {
-                        crate::dma::Transfer::new_write(
-                            dma_channel,
-                            tx_request,
-                            buf,
-                            T::regs().dhr8r(Self::IDX).as_ptr() as *mut u8,
-                            tx_options,
-                        )
-                    },
-                    ValueArray::Bit12Left(buf) => unsafe {
-                        crate::dma::Transfer::new_write(
-                            dma_channel,
-                            tx_request,
-                            buf,
-                            T::regs().dhr12l(Self::IDX).as_ptr() as *mut u16,
-                            tx_options,
-                        )
-                    },
-                    ValueArray::Bit12Right(buf) => unsafe {
-                        crate::dma::Transfer::new_write(
-                            dma_channel,
-                            tx_request,
-                            buf,
-                            T::regs().dhr12r(Self::IDX).as_ptr() as *mut u16,
-                            tx_options,
-                        )
-                    },
-                };
-                tx_f.await;
-                T::regs().cr().modify(|w| {
-                    w.set_en(Self::IDX, false);
-                    w.set_dmaen(Self::IDX, false);
-                });
-            }
-        }
-    };
-}
-impl_dma_methods!(1, DacDma1);
-impl_dma_methods!(2, DacDma2);
-impl<'d, T: Instance, const N: u8, DMA> Drop for DacChannel<'d, T, N, DMA> {
    fn drop(&mut self) {
        rcc::disable::<T>();
    }
@@ -368,14 +366,14 @@ impl<'d, T: Instance, const N: u8, DMA> Drop for DacChannel<'d, T, N, DMA> {
 ///
 /// ```ignore
 /// // Pins may need to be changed for your specific device.
-/// let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new(p.DAC1, NoDma, NoDma, p.PA4, p.PA5).split();
+/// let (dac_ch1, dac_ch2) = embassy_stm32::dac::Dac::new_blocking(p.DAC1, p.PA4, p.PA5).split();
 /// ```
-pub struct Dac<'d, T: Instance, DMACh1 = NoDma, DMACh2 = NoDma> {
+pub struct Dac<'d, T: Instance, M: PeriMode> {
-    ch1: DacChannel<'d, T, 1, DMACh1>,
+    ch1: DacChannel<'d, T, Ch1, M>,
-    ch2: DacChannel<'d, T, 2, DMACh2>,
+    ch2: DacChannel<'d, T, Ch2, M>,
 }
-impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
+impl<'d, T: Instance> Dac<'d, T, Async> {
    /// Create a new `Dac` instance, consuming the underlying DAC peripheral.
    ///
    /// This struct allows you to access both channels of the DAC, where available. You can either
@@ -389,37 +387,79 @@ impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
    /// method on the underlying channels.
    pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma_ch1: impl Peripheral<P = DMACh1> + 'd,
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
-        dma_ch2: impl Peripheral<P = DMACh2> + 'd,
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
-        pin_ch1: impl Peripheral<P = impl DacPin<T, 1> + crate::gpio::Pin> + 'd,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
-        pin_ch2: impl Peripheral<P = impl DacPin<T, 2> + crate::gpio::Pin> + 'd,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
    ) -> Self {
-        into_ref!(dma_ch1, dma_ch2, pin_ch1, pin_ch2);
        pin_ch1.set_as_analog();
        pin_ch2.set_as_analog();
+        Self::new_inner(
+            peri,
+            new_dma!(dma_ch1),
+            new_dma!(dma_ch2),
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+            Mode::NormalExternalBuffered,
+        )
+    }
-        // Enable twice to increment the DAC refcount for each channel.
+    /// Create a new `Dac` instance where the external output pins are not used,
-        rcc::enable_and_reset::<T>();
+    /// so the DAC can only be used to generate internal signals but the GPIO
-        rcc::enable_and_reset::<T>();
+    /// pins remain available for other functions.
+    ///
-        let mut ch1 = DacCh1 {
+    /// This struct allows you to access both channels of the DAC, where available. You can either
-            phantom: PhantomData,
+    /// call `split()` to obtain separate `DacChannel`s, or use methods on `Dac` to use the two
-            dma: dma_ch1,
+    /// channels together.
-        };
+    ///
-        #[cfg(any(dac_v5, dac_v6, dac_v7))]
+    /// The channels are set to [`Mode::NormalInternalUnbuffered`] and enabled on creation.
-        ch1.set_hfsel();
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will disable the
-        ch1.enable();
+    /// channel; you must re-enable them with `enable()`.
+    ///
-        let mut ch2 = DacCh2 {
+    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
-            phantom: PhantomData,
+    /// method on the underlying channels.
-            dma: dma_ch2,
+    #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-        };
+    pub fn new_internal(
-        #[cfg(any(dac_v5, dac_v6, dac_v7))]
+        peri: Peri<'d, T>,
-        ch2.set_hfsel();
+        dma_ch1: Peri<'d, impl Dma<T, Ch1>>,
-        ch2.enable();
+        dma_ch2: Peri<'d, impl Dma<T, Ch2>>,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_dma!(dma_ch1),
+            new_dma!(dma_ch2),
+            Mode::NormalInternalUnbuffered,
+        )
+    }
+}
-        Self { ch1, ch2 }
+impl<'d, T: Instance> Dac<'d, T, Blocking> {
+    /// Create a new `Dac` instance, consuming the underlying DAC peripheral.
+    ///
+    /// This struct allows you to access both channels of the DAC, where available. You can either
+    /// call `split()` to obtain separate `DacChannel`s, or use methods on `Dac` to use
+    /// the two channels together.
+    ///
+    /// The channels are enabled on creation and begin to drive their output pins.
+    /// Note that some methods, such as `set_trigger()` and `set_mode()`, will
+    /// disable the channel; you must re-enable them with `enable()`.
+    ///
+    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
+    /// method on the underlying channels.
+    pub fn new_blocking(
+        peri: Peri<'d, T>,
+        pin_ch1: Peri<'d, impl DacPin<T, Ch1> + crate::gpio::Pin>,
+        pin_ch2: Peri<'d, impl DacPin<T, Ch2> + crate::gpio::Pin>,
+    ) -> Self {
+        pin_ch1.set_as_analog();
+        pin_ch2.set_as_analog();
+        Self::new_inner(
+            peri,
+            None,
+            None,
+            #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+            Mode::NormalExternalBuffered,
+        )
    }
    /// Create a new `Dac` instance where the external output pins are not used,
@@ -437,12 +477,18 @@ impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
    /// By default, triggering is disabled, but it can be enabled using the `set_trigger()`
    /// method on the underlying channels.
    #[cfg(all(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7), not(any(stm32h56x, stm32h57x))))]
-    pub fn new_internal(
+    pub fn new_internal(peri: Peri<'d, T>) -> Self {
-        _peri: impl Peripheral<P = T> + 'd,
+        Self::new_inner(peri, None, None, Mode::NormalInternalUnbuffered)
-        dma_ch1: impl Peripheral<P = DMACh1> + 'd,
+    }
-        dma_ch2: impl Peripheral<P = DMACh2> + 'd,
+}
+impl<'d, T: Instance, M: PeriMode> Dac<'d, T, M> {
+    fn new_inner(
+        _peri: Peri<'d, T>,
+        dma_ch1: Option<ChannelAndRequest<'d>>,
+        dma_ch2: Option<ChannelAndRequest<'d>>,
+        #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))] mode: Mode,
    ) -> Self {
-        into_ref!(dma_ch1, dma_ch2);
        // Enable twice to increment the DAC refcount for each channel.
        rcc::enable_and_reset::<T>();
        rcc::enable_and_reset::<T>();
@@ -453,7 +499,8 @@ impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
        };
        #[cfg(any(dac_v5, dac_v6, dac_v7))]
        ch1.set_hfsel();
-        ch1.set_mode(Mode::NormalInternalUnbuffered);
+        #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+        ch1.set_mode(mode);
        ch1.enable();
        let mut ch2 = DacCh2 {
@@ -462,7 +509,8 @@ impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
        };
        #[cfg(any(dac_v5, dac_v6, dac_v7))]
        ch2.set_hfsel();
-        ch2.set_mode(Mode::NormalInternalUnbuffered);
+        #[cfg(any(dac_v3, dac_v4, dac_v5, dac_v6, dac_v7))]
+        ch2.set_mode(mode);
        ch2.enable();
        Self { ch1, ch2 }
@@ -471,17 +519,17 @@ impl<'d, T: Instance, DMACh1, DMACh2> Dac<'d, T, DMACh1, DMACh2> {
    /// Split this `Dac` into separate channels.
    ///
    /// You can access and move the channels around separately after splitting.
-    pub fn split(self) -> (DacCh1<'d, T, DMACh1>, DacCh2<'d, T, DMACh2>) {
+    pub fn split(self) -> (DacCh1<'d, T, M>, DacCh2<'d, T, M>) {
        (self.ch1, self.ch2)
    }
    /// Temporarily access channel 1.
-    pub fn ch1(&mut self) -> &mut DacCh1<'d, T, DMACh1> {
+    pub fn ch1(&mut self) -> &mut DacCh1<'d, T, M> {
        &mut self.ch1
    }
    /// Temporarily access channel 2.
-    pub fn ch2(&mut self) -> &mut DacCh2<'d, T, DMACh2> {
+    pub fn ch2(&mut self) -> &mut DacCh2<'d, T, M> {
        &mut self.ch2
    }
@@ -513,12 +561,31 @@ trait SealedInstance {
 /// DAC instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {}
-dma_trait!(DacDma1, Instance);
-dma_trait!(DacDma2, Instance);
+/// Channel 1 marker type.
+pub enum Ch1 {}
+/// Channel 2 marker type.
+pub enum Ch2 {}
+trait SealedChannel {
+    const IDX: usize;
+}
+/// DAC channel trait.
+#[allow(private_bounds)]
+pub trait Channel: SealedChannel {}
+impl SealedChannel for Ch1 {
+    const IDX: usize = 0;
+}
+impl SealedChannel for Ch2 {
+    const IDX: usize = 1;
+}
+impl Channel for Ch1 {}
+impl Channel for Ch2 {}
-/// Marks a pin that can be used with the DAC
+dma_trait!(Dma, Instance, Channel);
-pub trait DacPin<T: Instance, const C: u8>: crate::gpio::Pin + 'static {}
+pin_trait!(DacPin, Instance, Channel);
 foreach_peripheral!(
    (dac, $inst:ident) => {
@@ -531,9 +598,3 @@ foreach_peripheral!(
        impl crate::dac::Instance for peripherals::$inst {}
    };
 );
-macro_rules! impl_dac_pin {
-    ($inst:ident, $pin:ident, $ch:expr) => {
-        impl crate::dac::DacPin<peripherals::$inst, $ch> for crate::peripherals::$pin {}
-    };
-}
diff --git a/embassy-stm32/src/dcmi.rs b/embassy-stm32/src/dcmi.rs
index 4ba4e824e..d05faee21 100644
--- a/embassy-stm32/src/dcmi.rs
+++ b/embassy-stm32/src/dcmi.rs
@@ -3,13 +3,13 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use crate::dma::Transfer;
 use crate::gpio::{AfType, Pull};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, rcc, Peripheral};
+use crate::{interrupt, rcc, Peri};
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -106,8 +106,7 @@ impl Default for Config {
 macro_rules! config_pins {
    ($($pin:ident),*) => {
-        into_ref!($($pin),*);
+                critical_section::with(|_| {
-        critical_section::with(|_| {
            $(
                $pin.set_as_af($pin.af_num(), AfType::input(Pull::None));
            )*
@@ -117,8 +116,8 @@ macro_rules! config_pins {
 /// DCMI driver.
 pub struct Dcmi<'d, T: Instance, Dma: FrameDma<T>> {
-    inner: PeripheralRef<'d, T>,
+    inner: Peri<'d, T>,
-    dma: PeripheralRef<'d, Dma>,
+    dma: Peri<'d, Dma>,
 }
 impl<'d, T, Dma> Dcmi<'d, T, Dma>
@@ -128,23 +127,22 @@ where
 {
    /// Create a new DCMI driver with 8 data bits.
    pub fn new_8bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
        config_pins!(v_sync, h_sync, pixclk);
@@ -153,25 +151,24 @@ where
    /// Create a new DCMI driver with 10 data bits.
    pub fn new_10bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
        config_pins!(v_sync, h_sync, pixclk);
@@ -180,27 +177,26 @@ where
    /// Create a new DCMI driver with 12 data bits.
    pub fn new_12bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
+        d10: Peri<'d, impl D10Pin<T>>,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
+        d11: Peri<'d, impl D11Pin<T>>,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
        config_pins!(v_sync, h_sync, pixclk);
@@ -209,29 +205,28 @@ where
    /// Create a new DCMI driver with 14 data bits.
    pub fn new_14bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
+        d10: Peri<'d, impl D10Pin<T>>,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
+        d11: Peri<'d, impl D11Pin<T>>,
-        d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
+        d12: Peri<'d, impl D12Pin<T>>,
-        d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
+        d13: Peri<'d, impl D13Pin<T>>,
-        v_sync: impl Peripheral<P = impl VSyncPin<T>> + 'd,
+        v_sync: Peri<'d, impl VSyncPin<T>>,
-        h_sync: impl Peripheral<P = impl HSyncPin<T>> + 'd,
+        h_sync: Peri<'d, impl HSyncPin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
        config_pins!(v_sync, h_sync, pixclk);
@@ -240,21 +235,20 @@ where
    /// Create a new DCMI driver with 8 data bits, with embedded synchronization.
    pub fn new_es_8bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7);
        config_pins!(pixclk);
@@ -263,23 +257,22 @@ where
    /// Create a new DCMI driver with 10 data bits, with embedded synchronization.
    pub fn new_es_10bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9);
        config_pins!(pixclk);
@@ -288,25 +281,24 @@ where
    /// Create a new DCMI driver with 12 data bits, with embedded synchronization.
    pub fn new_es_12bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
+        d10: Peri<'d, impl D10Pin<T>>,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
+        d11: Peri<'d, impl D11Pin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11);
        config_pins!(pixclk);
@@ -315,27 +307,26 @@ where
    /// Create a new DCMI driver with 14 data bits, with embedded synchronization.
    pub fn new_es_14bit(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, Dma>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        d8: impl Peripheral<P = impl D8Pin<T>> + 'd,
+        d8: Peri<'d, impl D8Pin<T>>,
-        d9: impl Peripheral<P = impl D9Pin<T>> + 'd,
+        d9: Peri<'d, impl D9Pin<T>>,
-        d10: impl Peripheral<P = impl D10Pin<T>> + 'd,
+        d10: Peri<'d, impl D10Pin<T>>,
-        d11: impl Peripheral<P = impl D11Pin<T>> + 'd,
+        d11: Peri<'d, impl D11Pin<T>>,
-        d12: impl Peripheral<P = impl D12Pin<T>> + 'd,
+        d12: Peri<'d, impl D12Pin<T>>,
-        d13: impl Peripheral<P = impl D13Pin<T>> + 'd,
+        d13: Peri<'d, impl D13Pin<T>>,
-        pixclk: impl Peripheral<P = impl PixClkPin<T>> + 'd,
+        pixclk: Peri<'d, impl PixClkPin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(peri, dma);
        config_pins!(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13);
        config_pins!(pixclk);
@@ -343,8 +334,8 @@ where
    }
    fn new_inner(
-        peri: PeripheralRef<'d, T>,
+        peri: Peri<'d, T>,
-        dma: PeripheralRef<'d, Dma>,
+        dma: Peri<'d, Dma>,
        config: Config,
        use_embedded_synchronization: bool,
        edm: u8,
@@ -396,7 +387,7 @@ where
        let r = self.inner.regs();
        let src = r.dr().as_ptr() as *mut u32;
        let request = self.dma.request();
-        let dma_read = unsafe { Transfer::new_read(&mut self.dma, request, src, buffer, Default::default()) };
+        let dma_read = unsafe { Transfer::new_read(self.dma.reborrow(), request, src, buffer, Default::default()) };
        Self::clear_interrupt_flags();
        Self::enable_irqs();
@@ -435,7 +426,7 @@ trait SealedInstance: crate::rcc::RccPeripheral {
 /// DCMI instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {
+pub trait Instance: SealedInstance + PeripheralType + 'static {
    /// Interrupt for this instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/dma/dma_bdma.rs b/embassy-stm32/src/dma/dma_bdma.rs
index 8a6aa53a0..7dbbe7b72 100644
--- a/embassy-stm32/src/dma/dma_bdma.rs
+++ b/embassy-stm32/src/dma/dma_bdma.rs
@@ -3,10 +3,10 @@ use core::pin::Pin;
 use core::sync::atomic::{fence, AtomicUsize, Ordering};
 use core::task::{Context, Poll, Waker};
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
-use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
+use super::ringbuffer::{DmaCtrl, Error, ReadableDmaRingBuffer, WritableDmaRingBuffer};
 use super::word::{Word, WordSize};
 use super::{AnyChannel, Channel, Dir, Request, STATE};
 use crate::interrupt::typelevel::Interrupt;
@@ -15,6 +15,8 @@ use crate::{interrupt, pac};
 pub(crate) struct ChannelInfo {
    pub(crate) dma: DmaInfo,
    pub(crate) num: usize,
+    #[cfg(feature = "_dual-core")]
+    pub(crate) irq: pac::Interrupt,
    #[cfg(dmamux)]
    pub(crate) dmamux: super::DmamuxInfo,
 }
@@ -98,7 +100,7 @@ impl From<Priority> for pac::dma::vals::Pl {
            Priority::Low => pac::dma::vals::Pl::LOW,
            Priority::Medium => pac::dma::vals::Pl::MEDIUM,
            Priority::High => pac::dma::vals::Pl::HIGH,
-            Priority::VeryHigh => pac::dma::vals::Pl::VERYHIGH,
+            Priority::VeryHigh => pac::dma::vals::Pl::VERY_HIGH,
        }
    }
 }
@@ -110,7 +112,7 @@ impl From<Priority> for pac::bdma::vals::Pl {
            Priority::Low => pac::bdma::vals::Pl::LOW,
            Priority::Medium => pac::bdma::vals::Pl::MEDIUM,
            Priority::High => pac::bdma::vals::Pl::HIGH,
-            Priority::VeryHigh => pac::bdma::vals::Pl::VERYHIGH,
+            Priority::VeryHigh => pac::bdma::vals::Pl::VERY_HIGH,
        }
    }
 }
@@ -136,8 +138,8 @@ mod dma_only {
    impl From<Dir> for vals::Dir {
        fn from(raw: Dir) -> Self {
            match raw {
-                Dir::MemoryToPeripheral => Self::MEMORYTOPERIPHERAL,
+                Dir::MemoryToPeripheral => Self::MEMORY_TO_PERIPHERAL,
-                Dir::PeripheralToMemory => Self::PERIPHERALTOMEMORY,
+                Dir::PeripheralToMemory => Self::PERIPHERAL_TO_MEMORY,
            }
        }
    }
@@ -205,7 +207,7 @@ mod dma_only {
            match value {
                FifoThreshold::Quarter => vals::Fth::QUARTER,
                FifoThreshold::Half => vals::Fth::HALF,
-                FifoThreshold::ThreeQuarters => vals::Fth::THREEQUARTERS,
+                FifoThreshold::ThreeQuarters => vals::Fth::THREE_QUARTERS,
                FifoThreshold::Full => vals::Fth::FULL,
            }
        }
@@ -231,8 +233,8 @@ mod bdma_only {
    impl From<Dir> for vals::Dir {
        fn from(raw: Dir) -> Self {
            match raw {
-                Dir::MemoryToPeripheral => Self::FROMMEMORY,
+                Dir::MemoryToPeripheral => Self::FROM_MEMORY,
-                Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
+                Dir::PeripheralToMemory => Self::FROM_PERIPHERAL,
            }
        }
    }
@@ -259,10 +261,12 @@ pub(crate) unsafe fn init(
    foreach_interrupt! {
        ($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
            crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, dma_priority);
+            #[cfg(not(feature = "_dual-core"))]
            crate::interrupt::typelevel::$irq::enable();
        };
        ($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
            crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, bdma_priority);
+            #[cfg(not(feature = "_dual-core"))]
            crate::interrupt::typelevel::$irq::enable();
        };
    }
@@ -295,7 +299,6 @@ impl AnyChannel {
                } else {
                    return;
                }
                state.waker.wake();
            }
            #[cfg(bdma)]
@@ -337,10 +340,16 @@ impl AnyChannel {
        mem_addr: *mut u32,
        mem_len: usize,
        incr_mem: bool,
-        data_size: WordSize,
+        mem_size: WordSize,
+        peripheral_size: WordSize,
        options: TransferOptions,
    ) {
        let info = self.info();
+        #[cfg(feature = "_dual-core")]
+        {
+            use embassy_hal_internal::interrupt::InterruptExt as _;
+            info.irq.enable();
+        }
        #[cfg(dmamux)]
        super::dmamux::configure_dmamux(&info.dmamux, _request);
@@ -350,11 +359,13 @@ impl AnyChannel {
        match self.info().dma {
            #[cfg(dma)]
            DmaInfo::Dma(r) => {
+                let state: &ChannelState = &STATE[self.id as usize];
                let ch = r.st(info.num);
                // "Preceding reads and writes cannot be moved past subsequent writes."
                fence(Ordering::SeqCst);
+                state.complete_count.store(0, Ordering::Release);
                self.clear_irqs();
                ch.par().write_value(peri_addr as u32);
@@ -372,8 +383,8 @@ impl AnyChannel {
                });
                ch.cr().write(|w| {
                    w.set_dir(dir.into());
-                    w.set_msize(data_size.into());
+                    w.set_msize(mem_size.into());
-                    w.set_psize(data_size.into());
+                    w.set_psize(peripheral_size.into());
                    w.set_pl(options.priority.into());
                    w.set_minc(incr_mem);
                    w.set_pinc(false);
@@ -406,8 +417,8 @@ impl AnyChannel {
                ch.mar().write_value(mem_addr as u32);
                ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
                ch.cr().write(|w| {
-                    w.set_psize(data_size.into());
+                    w.set_psize(peripheral_size.into());
-                    w.set_msize(data_size.into());
+                    w.set_msize(mem_size.into());
                    w.set_minc(incr_mem);
                    w.set_dir(dir.into());
                    w.set_teie(true);
@@ -484,6 +495,26 @@ impl AnyChannel {
        }
    }
+    fn request_pause(&self) {
+        let info = self.info();
+        match self.info().dma {
+            #[cfg(dma)]
+            DmaInfo::Dma(r) => {
+                // Disable the channel without overwriting the existing configuration
+                r.st(info.num).cr().modify(|w| {
+                    w.set_en(false);
+                });
+            }
+            #[cfg(bdma)]
+            DmaInfo::Bdma(r) => {
+                // Disable the channel without overwriting the existing configuration
+                r.ch(info.num).cr().modify(|w| {
+                    w.set_en(false);
+                });
+            }
+        }
+    }
    fn is_running(&self) -> bool {
        let info = self.info();
        match self.info().dma {
@@ -540,13 +571,13 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
 }
 impl<'a> Transfer<'a> {
    /// Create a new read DMA transfer (peripheral to memory).
    pub unsafe fn new_read<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
        peri_addr: *mut W,
        buf: &'a mut [W],
@@ -557,16 +588,14 @@ impl<'a> Transfer<'a> {
    /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
    pub unsafe fn new_read_raw<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
        peri_addr: *mut W,
        buf: *mut [W],
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::PeripheralToMemory,
            peri_addr as *const u32,
@@ -574,57 +603,55 @@ impl<'a> Transfer<'a> {
            buf.len(),
            true,
            W::size(),
+            W::size(),
            options,
        )
    }
    /// Create a new write DMA transfer (memory to peripheral).
-    pub unsafe fn new_write<W: Word>(
+    pub unsafe fn new_write<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
-        buf: &'a [W],
+        buf: &'a [MW],
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Self {
        Self::new_write_raw(channel, request, buf, peri_addr, options)
    }
    /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
-    pub unsafe fn new_write_raw<W: Word>(
+    pub unsafe fn new_write_raw<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
-        buf: *const [W],
+        buf: *const [MW],
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::MemoryToPeripheral,
            peri_addr as *const u32,
-            buf as *const W as *mut u32,
+            buf as *const MW as *mut u32,
            buf.len(),
            true,
-            W::size(),
+            MW::size(),
+            PW::size(),
            options,
        )
    }
    /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
    pub unsafe fn new_write_repeated<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
        repeated: &'a W,
        count: usize,
        peri_addr: *mut W,
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::MemoryToPeripheral,
            peri_addr as *const u32,
@@ -632,12 +659,13 @@ impl<'a> Transfer<'a> {
            count,
            false,
            W::size(),
+            W::size(),
            options,
        )
    }
    unsafe fn new_inner(
-        channel: PeripheralRef<'a, AnyChannel>,
+        channel: Peri<'a, AnyChannel>,
        _request: Request,
        dir: Dir,
        peri_addr: *const u32,
@@ -645,25 +673,43 @@ impl<'a> Transfer<'a> {
        mem_len: usize,
        incr_mem: bool,
        data_size: WordSize,
+        peripheral_size: WordSize,
        options: TransferOptions,
    ) -> Self {
        assert!(mem_len > 0 && mem_len <= 0xFFFF);
        channel.configure(
-            _request, dir, peri_addr, mem_addr, mem_len, incr_mem, data_size, options,
+            _request,
+            dir,
+            peri_addr,
+            mem_addr,
+            mem_len,
+            incr_mem,
+            data_size,
+            peripheral_size,
+            options,
        );
        channel.start();
        Self { channel }
    }
    /// Request the transfer to stop.
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
    ///
    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
    pub fn request_stop(&mut self) {
        self.channel.request_stop()
    }
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
    /// Return whether this transfer is still running.
    ///
    /// If this returns `false`, it can be because either the transfer finished, or
@@ -717,17 +763,13 @@ impl<'a> Future for Transfer<'a> {
 // ==============================
-struct DmaCtrlImpl<'a>(PeripheralRef<'a, AnyChannel>);
+struct DmaCtrlImpl<'a>(Peri<'a, AnyChannel>);
 impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
    fn get_remaining_transfers(&self) -> usize {
        self.0.get_remaining_transfers() as _
    }
-    fn get_complete_count(&self) -> usize {
-        STATE[self.0.id as usize].complete_count.load(Ordering::Acquire)
-    }
    fn reset_complete_count(&mut self) -> usize {
        let state = &STATE[self.0.id as usize];
        #[cfg(not(armv6m))]
@@ -747,27 +789,27 @@ impl<'a> DmaCtrl for DmaCtrlImpl<'a> {
 /// Ringbuffer for receiving data using DMA circular mode.
 pub struct ReadableRingBuffer<'a, W: Word> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
    ringbuf: ReadableDmaRingBuffer<'a, W>,
 }
 impl<'a, W: Word> ReadableRingBuffer<'a, W> {
    /// Create a new ring buffer.
    pub unsafe fn new(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        _request: Request,
        peri_addr: *mut W,
        buffer: &'a mut [W],
        mut options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
+        let channel: Peri<'a, AnyChannel> = channel.into();
-        let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
        let buffer_ptr = buffer.as_mut_ptr();
        let len = buffer.len();
        let dir = Dir::PeripheralToMemory;
        let data_size = W::size();
+        options.half_transfer_ir = true;
        options.complete_transfer_ir = true;
        options.circular = true;
@@ -779,6 +821,7 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
            len,
            true,
            data_size,
+            data_size,
            options,
        );
@@ -792,27 +835,27 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
    ///
    /// You must call this after creating it for it to work.
    pub fn start(&mut self) {
-        self.channel.start()
+        self.channel.start();
    }
    /// Clear all data in the ring buffer.
    pub fn clear(&mut self) {
-        self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
+        self.ringbuf.reset(&mut DmaCtrlImpl(self.channel.reborrow()));
    }
    /// Read elements from the ring buffer
    /// Return a tuple of the length read and the length remaining in the buffer
    /// If not all of the elements were read, then there will be some elements in the buffer remaining
    /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
-    /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
+    /// Error is returned if the portion to be read was overwritten by the DMA controller.
-    pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
+    pub fn read(&mut self, buf: &mut [W]) -> Result<(usize, usize), Error> {
        self.ringbuf.read(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
    }
    /// Read an exact number of elements from the ringbuffer.
    ///
    /// Returns the remaining number of elements available for immediate reading.
-    /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
+    /// Error is returned if the portion to be read was overwritten by the DMA controller.
    ///
    /// Async/Wake Behavior:
    /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
@@ -820,12 +863,17 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
    /// ring buffer was created with a buffer of size 'N':
    /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
    /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
-    pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, OverrunError> {
+    pub async fn read_exact(&mut self, buffer: &mut [W]) -> Result<usize, Error> {
        self.ringbuf
            .read_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
            .await
    }
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?)
+    }
    /// The capacity of the ringbuffer
    pub const fn capacity(&self) -> usize {
        self.ringbuf.cap()
@@ -836,13 +884,23 @@ impl<'a, W: Word> ReadableRingBuffer<'a, W> {
        DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
    }
-    /// Request DMA to stop.
+    /// Request the DMA to stop.
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
    ///
    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
    pub fn request_stop(&mut self) {
        self.channel.request_stop()
    }
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
    /// Return whether DMA is still running.
    ///
    /// If this returns `false`, it can be because either the transfer finished, or
@@ -883,21 +941,20 @@ impl<'a, W: Word> Drop for ReadableRingBuffer<'a, W> {
 /// Ringbuffer for writing data using DMA circular mode.
 pub struct WritableRingBuffer<'a, W: Word> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
    ringbuf: WritableDmaRingBuffer<'a, W>,
 }
 impl<'a, W: Word> WritableRingBuffer<'a, W> {
    /// Create a new ring buffer.
    pub unsafe fn new(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        _request: Request,
        peri_addr: *mut W,
        buffer: &'a mut [W],
        mut options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
+        let channel: Peri<'a, AnyChannel> = channel.into();
-        let channel: PeripheralRef<'a, AnyChannel> = channel.map_into();
        let len = buffer.len();
        let dir = Dir::MemoryToPeripheral;
@@ -916,6 +973,7 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
            len,
            true,
            data_size,
+            data_size,
            options,
        );
@@ -929,34 +987,45 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
    ///
    /// You must call this after creating it for it to work.
    pub fn start(&mut self) {
-        self.channel.start()
+        self.channel.start();
    }
    /// Clear all data in the ring buffer.
    pub fn clear(&mut self) {
-        self.ringbuf.clear(&mut DmaCtrlImpl(self.channel.reborrow()));
+        self.ringbuf.reset(&mut DmaCtrlImpl(self.channel.reborrow()));
    }
    /// Write elements directly to the raw buffer.
    /// This can be used to fill the buffer before starting the DMA transfer.
-    #[allow(dead_code)]
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
-    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
        self.ringbuf.write_immediate(buf)
    }
    /// Write elements from the ring buffer
    /// Return a tuple of the length written and the length remaining in the buffer
-    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
+    pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
        self.ringbuf.write(&mut DmaCtrlImpl(self.channel.reborrow()), buf)
    }
    /// Write an exact number of elements to the ringbuffer.
-    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
+    pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, Error> {
        self.ringbuf
            .write_exact(&mut DmaCtrlImpl(self.channel.reborrow()), buffer)
            .await
    }
+    /// Wait for any ring buffer write error.
+    pub async fn wait_write_error(&mut self) -> Result<usize, Error> {
+        self.ringbuf
+            .wait_write_error(&mut DmaCtrlImpl(self.channel.reborrow()))
+            .await
+    }
+    /// The current length of the ringbuffer
+    pub fn len(&mut self) -> Result<usize, Error> {
+        Ok(self.ringbuf.len(&mut DmaCtrlImpl(self.channel.reborrow()))?)
+    }
    /// The capacity of the ringbuffer
    pub const fn capacity(&self) -> usize {
        self.ringbuf.cap()
@@ -967,13 +1036,23 @@ impl<'a, W: Word> WritableRingBuffer<'a, W> {
        DmaCtrlImpl(self.channel.reborrow()).set_waker(waker);
    }
-    /// Request DMA to stop.
+    /// Request the DMA to stop.
+    /// The configuration for this channel will **not be preserved**. If you need to restart the transfer
+    /// at a later point with the same configuration, see [`request_pause`](Self::request_pause) instead.
    ///
    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
    pub fn request_stop(&mut self) {
        self.channel.request_stop()
    }
+    /// Request the transfer to pause, keeping the existing configuration for this channel.
+    /// To restart the transfer, call [`start`](Self::start) again.
+    ///
+    /// This doesn't immediately stop the transfer, you have to wait until [`is_running`](Self::is_running) returns false.
+    pub fn request_pause(&mut self) {
+        self.channel.request_pause()
+    }
    /// Return whether DMA is still running.
    ///
    /// If this returns `false`, it can be because either the transfer finished, or
diff --git a/embassy-stm32/src/dma/gpdma.rs b/embassy-stm32/src/dma/gpdma.rs
index 13d5d15be..ade70fb55 100644
--- a/embassy-stm32/src/dma/gpdma.rs
+++ b/embassy-stm32/src/dma/gpdma.rs
@@ -5,7 +5,7 @@ use core::pin::Pin;
 use core::sync::atomic::{fence, Ordering};
 use core::task::{Context, Poll};
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 use super::word::{Word, WordSize};
@@ -18,6 +18,8 @@ use crate::pac::gpdma::vals;
 pub(crate) struct ChannelInfo {
    pub(crate) dma: pac::gpdma::Gpdma,
    pub(crate) num: usize,
+    #[cfg(feature = "_dual-core")]
+    pub(crate) irq: pac::Interrupt,
 }
 /// GPDMA transfer options.
@@ -36,7 +38,7 @@ impl From<WordSize> for vals::Dw {
    fn from(raw: WordSize) -> Self {
        match raw {
            WordSize::OneByte => Self::BYTE,
-            WordSize::TwoBytes => Self::HALFWORD,
+            WordSize::TwoBytes => Self::HALF_WORD,
            WordSize::FourBytes => Self::WORD,
        }
    }
@@ -57,6 +59,7 @@ pub(crate) unsafe fn init(cs: critical_section::CriticalSection, irq_priority: P
    foreach_interrupt! {
        ($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
            crate::interrupt::typelevel::$irq::set_priority_with_cs(cs, irq_priority);
+            #[cfg(not(feature = "_dual-core"))]
            crate::interrupt::typelevel::$irq::enable();
        };
    }
@@ -67,6 +70,12 @@ impl AnyChannel {
    /// Safety: Must be called with a matching set of parameters for a valid dma channel
    pub(crate) unsafe fn on_irq(&self) {
        let info = self.info();
+        #[cfg(feature = "_dual-core")]
+        {
+            use embassy_hal_internal::interrupt::InterruptExt as _;
+            info.irq.enable();
+        }
        let state = &STATE[self.id as usize];
        let ch = info.dma.ch(info.num);
@@ -100,13 +109,13 @@ impl AnyChannel {
 /// DMA transfer.
 #[must_use = "futures do nothing unless you `.await` or poll them"]
 pub struct Transfer<'a> {
-    channel: PeripheralRef<'a, AnyChannel>,
+    channel: Peri<'a, AnyChannel>,
 }
 impl<'a> Transfer<'a> {
    /// Create a new read DMA transfer (peripheral to memory).
    pub unsafe fn new_read<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
        peri_addr: *mut W,
        buf: &'a mut [W],
@@ -117,16 +126,14 @@ impl<'a> Transfer<'a> {
    /// Create a new read DMA transfer (peripheral to memory), using raw pointers.
    pub unsafe fn new_read_raw<W: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
        peri_addr: *mut W,
        buf: *mut [W],
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::PeripheralToMemory,
            peri_addr as *const u32,
@@ -134,70 +141,69 @@ impl<'a> Transfer<'a> {
            buf.len(),
            true,
            W::size(),
+            W::size(),
            options,
        )
    }
    /// Create a new write DMA transfer (memory to peripheral).
-    pub unsafe fn new_write<W: Word>(
+    pub unsafe fn new_write<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
-        buf: &'a [W],
+        buf: &'a [MW],
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Self {
        Self::new_write_raw(channel, request, buf, peri_addr, options)
    }
    /// Create a new write DMA transfer (memory to peripheral), using raw pointers.
-    pub unsafe fn new_write_raw<W: Word>(
+    pub unsafe fn new_write_raw<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
-        buf: *const [W],
+        buf: *const [MW],
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::MemoryToPeripheral,
            peri_addr as *const u32,
-            buf as *const W as *mut u32,
+            buf as *const MW as *mut u32,
            buf.len(),
            true,
-            W::size(),
+            MW::size(),
+            PW::size(),
            options,
        )
    }
    /// Create a new write DMA transfer (memory to peripheral), writing the same value repeatedly.
-    pub unsafe fn new_write_repeated<W: Word>(
+    pub unsafe fn new_write_repeated<MW: Word, PW: Word>(
-        channel: impl Peripheral<P = impl Channel> + 'a,
+        channel: Peri<'a, impl Channel>,
        request: Request,
-        repeated: &'a W,
+        repeated: &'a MW,
        count: usize,
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Self {
-        into_ref!(channel);
        Self::new_inner(
-            channel.map_into(),
+            channel.into(),
            request,
            Dir::MemoryToPeripheral,
            peri_addr as *const u32,
-            repeated as *const W as *mut u32,
+            repeated as *const MW as *mut u32,
            count,
            false,
-            W::size(),
+            MW::size(),
+            PW::size(),
            options,
        )
    }
    unsafe fn new_inner(
-        channel: PeripheralRef<'a, AnyChannel>,
+        channel: Peri<'a, AnyChannel>,
        request: Request,
        dir: Dir,
        peri_addr: *const u32,
@@ -205,9 +211,13 @@ impl<'a> Transfer<'a> {
        mem_len: usize,
        incr_mem: bool,
        data_size: WordSize,
+        dst_size: WordSize,
        _options: TransferOptions,
    ) -> Self {
-        assert!(mem_len > 0 && mem_len <= 0xFFFF);
+        // BNDT is specified as bytes, not as number of transfers.
+        let Ok(bndt) = (mem_len * data_size.bytes()).try_into() else {
+            panic!("DMA transfers may not be larger than 65535 bytes.");
+        };
        let info = channel.info();
        let ch = info.dma.ch(info.num);
@@ -217,29 +227,24 @@ impl<'a> Transfer<'a> {
        let this = Self { channel };
-        #[cfg(dmamux)]
-        super::dmamux::configure_dmamux(&*this.channel, request);
        ch.cr().write(|w| w.set_reset(true));
        ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
        ch.llr().write(|_| {}); // no linked list
        ch.tr1().write(|w| {
            w.set_sdw(data_size.into());
-            w.set_ddw(data_size.into());
+            w.set_ddw(dst_size.into());
            w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
            w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
        });
        ch.tr2().write(|w| {
            w.set_dreq(match dir {
-                Dir::MemoryToPeripheral => vals::Dreq::DESTINATIONPERIPHERAL,
+                Dir::MemoryToPeripheral => vals::Dreq::DESTINATION_PERIPHERAL,
-                Dir::PeripheralToMemory => vals::Dreq::SOURCEPERIPHERAL,
+                Dir::PeripheralToMemory => vals::Dreq::SOURCE_PERIPHERAL,
            });
            w.set_reqsel(request);
        });
-        ch.br1().write(|w| {
+        ch.tr3().write(|_| {}); // no address offsets.
-            // BNDT is specified as bytes, not as number of transfers.
+        ch.br1().write(|w| w.set_bndt(bndt));
-            w.set_bndt((mem_len * data_size.bytes()) as u16)
-        });
        match dir {
            Dir::MemoryToPeripheral => {
diff --git a/embassy-stm32/src/dma/mod.rs b/embassy-stm32/src/dma/mod.rs
index 66c4aa53c..d3b070a6d 100644
--- a/embassy-stm32/src/dma/mod.rs
+++ b/embassy-stm32/src/dma/mod.rs
@@ -22,7 +22,7 @@ pub(crate) use util::*;
 pub(crate) mod ringbuffer;
 pub mod word;
-use embassy_hal_internal::{impl_peripheral, Peripheral};
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 use crate::interrupt;
@@ -51,17 +51,7 @@ pub(crate) trait ChannelInterrupt {
 /// DMA channel.
 #[allow(private_bounds)]
-pub trait Channel: SealedChannel + Peripheral<P = Self> + Into<AnyChannel> + 'static {
+pub trait Channel: SealedChannel + PeripheralType + Into<AnyChannel> + 'static {}
-    /// Type-erase (degrade) this pin into an `AnyChannel`.
-    ///
-    /// This converts DMA channel singletons (`DMA1_CH3`, `DMA2_CH1`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of channels, or avoiding generics.
-    #[inline]
-    fn degrade(self) -> AnyChannel {
-        AnyChannel { id: self.id() }
-    }
-}
 macro_rules! dma_channel_impl {
    ($channel_peri:ident, $index:expr) => {
@@ -79,8 +69,10 @@ macro_rules! dma_channel_impl {
        impl crate::dma::Channel for crate::peripherals::$channel_peri {}
        impl From<crate::peripherals::$channel_peri> for crate::dma::AnyChannel {
-            fn from(x: crate::peripherals::$channel_peri) -> Self {
+            fn from(val: crate::peripherals::$channel_peri) -> Self {
-                crate::dma::Channel::degrade(x)
+                Self {
+                    id: crate::dma::SealedChannel::id(&val),
+                }
            }
        }
    };
@@ -108,17 +100,6 @@ impl Channel for AnyChannel {}
 const CHANNEL_COUNT: usize = crate::_generated::DMA_CHANNELS.len();
 static STATE: [ChannelState; CHANNEL_COUNT] = [ChannelState::NEW; CHANNEL_COUNT];
-/// "No DMA" placeholder.
-///
-/// You may pass this in place of a real DMA channel when creating a driver
-/// to indicate it should not use DMA.
-///
-/// This often causes async functionality to not be available on the instance,
-/// leaving only blocking functionality.
-pub struct NoDma;
-impl_peripheral!(NoDma);
 // safety: must be called only once at startup
 pub(crate) unsafe fn init(
    cs: critical_section::CriticalSection,
diff --git a/embassy-stm32/src/dma/ringbuffer.rs b/embassy-stm32/src/dma/ringbuffer.rs
deleted file mode 100644
index 23f1d67d5..000000000
--- a/embassy-stm32/src/dma/ringbuffer.rs
+++ /dev/null
@@ -1,668 +0,0 @@
-#![cfg_attr(gpdma, allow(unused))]
-use core::future::poll_fn;
-use core::ops::Range;
-use core::sync::atomic::{compiler_fence, Ordering};
-use core::task::{Poll, Waker};
-use super::word::Word;
-/// A "read-only" ring-buffer to be used together with the DMA controller which
-/// writes in a circular way, "uncontrolled" to the buffer.
-///
-/// A snapshot of the ring buffer state can be attained by setting the `ndtr` field
-/// to the current register value. `ndtr` describes the current position of the DMA
-/// write.
-///
-/// # Buffer layout
-///
-/// ```text
-/// Without wraparound:                             With wraparound:
-///
-///  + buf                      +--- NDTR ---+       + buf        +---------- NDTR ----------+
-///  |                          |            |       |            |                          |
-///  v                          v            v       v            v                          v
-/// +-----------------------------------------+     +-----------------------------------------+
-/// |oooooooooooXXXXXXXXXXXXXXXXoooooooooooooo|     |XXXXXXXXXXXXXooooooooooooXXXXXXXXXXXXXXXX|
-/// +-----------------------------------------+     +-----------------------------------------+
-///  ^          ^               ^                    ^            ^           ^
-///  |          |               |                    |            |           |
-///  +- start --+               |                    +- end ------+           |
-///  |                          |                    |                        |
-///  +- end --------------------+                    +- start ----------------+
-/// ```
-pub struct ReadableDmaRingBuffer<'a, W: Word> {
-    pub(crate) dma_buf: &'a mut [W],
-    start: usize,
-}
-#[derive(Debug, PartialEq)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-pub struct OverrunError;
-pub trait DmaCtrl {
-    /// Get the NDTR register value, i.e. the space left in the underlying
-    /// buffer until the dma writer wraps.
-    fn get_remaining_transfers(&self) -> usize;
-    /// Get the transfer completed counter.
-    /// This counter is incremented by the dma controller when NDTR is reloaded,
-    /// i.e. when the writing wraps.
-    fn get_complete_count(&self) -> usize;
-    /// Reset the transfer completed counter to 0 and return the value just prior to the reset.
-    fn reset_complete_count(&mut self) -> usize;
-    /// Set the waker for a running poll_fn
-    fn set_waker(&mut self, waker: &Waker);
-}
-impl<'a, W: Word> ReadableDmaRingBuffer<'a, W> {
-    pub fn new(dma_buf: &'a mut [W]) -> Self {
-        Self { dma_buf, start: 0 }
-    }
-    /// Reset the ring buffer to its initial state
-    pub fn clear(&mut self, dma: &mut impl DmaCtrl) {
-        self.start = 0;
-        dma.reset_complete_count();
-    }
-    /// The capacity of the ringbuffer
-    pub const fn cap(&self) -> usize {
-        self.dma_buf.len()
-    }
-    /// The current position of the ringbuffer
-    fn pos(&self, dma: &mut impl DmaCtrl) -> usize {
-        self.cap() - dma.get_remaining_transfers()
-    }
-    /// Read an exact number of elements from the ringbuffer.
-    ///
-    /// Returns the remaining number of elements available for immediate reading.
-    /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
-    ///
-    /// Async/Wake Behavior:
-    /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
-    /// and when it wraps around. This means that when called with a buffer of length 'M', when this
-    /// ring buffer was created with a buffer of size 'N':
-    /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
-    /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
-    pub async fn read_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &mut [W]) -> Result<usize, OverrunError> {
-        let mut read_data = 0;
-        let buffer_len = buffer.len();
-        poll_fn(|cx| {
-            dma.set_waker(cx.waker());
-            compiler_fence(Ordering::SeqCst);
-            match self.read(dma, &mut buffer[read_data..buffer_len]) {
-                Ok((len, remaining)) => {
-                    read_data += len;
-                    if read_data == buffer_len {
-                        Poll::Ready(Ok(remaining))
-                    } else {
-                        Poll::Pending
-                    }
-                }
-                Err(e) => Poll::Ready(Err(e)),
-            }
-        })
-        .await
-    }
-    /// Read elements from the ring buffer
-    /// Return a tuple of the length read and the length remaining in the buffer
-    /// If not all of the elements were read, then there will be some elements in the buffer remaining
-    /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
-    /// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
-    pub fn read(&mut self, dma: &mut impl DmaCtrl, buf: &mut [W]) -> Result<(usize, usize), OverrunError> {
-        /*
-            This algorithm is optimistic: we assume we haven't overrun more than a full buffer and then check
-            after we've done our work to see we have. This is because on stm32, an interrupt is not guaranteed
-            to fire in the same clock cycle that a register is read, so checking get_complete_count early does
-            not yield relevant information.
-            Therefore, the only variable we really need to know is ndtr. If the dma has overrun by more than a full
-            buffer, we will do a bit more work than we have to, but algorithms should not be optimized for error
-            conditions.
-            After we've done our work, we confirm that we haven't overrun more than a full buffer, and also that
-            the dma has not overrun within the data we could have copied. We check the data we could have copied
-            rather than the data we actually copied because it costs nothing and confirms an error condition
-            earlier.
-        */
-        let end = self.pos(dma);
-        if self.start == end && dma.get_complete_count() == 0 {
-            // No elements are available in the buffer
-            Ok((0, self.cap()))
-        } else if self.start < end {
-            // The available, unread portion in the ring buffer DOES NOT wrap
-            // Copy out the elements from the dma buffer
-            let len = self.copy_to(buf, self.start..end);
-            compiler_fence(Ordering::SeqCst);
-            /*
-                first, check if the dma has wrapped at all if it's after end
-                or more than once if it's before start
-                this is in a critical section to try to reduce mushy behavior.
-                it's not ideal but it's the best we can do
-                then, get the current position of of the dma write and check
-                if it's inside data we could have copied
-            */
-            let (pos, complete_count) = critical_section::with(|_| (self.pos(dma), dma.get_complete_count()));
-            if (pos >= self.start && pos < end) || (complete_count > 0 && pos >= end) || complete_count > 1 {
-                Err(OverrunError)
-            } else {
-                self.start = (self.start + len) % self.cap();
-                Ok((len, self.cap() - self.start))
-            }
-        } else if self.start + buf.len() < self.cap() {
-            // The available, unread portion in the ring buffer DOES wrap
-            // The DMA writer has wrapped since we last read and is currently
-            // writing (or the next byte added will be) in the beginning of the ring buffer.
-            // The provided read buffer is not large enough to include all elements from the tail of the dma buffer.
-            // Copy out from the dma buffer
-            let len = self.copy_to(buf, self.start..self.cap());
-            compiler_fence(Ordering::SeqCst);
-            /*
-                first, check if the dma has wrapped around more than once
-                then, get the current position of of the dma write and check
-                if it's inside data we could have copied
-            */
-            let pos = self.pos(dma);
-            if pos > self.start || pos < end || dma.get_complete_count() > 1 {
-                Err(OverrunError)
-            } else {
-                self.start = (self.start + len) % self.cap();
-                Ok((len, self.start + end))
-            }
-        } else {
-            // The available, unread portion in the ring buffer DOES wrap
-            // The DMA writer has wrapped since we last read and is currently
-            // writing (or the next byte added will be) in the beginning of the ring buffer.
-            // The provided read buffer is large enough to include all elements from the tail of the dma buffer,
-            // so the next read will not have any unread tail elements in the ring buffer.
-            // Copy out from the dma buffer
-            let tail = self.copy_to(buf, self.start..self.cap());
-            let head = self.copy_to(&mut buf[tail..], 0..end);
-            compiler_fence(Ordering::SeqCst);
-            /*
-                first, check if the dma has wrapped around more than once
-                then, get the current position of of the dma write and check
-                if it's inside data we could have copied
-            */
-            let pos = self.pos(dma);
-            if pos > self.start || pos < end || dma.reset_complete_count() > 1 {
-                Err(OverrunError)
-            } else {
-                self.start = head;
-                Ok((tail + head, self.cap() - self.start))
-            }
-        }
-    }
-    /// Copy from the dma buffer at `data_range` into `buf`
-    fn copy_to(&mut self, buf: &mut [W], data_range: Range<usize>) -> usize {
-        // Limit the number of elements that can be copied
-        let length = usize::min(data_range.len(), buf.len());
-        // Copy from dma buffer into read buffer
-        // We need to do it like this instead of a simple copy_from_slice() because
-        // reading from a part of memory that may be simultaneously written to is unsafe
-        unsafe {
-            let dma_buf = self.dma_buf.as_ptr();
-            for i in 0..length {
-                buf[i] = core::ptr::read_volatile(dma_buf.offset((data_range.start + i) as isize));
-            }
-        }
-        length
-    }
-}
-pub struct WritableDmaRingBuffer<'a, W: Word> {
-    pub(crate) dma_buf: &'a mut [W],
-    end: usize,
-}
-impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
-    pub fn new(dma_buf: &'a mut [W]) -> Self {
-        Self { dma_buf, end: 0 }
-    }
-    /// Reset the ring buffer to its initial state
-    pub fn clear(&mut self, dma: &mut impl DmaCtrl) {
-        self.end = 0;
-        dma.reset_complete_count();
-    }
-    /// The capacity of the ringbuffer
-    pub const fn cap(&self) -> usize {
-        self.dma_buf.len()
-    }
-    /// The current position of the ringbuffer
-    fn pos(&self, dma: &mut impl DmaCtrl) -> usize {
-        self.cap() - dma.get_remaining_transfers()
-    }
-    /// Write elements directly to the buffer. This must be done before the DMA is started
-    /// or after the buffer has been cleared using `clear()`.
-    pub fn write_immediate(&mut self, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
-        if self.end != 0 {
-            return Err(OverrunError);
-        }
-        let written = self.copy_from(buffer, 0..self.cap());
-        self.end = written % self.cap();
-        Ok((written, self.cap() - written))
-    }
-    /// Write an exact number of elements to the ringbuffer.
-    pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, OverrunError> {
-        let mut written_data = 0;
-        let buffer_len = buffer.len();
-        poll_fn(|cx| {
-            dma.set_waker(cx.waker());
-            compiler_fence(Ordering::SeqCst);
-            match self.write(dma, &buffer[written_data..buffer_len]) {
-                Ok((len, remaining)) => {
-                    written_data += len;
-                    if written_data == buffer_len {
-                        Poll::Ready(Ok(remaining))
-                    } else {
-                        Poll::Pending
-                    }
-                }
-                Err(e) => Poll::Ready(Err(e)),
-            }
-        })
-        .await
-    }
-    /// Write elements from the ring buffer
-    /// Return a tuple of the length written and the capacity remaining to be written in the buffer
-    pub fn write(&mut self, dma: &mut impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> {
-        let start = self.pos(dma);
-        if start > self.end {
-            // The occupied portion in the ring buffer DOES wrap
-            let len = self.copy_from(buf, self.end..start);
-            compiler_fence(Ordering::SeqCst);
-            // Confirm that the DMA is not inside data we could have written
-            let (pos, complete_count) = critical_section::with(|_| (self.pos(dma), dma.get_complete_count()));
-            if (pos >= self.end && pos < start) || (complete_count > 0 && pos >= start) || complete_count > 1 {
-                Err(OverrunError)
-            } else {
-                self.end = (self.end + len) % self.cap();
-                Ok((len, self.cap() - (start - self.end)))
-            }
-        } else if start == self.end && dma.get_complete_count() == 0 {
-            Ok((0, 0))
-        } else if start <= self.end && self.end + buf.len() < self.cap() {
-            // The occupied portion in the ring buffer DOES NOT wrap
-            // and copying elements into the buffer WILL NOT cause it to
-            // Copy into the dma buffer
-            let len = self.copy_from(buf, self.end..self.cap());
-            compiler_fence(Ordering::SeqCst);
-            // Confirm that the DMA is not inside data we could have written
-            let pos = self.pos(dma);
-            if pos > self.end || pos < start || dma.get_complete_count() > 1 {
-                Err(OverrunError)
-            } else {
-                self.end = (self.end + len) % self.cap();
-                Ok((len, self.cap() - (self.end - start)))
-            }
-        } else {
-            // The occupied portion in the ring buffer DOES NOT wrap
-            // and copying elements into the buffer WILL cause it to
-            let tail = self.copy_from(buf, self.end..self.cap());
-            let head = self.copy_from(&buf[tail..], 0..start);
-            compiler_fence(Ordering::SeqCst);
-            // Confirm that the DMA is not inside data we could have written
-            let pos = self.pos(dma);
-            if pos > self.end || pos < start || dma.reset_complete_count() > 1 {
-                Err(OverrunError)
-            } else {
-                self.end = head;
-                Ok((tail + head, self.cap() - (start - self.end)))
-            }
-        }
-    }
-    /// Copy into the dma buffer at `data_range` from `buf`
-    fn copy_from(&mut self, buf: &[W], data_range: Range<usize>) -> usize {
-        // Limit the number of elements that can be copied
-        let length = usize::min(data_range.len(), buf.len());
-        // Copy into dma buffer from read buffer
-        // We need to do it like this instead of a simple copy_from_slice() because
-        // reading from a part of memory that may be simultaneously written to is unsafe
-        unsafe {
-            let dma_buf = self.dma_buf.as_mut_ptr();
-            for i in 0..length {
-                core::ptr::write_volatile(dma_buf.offset((data_range.start + i) as isize), buf[i]);
-            }
-        }
-        length
-    }
-}
-#[cfg(test)]
-mod tests {
-    use core::array;
-    use std::{cell, vec};
-    use super::*;
-    #[allow(dead_code)]
-    #[derive(PartialEq, Debug)]
-    enum TestCircularTransferRequest {
-        GetCompleteCount(usize),
-        ResetCompleteCount(usize),
-        PositionRequest(usize),
-    }
-    struct TestCircularTransfer {
-        len: usize,
-        requests: cell::RefCell<vec::Vec<TestCircularTransferRequest>>,
-    }
-    impl DmaCtrl for TestCircularTransfer {
-        fn get_remaining_transfers(&self) -> usize {
-            match self.requests.borrow_mut().pop().unwrap() {
-                TestCircularTransferRequest::PositionRequest(pos) => {
-                    let len = self.len;
-                    assert!(len >= pos);
-                    len - pos
-                }
-                _ => unreachable!(),
-            }
-        }
-        fn get_complete_count(&self) -> usize {
-            match self.requests.borrow_mut().pop().unwrap() {
-                TestCircularTransferRequest::GetCompleteCount(complete_count) => complete_count,
-                _ => unreachable!(),
-            }
-        }
-        fn reset_complete_count(&mut self) -> usize {
-            match self.requests.get_mut().pop().unwrap() {
-                TestCircularTransferRequest::ResetCompleteCount(complete_count) => complete_count,
-                _ => unreachable!(),
-            }
-        }
-        fn set_waker(&mut self, waker: &Waker) {}
-    }
-    impl TestCircularTransfer {
-        pub fn new(len: usize) -> Self {
-            Self {
-                requests: cell::RefCell::new(vec![]),
-                len,
-            }
-        }
-        pub fn setup(&self, mut requests: vec::Vec<TestCircularTransferRequest>) {
-            requests.reverse();
-            self.requests.replace(requests);
-        }
-    }
-    #[test]
-    fn empty_and_read_not_started() {
-        let mut dma_buf = [0u8; 16];
-        let ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-    }
-    #[test]
-    fn can_read() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(8),
-            TestCircularTransferRequest::PositionRequest(10),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 2];
-        assert_eq!(2, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!([0, 1], buf);
-        assert_eq!(2, ringbuf.start);
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(10),
-            TestCircularTransferRequest::PositionRequest(12),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 2];
-        assert_eq!(2, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!([2, 3], buf);
-        assert_eq!(4, ringbuf.start);
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(12),
-            TestCircularTransferRequest::PositionRequest(14),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 8];
-        assert_eq!(8, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!([4, 5, 6, 7, 8, 9], buf[..6]);
-        assert_eq!(12, ringbuf.start);
-    }
-    #[test]
-    fn can_read_with_wrap() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        /*
-            Read to close to the end of the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(14),
-            TestCircularTransferRequest::PositionRequest(16),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 14];
-        assert_eq!(14, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(14, ringbuf.start);
-        /*
-            Now, read around the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::PositionRequest(8),
-            TestCircularTransferRequest::ResetCompleteCount(1),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(6, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(4, ringbuf.start);
-    }
-    #[test]
-    fn can_read_when_dma_writer_is_wrapped_and_read_does_not_wrap() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        /*
-            Read to close to the end of the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(14),
-            TestCircularTransferRequest::PositionRequest(16),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 14];
-        assert_eq!(14, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(14, ringbuf.start);
-        /*
-            Now, read to the end of the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::PositionRequest(8),
-            TestCircularTransferRequest::ResetCompleteCount(1),
-        ]);
-        let mut buf = [0; 2];
-        assert_eq!(2, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(0, ringbuf.start);
-    }
-    #[test]
-    fn can_read_when_dma_writer_wraps_once_with_same_ndtr() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        /*
-            Read to about the middle of the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(6, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(6, ringbuf.start);
-        /*
-            Now, wrap the DMA controller around
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::GetCompleteCount(1),
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::GetCompleteCount(1),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(6, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(12, ringbuf.start);
-    }
-    #[test]
-    fn cannot_read_when_dma_writer_overwrites_during_not_wrapping_read() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        /*
-            Read a few bytes
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(2),
-            TestCircularTransferRequest::PositionRequest(2),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(2, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(2, ringbuf.start);
-        /*
-            Now, overtake the reader
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(4),
-            TestCircularTransferRequest::PositionRequest(6),
-            TestCircularTransferRequest::GetCompleteCount(1),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(OverrunError, ringbuf.read(&mut dma, &mut buf).unwrap_err());
-    }
-    #[test]
-    fn cannot_read_when_dma_writer_overwrites_during_wrapping_read() {
-        let mut dma = TestCircularTransfer::new(16);
-        let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
-        let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
-        assert_eq!(0, ringbuf.start);
-        assert_eq!(16, ringbuf.cap());
-        /*
-            Read to close to the end of the buffer
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(14),
-            TestCircularTransferRequest::PositionRequest(16),
-            TestCircularTransferRequest::GetCompleteCount(0),
-        ]);
-        let mut buf = [0; 14];
-        assert_eq!(14, ringbuf.read(&mut dma, &mut buf).unwrap().0);
-        assert_eq!(14, ringbuf.start);
-        /*
-            Now, overtake the reader
-        */
-        dma.setup(vec![
-            TestCircularTransferRequest::PositionRequest(8),
-            TestCircularTransferRequest::PositionRequest(10),
-            TestCircularTransferRequest::ResetCompleteCount(2),
-        ]);
-        let mut buf = [0; 6];
-        assert_eq!(OverrunError, ringbuf.read(&mut dma, &mut buf).unwrap_err());
-    }
-}
diff --git a/embassy-stm32/src/dma/ringbuffer/mod.rs b/embassy-stm32/src/dma/ringbuffer/mod.rs
new file mode 100644
index 000000000..44ea497fe
--- /dev/null
+++ b/embassy-stm32/src/dma/ringbuffer/mod.rs
@@ -0,0 +1,333 @@
+#![cfg_attr(gpdma, allow(unused))]
+use core::future::poll_fn;
+use core::task::{Poll, Waker};
+use crate::dma::word::Word;
+pub trait DmaCtrl {
+    /// Get the NDTR register value, i.e. the space left in the underlying
+    /// buffer until the dma writer wraps.
+    fn get_remaining_transfers(&self) -> usize;
+    /// Reset the transfer completed counter to 0 and return the value just prior to the reset.
+    fn reset_complete_count(&mut self) -> usize;
+    /// Set the waker for a running poll_fn
+    fn set_waker(&mut self, waker: &Waker);
+}
+#[derive(Debug, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    Overrun,
+    /// the newly read DMA positions don't make sense compared to the previous
+    /// ones. This can usually only occur due to wrong Driver implementation, if
+    /// the driver author (or the user using raw metapac code) directly resets
+    /// the channel for instance.
+    DmaUnsynced,
+}
+#[derive(Debug, Clone, Copy, Default)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+struct DmaIndex {
+    complete_count: usize,
+    pos: usize,
+}
+impl DmaIndex {
+    fn reset(&mut self) {
+        self.pos = 0;
+        self.complete_count = 0;
+    }
+    fn as_index(&self, cap: usize, offset: usize) -> usize {
+        (self.pos + offset) % cap
+    }
+    fn dma_sync(&mut self, cap: usize, dma: &mut impl DmaCtrl) {
+        // Important!
+        // The ordering of the first two lines matters!
+        // If changed, the code will detect a wrong +capacity
+        // jump at wrap-around.
+        let count_diff = dma.reset_complete_count();
+        let pos = cap - dma.get_remaining_transfers();
+        self.pos = if pos < self.pos && count_diff == 0 {
+            cap - 1
+        } else {
+            pos
+        };
+        self.complete_count += count_diff;
+    }
+    fn advance(&mut self, cap: usize, steps: usize) {
+        let next = self.pos + steps;
+        self.complete_count += next / cap;
+        self.pos = next % cap;
+    }
+    fn normalize(lhs: &mut DmaIndex, rhs: &mut DmaIndex) {
+        let min_count = lhs.complete_count.min(rhs.complete_count);
+        lhs.complete_count -= min_count;
+        rhs.complete_count -= min_count;
+    }
+    fn diff(&self, cap: usize, rhs: &DmaIndex) -> isize {
+        (self.complete_count * cap + self.pos) as isize - (rhs.complete_count * cap + rhs.pos) as isize
+    }
+}
+pub struct ReadableDmaRingBuffer<'a, W: Word> {
+    dma_buf: &'a mut [W],
+    write_index: DmaIndex,
+    read_index: DmaIndex,
+}
+impl<'a, W: Word> ReadableDmaRingBuffer<'a, W> {
+    /// Construct an empty buffer.
+    pub fn new(dma_buf: &'a mut [W]) -> Self {
+        Self {
+            dma_buf,
+            write_index: Default::default(),
+            read_index: Default::default(),
+        }
+    }
+    /// Reset the ring buffer to its initial state.
+    pub fn reset(&mut self, dma: &mut impl DmaCtrl) {
+        dma.reset_complete_count();
+        self.write_index.reset();
+        self.write_index.dma_sync(self.cap(), dma);
+        self.read_index = self.write_index;
+    }
+    /// Get the full ringbuffer capacity.
+    pub const fn cap(&self) -> usize {
+        self.dma_buf.len()
+    }
+    /// Get the available readable dma samples.
+    pub fn len(&mut self, dma: &mut impl DmaCtrl) -> Result<usize, Error> {
+        self.write_index.dma_sync(self.cap(), dma);
+        DmaIndex::normalize(&mut self.write_index, &mut self.read_index);
+        let diff = self.write_index.diff(self.cap(), &self.read_index);
+        if diff < 0 {
+            Err(Error::DmaUnsynced)
+        } else if diff > self.cap() as isize {
+            Err(Error::Overrun)
+        } else {
+            Ok(diff as usize)
+        }
+    }
+    /// Read elements from the ring buffer.
+    ///
+    /// Return a tuple of the length read and the length remaining in the buffer
+    /// If not all of the elements were read, then there will be some elements in the buffer remaining
+    /// The length remaining is the capacity, ring_buf.len(), less the elements remaining after the read
+    /// Error is returned if the portion to be read was overwritten by the DMA controller,
+    /// in which case the rinbuffer will automatically reset itself.
+    pub fn read(&mut self, dma: &mut impl DmaCtrl, buf: &mut [W]) -> Result<(usize, usize), Error> {
+        self.read_raw(dma, buf).inspect_err(|_e| {
+            self.reset(dma);
+        })
+    }
+    /// Read an exact number of elements from the ringbuffer.
+    ///
+    /// Returns the remaining number of elements available for immediate reading.
+    /// Error is returned if the portion to be read was overwritten by the DMA controller.
+    ///
+    /// Async/Wake Behavior:
+    /// The underlying DMA peripheral only can wake us when its buffer pointer has reached the halfway point,
+    /// and when it wraps around. This means that when called with a buffer of length 'M', when this
+    /// ring buffer was created with a buffer of size 'N':
+    /// - If M equals N/2 or N/2 divides evenly into M, this function will return every N/2 elements read on the DMA source.
+    /// - Otherwise, this function may need up to N/2 extra elements to arrive before returning.
+    pub async fn read_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &mut [W]) -> Result<usize, Error> {
+        let mut read_data = 0;
+        let buffer_len = buffer.len();
+        poll_fn(|cx| {
+            dma.set_waker(cx.waker());
+            match self.read(dma, &mut buffer[read_data..buffer_len]) {
+                Ok((len, remaining)) => {
+                    read_data += len;
+                    if read_data == buffer_len {
+                        Poll::Ready(Ok(remaining))
+                    } else {
+                        Poll::Pending
+                    }
+                }
+                Err(e) => Poll::Ready(Err(e)),
+            }
+        })
+        .await
+    }
+    fn read_raw(&mut self, dma: &mut impl DmaCtrl, buf: &mut [W]) -> Result<(usize, usize), Error> {
+        let readable = self.len(dma)?.min(buf.len());
+        for i in 0..readable {
+            buf[i] = self.read_buf(i);
+        }
+        let available = self.len(dma)?;
+        self.read_index.advance(self.cap(), readable);
+        Ok((readable, available - readable))
+    }
+    fn read_buf(&self, offset: usize) -> W {
+        unsafe {
+            core::ptr::read_volatile(
+                self.dma_buf
+                    .as_ptr()
+                    .offset(self.read_index.as_index(self.cap(), offset) as isize),
+            )
+        }
+    }
+}
+pub struct WritableDmaRingBuffer<'a, W: Word> {
+    dma_buf: &'a mut [W],
+    read_index: DmaIndex,
+    write_index: DmaIndex,
+}
+impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
+    /// Construct a ringbuffer filled with the given buffer data.
+    pub fn new(dma_buf: &'a mut [W]) -> Self {
+        let len = dma_buf.len();
+        Self {
+            dma_buf,
+            read_index: Default::default(),
+            write_index: DmaIndex {
+                complete_count: 0,
+                pos: len,
+            },
+        }
+    }
+    /// Reset the ring buffer to its initial state. The buffer after the reset will be full.
+    pub fn reset(&mut self, dma: &mut impl DmaCtrl) {
+        dma.reset_complete_count();
+        self.read_index.reset();
+        self.read_index.dma_sync(self.cap(), dma);
+        self.write_index = self.read_index;
+        self.write_index.advance(self.cap(), self.cap());
+    }
+    /// Get the remaining writable dma samples.
+    pub fn len(&mut self, dma: &mut impl DmaCtrl) -> Result<usize, Error> {
+        self.read_index.dma_sync(self.cap(), dma);
+        DmaIndex::normalize(&mut self.read_index, &mut self.write_index);
+        let diff = self.write_index.diff(self.cap(), &self.read_index);
+        if diff < 0 {
+            Err(Error::Overrun)
+        } else if diff > self.cap() as isize {
+            Err(Error::DmaUnsynced)
+        } else {
+            Ok(self.cap().saturating_sub(diff as usize))
+        }
+    }
+    /// Get the full ringbuffer capacity.
+    pub const fn cap(&self) -> usize {
+        self.dma_buf.len()
+    }
+    /// Append data to the ring buffer.
+    /// Returns a tuple of the data written and the remaining write capacity in the buffer.
+    /// Error is returned if the portion to be written was previously read by the DMA controller.
+    /// In this case, the ringbuffer will automatically reset itself, giving a full buffer worth of
+    /// leeway between the write index and the DMA.
+    pub fn write(&mut self, dma: &mut impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), Error> {
+        self.write_raw(dma, buf).inspect_err(|_e| {
+            self.reset(dma);
+        })
+    }
+    /// Write elements directly to the buffer.
+    ///
+    /// Subsequent writes will overwrite the content of the buffer, so it is not useful to call this more than once.
+    /// Data is aligned towards the end of the buffer.
+    ///
+    /// In case of success, returns the written length, and the empty space in front of the written block.
+    /// Fails if the data to write exceeds the buffer capacity.
+    pub fn write_immediate(&mut self, buf: &[W]) -> Result<(usize, usize), Error> {
+        if buf.len() > self.cap() {
+            return Err(Error::Overrun);
+        }
+        let start = self.cap() - buf.len();
+        for (i, data) in buf.iter().enumerate() {
+            self.write_buf(start + i, *data)
+        }
+        let written = buf.len().min(self.cap());
+        Ok((written, self.cap() - written))
+    }
+    /// Wait for any ring buffer write error.
+    pub async fn wait_write_error(&mut self, dma: &mut impl DmaCtrl) -> Result<usize, Error> {
+        poll_fn(|cx| {
+            dma.set_waker(cx.waker());
+            match self.len(dma) {
+                Ok(_) => Poll::Pending,
+                Err(e) => Poll::Ready(Err(e)),
+            }
+        })
+        .await
+    }
+    /// Write an exact number of elements to the ringbuffer.
+    pub async fn write_exact(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<usize, Error> {
+        let mut written_data = 0;
+        let buffer_len = buffer.len();
+        poll_fn(|cx| {
+            dma.set_waker(cx.waker());
+            match self.write(dma, &buffer[written_data..buffer_len]) {
+                Ok((len, remaining)) => {
+                    written_data += len;
+                    if written_data == buffer_len {
+                        Poll::Ready(Ok(remaining))
+                    } else {
+                        Poll::Pending
+                    }
+                }
+                Err(e) => Poll::Ready(Err(e)),
+            }
+        })
+        .await
+    }
+    fn write_raw(&mut self, dma: &mut impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), Error> {
+        let writable = self.len(dma)?.min(buf.len());
+        for i in 0..writable {
+            self.write_buf(i, buf[i]);
+        }
+        let available = self.len(dma)?;
+        self.write_index.advance(self.cap(), writable);
+        Ok((writable, available - writable))
+    }
+    fn write_buf(&mut self, offset: usize, value: W) {
+        unsafe {
+            core::ptr::write_volatile(
+                self.dma_buf
+                    .as_mut_ptr()
+                    .offset(self.write_index.as_index(self.cap(), offset) as isize),
+                value,
+            )
+        }
+    }
+}
+#[cfg(test)]
+mod tests;
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/mod.rs b/embassy-stm32/src/dma/ringbuffer/tests/mod.rs
new file mode 100644
index 000000000..6fabedb83
--- /dev/null
+++ b/embassy-stm32/src/dma/ringbuffer/tests/mod.rs
@@ -0,0 +1,90 @@
+use std::{cell, vec};
+use super::*;
+#[allow(unused)]
+#[derive(PartialEq, Debug)]
+enum TestCircularTransferRequest {
+    ResetCompleteCount(usize),
+    PositionRequest(usize),
+}
+#[allow(unused)]
+struct TestCircularTransfer {
+    len: usize,
+    requests: cell::RefCell<vec::Vec<TestCircularTransferRequest>>,
+}
+impl DmaCtrl for TestCircularTransfer {
+    fn get_remaining_transfers(&self) -> usize {
+        match self.requests.borrow_mut().pop().unwrap() {
+            TestCircularTransferRequest::PositionRequest(pos) => {
+                let len = self.len;
+                assert!(len >= pos);
+                len - pos
+            }
+            _ => unreachable!(),
+        }
+    }
+    fn reset_complete_count(&mut self) -> usize {
+        match self.requests.get_mut().pop().unwrap() {
+            TestCircularTransferRequest::ResetCompleteCount(complete_count) => complete_count,
+            _ => unreachable!(),
+        }
+    }
+    fn set_waker(&mut self, _waker: &Waker) {}
+}
+impl TestCircularTransfer {
+    #[allow(unused)]
+    pub fn new(len: usize) -> Self {
+        Self {
+            requests: cell::RefCell::new(vec![]),
+            len,
+        }
+    }
+    #[allow(unused)]
+    pub fn setup(&self, mut requests: vec::Vec<TestCircularTransferRequest>) {
+        requests.reverse();
+        self.requests.replace(requests);
+    }
+}
+const CAP: usize = 16;
+#[test]
+fn dma_index_as_index_returns_index_mod_cap_by_default() {
+    let index = DmaIndex::default();
+    assert_eq!(index.as_index(CAP, 0), 0);
+    assert_eq!(index.as_index(CAP, 1), 1);
+    assert_eq!(index.as_index(CAP, 2), 2);
+    assert_eq!(index.as_index(CAP, 3), 3);
+    assert_eq!(index.as_index(CAP, 4), 4);
+    assert_eq!(index.as_index(CAP, CAP), 0);
+    assert_eq!(index.as_index(CAP, CAP + 1), 1);
+}
+#[test]
+fn dma_index_advancing_increases_as_index() {
+    let mut index = DmaIndex::default();
+    assert_eq!(index.as_index(CAP, 0), 0);
+    index.advance(CAP, 1);
+    assert_eq!(index.as_index(CAP, 0), 1);
+    index.advance(CAP, 1);
+    assert_eq!(index.as_index(CAP, 0), 2);
+    index.advance(CAP, 1);
+    assert_eq!(index.as_index(CAP, 0), 3);
+    index.advance(CAP, 1);
+    assert_eq!(index.as_index(CAP, 0), 4);
+    index.advance(CAP, CAP - 4);
+    assert_eq!(index.as_index(CAP, 0), 0);
+    index.advance(CAP, 1);
+    assert_eq!(index.as_index(CAP, 0), 1);
+}
+mod prop_test;
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
new file mode 100644
index 000000000..661fb1728
--- /dev/null
+++ b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/mod.rs
@@ -0,0 +1,50 @@
+use std::task::Waker;
+use proptest::prop_oneof;
+use proptest::strategy::{self, BoxedStrategy, Strategy as _};
+use proptest_state_machine::{prop_state_machine, ReferenceStateMachine, StateMachineTest};
+use super::*;
+const CAP: usize = 128;
+#[derive(Debug, Default)]
+struct DmaMock {
+    pos: usize,
+    wraps: usize,
+}
+impl DmaMock {
+    pub fn advance(&mut self, steps: usize) {
+        let next = self.pos + steps;
+        self.pos = next % CAP;
+        self.wraps += next / CAP;
+    }
+}
+impl DmaCtrl for DmaMock {
+    fn get_remaining_transfers(&self) -> usize {
+        CAP - self.pos
+    }
+    fn reset_complete_count(&mut self) -> usize {
+        core::mem::replace(&mut self.wraps, 0)
+    }
+    fn set_waker(&mut self, _waker: &Waker) {}
+}
+#[derive(Debug, Clone)]
+enum Status {
+    Available(usize),
+    Failed,
+}
+impl Status {
+    pub fn new(capacity: usize) -> Self {
+        Self::Available(capacity)
+    }
+}
+mod reader;
+mod writer;
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/reader.rs b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/reader.rs
new file mode 100644
index 000000000..4f3957a68
--- /dev/null
+++ b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/reader.rs
@@ -0,0 +1,123 @@
+use core::fmt::Debug;
+use super::*;
+#[derive(Debug, Clone)]
+enum ReaderTransition {
+    Write(usize),
+    Reset,
+    ReadUpTo(usize),
+}
+struct ReaderSM;
+impl ReferenceStateMachine for ReaderSM {
+    type State = Status;
+    type Transition = ReaderTransition;
+    fn init_state() -> BoxedStrategy<Self::State> {
+        strategy::Just(Status::new(0)).boxed()
+    }
+    fn transitions(_state: &Self::State) -> BoxedStrategy<Self::Transition> {
+        prop_oneof![
+            (1..50_usize).prop_map(ReaderTransition::Write),
+            (1..50_usize).prop_map(ReaderTransition::ReadUpTo),
+            strategy::Just(ReaderTransition::Reset),
+        ]
+        .boxed()
+    }
+    fn apply(status: Self::State, transition: &Self::Transition) -> Self::State {
+        match (status, transition) {
+            (_, ReaderTransition::Reset) => Status::Available(0),
+            (Status::Available(x), ReaderTransition::Write(y)) => {
+                if x + y > CAP {
+                    Status::Failed
+                } else {
+                    Status::Available(x + y)
+                }
+            }
+            (Status::Failed, ReaderTransition::Write(_)) => Status::Failed,
+            (Status::Available(x), ReaderTransition::ReadUpTo(y)) => Status::Available(x.saturating_sub(*y)),
+            (Status::Failed, ReaderTransition::ReadUpTo(_)) => Status::Available(0),
+        }
+    }
+}
+struct ReaderSut {
+    status: Status,
+    buffer: *mut [u8],
+    producer: DmaMock,
+    consumer: ReadableDmaRingBuffer<'static, u8>,
+}
+impl Debug for ReaderSut {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        <DmaMock as Debug>::fmt(&self.producer, f)
+    }
+}
+struct ReaderTest;
+impl StateMachineTest for ReaderTest {
+    type SystemUnderTest = ReaderSut;
+    type Reference = ReaderSM;
+    fn init_test(ref_status: &<Self::Reference as ReferenceStateMachine>::State) -> Self::SystemUnderTest {
+        let buffer = Box::into_raw(Box::new([0; CAP]));
+        ReaderSut {
+            status: ref_status.clone(),
+            buffer,
+            producer: DmaMock::default(),
+            consumer: ReadableDmaRingBuffer::new(unsafe { &mut *buffer }),
+        }
+    }
+    fn teardown(state: Self::SystemUnderTest) {
+        unsafe {
+            let _ = Box::from_raw(state.buffer);
+        };
+    }
+    fn apply(
+        mut sut: Self::SystemUnderTest,
+        ref_state: &<Self::Reference as ReferenceStateMachine>::State,
+        transition: <Self::Reference as ReferenceStateMachine>::Transition,
+    ) -> Self::SystemUnderTest {
+        match transition {
+            ReaderTransition::Write(x) => sut.producer.advance(x),
+            ReaderTransition::Reset => {
+                sut.consumer.reset(&mut sut.producer);
+            }
+            ReaderTransition::ReadUpTo(x) => {
+                let status = sut.status;
+                let ReaderSut {
+                    ref mut producer,
+                    ref mut consumer,
+                    ..
+                } = sut;
+                let mut buf = vec![0; x];
+                let res = consumer.read(producer, &mut buf);
+                match status {
+                    Status::Available(n) => {
+                        let readable = x.min(n);
+                        assert_eq!(res.unwrap().0, readable);
+                    }
+                    Status::Failed => assert!(res.is_err()),
+                }
+            }
+        }
+        ReaderSut {
+            status: ref_state.clone(),
+            ..sut
+        }
+    }
+}
+prop_state_machine! {
+    #[test]
+    fn reader_state_test(sequential 1..20 => ReaderTest);
+}
diff --git a/embassy-stm32/src/dma/ringbuffer/tests/prop_test/writer.rs b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/writer.rs
new file mode 100644
index 000000000..15433c0ee
--- /dev/null
+++ b/embassy-stm32/src/dma/ringbuffer/tests/prop_test/writer.rs
@@ -0,0 +1,122 @@
+use core::fmt::Debug;
+use super::*;
+#[derive(Debug, Clone)]
+enum WriterTransition {
+    Read(usize),
+    WriteUpTo(usize),
+    Reset,
+}
+struct WriterSM;
+impl ReferenceStateMachine for WriterSM {
+    type State = Status;
+    type Transition = WriterTransition;
+    fn init_state() -> BoxedStrategy<Self::State> {
+        strategy::Just(Status::new(CAP)).boxed()
+    }
+    fn transitions(_state: &Self::State) -> BoxedStrategy<Self::Transition> {
+        prop_oneof![
+            (1..50_usize).prop_map(WriterTransition::Read),
+            (1..50_usize).prop_map(WriterTransition::WriteUpTo),
+            strategy::Just(WriterTransition::Reset),
+        ]
+        .boxed()
+    }
+    fn apply(status: Self::State, transition: &Self::Transition) -> Self::State {
+        match (status, transition) {
+            (_, WriterTransition::Reset) => Status::Available(CAP),
+            (Status::Available(x), WriterTransition::Read(y)) => {
+                if x < *y {
+                    Status::Failed
+                } else {
+                    Status::Available(x - y)
+                }
+            }
+            (Status::Failed, WriterTransition::Read(_)) => Status::Failed,
+            (Status::Available(x), WriterTransition::WriteUpTo(y)) => Status::Available((x + *y).min(CAP)),
+            (Status::Failed, WriterTransition::WriteUpTo(_)) => Status::Available(CAP),
+        }
+    }
+}
+struct WriterSut {
+    status: Status,
+    buffer: *mut [u8],
+    producer: WritableDmaRingBuffer<'static, u8>,
+    consumer: DmaMock,
+}
+impl Debug for WriterSut {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        <DmaMock as Debug>::fmt(&self.consumer, f)
+    }
+}
+struct WriterTest;
+impl StateMachineTest for WriterTest {
+    type SystemUnderTest = WriterSut;
+    type Reference = WriterSM;
+    fn init_test(ref_status: &<Self::Reference as ReferenceStateMachine>::State) -> Self::SystemUnderTest {
+        let buffer = Box::into_raw(Box::new([0; CAP]));
+        WriterSut {
+            status: ref_status.clone(),
+            buffer,
+            producer: WritableDmaRingBuffer::new(unsafe { &mut *buffer }),
+            consumer: DmaMock::default(),
+        }
+    }
+    fn teardown(state: Self::SystemUnderTest) {
+        unsafe {
+            let _ = Box::from_raw(state.buffer);
+        };
+    }
+    fn apply(
+        mut sut: Self::SystemUnderTest,
+        ref_status: &<Self::Reference as ReferenceStateMachine>::State,
+        transition: <Self::Reference as ReferenceStateMachine>::Transition,
+    ) -> Self::SystemUnderTest {
+        match transition {
+            WriterTransition::Read(x) => sut.consumer.advance(x),
+            WriterTransition::Reset => {
+                sut.producer.reset(&mut sut.consumer);
+            }
+            WriterTransition::WriteUpTo(x) => {
+                let status = sut.status;
+                let WriterSut {
+                    ref mut producer,
+                    ref mut consumer,
+                    ..
+                } = sut;
+                let mut buf = vec![0; x];
+                let res = producer.write(consumer, &mut buf);
+                match status {
+                    Status::Available(n) => {
+                        let writable = x.min(CAP - n.min(CAP));
+                        assert_eq!(res.unwrap().0, writable);
+                    }
+                    Status::Failed => assert!(res.is_err()),
+                }
+            }
+        }
+        WriterSut {
+            status: ref_status.clone(),
+            ..sut
+        }
+    }
+}
+prop_state_machine! {
+    #[test]
+    fn writer_state_test(sequential 1..20 => WriterTest);
+}
diff --git a/embassy-stm32/src/dma/util.rs b/embassy-stm32/src/dma/util.rs
index 5aaca57c9..8bf89e2fe 100644
--- a/embassy-stm32/src/dma/util.rs
+++ b/embassy-stm32/src/dma/util.rs
@@ -1,13 +1,12 @@
-use embassy_hal_internal::PeripheralRef;
 use super::word::Word;
 use super::{AnyChannel, Request, Transfer, TransferOptions};
+use crate::Peri;
 /// Convenience wrapper, contains a channel and a request number.
 ///
 /// Commonly used in peripheral drivers that own DMA channels.
 pub(crate) struct ChannelAndRequest<'d> {
-    pub channel: PeripheralRef<'d, AnyChannel>,
+    pub channel: Peri<'d, AnyChannel>,
    pub request: Request,
 }
@@ -18,7 +17,7 @@ impl<'d> ChannelAndRequest<'d> {
        buf: &'a mut [W],
        options: TransferOptions,
    ) -> Transfer<'a> {
-        Transfer::new_read(&mut self.channel, self.request, peri_addr, buf, options)
+        Transfer::new_read(self.channel.reborrow(), self.request, peri_addr, buf, options)
    }
    pub unsafe fn read_raw<'a, W: Word>(
@@ -27,7 +26,7 @@ impl<'d> ChannelAndRequest<'d> {
        buf: *mut [W],
        options: TransferOptions,
    ) -> Transfer<'a> {
-        Transfer::new_read_raw(&mut self.channel, self.request, peri_addr, buf, options)
+        Transfer::new_read_raw(self.channel.reborrow(), self.request, peri_addr, buf, options)
    }
    pub unsafe fn write<'a, W: Word>(
@@ -36,16 +35,16 @@ impl<'d> ChannelAndRequest<'d> {
        peri_addr: *mut W,
        options: TransferOptions,
    ) -> Transfer<'a> {
-        Transfer::new_write(&mut self.channel, self.request, buf, peri_addr, options)
+        Transfer::new_write(self.channel.reborrow(), self.request, buf, peri_addr, options)
    }
-    pub unsafe fn write_raw<'a, W: Word>(
+    pub unsafe fn write_raw<'a, MW: Word, PW: Word>(
        &'a mut self,
-        buf: *const [W],
+        buf: *const [MW],
-        peri_addr: *mut W,
+        peri_addr: *mut PW,
        options: TransferOptions,
    ) -> Transfer<'a> {
-        Transfer::new_write_raw(&mut self.channel, self.request, buf, peri_addr, options)
+        Transfer::new_write_raw(self.channel.reborrow(), self.request, buf, peri_addr, options)
    }
    #[allow(dead_code)]
@@ -56,6 +55,13 @@ impl<'d> ChannelAndRequest<'d> {
        peri_addr: *mut W,
        options: TransferOptions,
    ) -> Transfer<'a> {
-        Transfer::new_write_repeated(&mut self.channel, self.request, repeated, count, peri_addr, options)
+        Transfer::new_write_repeated(
+            self.channel.reborrow(),
+            self.request,
+            repeated,
+            count,
+            peri_addr,
+            options,
+        )
    }
 }
diff --git a/embassy-stm32/src/dsihost.rs b/embassy-stm32/src/dsihost.rs
index 77c3d95c3..e97ccd9d0 100644
--- a/embassy-stm32/src/dsihost.rs
+++ b/embassy-stm32/src/dsihost.rs
@@ -2,12 +2,12 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 //use crate::gpio::{AnyPin, SealedPin};
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 /// Performs a busy-wait delay for a specified number of microseconds.
 pub fn blocking_delay_ms(ms: u32) {
@@ -69,14 +69,12 @@ impl From<PacketType> for u8 {
 /// DSIHOST driver.
 pub struct DsiHost<'d, T: Instance> {
    _peri: PhantomData<&'d mut T>,
-    _te: PeripheralRef<'d, AnyPin>,
+    _te: Peri<'d, AnyPin>,
 }
 impl<'d, T: Instance> DsiHost<'d, T> {
    /// Note: Full-Duplex modes are not supported at this time
-    pub fn new(_peri: impl Peripheral<P = T> + 'd, te: impl Peripheral<P = impl TePin<T>> + 'd) -> Self {
+    pub fn new(_peri: Peri<'d, T>, te: Peri<'d, impl TePin<T>>) -> Self {
-        into_ref!(te);
        rcc::enable_and_reset::<T>();
        // Set Tearing Enable pin according to CubeMx example
@@ -88,7 +86,7 @@ impl<'d, T: Instance> DsiHost<'d, T> {
        */
        Self {
            _peri: PhantomData,
-            _te: te.map_into(),
+            _te: te.into(),
        }
    }
@@ -412,7 +410,7 @@ trait SealedInstance: crate::rcc::SealedRccPeripheral {
 /// DSI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {}
 pin_trait!(TePin, Instance);
diff --git a/embassy-stm32/src/dts/mod.rs b/embassy-stm32/src/dts/mod.rs
new file mode 100644
index 000000000..1f39c8db5
--- /dev/null
+++ b/embassy-stm32/src/dts/mod.rs
@@ -0,0 +1,238 @@
+//! Digital Temperature Sensor (DTS)
+use core::future::poll_fn;
+use core::sync::atomic::{compiler_fence, Ordering};
+use core::task::Poll;
+use embassy_hal_internal::Peri;
+use embassy_sync::waitqueue::AtomicWaker;
+use crate::interrupt::InterruptExt;
+use crate::peripherals::DTS;
+use crate::time::Hertz;
+use crate::{interrupt, pac, rcc};
+mod tsel;
+pub use tsel::TriggerSel;
+#[allow(missing_docs)]
+#[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum SampleTime {
+    ClockCycles1 = 1,
+    ClockCycles2 = 2,
+    ClockCycles3 = 3,
+    ClockCycles4 = 4,
+    ClockCycles5 = 5,
+    ClockCycles6 = 6,
+    ClockCycles7 = 7,
+    ClockCycles8 = 8,
+    ClockCycles9 = 9,
+    ClockCycles10 = 10,
+    ClockCycles11 = 11,
+    ClockCycles12 = 12,
+    ClockCycles13 = 13,
+    ClockCycles14 = 14,
+    ClockCycles15 = 15,
+}
+#[non_exhaustive]
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+/// Config
+pub struct Config {
+    /// Sample time
+    pub sample_time: SampleTime,
+    /// Trigger selection
+    pub trigger: TriggerSel,
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            sample_time: SampleTime::ClockCycles1,
+            trigger: TriggerSel::Software,
+        }
+    }
+}
+/// The read-only factory calibration values used for converting a
+/// measurement to a temperature.
+#[derive(Clone, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct FactoryCalibration {
+    /// The calibration temperature in degrees Celsius.
+    pub t0: u8,
+    /// The frequency at the calibration temperature.
+    pub fmt0: Hertz,
+    /// The ramp coefficient in Hertz per degree Celsius.
+    pub ramp_coeff: u16,
+}
+const MAX_DTS_CLK_FREQ: Hertz = Hertz::mhz(1);
+/// Digital temperature sensor driver.
+pub struct Dts<'d> {
+    _peri: Peri<'d, DTS>,
+}
+static WAKER: AtomicWaker = AtomicWaker::new();
+impl<'d> Dts<'d> {
+    /// Create a new temperature sensor driver.
+    pub fn new(
+        _peri: Peri<'d, DTS>,
+        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::DTS, InterruptHandler> + 'd,
+        config: Config,
+    ) -> Self {
+        rcc::enable_and_reset::<DTS>();
+        let prescaler = rcc::frequency::<DTS>() / MAX_DTS_CLK_FREQ;
+        if prescaler > 127 {
+            panic!("DTS PCLK frequency must be less than 127 MHz.");
+        }
+        Self::regs().cfgr1().modify(|w| {
+            w.set_refclk_sel(false);
+            w.set_hsref_clk_div(prescaler as u8);
+            w.set_q_meas_opt(false);
+            // Software trigger
+            w.set_intrig_sel(0);
+            w.set_smp_time(config.sample_time as u8);
+            w.set_intrig_sel(config.trigger as u8);
+            w.set_start(true);
+            w.set_en(true);
+        });
+        interrupt::DTS.unpend();
+        unsafe { interrupt::DTS.enable() };
+        Self { _peri }
+    }
+    /// Reconfigure the driver.
+    pub fn set_config(&mut self, config: &Config) {
+        Self::regs().cfgr1().modify(|w| {
+            w.set_smp_time(config.sample_time as u8);
+            w.set_intrig_sel(config.trigger as u8);
+        });
+    }
+    /// Get the read-only factory calibration values used for converting a
+    /// measurement to a temperature.
+    pub fn factory_calibration() -> FactoryCalibration {
+        let t0valr1 = Self::regs().t0valr1().read();
+        let t0 = match t0valr1.t0() {
+            0 => 30,
+            1 => 130,
+            _ => unimplemented!(),
+        };
+        let fmt0 = Hertz::hz(t0valr1.fmt0() as u32 * 100);
+        let ramp_coeff = Self::regs().rampvalr().read().ramp_coeff();
+        FactoryCalibration { t0, fmt0, ramp_coeff }
+    }
+    /// Perform an asynchronous temperature measurement. The returned future can
+    /// be awaited to obtain the measurement.
+    ///
+    /// The future returned waits for the next measurement to complete.
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// use embassy_stm32::{bind_interrupts, dts};
+    /// use embassy_stm32::dts::Dts;
+    ///
+    /// bind_interrupts!(struct Irqs {
+    ///     DTS => temp::InterruptHandler;
+    /// });
+    ///
+    /// # async {
+    /// # let p: embassy_stm32::Peripherals = todo!();
+    /// let mut dts = Dts::new(p.DTS, Irqs, Default::default());
+    /// let v: u16 = dts.read().await;
+    /// # };
+    /// ```
+    pub async fn read(&mut self) -> u16 {
+        let r = Self::regs();
+        r.itenr().modify(|w| w.set_iteen(true));
+        poll_fn(|cx| {
+            WAKER.register(cx.waker());
+            if r.itenr().read().iteen() {
+                Poll::Pending
+            } else {
+                Poll::Ready(r.dr().read().mfreq())
+            }
+        })
+        .await
+    }
+    /// Returns the last measurement made, if any.
+    ///
+    /// There is no guarantee that the measurement is recent or that a
+    /// measurement has ever completed.
+    pub fn read_immediate(&mut self) -> u16 {
+        Self::regs().dr().read().mfreq()
+    }
+    fn regs() -> pac::dts::Dts {
+        pac::DTS
+    }
+}
+impl<'d> Drop for Dts<'d> {
+    fn drop(&mut self) {
+        Self::regs().cfgr1().modify(|w| w.set_en(false));
+        rcc::disable::<DTS>();
+    }
+}
+/// Interrupt handler.
+pub struct InterruptHandler {
+    _private: (),
+}
+impl interrupt::typelevel::Handler<interrupt::typelevel::DTS> for InterruptHandler {
+    unsafe fn on_interrupt() {
+        let r = pac::DTS;
+        let (sr, itenr) = (r.sr().read(), r.itenr().read());
+        if (itenr.iteen() && sr.itef()) || (itenr.aiteen() && sr.aitef()) {
+            r.itenr().modify(|w| {
+                w.set_iteen(false);
+                w.set_aiteen(false);
+            });
+            r.icifr().modify(|w| {
+                w.set_citef(true);
+                w.set_caitef(true);
+            });
+        } else if (itenr.itlen() && sr.itlf()) || (itenr.aitlen() && sr.aitlf()) {
+            r.itenr().modify(|w| {
+                w.set_itlen(false);
+                w.set_aitlen(false);
+            });
+            r.icifr().modify(|w| {
+                w.set_citlf(true);
+                w.set_caitlf(true);
+            });
+        } else if (itenr.ithen() && sr.ithf()) || (itenr.aithen() && sr.aithf()) {
+            r.itenr().modify(|w| {
+                w.set_ithen(false);
+                w.set_aithen(false);
+            });
+            r.icifr().modify(|w| {
+                w.set_cithf(true);
+                w.set_caithf(true);
+            });
+        } else {
+            return;
+        }
+        compiler_fence(Ordering::SeqCst);
+        WAKER.wake();
+    }
+}
diff --git a/embassy-stm32/src/dts/tsel.rs b/embassy-stm32/src/dts/tsel.rs
new file mode 100644
index 000000000..99eab6dd8
--- /dev/null
+++ b/embassy-stm32/src/dts/tsel.rs
@@ -0,0 +1,51 @@
+/// Trigger selection for H5
+#[cfg(stm32h5)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM1 CH1
+    Lptim1 = 1,
+    /// LPTIM2 CH1
+    Lptim2 = 2,
+    /// LPTIM3 CH1
+    #[cfg(not(stm32h503))]
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
+/// Trigger selection for H7, except for H7R and H7S
+#[cfg(stm32h7)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM1 OUT
+    Lptim1 = 1,
+    /// LPTIM2 OUT
+    Lptim2 = 2,
+    /// LPTIM3 OUT
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
+/// Trigger selection for H7R and H7S
+#[cfg(stm32h7rs)]
+#[derive(Debug, Copy, Clone, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum TriggerSel {
+    /// Software triggering. Performs continuous measurements.
+    Software = 0,
+    /// LPTIM4 OUT
+    Lptim4 = 1,
+    /// LPTIM2 CH1
+    Lptim2 = 2,
+    /// LPTIM3 CH1
+    Lptim3 = 3,
+    /// EXTI13
+    Exti13 = 4,
+}
diff --git a/embassy-stm32/src/eth/generic_smi.rs b/embassy-stm32/src/eth/generic_phy.rs
index 3b43051f4..774beef80 100644
--- a/embassy-stm32/src/eth/generic_smi.rs
+++ b/embassy-stm32/src/eth/generic_phy.rs
@@ -7,7 +7,7 @@ use embassy_time::{Duration, Timer};
 #[cfg(feature = "time")]
 use futures_util::FutureExt;
-use super::{StationManagement, PHY};
+use super::{Phy, StationManagement};
 #[allow(dead_code)]
 mod phy_consts {
@@ -43,25 +43,71 @@ mod phy_consts {
 use self::phy_consts::*;
 /// Generic SMI Ethernet PHY implementation
-pub struct GenericSMI {
+pub struct GenericPhy {
    phy_addr: u8,
    #[cfg(feature = "time")]
    poll_interval: Duration,
 }
-impl GenericSMI {
+impl GenericPhy {
    /// Construct the PHY. It assumes the address `phy_addr` in the SMI communication
+    ///
+    /// # Panics
+    /// `phy_addr` must be in range `0..32`
    pub fn new(phy_addr: u8) -> Self {
+        assert!(phy_addr < 32);
        Self {
            phy_addr,
            #[cfg(feature = "time")]
            poll_interval: Duration::from_millis(500),
        }
    }
+    /// Construct the PHY. Try to probe all addresses from 0 to 31 during initialization
+    ///
+    /// # Panics
+    /// Initialization panics if PHY didn't respond on any address
+    pub fn new_auto() -> Self {
+        Self {
+            phy_addr: 0xFF,
+            #[cfg(feature = "time")]
+            poll_interval: Duration::from_millis(500),
+        }
+    }
 }
-unsafe impl PHY for GenericSMI {
+// TODO: Factor out to shared functionality
+fn blocking_delay_us(us: u32) {
+    #[cfg(feature = "time")]
+    embassy_time::block_for(Duration::from_micros(us as u64));
+    #[cfg(not(feature = "time"))]
+    {
+        let freq = unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 as u64;
+        let us = us as u64;
+        let cycles = freq * us / 1_000_000;
+        cortex_m::asm::delay(cycles as u32);
+    }
+}
+impl Phy for GenericPhy {
    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S) {
+        // Detect SMI address
+        if self.phy_addr == 0xFF {
+            for addr in 0..32 {
+                sm.smi_write(addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
+                for _ in 0..10 {
+                    if sm.smi_read(addr, PHY_REG_BCR) & PHY_REG_BCR_RESET != PHY_REG_BCR_RESET {
+                        trace!("Found ETH PHY on address {}", addr);
+                        self.phy_addr = addr;
+                        return;
+                    }
+                    // Give PHY a total of 100ms to respond
+                    blocking_delay_us(10000);
+                }
+            }
+            panic!("PHY did not respond");
+        }
        sm.smi_write(self.phy_addr, PHY_REG_BCR, PHY_REG_BCR_RESET);
        while sm.smi_read(self.phy_addr, PHY_REG_BCR) & PHY_REG_BCR_RESET == PHY_REG_BCR_RESET {}
    }
@@ -102,7 +148,7 @@ unsafe impl PHY for GenericSMI {
 }
 /// Public functions for the PHY
-impl GenericSMI {
+impl GenericPhy {
    /// Set the SMI polling interval.
    #[cfg(feature = "time")]
    pub fn set_poll_interval(&mut self, poll_interval: Duration) {
diff --git a/embassy-stm32/src/eth/mod.rs b/embassy-stm32/src/eth/mod.rs
index bfe8a60d6..97d7b4347 100644
--- a/embassy-stm32/src/eth/mod.rs
+++ b/embassy-stm32/src/eth/mod.rs
@@ -4,15 +4,17 @@
 #[cfg_attr(any(eth_v1a, eth_v1b, eth_v1c), path = "v1/mod.rs")]
 #[cfg_attr(eth_v2, path = "v2/mod.rs")]
 mod _version;
-pub mod generic_smi;
+mod generic_phy;
 use core::mem::MaybeUninit;
 use core::task::Context;
+use embassy_hal_internal::PeripheralType;
 use embassy_net_driver::{Capabilities, HardwareAddress, LinkState};
 use embassy_sync::waitqueue::AtomicWaker;
 pub use self::_version::{InterruptHandler, *};
+pub use self::generic_phy::*;
 use crate::rcc::RccPeripheral;
 #[allow(unused)]
@@ -42,11 +44,9 @@ pub struct PacketQueue<const TX: usize, const RX: usize> {
 impl<const TX: usize, const RX: usize> PacketQueue<TX, RX> {
    /// Create a new packet queue.
    pub const fn new() -> Self {
-        const NEW_TDES: TDes = TDes::new();
-        const NEW_RDES: RDes = RDes::new();
        Self {
-            tx_desc: [NEW_TDES; TX],
+            tx_desc: [const { TDes::new() }; TX],
-            rx_desc: [NEW_RDES; RX],
+            rx_desc: [const { RDes::new() }; RX],
            tx_buf: [Packet([0; TX_BUFFER_SIZE]); TX],
            rx_buf: [Packet([0; RX_BUFFER_SIZE]); RX],
        }
@@ -73,9 +73,15 @@ impl<const TX: usize, const RX: usize> PacketQueue<TX, RX> {
 static WAKER: AtomicWaker = AtomicWaker::new();
-impl<'d, T: Instance, P: PHY> embassy_net_driver::Driver for Ethernet<'d, T, P> {
+impl<'d, T: Instance, P: Phy> embassy_net_driver::Driver for Ethernet<'d, T, P> {
-    type RxToken<'a> = RxToken<'a, 'd> where Self: 'a;
+    type RxToken<'a>
-    type TxToken<'a> = TxToken<'a, 'd> where Self: 'a;
+        = RxToken<'a, 'd>
+    where
+        Self: 'a;
+    type TxToken<'a>
+        = TxToken<'a, 'd>
+    where
+        Self: 'a;
    fn receive(&mut self, cx: &mut Context) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
        WAKER.register(cx.waker());
@@ -152,23 +158,15 @@ impl<'a, 'd> embassy_net_driver::TxToken for TxToken<'a, 'd> {
 }
 /// Station Management Interface (SMI) on an ethernet PHY
-///
+pub trait StationManagement {
-/// # Safety
-///
-/// The methods cannot move out of self
-pub unsafe trait StationManagement {
    /// Read a register over SMI.
    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16;
    /// Write a register over SMI.
    fn smi_write(&mut self, phy_addr: u8, reg: u8, val: u16);
 }
-/// Traits for an Ethernet PHY
+/// Trait for an Ethernet PHY
-///
+pub trait Phy {
-/// # Safety
-///
-/// The methods cannot move S
-pub unsafe trait PHY {
    /// Reset PHY and wait for it to come out of reset.
    fn phy_reset<S: StationManagement>(&mut self, sm: &mut S);
    /// PHY initialisation.
@@ -177,13 +175,32 @@ pub unsafe trait PHY {
    fn poll_link<S: StationManagement>(&mut self, sm: &mut S, cx: &mut Context) -> bool;
 }
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
+    /// Directly expose the SMI interface used by the Ethernet driver.
+    ///
+    /// This can be used to for example configure special PHY registers for compliance testing.
+    pub fn station_management(&mut self) -> &mut impl StationManagement {
+        &mut self.station_management
+    }
+    /// Access the user-supplied `Phy`.
+    pub fn phy(&self) -> &P {
+        &self.phy
+    }
+    /// Mutably access the user-supplied `Phy`.
+    pub fn phy_mut(&mut self) -> &mut P {
+        &mut self.phy
+    }
+}
 trait SealedInstance {
    fn regs() -> crate::pac::eth::Eth;
 }
 /// Ethernet instance.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
 impl SealedInstance for crate::peripherals::ETH {
    fn regs() -> crate::pac::eth::Eth {
diff --git a/embassy-stm32/src/eth/v1/mod.rs b/embassy-stm32/src/eth/v1/mod.rs
index cce75ece7..01e321bce 100644
--- a/embassy-stm32/src/eth/v1/mod.rs
+++ b/embassy-stm32/src/eth/v1/mod.rs
@@ -6,7 +6,7 @@ mod tx_desc;
 use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
 pub(crate) use self::rx_desc::{RDes, RDesRing};
@@ -15,6 +15,7 @@ use super::*;
 #[cfg(eth_v1a)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
+use crate::interrupt;
 use crate::interrupt::InterruptExt;
 #[cfg(eth_v1a)]
 use crate::pac::AFIO;
@@ -22,7 +23,6 @@ use crate::pac::AFIO;
 use crate::pac::SYSCFG;
 use crate::pac::{ETH, RCC};
 use crate::rcc::SealedRccPeripheral;
-use crate::{interrupt, Peripheral};
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -46,17 +46,23 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandl
 }
 /// Ethernet driver.
-pub struct Ethernet<'d, T: Instance, P: PHY> {
+pub struct Ethernet<'d, T: Instance, P: Phy> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
    pub(crate) tx: TDesRing<'d>,
    pub(crate) rx: RDesRing<'d>,
-    pins: [PeripheralRef<'d, AnyPin>; 9],
+    pins: Pins<'d>,
    pub(crate) phy: P,
    pub(crate) station_management: EthernetStationManagement<T>,
    pub(crate) mac_addr: [u8; 6],
 }
+/// Pins of ethernet driver.
+enum Pins<'d> {
+    Rmii([Peri<'d, AnyPin>; 9]),
+    Mii([Peri<'d, AnyPin>; 14]),
+}
 #[cfg(eth_v1a)]
 macro_rules! config_in_pins {
    ($($pin:ident),*) => {
@@ -91,26 +97,24 @@ macro_rules! config_pins {
    };
 }
-impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
    /// safety: the returned instance is not leak-safe
    pub fn new<const TX: usize, const RX: usize>(
        queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
+        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
+        mdc: Peri<'d, impl MDCPin<T>>,
-        crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
+        crs: Peri<'d, impl CRSPin<T>>,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
        phy: P,
        mac_addr: [u8; 6],
    ) -> Self {
-        into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
        // Enable the necessary Clocks
        #[cfg(eth_v1a)]
        critical_section::with(|_| {
@@ -148,6 +152,29 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
        #[cfg(any(eth_v1b, eth_v1c))]
        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
+        let pins = Pins::Rmii([
+            ref_clk.into(),
+            mdio.into(),
+            mdc.into(),
+            crs.into(),
+            rx_d0.into(),
+            rx_d1.into(),
+            tx_d0.into(),
+            tx_d1.into(),
+            tx_en.into(),
+        ]);
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+    }
+    fn new_inner<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        pins: Pins<'d>,
+        phy: P,
+        mac_addr: [u8; 6],
+    ) -> Self {
        let dma = T::regs().ethernet_dma();
        let mac = T::regs().ethernet_mac();
@@ -159,8 +186,13 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
            w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
            w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
            w.set_fes(Fes::FES100); // fast ethernet speed
-            w.set_dm(Dm::FULLDUPLEX); // full duplex
+            w.set_dm(Dm::FULL_DUPLEX); // full duplex
-                                      // TODO: Carrier sense ? ECRSFD
+                                       // TODO: Carrier sense ? ECRSFD
+        });
+        // Set the mac to pass all multicast packets
+        mac.macffr().modify(|w| {
+            w.set_pam(true);
        });
        // Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
@@ -181,8 +213,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
        // Transfer and Forward, Receive and Forward
        dma.dmaomr().modify(|w| {
-            w.set_tsf(Tsf::STOREFORWARD);
+            w.set_tsf(Tsf::STORE_FORWARD);
-            w.set_rsf(Rsf::STOREFORWARD);
+            w.set_rsf(Rsf::STORE_FORWARD);
        });
        dma.dmabmr().modify(|w| {
@@ -207,18 +239,6 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
            }
        };
-        let pins = [
-            ref_clk.map_into(),
-            mdio.map_into(),
-            mdc.map_into(),
-            crs.map_into(),
-            rx_d0.map_into(),
-            rx_d1.map_into(),
-            tx_d0.map_into(),
-            tx_d1.map_into(),
-            tx_en.map_into(),
-        ];
        let mut this = Self {
            _peri: peri,
            pins,
@@ -264,15 +284,96 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
        this
    }
+    /// Create a new MII ethernet driver using 14 pins.
+    pub fn new_mii<const TX: usize, const RX: usize>(
+        queue: &'d mut PacketQueue<TX, RX>,
+        peri: Peri<'d, T>,
+        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
+        rx_clk: Peri<'d, impl RXClkPin<T>>,
+        tx_clk: Peri<'d, impl TXClkPin<T>>,
+        mdio: Peri<'d, impl MDIOPin<T>>,
+        mdc: Peri<'d, impl MDCPin<T>>,
+        rxdv: Peri<'d, impl RXDVPin<T>>,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
+        rx_d2: Peri<'d, impl RXD2Pin<T>>,
+        rx_d3: Peri<'d, impl RXD3Pin<T>>,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
+        tx_d2: Peri<'d, impl TXD2Pin<T>>,
+        tx_d3: Peri<'d, impl TXD3Pin<T>>,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
+        phy: P,
+        mac_addr: [u8; 6],
+    ) -> Self {
+        // TODO: Handle optional signals like CRS, MII_COL, RX_ER?
+        // Enable the necessary Clocks
+        #[cfg(eth_v1a)]
+        critical_section::with(|_| {
+            RCC.apb2enr().modify(|w| w.set_afioen(true));
+            // Select MII (Media Independent Interface)
+            // Must be done prior to enabling peripheral clock
+            AFIO.mapr().modify(|w| w.set_mii_rmii_sel(false));
+            RCC.ahbenr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+        });
+        #[cfg(any(eth_v1b, eth_v1c))]
+        critical_section::with(|_| {
+            RCC.ahb1enr().modify(|w| {
+                w.set_ethen(true);
+                w.set_ethtxen(true);
+                w.set_ethrxen(true);
+            });
+            // MII (Media Independent Interface)
+            SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(false));
+        });
+        #[cfg(eth_v1a)]
+        {
+            config_in_pins!(rx_clk, tx_clk, rx_d0, rx_d1, rx_d2, rx_d3, rxdv);
+            config_af_pins!(mdio, mdc, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        }
+        #[cfg(any(eth_v1b, eth_v1c))]
+        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
+        let pins = Pins::Mii([
+            rx_clk.into(),
+            tx_clk.into(),
+            mdio.into(),
+            mdc.into(),
+            rxdv.into(),
+            rx_d0.into(),
+            rx_d1.into(),
+            rx_d2.into(),
+            rx_d3.into(),
+            tx_d0.into(),
+            tx_d1.into(),
+            tx_d2.into(),
+            tx_d3.into(),
+            tx_en.into(),
+        ]);
+        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
+    }
 }
 /// Ethernet station management interface.
-pub struct EthernetStationManagement<T: Instance> {
+pub(crate) struct EthernetStationManagement<T: Instance> {
    peri: PhantomData<T>,
    clock_range: Cr,
 }
-unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
+impl<T: Instance> StationManagement for EthernetStationManagement<T> {
    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
        let mac = T::regs().ethernet_mac();
@@ -302,7 +403,7 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
    }
 }
-impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
+impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
    fn drop(&mut self) {
        let dma = T::regs().ethernet_dma();
        let mac = T::regs().ethernet_mac();
@@ -319,7 +420,10 @@ impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
        dma.dmaomr().modify(|w| w.set_sr(DmaomrSr::STOPPED));
        critical_section::with(|_| {
-            for pin in self.pins.iter_mut() {
+            for pin in match self.pins {
+                Pins::Rmii(ref mut pins) => pins.iter_mut(),
+                Pins::Mii(ref mut pins) => pins.iter_mut(),
+            } {
                pin.set_as_disconnected();
            }
        })
diff --git a/embassy-stm32/src/eth/v1/rx_desc.rs b/embassy-stm32/src/eth/v1/rx_desc.rs
index 668378bea..2a46c1895 100644
--- a/embassy-stm32/src/eth/v1/rx_desc.rs
+++ b/embassy-stm32/src/eth/v1/rx_desc.rs
@@ -168,15 +168,15 @@ impl<'a> RDesRing<'a> {
            //  Reset or Stop Receive Command issued
            Rps::STOPPED => RunningState::Stopped,
            //  Fetching receive transfer descriptor
-            Rps::RUNNINGFETCHING => RunningState::Running,
+            Rps::RUNNING_FETCHING => RunningState::Running,
            //  Waiting for receive packet
-            Rps::RUNNINGWAITING => RunningState::Running,
+            Rps::RUNNING_WAITING => RunningState::Running,
            //  Receive descriptor unavailable
            Rps::SUSPENDED => RunningState::Stopped,
            //  Closing receive descriptor
            Rps::_RESERVED_5 => RunningState::Running,
            //  Transferring the receive packet data from receive buffer to host memory
-            Rps::RUNNINGWRITING => RunningState::Running,
+            Rps::RUNNING_WRITING => RunningState::Running,
            _ => RunningState::Unknown,
        }
    }
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index b26f08cd9..034c5dd88 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -3,16 +3,16 @@ mod descriptors;
 use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 use stm32_metapac::syscfg::vals::EthSelPhy;
 pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
 use super::*;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin as _, Speed};
+use crate::interrupt;
 use crate::interrupt::InterruptExt;
 use crate::pac::ETH;
 use crate::rcc::SealedRccPeripheral;
-use crate::{interrupt, Peripheral};
 /// Interrupt handler.
 pub struct InterruptHandler {}
@@ -36,8 +36,8 @@ impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandl
 }
 /// Ethernet driver.
-pub struct Ethernet<'d, T: Instance, P: PHY> {
+pub struct Ethernet<'d, T: Instance, P: Phy> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
    pub(crate) tx: TDesRing<'d>,
    pub(crate) rx: RDesRing<'d>,
    pins: Pins<'d>,
@@ -48,8 +48,8 @@ pub struct Ethernet<'d, T: Instance, P: PHY> {
 /// Pins of ethernet driver.
 enum Pins<'d> {
-    Rmii([PeripheralRef<'d, AnyPin>; 9]),
+    Rmii([Peri<'d, AnyPin>; 9]),
-    Mii([PeripheralRef<'d, AnyPin>; 14]),
+    Mii([Peri<'d, AnyPin>; 14]),
 }
 macro_rules! config_pins {
@@ -63,21 +63,21 @@ macro_rules! config_pins {
    };
 }
-impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
+impl<'d, T: Instance, P: Phy> Ethernet<'d, T, P> {
    /// Create a new RMII ethernet driver using 9 pins.
    pub fn new<const TX: usize, const RX: usize>(
        queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
+        ref_clk: Peri<'d, impl RefClkPin<T>>,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
+        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
+        mdc: Peri<'d, impl MDCPin<T>>,
-        crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
+        crs: Peri<'d, impl CRSPin<T>>,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
        phy: P,
        mac_addr: [u8; 6],
    ) -> Self {
@@ -92,19 +92,18 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
        });
-        into_ref!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
        config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
        let pins = Pins::Rmii([
-            ref_clk.map_into(),
+            ref_clk.into(),
-            mdio.map_into(),
+            mdio.into(),
-            mdc.map_into(),
+            mdc.into(),
-            crs.map_into(),
+            crs.into(),
-            rx_d0.map_into(),
+            rx_d0.into(),
-            rx_d1.map_into(),
+            rx_d1.into(),
-            tx_d0.map_into(),
+            tx_d0.into(),
-            tx_d1.map_into(),
+            tx_d1.into(),
-            tx_en.map_into(),
+            tx_en.into(),
        ]);
        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
@@ -113,22 +112,22 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
    /// Create a new MII ethernet driver using 14 pins.
    pub fn new_mii<const TX: usize, const RX: usize>(
        queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
-        rx_clk: impl Peripheral<P = impl RXClkPin<T>> + 'd,
+        rx_clk: Peri<'d, impl RXClkPin<T>>,
-        tx_clk: impl Peripheral<P = impl TXClkPin<T>> + 'd,
+        tx_clk: Peri<'d, impl TXClkPin<T>>,
-        mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
+        mdio: Peri<'d, impl MDIOPin<T>>,
-        mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
+        mdc: Peri<'d, impl MDCPin<T>>,
-        rxdv: impl Peripheral<P = impl RXDVPin<T>> + 'd,
+        rxdv: Peri<'d, impl RXDVPin<T>>,
-        rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
+        rx_d0: Peri<'d, impl RXD0Pin<T>>,
-        rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
+        rx_d1: Peri<'d, impl RXD1Pin<T>>,
-        rx_d2: impl Peripheral<P = impl RXD2Pin<T>> + 'd,
+        rx_d2: Peri<'d, impl RXD2Pin<T>>,
-        rx_d3: impl Peripheral<P = impl RXD3Pin<T>> + 'd,
+        rx_d3: Peri<'d, impl RXD3Pin<T>>,
-        tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
+        tx_d0: Peri<'d, impl TXD0Pin<T>>,
-        tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
+        tx_d1: Peri<'d, impl TXD1Pin<T>>,
-        tx_d2: impl Peripheral<P = impl TXD2Pin<T>> + 'd,
+        tx_d2: Peri<'d, impl TXD2Pin<T>>,
-        tx_d3: impl Peripheral<P = impl TXD3Pin<T>> + 'd,
+        tx_d3: Peri<'d, impl TXD3Pin<T>>,
-        tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
+        tx_en: Peri<'d, impl TXEnPin<T>>,
        phy: P,
        mac_addr: [u8; 6],
    ) -> Self {
@@ -145,24 +144,23 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
        });
-        into_ref!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
        config_pins!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
        let pins = Pins::Mii([
-            rx_clk.map_into(),
+            rx_clk.into(),
-            tx_clk.map_into(),
+            tx_clk.into(),
-            mdio.map_into(),
+            mdio.into(),
-            mdc.map_into(),
+            mdc.into(),
-            rxdv.map_into(),
+            rxdv.into(),
-            rx_d0.map_into(),
+            rx_d0.into(),
-            rx_d1.map_into(),
+            rx_d1.into(),
-            rx_d2.map_into(),
+            rx_d2.into(),
-            rx_d3.map_into(),
+            rx_d3.into(),
-            tx_d0.map_into(),
+            tx_d0.into(),
-            tx_d1.map_into(),
+            tx_d1.into(),
-            tx_d2.map_into(),
+            tx_d2.into(),
-            tx_d3.map_into(),
+            tx_d3.into(),
-            tx_en.map_into(),
+            tx_en.into(),
        ]);
        Self::new_inner(queue, peri, irq, pins, phy, mac_addr)
@@ -170,7 +168,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
    fn new_inner<const TX: usize, const RX: usize>(
        queue: &'d mut PacketQueue<TX, RX>,
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
        pins: Pins<'d>,
        phy: P,
@@ -192,6 +190,9 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
            // TODO: Carrier sense ? ECRSFD
        });
+        // Disable multicast filter
+        mac.macpfr().modify(|w| w.set_pm(true));
        // Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
        // so the LR write must happen after the HR write.
        mac.maca0hr()
@@ -251,7 +252,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
        };
        let mut this = Self {
-            _peri: peri.into_ref(),
+            _peri: peri,
            tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
            rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
            pins,
@@ -301,7 +302,7 @@ pub struct EthernetStationManagement<T: Instance> {
    clock_range: u8,
 }
-unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
+impl<T: Instance> StationManagement for EthernetStationManagement<T> {
    fn smi_read(&mut self, phy_addr: u8, reg: u8) -> u16 {
        let mac = T::regs().ethernet_mac();
@@ -331,7 +332,7 @@ unsafe impl<T: Instance> StationManagement for EthernetStationManagement<T> {
    }
 }
-impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
+impl<'d, T: Instance, P: Phy> Drop for Ethernet<'d, T, P> {
    fn drop(&mut self) {
        let dma = T::regs().ethernet_dma();
        let mac = T::regs().ethernet_mac();
diff --git a/embassy-stm32/src/exti.rs b/embassy-stm32/src/exti.rs
index 224d51b84..9fce78f95 100644
--- a/embassy-stm32/src/exti.rs
+++ b/embassy-stm32/src/exti.rs
@@ -5,21 +5,25 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
-use embassy_hal_internal::{impl_peripheral, into_ref};
+use embassy_hal_internal::{impl_peripheral, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
 use crate::gpio::{AnyPin, Input, Level, Pin as GpioPin, Pull};
 use crate::pac::exti::regs::Lines;
 use crate::pac::EXTI;
-use crate::{interrupt, pac, peripherals, Peripheral};
+use crate::{interrupt, pac, peripherals, Peri};
 const EXTI_COUNT: usize = 16;
-const NEW_AW: AtomicWaker = AtomicWaker::new();
+static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [const { AtomicWaker::new() }; EXTI_COUNT];
-static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [NEW_AW; EXTI_COUNT];
-#[cfg(exti_w)]
+#[cfg(all(exti_w, feature = "_core-cm0p"))]
 fn cpu_regs() -> pac::exti::Cpu {
-    EXTI.cpu(crate::pac::CORE_INDEX)
+    EXTI.cpu(1)
+}
+#[cfg(all(exti_w, not(feature = "_core-cm0p")))]
+fn cpu_regs() -> pac::exti::Cpu {
+    EXTI.cpu(0)
 }
 #[cfg(not(exti_w))]
@@ -41,9 +45,6 @@ fn exticr_regs() -> pac::afio::Afio {
 }
 unsafe fn on_irq() {
-    #[cfg(feature = "low-power")]
-    crate::low_power::on_wakeup_irq();
    #[cfg(not(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50)))]
    let bits = EXTI.pr(0).read().0;
    #[cfg(any(exti_c0, exti_g0, exti_u0, exti_l5, exti_u5, exti_h5, exti_h50))]
@@ -68,6 +69,9 @@ unsafe fn on_irq() {
        EXTI.rpr(0).write_value(Lines(bits));
        EXTI.fpr(0).write_value(Lines(bits));
    }
+    #[cfg(feature = "low-power")]
+    crate::low_power::on_wakeup_irq();
 }
 struct BitIter(u32);
@@ -101,13 +105,7 @@ impl<'d> Unpin for ExtiInput<'d> {}
 impl<'d> ExtiInput<'d> {
    /// Create an EXTI input.
-    pub fn new<T: GpioPin>(
+    pub fn new<T: GpioPin>(pin: Peri<'d, T>, ch: Peri<'d, T::ExtiChannel>, pull: Pull) -> Self {
-        pin: impl Peripheral<P = T> + 'd,
-        ch: impl Peripheral<P = T::ExtiChannel> + 'd,
-        pull: Pull,
-    ) -> Self {
-        into_ref!(pin, ch);
        // Needed if using AnyPin+AnyChannel.
        assert_eq!(pin.pin(), ch.number());
@@ -334,23 +332,12 @@ trait SealedChannel {}
 /// EXTI channel trait.
 #[allow(private_bounds)]
-pub trait Channel: SealedChannel + Sized {
+pub trait Channel: PeripheralType + SealedChannel + Sized {
    /// Get the EXTI channel number.
    fn number(&self) -> u8;
-    /// Type-erase (degrade) this channel into an `AnyChannel`.
-    ///
-    /// This converts EXTI channel singletons (`EXTI0`, `EXTI1`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of channels, or avoiding generics.
-    fn degrade(self) -> AnyChannel {
-        AnyChannel {
-            number: self.number() as u8,
-        }
-    }
 }
-/// Type-erased (degraded) EXTI channel.
+/// Type-erased EXTI channel.
 ///
 /// This represents ownership over any EXTI channel, known at runtime.
 pub struct AnyChannel {
@@ -373,6 +360,14 @@ macro_rules! impl_exti {
                $number
            }
        }
+        impl From<peripherals::$type> for AnyChannel {
+            fn from(val: peripherals::$type) -> Self {
+                Self {
+                    number: val.number() as u8,
+                }
+            }
+        }
    };
 }
diff --git a/embassy-stm32/src/flash/asynch.rs b/embassy-stm32/src/flash/asynch.rs
index 9468ac632..006dcddeb 100644
--- a/embassy-stm32/src/flash/asynch.rs
+++ b/embassy-stm32/src/flash/asynch.rs
@@ -2,28 +2,25 @@ use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::into_ref;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::mutex::Mutex;
 use super::{
-    blocking_read, ensure_sector_aligned, family, get_sector, Async, Error, Flash, FlashLayout, FLASH_BASE, FLASH_SIZE,
+    blocking_read, ensure_sector_aligned, family, get_flash_regions, get_sector, Async, Error, Flash, FlashLayout,
-    WRITE_SIZE,
+    FLASH_BASE, FLASH_SIZE, WRITE_SIZE,
 };
 use crate::interrupt::InterruptExt;
 use crate::peripherals::FLASH;
-use crate::{interrupt, Peripheral};
+use crate::{interrupt, Peri};
 pub(super) static REGION_ACCESS: Mutex<CriticalSectionRawMutex, ()> = Mutex::new(());
 impl<'d> Flash<'d, Async> {
    /// Create a new flash driver with async capabilities.
    pub fn new(
-        p: impl Peripheral<P = FLASH> + 'd,
+        p: Peri<'d, FLASH>,
        _irq: impl interrupt::typelevel::Binding<crate::interrupt::typelevel::FLASH, InterruptHandler> + 'd,
    ) -> Self {
-        into_ref!(p);
        crate::interrupt::FLASH.unpend();
        unsafe { crate::interrupt::FLASH.enable() };
@@ -37,7 +34,6 @@ impl<'d> Flash<'d, Async> {
    ///
    /// See module-level documentation for details on how memory regions work.
    pub fn into_regions(self) -> FlashLayout<'d, Async> {
-        assert!(family::is_default_layout());
        FlashLayout::new(self.inner)
    }
@@ -126,7 +122,7 @@ pub(super) async unsafe fn write_chunked(base: u32, size: u32, offset: u32, byte
 pub(super) async unsafe fn erase_sectored(base: u32, from: u32, to: u32) -> Result<(), Error> {
    let start_address = base + from;
    let end_address = base + to;
-    let regions = family::get_flash_regions();
+    let regions = get_flash_regions();
    ensure_sector_aligned(start_address, end_address, regions)?;
diff --git a/embassy-stm32/src/flash/common.rs b/embassy-stm32/src/flash/common.rs
index 8ec4bb2a1..10023e637 100644
--- a/embassy-stm32/src/flash/common.rs
+++ b/embassy-stm32/src/flash/common.rs
@@ -2,26 +2,27 @@ use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, PeripheralRef};
-use stm32_metapac::FLASH_BASE;
 use super::{
-    family, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE, MAX_ERASE_SIZE,
+    family, get_flash_regions, Async, Blocking, Error, FlashBank, FlashLayout, FlashRegion, FlashSector, FLASH_SIZE,
-    READ_SIZE, WRITE_SIZE,
+    MAX_ERASE_SIZE, READ_SIZE, WRITE_SIZE,
 };
+use crate::Peri;
+use crate::_generated::FLASH_BASE;
 use crate::peripherals::FLASH;
-use crate::Peripheral;
 /// Internal flash memory driver.
 pub struct Flash<'d, MODE = Async> {
-    pub(crate) inner: PeripheralRef<'d, FLASH>,
+    pub(crate) inner: Peri<'d, FLASH>,
    pub(crate) _mode: PhantomData<MODE>,
 }
 impl<'d> Flash<'d, Blocking> {
    /// Create a new flash driver, usable in blocking mode.
-    pub fn new_blocking(p: impl Peripheral<P = FLASH> + 'd) -> Self {
+    pub fn new_blocking(p: Peri<'d, FLASH>) -> Self {
-        into_ref!(p);
+        #[cfg(bank_setup_configurable)]
+        // Check if the configuration matches the embassy setup
+        super::check_bank_setup();
        Self {
            inner: p,
@@ -35,7 +36,6 @@ impl<'d, MODE> Flash<'d, MODE> {
    ///
    /// See module-level documentation for details on how memory regions work.
    pub fn into_blocking_regions(self) -> FlashLayout<'d, Blocking> {
-        assert!(family::is_default_layout());
        FlashLayout::new(self.inner)
    }
@@ -140,7 +140,7 @@ pub(super) unsafe fn blocking_erase(
 ) -> Result<(), Error> {
    let start_address = base + from;
    let end_address = base + to;
-    let regions = family::get_flash_regions();
+    let regions = get_flash_regions();
    ensure_sector_aligned(start_address, end_address, regions)?;
diff --git a/embassy-stm32/src/flash/eeprom.rs b/embassy-stm32/src/flash/eeprom.rs
new file mode 100644
index 000000000..cc3529eb9
--- /dev/null
+++ b/embassy-stm32/src/flash/eeprom.rs
@@ -0,0 +1,236 @@
+use embassy_hal_internal::drop::OnDrop;
+use super::{family, Blocking, Error, Flash, EEPROM_BASE, EEPROM_SIZE};
+#[cfg(eeprom)]
+impl<'d> Flash<'d, Blocking> {
+    // --- Internal helpers ---
+    /// Checks if the given offset and size are within the EEPROM bounds.
+    fn check_eeprom_offset(&self, offset: u32, size: u32) -> Result<(), Error> {
+        if offset
+            .checked_add(size)
+            .filter(|&end| end <= EEPROM_SIZE as u32)
+            .is_some()
+        {
+            Ok(())
+        } else {
+            Err(Error::Size)
+        }
+    }
+    // --- Unlocked (unsafe, internal) functions ---
+    /// Writes a slice of bytes to EEPROM at the given offset without locking.
+    ///
+    /// # Safety
+    /// Caller must ensure EEPROM is unlocked and offset is valid.
+    unsafe fn eeprom_write_u8_slice_unlocked(&self, offset: u32, data: &[u8]) -> Result<(), Error> {
+        for (i, &byte) in data.iter().enumerate() {
+            let addr = EEPROM_BASE as u32 + offset + i as u32;
+            core::ptr::write_volatile(addr as *mut u8, byte);
+            family::wait_ready_blocking()?;
+            family::clear_all_err();
+        }
+        Ok(())
+    }
+    /// Writes a slice of u16 values to EEPROM at the given offset without locking.
+    ///
+    /// # Safety
+    /// Caller must ensure EEPROM is unlocked and offset is valid and aligned.
+    unsafe fn eeprom_write_u16_slice_unlocked(&self, offset: u32, data: &[u16]) -> Result<(), Error> {
+        for (i, &value) in data.iter().enumerate() {
+            let addr = EEPROM_BASE as u32 + offset + i as u32 * 2;
+            core::ptr::write_volatile(addr as *mut u16, value);
+            family::wait_ready_blocking()?;
+            family::clear_all_err();
+        }
+        Ok(())
+    }
+    /// Writes a slice of u32 values to EEPROM at the given offset without locking.
+    ///
+    /// # Safety
+    /// Caller must ensure EEPROM is unlocked and offset is valid and aligned.
+    unsafe fn eeprom_write_u32_slice_unlocked(&self, offset: u32, data: &[u32]) -> Result<(), Error> {
+        for (i, &value) in data.iter().enumerate() {
+            let addr = EEPROM_BASE as u32 + offset + i as u32 * 4;
+            core::ptr::write_volatile(addr as *mut u32, value);
+            family::wait_ready_blocking()?;
+            family::clear_all_err();
+        }
+        Ok(())
+    }
+    // --- Public, safe API ---
+    /// Writes a single byte to EEPROM at the given offset.
+    pub fn eeprom_write_u8(&mut self, offset: u32, value: u8) -> Result<(), Error> {
+        self.check_eeprom_offset(offset, 1)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u8_slice_unlocked(offset, core::slice::from_ref(&value))?;
+        }
+        Ok(())
+    }
+    /// Writes a single 16-bit value to EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 2-byte aligned.
+    pub fn eeprom_write_u16(&mut self, offset: u32, value: u16) -> Result<(), Error> {
+        if offset % 2 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, 2)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u16_slice_unlocked(offset, core::slice::from_ref(&value))?;
+        }
+        Ok(())
+    }
+    /// Writes a single 32-bit value to EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 4-byte aligned.
+    pub fn eeprom_write_u32(&mut self, offset: u32, value: u32) -> Result<(), Error> {
+        if offset % 4 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, 4)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u32_slice_unlocked(offset, core::slice::from_ref(&value))?;
+        }
+        Ok(())
+    }
+    /// Writes a slice of bytes to EEPROM at the given offset.
+    pub fn eeprom_write_u8_slice(&mut self, offset: u32, data: &[u8]) -> Result<(), Error> {
+        self.check_eeprom_offset(offset, data.len() as u32)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u8_slice_unlocked(offset, data)?;
+        }
+        Ok(())
+    }
+    /// Writes a slice of 16-bit values to EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 2-byte aligned.
+    pub fn eeprom_write_u16_slice(&mut self, offset: u32, data: &[u16]) -> Result<(), Error> {
+        if offset % 2 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, data.len() as u32 * 2)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u16_slice_unlocked(offset, data)?;
+        }
+        Ok(())
+    }
+    /// Writes a slice of 32-bit values to EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 4-byte aligned.
+    pub fn eeprom_write_u32_slice(&mut self, offset: u32, data: &[u32]) -> Result<(), Error> {
+        if offset % 4 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, data.len() as u32 * 4)?;
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            self.eeprom_write_u32_slice_unlocked(offset, data)?;
+        }
+        Ok(())
+    }
+    /// Writes a byte slice to EEPROM at the given offset, handling alignment.
+    ///
+    /// This method will write unaligned prefix and suffix as bytes, and aligned middle as u32.
+    pub fn eeprom_write_slice(&mut self, offset: u32, data: &[u8]) -> Result<(), Error> {
+        self.check_eeprom_offset(offset, data.len() as u32)?;
+        let start = offset;
+        let misalign = (start % 4) as usize;
+        let prefix_len = if misalign == 0 {
+            0
+        } else {
+            (4 - misalign).min(data.len())
+        };
+        let (prefix, rest) = data.split_at(prefix_len);
+        let aligned_len = (rest.len() / 4) * 4;
+        let (bytes_for_u32_write, suffix) = rest.split_at(aligned_len);
+        unsafe {
+            family::unlock();
+            let _on_drop = OnDrop::new(|| family::lock());
+            if !prefix.is_empty() {
+                self.eeprom_write_u8_slice_unlocked(start, prefix)?;
+            }
+            if !bytes_for_u32_write.is_empty() {
+                let aligned_eeprom_offset = start + prefix_len as u32;
+                let base_eeprom_addr = EEPROM_BASE as u32 + aligned_eeprom_offset;
+                for (i, chunk) in bytes_for_u32_write.chunks_exact(4).enumerate() {
+                    // Safely read a u32 from a potentially unaligned pointer into the chunk.
+                    let value = (chunk.as_ptr() as *const u32).read_unaligned();
+                    let current_eeprom_addr = base_eeprom_addr + (i * 4) as u32;
+                    core::ptr::write_volatile(current_eeprom_addr as *mut u32, value);
+                    family::wait_ready_blocking()?;
+                    family::clear_all_err();
+                }
+            }
+            if !suffix.is_empty() {
+                let suffix_offset = start + (prefix_len + aligned_len) as u32;
+                self.eeprom_write_u8_slice_unlocked(suffix_offset, suffix)?;
+            }
+        }
+        Ok(())
+    }
+    /// Reads a single byte from EEPROM at the given offset.
+    pub fn eeprom_read_u8(&self, offset: u32) -> Result<u8, Error> {
+        self.check_eeprom_offset(offset, 1)?;
+        let addr = EEPROM_BASE as u32 + offset;
+        Ok(unsafe { core::ptr::read_volatile(addr as *const u8) })
+    }
+    /// Reads a single 16-bit value from EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 2-byte aligned.
+    pub fn eeprom_read_u16(&self, offset: u32) -> Result<u16, Error> {
+        if offset % 2 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, 2)?;
+        let addr = EEPROM_BASE as u32 + offset;
+        Ok(unsafe { core::ptr::read_volatile(addr as *const u16) })
+    }
+    /// Reads a single 32-bit value from EEPROM at the given offset.
+    ///
+    /// Returns an error if the offset is not 4-byte aligned.
+    pub fn eeprom_read_u32(&self, offset: u32) -> Result<u32, Error> {
+        if offset % 4 != 0 {
+            return Err(Error::Unaligned);
+        }
+        self.check_eeprom_offset(offset, 4)?;
+        let addr = EEPROM_BASE as u32 + offset;
+        Ok(unsafe { core::ptr::read_volatile(addr as *const u32) })
+    }
+    /// Reads a slice of bytes from EEPROM at the given offset into the provided buffer.
+    pub fn eeprom_read_slice(&self, offset: u32, buf: &mut [u8]) -> Result<(), Error> {
+        self.check_eeprom_offset(offset, buf.len() as u32)?;
+        let addr = EEPROM_BASE as u32 + offset;
+        let src = unsafe { core::slice::from_raw_parts(addr as *const u8, buf.len()) };
+        buf.copy_from_slice(src);
+        Ok(())
+    }
+}
diff --git a/embassy-stm32/src/flash/f0.rs b/embassy-stm32/src/flash/f0.rs
index 402312f68..3f9dbe945 100644
--- a/embassy-stm32/src/flash/f0.rs
+++ b/embassy-stm32/src/flash/f0.rs
@@ -1,18 +1,10 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.cr().modify(|w| w.set_lock(true));
 }
diff --git a/embassy-stm32/src/flash/f1f3.rs b/embassy-stm32/src/flash/f1f3.rs
index ff7f810ea..bf9ad2893 100644
--- a/embassy-stm32/src/flash/f1f3.rs
+++ b/embassy-stm32/src/flash/f1f3.rs
@@ -1,18 +1,10 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.cr().modify(|w| w.set_lock(true));
 }
@@ -64,8 +56,8 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
    // BSY bit, because there is a one-cycle delay between
    // setting the STRT bit and the BSY bit being asserted
    // by hardware. See STM32F105xx, STM32F107xx device errata,
-    // section 2.2.8
+    // section 2.2.8, and also RM0316 Rev 10 section 4.2.3 for
-    #[cfg(stm32f1)]
+    // STM32F3xx series.
    pac::FLASH.cr().read();
    let mut ret: Result<(), Error> = wait_ready_blocking();
diff --git a/embassy-stm32/src/flash/f2.rs b/embassy-stm32/src/flash/f2.rs
new file mode 100644
index 000000000..67e380619
--- /dev/null
+++ b/embassy-stm32/src/flash/f2.rs
@@ -0,0 +1,134 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{fence, AtomicBool, Ordering};
+use pac::flash::regs::Sr;
+use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+static DATA_CACHE_WAS_ENABLED: AtomicBool = AtomicBool::new(false);
+impl FlashSector {
+    const fn snb(&self) -> u8 {
+        ((self.bank as u8) << 4) + self.index_in_bank
+    }
+}
+pub(crate) unsafe fn lock() {
+    pac::FLASH.cr().modify(|w| w.set_lock(true));
+}
+pub(crate) unsafe fn unlock() {
+    if pac::FLASH.cr().read().lock() {
+        pac::FLASH.keyr().write_value(0x4567_0123);
+        pac::FLASH.keyr().write_value(0xCDEF_89AB);
+    }
+}
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+    save_data_cache_state();
+    pac::FLASH.cr().write(|w| {
+        w.set_pg(true);
+        w.set_psize(pac::flash::vals::Psize::PSIZE32);
+    });
+}
+pub(crate) unsafe fn disable_blocking_write() {
+    pac::FLASH.cr().write(|w| w.set_pg(false));
+    restore_data_cache_state();
+}
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    write_start(start_address, buf);
+    blocking_wait_ready()
+}
+unsafe fn write_start(start_address: u32, buf: &[u8; WRITE_SIZE]) {
+    let mut address = start_address;
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+        // prevents parallelism errors
+        fence(Ordering::SeqCst);
+    }
+}
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    save_data_cache_state();
+    trace!("Blocking erasing sector number {}", sector.snb());
+    pac::FLASH.cr().modify(|w| {
+        w.set_ser(true);
+        w.set_snb(sector.snb())
+    });
+    pac::FLASH.cr().modify(|w| {
+        w.set_strt(true);
+    });
+    let ret: Result<(), Error> = blocking_wait_ready();
+    clear_all_err();
+    restore_data_cache_state();
+    ret
+}
+pub(crate) unsafe fn clear_all_err() {
+    // read and write back the same value.
+    // This clears all "write 1 to clear" bits.
+    pac::FLASH.sr().modify(|_| {});
+}
+unsafe fn blocking_wait_ready() -> Result<(), Error> {
+    loop {
+        let sr = pac::FLASH.sr().read();
+        if !sr.bsy() {
+            return get_result(sr);
+        }
+    }
+}
+fn get_result(sr: Sr) -> Result<(), Error> {
+    if sr.pgserr() {
+        Err(Error::Seq)
+    } else if sr.pgperr() {
+        Err(Error::Parallelism)
+    } else if sr.pgaerr() {
+        Err(Error::Unaligned)
+    } else if sr.wrperr() {
+        Err(Error::Protected)
+    } else {
+        Ok(())
+    }
+}
+fn save_data_cache_state() {
+    let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
+    if dual_bank {
+        // Disable data cache during write/erase if there are two banks, see errata 2.2.12
+        let dcen = pac::FLASH.acr().read().dcen();
+        DATA_CACHE_WAS_ENABLED.store(dcen, Ordering::Relaxed);
+        if dcen {
+            pac::FLASH.acr().modify(|w| w.set_dcen(false));
+        }
+    }
+}
+fn restore_data_cache_state() {
+    let dual_bank = unwrap!(get_flash_regions().last()).bank == FlashBank::Bank2;
+    if dual_bank {
+        // Restore data cache if it was enabled
+        let dcen = DATA_CACHE_WAS_ENABLED.load(Ordering::Relaxed);
+        if dcen {
+            // Reset data cache before we enable it again
+            pac::FLASH.acr().modify(|w| w.set_dcrst(true));
+            pac::FLASH.acr().modify(|w| w.set_dcrst(false));
+            pac::FLASH.acr().modify(|w| w.set_dcen(true))
+        }
+    }
+}
diff --git a/embassy-stm32/src/flash/f4.rs b/embassy-stm32/src/flash/f4.rs
index d0bb957ee..62e0492b5 100644
--- a/embassy-stm32/src/flash/f4.rs
+++ b/embassy-stm32/src/flash/f4.rs
@@ -3,176 +3,11 @@ use core::sync::atomic::{fence, AtomicBool, Ordering};
 use embassy_sync::waitqueue::AtomicWaker;
 use pac::flash::regs::Sr;
-use pac::FLASH_SIZE;
-use super::{FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{get_flash_regions, FlashBank, FlashSector, WRITE_SIZE};
+use crate::_generated::FLASH_SIZE;
 use crate::flash::Error;
 use crate::pac;
-#[allow(missing_docs)] // TODO
-#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
-mod alt_regions {
-    use core::marker::PhantomData;
-    use embassy_hal_internal::PeripheralRef;
-    use stm32_metapac::FLASH_SIZE;
-    use crate::_generated::flash_regions::{BANK1_REGION1, BANK1_REGION2, BANK1_REGION3};
-    use crate::flash::{asynch, Async, Bank1Region1, Bank1Region2, Blocking, Error, Flash, FlashBank, FlashRegion};
-    use crate::peripherals::FLASH;
-    pub const ALT_BANK1_REGION3: FlashRegion = FlashRegion {
-        size: 3 * BANK1_REGION3.erase_size,
-        ..BANK1_REGION3
-    };
-    pub const ALT_BANK2_REGION1: FlashRegion = FlashRegion {
-        bank: FlashBank::Bank2,
-        base: BANK1_REGION1.base + FLASH_SIZE as u32 / 2,
-        ..BANK1_REGION1
-    };
-    pub const ALT_BANK2_REGION2: FlashRegion = FlashRegion {
-        bank: FlashBank::Bank2,
-        base: BANK1_REGION2.base + FLASH_SIZE as u32 / 2,
-        ..BANK1_REGION2
-    };
-    pub const ALT_BANK2_REGION3: FlashRegion = FlashRegion {
-        bank: FlashBank::Bank2,
-        base: BANK1_REGION3.base + FLASH_SIZE as u32 / 2,
-        size: 3 * BANK1_REGION3.erase_size,
-        ..BANK1_REGION3
-    };
-    pub const ALT_FLASH_REGIONS: [&FlashRegion; 6] = [
-        &BANK1_REGION1,
-        &BANK1_REGION2,
-        &ALT_BANK1_REGION3,
-        &ALT_BANK2_REGION1,
-        &ALT_BANK2_REGION2,
-        &ALT_BANK2_REGION3,
-    ];
-    pub struct AltBank1Region3<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region1<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region2<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltBank2Region3<'d, MODE = Async>(pub &'static FlashRegion, PeripheralRef<'d, FLASH>, PhantomData<MODE>);
-    pub struct AltFlashLayout<'d, MODE = Async> {
-        pub bank1_region1: Bank1Region1<'d, MODE>,
-        pub bank1_region2: Bank1Region2<'d, MODE>,
-        pub bank1_region3: AltBank1Region3<'d, MODE>,
-        pub bank2_region1: AltBank2Region1<'d, MODE>,
-        pub bank2_region2: AltBank2Region2<'d, MODE>,
-        pub bank2_region3: AltBank2Region3<'d, MODE>,
-    }
-    impl<'d> Flash<'d> {
-        pub fn into_alt_regions(self) -> AltFlashLayout<'d, Async> {
-            assert!(!super::is_default_layout());
-            // SAFETY: We never expose the cloned peripheral references, and their instance is not public.
-            // Also, all async flash region operations are protected with a mutex.
-            let p = self.inner;
-            AltFlashLayout {
-                bank1_region1: Bank1Region1(&BANK1_REGION1, unsafe { p.clone_unchecked() }, PhantomData),
-                bank1_region2: Bank1Region2(&BANK1_REGION2, unsafe { p.clone_unchecked() }, PhantomData),
-                bank1_region3: AltBank1Region3(&ALT_BANK1_REGION3, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region1: AltBank2Region1(&ALT_BANK2_REGION1, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region2: AltBank2Region2(&ALT_BANK2_REGION2, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region3: AltBank2Region3(&ALT_BANK2_REGION3, unsafe { p.clone_unchecked() }, PhantomData),
-            }
-        }
-        pub fn into_alt_blocking_regions(self) -> AltFlashLayout<'d, Blocking> {
-            assert!(!super::is_default_layout());
-            // SAFETY: We never expose the cloned peripheral references, and their instance is not public.
-            // Also, all blocking flash region operations are protected with a cs.
-            let p = self.inner;
-            AltFlashLayout {
-                bank1_region1: Bank1Region1(&BANK1_REGION1, unsafe { p.clone_unchecked() }, PhantomData),
-                bank1_region2: Bank1Region2(&BANK1_REGION2, unsafe { p.clone_unchecked() }, PhantomData),
-                bank1_region3: AltBank1Region3(&ALT_BANK1_REGION3, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region1: AltBank2Region1(&ALT_BANK2_REGION1, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region2: AltBank2Region2(&ALT_BANK2_REGION2, unsafe { p.clone_unchecked() }, PhantomData),
-                bank2_region3: AltBank2Region3(&ALT_BANK2_REGION3, unsafe { p.clone_unchecked() }, PhantomData),
-            }
-        }
-    }
-    macro_rules! foreach_altflash_region {
-        ($type_name:ident, $region:ident) => {
-            impl<MODE> $type_name<'_, MODE> {
-                pub fn blocking_read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
-                    crate::flash::common::blocking_read(self.0.base, self.0.size, offset, bytes)
-                }
-            }
-            impl $type_name<'_, Async> {
-                pub async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
-                    self.blocking_read(offset, bytes)
-                }
-                pub async fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
-                    let _guard = asynch::REGION_ACCESS.lock().await;
-                    unsafe { asynch::write_chunked(self.0.base, self.0.size, offset, bytes).await }
-                }
-                pub async fn erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
-                    let _guard = asynch::REGION_ACCESS.lock().await;
-                    unsafe { asynch::erase_sectored(self.0.base, from, to).await }
-                }
-            }
-            impl<MODE> embedded_storage::nor_flash::ErrorType for $type_name<'_, MODE> {
-                type Error = Error;
-            }
-            impl<MODE> embedded_storage::nor_flash::ReadNorFlash for $type_name<'_, MODE> {
-                const READ_SIZE: usize = crate::flash::READ_SIZE;
-                fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
-                    self.blocking_read(offset, bytes)
-                }
-                fn capacity(&self) -> usize {
-                    self.0.size as usize
-                }
-            }
-            impl embedded_storage_async::nor_flash::ReadNorFlash for $type_name<'_, Async> {
-                const READ_SIZE: usize = crate::flash::READ_SIZE;
-                async fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
-                    self.read(offset, bytes).await
-                }
-                fn capacity(&self) -> usize {
-                    self.0.size as usize
-                }
-            }
-            impl embedded_storage_async::nor_flash::NorFlash for $type_name<'_, Async> {
-                const WRITE_SIZE: usize = $region.write_size as usize;
-                const ERASE_SIZE: usize = $region.erase_size as usize;
-                async fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
-                    self.write(offset, bytes).await
-                }
-                async fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
-                    self.erase(from, to).await
-                }
-            }
-        };
-    }
-    foreach_altflash_region!(AltBank1Region3, ALT_BANK1_REGION3);
-    foreach_altflash_region!(AltBank2Region1, ALT_BANK2_REGION1);
-    foreach_altflash_region!(AltBank2Region2, ALT_BANK2_REGION2);
-    foreach_altflash_region!(AltBank2Region3, ALT_BANK2_REGION3);
-}
-#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
-pub use alt_regions::*;
 static WAKER: AtomicWaker = AtomicWaker::new();
 static DATA_CACHE_WAS_ENABLED: AtomicBool = AtomicBool::new(false);
@@ -183,30 +18,6 @@ impl FlashSector {
    }
 }
-#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
-pub(crate) fn is_default_layout() -> bool {
-    !pac::FLASH.optcr().read().db1m()
-}
-#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479)))]
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479))]
-pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    if is_default_layout() {
-        &FLASH_REGIONS
-    } else {
-        &ALT_FLASH_REGIONS
-    }
-}
-#[cfg(not(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f469, stm32f479)))]
-pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn on_interrupt() {
    // Clear IRQ flags
    pac::FLASH.sr().write(|w| {
@@ -469,7 +280,7 @@ fn pa12_is_output_pull_low() -> bool {
    use pac::GPIOA;
    const PIN: usize = 12;
    GPIOA.moder().read().moder(PIN) == vals::Moder::OUTPUT
-        && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULLDOWN
+        && GPIOA.pupdr().read().pupdr(PIN) == vals::Pupdr::PULL_DOWN
        && GPIOA.odr().read().odr(PIN) == vals::Odr::LOW
 }
@@ -485,71 +296,83 @@ mod tests {
        const MEDIUM_SECTOR_SIZE: u32 = 64 * 1024;
        const LARGE_SECTOR_SIZE: u32 = 128 * 1024;
-        let assert_sector = |snb: u8, index_in_bank: u8, start: u32, size: u32, address: u32| {
+        if !cfg!(feature = "dual-bank") {
-            let sector = get_sector(address, &FLASH_REGIONS);
+            let assert_sector = |snb: u8, index_in_bank: u8, start: u32, size: u32, address: u32| {
-            assert_eq!(snb, sector.snb());
+                let sector = get_sector(address, crate::flash::get_flash_regions());
-            assert_eq!(
+                assert_eq!(snb, sector.snb());
-                FlashSector {
+                assert_eq!(
-                    bank: FlashBank::Bank1,
+                    FlashSector {
-                    index_in_bank,
+                        bank: sector.bank,
-                    start,
+                        index_in_bank,
-                    size
+                        start,
-                },
+                        size
-                sector
+                    },
-            );
+                    sector
-        };
+                );
+            };
-        assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
-        assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
+            assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
-        assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
+            assert_sector(0x00, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
-        assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
+            assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
+            assert_sector(0x03, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
-        assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
-        assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
+            assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
+            assert_sector(0x04, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
-        assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
-        assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
+            assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
-        assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
+            assert_sector(0x05, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
-        assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
+            assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
+            assert_sector(0x0B, 11, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
-        let assert_sector = |snb: u8, bank: FlashBank, index_in_bank: u8, start: u32, size: u32, address: u32| {
+        } else {
-            let sector = get_sector(address, &ALT_FLASH_REGIONS);
+            let assert_sector = |snb: u8, bank: FlashBank, index_in_bank: u8, start: u32, size: u32, address: u32| {
-            assert_eq!(snb, sector.snb());
+                let sector = get_sector(address, crate::flash::get_flash_regions());
-            assert_eq!(
+                assert_eq!(snb, sector.snb());
-                FlashSector {
+                assert_eq!(
-                    bank,
+                    FlashSector {
-                    index_in_bank,
+                        bank,
-                    start,
+                        index_in_bank,
-                    size
+                        start,
-                },
+                        size
-                sector
+                    },
-            )
+                    sector
-        };
+                )
+            };
-        assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
-        assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
+            assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000);
-        assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
+            assert_sector(0x00, FlashBank::Bank1, 0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF);
-        assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
+            assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000);
+            assert_sector(0x03, FlashBank::Bank1, 3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF);
-        assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
-        assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
+            assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000);
+            assert_sector(0x04, FlashBank::Bank1, 4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF);
-        assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
-        assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
+            assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000);
-        assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0806_0000);
+            assert_sector(0x05, FlashBank::Bank1, 5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF);
-        assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
+            assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0806_0000);
+            assert_sector(0x07, FlashBank::Bank1, 7, 0x0806_0000, LARGE_SECTOR_SIZE, 0x0807_FFFF);
-        assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_0000);
-        assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_3FFF);
+            assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_0000);
-        assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_C000);
+            assert_sector(0x10, FlashBank::Bank2, 0, 0x0808_0000, SMALL_SECTOR_SIZE, 0x0808_3FFF);
-        assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_FFFF);
+            assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_C000);
+            assert_sector(0x13, FlashBank::Bank2, 3, 0x0808_C000, SMALL_SECTOR_SIZE, 0x0808_FFFF);
-        assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_0000);
-        assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_FFFF);
+            assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_0000);
+            assert_sector(0x14, FlashBank::Bank2, 4, 0x0809_0000, MEDIUM_SECTOR_SIZE, 0x0809_FFFF);
-        assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080A_0000);
-        assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080B_FFFF);
+            assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080A_0000);
-        assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
+            assert_sector(0x15, FlashBank::Bank2, 5, 0x080A_0000, LARGE_SECTOR_SIZE, 0x080B_FFFF);
-        assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
+            assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080E_0000);
+            assert_sector(0x17, FlashBank::Bank2, 7, 0x080E_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
+        }
+    }
+}
+#[cfg(all(bank_setup_configurable))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && pac::FLASH.optcr().read().db1m() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && !pac::FLASH.optcr().read().db1m() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the db1m value in the user option bytes or configure embassy to use single-bank config");
    }
 }
diff --git a/embassy-stm32/src/flash/f7.rs b/embassy-stm32/src/flash/f7.rs
index 09ebe9db9..0547c747a 100644
--- a/embassy-stm32/src/flash/f7.rs
+++ b/embassy-stm32/src/flash/f7.rs
@@ -1,16 +1,14 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
+impl FlashSector {
-    true
+    const fn snb(&self) -> u8 {
-}
+        ((self.bank as u8) << 4) + self.index_in_bank
+    }
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
 }
 pub(crate) unsafe fn lock() {
@@ -53,7 +51,7 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
    pac::FLASH.cr().modify(|w| {
        w.set_ser(true);
-        w.set_snb(sector.index_in_bank)
+        w.set_snb(sector.snb())
    });
    pac::FLASH.cr().modify(|w| {
@@ -118,7 +116,7 @@ mod tests {
                    start,
                    size
                },
-                get_sector(address, &FLASH_REGIONS)
+                get_sector(address, crate::flash::get_flash_regions())
            )
        };
@@ -137,7 +135,7 @@ mod tests {
    }
    #[test]
-    #[cfg(stm32f769)]
+    #[cfg(all(stm32f769, feature = "single-bank"))]
    fn can_get_sector() {
        const SMALL_SECTOR_SIZE: u32 = 32 * 1024;
        const MEDIUM_SECTOR_SIZE: u32 = 128 * 1024;
@@ -151,7 +149,7 @@ mod tests {
                    start,
                    size
                },
-                get_sector(address, &FLASH_REGIONS)
+                get_sector(address, crate::flash::get_flash_regions())
            )
        };
@@ -168,4 +166,61 @@ mod tests {
        assert_sector(7, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080C_0000);
        assert_sector(7, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080F_FFFF);
    }
+    #[test]
+    #[cfg(all(stm32f769, feature = "dual-bank"))]
+    fn can_get_sector() {
+        const SMALL_SECTOR_SIZE: u32 = 16 * 1024;
+        const MEDIUM_SECTOR_SIZE: u32 = 64 * 1024;
+        const LARGE_SECTOR_SIZE: u32 = 128 * 1024;
+        let assert_sector = |index_in_bank: u8, start: u32, size: u32, address: u32, snb: u8, bank: FlashBank| {
+            assert_eq!(
+                FlashSector {
+                    bank: bank,
+                    index_in_bank,
+                    start,
+                    size
+                },
+                get_sector(address, crate::flash::get_flash_regions())
+            );
+            assert_eq!(get_sector(address, crate::flash::get_flash_regions()).snb(), snb);
+        };
+        assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_0000, 0x00, FlashBank::Bank1);
+        assert_sector(0, 0x0800_0000, SMALL_SECTOR_SIZE, 0x0800_3FFF, 0x00, FlashBank::Bank1);
+        assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_C000, 0x03, FlashBank::Bank1);
+        assert_sector(3, 0x0800_C000, SMALL_SECTOR_SIZE, 0x0800_FFFF, 0x03, FlashBank::Bank1);
+        assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_0000, 0x04, FlashBank::Bank1);
+        assert_sector(4, 0x0801_0000, MEDIUM_SECTOR_SIZE, 0x0801_FFFF, 0x04, FlashBank::Bank1);
+        assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0802_0000, 0x05, FlashBank::Bank1);
+        assert_sector(5, 0x0802_0000, LARGE_SECTOR_SIZE, 0x0803_FFFF, 0x05, FlashBank::Bank1);
+        assert_sector(10, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080C_0000, 0x0A, FlashBank::Bank1);
+        assert_sector(10, 0x080C_0000, LARGE_SECTOR_SIZE, 0x080D_FFFF, 0x0A, FlashBank::Bank1);
+        assert_sector(0, 0x0810_0000, SMALL_SECTOR_SIZE, 0x0810_0000, 0x10, FlashBank::Bank2);
+        assert_sector(0, 0x0810_0000, SMALL_SECTOR_SIZE, 0x0810_3FFF, 0x10, FlashBank::Bank2);
+        assert_sector(3, 0x0810_C000, SMALL_SECTOR_SIZE, 0x0810_C000, 0x13, FlashBank::Bank2);
+        assert_sector(3, 0x0810_C000, SMALL_SECTOR_SIZE, 0x0810_FFFF, 0x13, FlashBank::Bank2);
+        assert_sector(4, 0x0811_0000, MEDIUM_SECTOR_SIZE, 0x0811_0000, 0x14, FlashBank::Bank2);
+        assert_sector(4, 0x0811_0000, MEDIUM_SECTOR_SIZE, 0x0811_FFFF, 0x14, FlashBank::Bank2);
+        assert_sector(5, 0x0812_0000, LARGE_SECTOR_SIZE, 0x0812_0000, 0x15, FlashBank::Bank2);
+        assert_sector(5, 0x0812_0000, LARGE_SECTOR_SIZE, 0x0813_FFFF, 0x15, FlashBank::Bank2);
+        assert_sector(10, 0x081C_0000, LARGE_SECTOR_SIZE, 0x081C_0000, 0x1A, FlashBank::Bank2);
+        assert_sector(10, 0x081C_0000, LARGE_SECTOR_SIZE, 0x081D_FFFF, 0x1A, FlashBank::Bank2);
+    }
+}
+#[cfg(all(bank_setup_configurable))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && !pac::FLASH.optcr().read().n_dbank() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && pac::FLASH.optcr().read().n_dbank() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the ndbank value in the user option bytes or configure embassy to use single-bank config");
+    }
 }
diff --git a/embassy-stm32/src/flash/g.rs b/embassy-stm32/src/flash/g.rs
index 01a0c603f..bc1fd360c 100644
--- a/embassy-stm32/src/flash/g.rs
+++ b/embassy-stm32/src/flash/g.rs
@@ -3,24 +3,16 @@ use core::sync::atomic::{fence, Ordering};
 use cortex_m::interrupt;
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.cr().modify(|w| w.set_lock(true));
 }
 pub(crate) unsafe fn unlock() {
    // Wait, while the memory interface is busy.
-    while pac::FLASH.sr().read().bsy() {}
+    wait_busy();
    // Unlock flash
    if pac::FLASH.cr().read().lock() {
@@ -53,12 +45,17 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
    let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
-    while pac::FLASH.sr().read().bsy() {}
+    wait_busy();
    clear_all_err();
    interrupt::free(|_| {
        pac::FLASH.cr().modify(|w| {
            w.set_per(true);
+            #[cfg(any(flash_g0x0, flash_g0x1, flash_g4c3))]
+            w.set_bker(sector.bank == crate::flash::FlashBank::Bank2);
+            #[cfg(flash_g0x0)]
+            w.set_pnb(idx as u16);
+            #[cfg(not(flash_g0x0))]
            w.set_pnb(idx as u8);
            w.set_strt(true);
        });
@@ -94,3 +91,33 @@ pub(crate) unsafe fn clear_all_err() {
    // This clears all "write 1 to clear" bits.
    pac::FLASH.sr().modify(|_| {});
 }
+#[cfg(any(flash_g0x0, flash_g0x1))]
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() | pac::FLASH.sr().read().bsy2() {}
+}
+#[cfg(not(any(flash_g0x0, flash_g0x1)))]
+fn wait_busy() {
+    while pac::FLASH.sr().read().bsy() {}
+}
+#[cfg(all(bank_setup_configurable, any(flash_g4c2, flash_g4c3, flash_g4c4)))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+    }
+}
+#[cfg(all(bank_setup_configurable, flash_g0x1))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dual_bank() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dual_bank() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dual_bank value in the user option bytes or configure embassy to use single-bank config");
+    }
+}
diff --git a/embassy-stm32/src/flash/h5.rs b/embassy-stm32/src/flash/h5.rs
new file mode 100644
index 000000000..fd9bfcc75
--- /dev/null
+++ b/embassy-stm32/src/flash/h5.rs
@@ -0,0 +1,166 @@
+use core::ptr::write_volatile;
+use core::sync::atomic::{fence, Ordering};
+use super::{FlashSector, WRITE_SIZE};
+use crate::flash::Error;
+use crate::pac;
+pub(crate) unsafe fn lock() {
+    if !pac::FLASH.nscr().read().lock() {
+        pac::FLASH.nscr().modify(|r| {
+            r.set_lock(true);
+        });
+    }
+}
+pub(crate) unsafe fn unlock() {
+    // TODO: check locked first
+    while pac::FLASH.nssr().read().bsy() {
+        #[cfg(feature = "defmt")]
+        defmt::trace!("busy")
+    }
+    // only unlock if locked to begin with
+    if pac::FLASH.nscr().read().lock() {
+        pac::FLASH.nskeyr().write_value(0x4567_0123);
+        pac::FLASH.nskeyr().write_value(0xCDEF_89AB);
+    }
+}
+pub(crate) unsafe fn enable_blocking_write() {
+    assert_eq!(0, WRITE_SIZE % 4);
+}
+pub(crate) unsafe fn disable_blocking_write() {}
+pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
+    // // We cannot have the write setup sequence in begin_write as it depends on the address
+    // let bank = if start_address < BANK1_REGION.end() {
+    //     pac::FLASH.bank(0)
+    // } else {
+    //     pac::FLASH.bank(1)
+    // };
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+    clear_all_err();
+    pac::FLASH.nscr().write(|w| {
+        w.set_pg(true);
+        // w.set_psize(2); // 32 bits at once
+    });
+    let mut res = None;
+    let mut address = start_address;
+    // TODO: see write size
+    for val in buf.chunks(4) {
+        write_volatile(address as *mut u32, u32::from_le_bytes(unwrap!(val.try_into())));
+        address += val.len() as u32;
+        res = Some(blocking_wait_ready().map_err(|e| {
+            error!("write err");
+            e
+        }));
+        pac::FLASH.nssr().modify(|w| {
+            if w.eop() {
+                w.set_eop(true);
+            }
+        });
+        if unwrap!(res).is_err() {
+            break;
+        }
+    }
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+    pac::FLASH.nscr().write(|w| w.set_pg(false));
+    unwrap!(res)
+}
+pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    // pac::FLASH.wrp2r_cur().read().wrpsg()
+    // TODO: write protection check
+    if pac::FLASH.nscr().read().lock() == true {
+        error!("flash locked");
+    }
+    loop {
+        let sr = pac::FLASH.nssr().read();
+        if !sr.bsy() && !sr.dbne() {
+            break;
+        }
+    }
+    clear_all_err();
+    pac::FLASH.nscr().modify(|r| {
+        // TODO: later check bank swap
+        r.set_bksel(match sector.bank {
+            crate::flash::FlashBank::Bank1 => stm32_metapac::flash::vals::NscrBksel::B_0X0,
+            crate::flash::FlashBank::Bank2 => stm32_metapac::flash::vals::NscrBksel::B_0X1,
+            _ => unreachable!(),
+        });
+        r.set_snb(sector.index_in_bank);
+        r.set_ser(true);
+    });
+    pac::FLASH.nscr().modify(|r| {
+        r.set_strt(true);
+    });
+    cortex_m::asm::isb();
+    cortex_m::asm::dsb();
+    fence(Ordering::SeqCst);
+    let ret: Result<(), Error> = blocking_wait_ready().map_err(|e| {
+        error!("erase err");
+        e
+    });
+    pac::FLASH.nscr().modify(|w| w.set_ser(false));
+    clear_all_err();
+    ret
+}
+pub(crate) unsafe fn clear_all_err() {
+    pac::FLASH.nssr().modify(|_| {})
+}
+unsafe fn blocking_wait_ready() -> Result<(), Error> {
+    loop {
+        let sr = pac::FLASH.nssr().read();
+        if !sr.bsy() {
+            if sr.optchangeerr() {
+                error!("optchangeerr");
+                return Err(Error::Prog);
+            }
+            if sr.obkwerr() {
+                error!("obkwerr");
+                return Err(Error::Seq);
+            }
+            if sr.obkerr() {
+                error!("obkerr");
+                return Err(Error::Seq);
+            }
+            if sr.incerr() {
+                error!("incerr");
+                return Err(Error::Unaligned);
+            }
+            if sr.strberr() {
+                error!("strberr");
+                return Err(Error::Parallelism);
+            }
+            if sr.wrperr() {
+                error!("protected");
+                return Err(Error::Protected);
+            }
+            return Ok(());
+        }
+    }
+}
diff --git a/embassy-stm32/src/flash/h50.rs b/embassy-stm32/src/flash/h50.rs
index 82e77d130..f8e210556 100644
--- a/embassy-stm32/src/flash/h50.rs
+++ b/embassy-stm32/src/flash/h50.rs
@@ -8,17 +8,9 @@ use cortex_m::interrupt;
 use pac::flash::regs::Nssr;
 use pac::flash::vals::Bksel;
-use super::{Error, FlashBank, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{Error, FlashBank, FlashSector, WRITE_SIZE};
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.nscr().modify(|w| w.set_lock(true));
 }
@@ -55,6 +47,7 @@ pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE])
 }
 pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), Error> {
+    assert!(sector.bank != FlashBank::Otp);
    assert!(sector.index_in_bank < 8);
    while busy() {}
@@ -67,6 +60,7 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
                (FlashBank::Bank2, true) => Bksel::BANK1,
                (FlashBank::Bank2, false) => Bksel::BANK2,
                (FlashBank::Bank1, true) => Bksel::BANK2,
+                _ => unreachable!(),
            });
            w.set_snb(sector.index_in_bank);
            w.set_ser(true);
diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs
index 254915381..f1d84101c 100644
--- a/embassy-stm32/src/flash/h7.rs
+++ b/embassy-stm32/src/flash/h7.rs
@@ -1,22 +1,14 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, BANK1_REGION, FLASH_REGIONS, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
 const fn is_dual_bank() -> bool {
    FLASH_REGIONS.len() >= 2
 }
-pub(crate) fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.bank(0).cr().modify(|w| w.set_lock(true));
    if is_dual_bank() {
diff --git a/embassy-stm32/src/flash/l.rs b/embassy-stm32/src/flash/l.rs
index a0bfeb395..1b82704ec 100644
--- a/embassy-stm32/src/flash/l.rs
+++ b/embassy-stm32/src/flash/l.rs
@@ -1,18 +1,10 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    #[cfg(any(flash_wl, flash_wb, flash_l4))]
    pac::FLASH.cr().modify(|w| w.set_lock(true));
@@ -23,6 +15,9 @@ pub(crate) unsafe fn lock() {
        w.set_prglock(true);
        w.set_pelock(true);
    });
+    #[cfg(any(flash_l5))]
+    pac::FLASH.nscr().modify(|w| w.set_nslock(true));
 }
 pub(crate) unsafe fn unlock() {
@@ -46,6 +41,14 @@ pub(crate) unsafe fn unlock() {
            pac::FLASH.prgkeyr().write_value(0x1314_1516);
        }
    }
+    #[cfg(any(flash_l5))]
+    {
+        if pac::FLASH.nscr().read().nslock() {
+            pac::FLASH.nskeyr().write_value(0x4567_0123);
+            pac::FLASH.nskeyr().write_value(0xCDEF_89AB);
+        }
+    }
 }
 pub(crate) unsafe fn enable_blocking_write() {
@@ -53,11 +56,17 @@ pub(crate) unsafe fn enable_blocking_write() {
    #[cfg(any(flash_wl, flash_wb, flash_l4))]
    pac::FLASH.cr().write(|w| w.set_pg(true));
+    #[cfg(any(flash_l5))]
+    pac::FLASH.nscr().write(|w| w.set_nspg(true));
 }
 pub(crate) unsafe fn disable_blocking_write() {
    #[cfg(any(flash_wl, flash_wb, flash_l4))]
    pac::FLASH.cr().write(|w| w.set_pg(false));
+    #[cfg(any(flash_l5))]
+    pac::FLASH.nscr().write(|w| w.set_nspg(false));
 }
 pub(crate) unsafe fn blocking_write(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
@@ -84,13 +93,25 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
        write_volatile(sector.start as *mut u32, 0xFFFFFFFF);
    }
-    #[cfg(any(flash_wl, flash_wb, flash_l4))]
+    #[cfg(any(flash_wl, flash_wb, flash_l4, flash_l5))]
    {
        let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
        #[cfg(flash_l4)]
        let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
+        #[cfg(flash_l5)]
+        let (idx, bank) = if pac::FLASH.optr().read().dbank() {
+            if idx > 255 {
+                (idx - 256, Some(true))
+            } else {
+                (idx, Some(false))
+            }
+        } else {
+            (idx, None)
+        };
+        #[cfg(not(flash_l5))]
        pac::FLASH.cr().modify(|w| {
            w.set_per(true);
            w.set_pnb(idx as u8);
@@ -101,6 +122,16 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
            #[cfg(any(flash_l4))]
            w.set_bker(bank);
        });
+        #[cfg(flash_l5)]
+        pac::FLASH.nscr().modify(|w| {
+            w.set_nsper(true);
+            w.set_nspnb(idx as u8);
+            if let Some(bank) = bank {
+                w.set_nsbker(bank);
+            }
+            w.set_nsstrt(true);
+        });
    }
    let ret: Result<(), Error> = wait_ready_blocking();
@@ -108,6 +139,9 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
    #[cfg(any(flash_wl, flash_wb, flash_l4))]
    pac::FLASH.cr().modify(|w| w.set_per(false));
+    #[cfg(any(flash_l5))]
+    pac::FLASH.nscr().modify(|w| w.set_nsper(false));
    #[cfg(any(flash_l0, flash_l1))]
    pac::FLASH.pecr().modify(|w| {
        w.set_erase(false);
@@ -121,42 +155,98 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
 pub(crate) unsafe fn clear_all_err() {
    // read and write back the same value.
    // This clears all "write 1 to clear" bits.
+    #[cfg(not(flash_l5))]
    pac::FLASH.sr().modify(|_| {});
+    #[cfg(flash_l5)]
+    pac::FLASH.nssr().modify(|_| {});
 }
-unsafe fn wait_ready_blocking() -> Result<(), Error> {
+pub(crate) unsafe fn wait_ready_blocking() -> Result<(), Error> {
    loop {
-        let sr = pac::FLASH.sr().read();
+        #[cfg(not(flash_l5))]
+        {
-        if !sr.bsy() {
+            let sr = pac::FLASH.sr().read();
-            #[cfg(any(flash_wl, flash_wb, flash_l4))]
-            if sr.progerr() {
+            if !sr.bsy() {
-                return Err(Error::Prog);
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.progerr() {
+                    return Err(Error::Prog);
+                }
+                if sr.wrperr() {
+                    return Err(Error::Protected);
+                }
+                if sr.pgaerr() {
+                    return Err(Error::Unaligned);
+                }
+                if sr.sizerr() {
+                    return Err(Error::Size);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.miserr() {
+                    return Err(Error::Miss);
+                }
+                #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if sr.pgserr() {
+                    return Err(Error::Seq);
+                }
+                return Ok(());
            }
+        }
-            if sr.wrperr() {
+        #[cfg(flash_l5)]
-                return Err(Error::Protected);
+        {
-            }
+            let nssr = pac::FLASH.nssr().read();
-            if sr.pgaerr() {
+            if !nssr.nsbsy() {
-                return Err(Error::Unaligned);
+                if nssr.nsprogerr() {
-            }
+                    return Err(Error::Prog);
+                }
-            if sr.sizerr() {
+                if nssr.nswrperr() {
-                return Err(Error::Size);
+                    return Err(Error::Protected);
-            }
+                }
-            #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if nssr.nspgaerr() {
-            if sr.miserr() {
+                    return Err(Error::Unaligned);
-                return Err(Error::Miss);
+                }
-            }
-            #[cfg(any(flash_wl, flash_wb, flash_l4))]
+                if nssr.nssizerr() {
-            if sr.pgserr() {
+                    return Err(Error::Size);
-                return Err(Error::Seq);
+                }
-            }
+                if nssr.nspgserr() {
+                    return Err(Error::Seq);
+                }
-            return Ok(());
+                return Ok(());
+            }
        }
    }
 }
+#[cfg(all(bank_setup_configurable, flash_l5))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dbank() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dbank() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dbank value in the user option bytes or configure embassy to use single-bank config");
+    }
+}
+#[cfg(all(bank_setup_configurable, flash_l4))]
+pub(crate) fn check_bank_setup() {
+    if cfg!(feature = "single-bank") && pac::FLASH.optr().read().dualbank() {
+        panic!("Embassy is configured as single-bank, but the hardware is running in dual-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use dual-bank config");
+    }
+    if cfg!(feature = "dual-bank") && !pac::FLASH.optr().read().dualbank() {
+        panic!("Embassy is configured as dual-bank, but the hardware is running in single-bank mode. Change the hardware by changing the dualbank value in the user option bytes or configure embassy to use single-bank config");
+    }
+}
diff --git a/embassy-stm32/src/flash/mod.rs b/embassy-stm32/src/flash/mod.rs
index ce2d1a04c..a3f9e00f7 100644
--- a/embassy-stm32/src/flash/mod.rs
+++ b/embassy-stm32/src/flash/mod.rs
@@ -5,27 +5,25 @@ use embedded_storage::nor_flash::{NorFlashError, NorFlashErrorKind};
 mod asynch;
 #[cfg(flash)]
 mod common;
+#[cfg(eeprom)]
+mod eeprom;
 #[cfg(flash_f4)]
 pub use asynch::InterruptHandler;
 #[cfg(flash)]
 pub use common::*;
+#[cfg(eeprom)]
+#[allow(unused_imports)]
+pub use eeprom::*;
 pub use crate::_generated::flash_regions::*;
-pub use crate::_generated::MAX_ERASE_SIZE;
+#[cfg(eeprom)]
-pub use crate::pac::{FLASH_BASE, FLASH_SIZE, WRITE_SIZE};
+pub use crate::_generated::{EEPROM_BASE, EEPROM_SIZE};
+pub use crate::_generated::{FLASH_BASE, FLASH_SIZE, MAX_ERASE_SIZE, WRITE_SIZE};
-/// Get whether the default flash layout is being used.
-///
-/// In some chips, dual-bank is not default. This will then return `false`
-/// when dual-bank is enabled.
-pub fn is_default_layout() -> bool {
-    family::is_default_layout()
-}
 /// Get all flash regions.
 pub fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    family::get_flash_regions()
+    &FLASH_REGIONS
 }
 /// Read size (always 1)
@@ -89,23 +87,29 @@ pub enum FlashBank {
    Bank1 = 0,
    /// Bank 2
    Bank2 = 1,
+    /// OTP region,
+    Otp,
 }
+#[cfg(all(eeprom, not(any(flash_l0, flash_l1))))]
-#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_wl, flash_wb), path = "l.rs")]
+compile_error!("The 'eeprom' cfg is enabled for a non-L0/L1 chip family. This is an unsupported configuration.");
+#[cfg_attr(any(flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb), path = "l.rs")]
 #[cfg_attr(flash_f0, path = "f0.rs")]
 #[cfg_attr(any(flash_f1, flash_f3), path = "f1f3.rs")]
+#[cfg_attr(flash_f2, path = "f2.rs")]
 #[cfg_attr(flash_f4, path = "f4.rs")]
 #[cfg_attr(flash_f7, path = "f7.rs")]
-#[cfg_attr(any(flash_g0, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
+#[cfg_attr(any(flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4), path = "g.rs")]
 #[cfg_attr(flash_h7, path = "h7.rs")]
 #[cfg_attr(flash_h7ab, path = "h7.rs")]
 #[cfg_attr(flash_u5, path = "u5.rs")]
+#[cfg_attr(flash_h5, path = "h5.rs")]
 #[cfg_attr(flash_h50, path = "h50.rs")]
 #[cfg_attr(flash_u0, path = "u0.rs")]
 #[cfg_attr(
    not(any(
-        flash_l0, flash_l1, flash_l4, flash_wl, flash_wb, flash_f0, flash_f1, flash_f3, flash_f4, flash_f7, flash_g0,
+        flash_l0, flash_l1, flash_l4, flash_l5, flash_wl, flash_wb, flash_f0, flash_f1, flash_f2, flash_f3, flash_f4,
-        flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5, flash_h50, flash_u0
+        flash_f7, flash_g0x0, flash_g0x1, flash_g4c2, flash_g4c3, flash_g4c4, flash_h7, flash_h7ab, flash_u5,
+        flash_h50, flash_u0, flash_h5,
    )),
    path = "other.rs"
 )]
diff --git a/embassy-stm32/src/flash/other.rs b/embassy-stm32/src/flash/other.rs
index 20f84a72f..293a79be3 100644
--- a/embassy-stm32/src/flash/other.rs
+++ b/embassy-stm32/src/flash/other.rs
@@ -1,14 +1,6 @@
 #![allow(unused)]
-use super::{Error, FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{Error, FlashSector, WRITE_SIZE};
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    unimplemented!();
diff --git a/embassy-stm32/src/flash/u0.rs b/embassy-stm32/src/flash/u0.rs
index bfdbd15a5..68d847eca 100644
--- a/embassy-stm32/src/flash/u0.rs
+++ b/embassy-stm32/src/flash/u0.rs
@@ -3,18 +3,10 @@ use core::sync::atomic::{fence, Ordering};
 use cortex_m::interrupt;
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    pac::FLASH.cr().modify(|w| w.set_lock(true));
 }
diff --git a/embassy-stm32/src/flash/u5.rs b/embassy-stm32/src/flash/u5.rs
index 0601017ce..131caa195 100644
--- a/embassy-stm32/src/flash/u5.rs
+++ b/embassy-stm32/src/flash/u5.rs
@@ -1,18 +1,10 @@
 use core::ptr::write_volatile;
 use core::sync::atomic::{fence, Ordering};
-use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
+use super::{FlashBank, FlashSector, WRITE_SIZE};
 use crate::flash::Error;
 use crate::pac;
-pub(crate) const fn is_default_layout() -> bool {
-    true
-}
-pub(crate) const fn get_flash_regions() -> &'static [&'static FlashRegion] {
-    &FLASH_REGIONS
-}
 pub(crate) unsafe fn lock() {
    #[cfg(feature = "trustzone-secure")]
    pac::FLASH.seccr().modify(|w| w.set_lock(true));
@@ -70,12 +62,24 @@ pub(crate) unsafe fn blocking_erase_sector(sector: &FlashSector) -> Result<(), E
    #[cfg(feature = "trustzone-secure")]
    pac::FLASH.seccr().modify(|w| {
        w.set_per(pac::flash::vals::SeccrPer::B_0X1);
-        w.set_pnb(sector.index_in_bank)
+        w.set_pnb(sector.index_in_bank);
+        // TODO: add check for bank swap
+        w.set_bker(match sector.bank {
+            FlashBank::Bank1 => pac::flash::vals::SeccrBker::B_0X0,
+            FlashBank::Bank2 => pac::flash::vals::SeccrBker::B_0X1,
+            _ => unreachable!(),
+        });
    });
    #[cfg(not(feature = "trustzone-secure"))]
    pac::FLASH.nscr().modify(|w| {
        w.set_per(pac::flash::vals::NscrPer::B_0X1);
-        w.set_pnb(sector.index_in_bank)
+        w.set_pnb(sector.index_in_bank);
+        // TODO: add check for bank swap
+        w.set_bker(match sector.bank {
+            FlashBank::Bank1 => pac::flash::vals::NscrBker::B_0X0,
+            FlashBank::Bank2 => pac::flash::vals::NscrBker::B_0X1,
+            _ => unreachable!(),
+        });
    });
    #[cfg(feature = "trustzone-secure")]
diff --git a/embassy-stm32/src/fmc.rs b/embassy-stm32/src/fmc.rs
index 83b49a3dd..71ca775cb 100644
--- a/embassy-stm32/src/fmc.rs
+++ b/embassy-stm32/src/fmc.rs
@@ -1,10 +1,10 @@
 //! Flexible Memory Controller (FMC) / Flexible Static Memory Controller (FSMC)
 use core::marker::PhantomData;
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use crate::gpio::{AfType, OutputType, Pull, Speed};
-use crate::{rcc, Peripheral};
+use crate::{rcc, Peri};
 /// FMC driver
 pub struct Fmc<'d, T: Instance> {
@@ -21,7 +21,7 @@ where
    ///
    /// **Note:** This is currently used to provide access to some basic FMC functions
    /// for manual configuration for memory types that stm32-fmc does not support.
-    pub fn new_raw(_instance: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new_raw(_instance: Peri<'d, T>) -> Self {
        Self { peri: PhantomData }
    }
@@ -74,8 +74,7 @@ where
 macro_rules! config_pins {
    ($($pin:ident),*) => {
-        into_ref!($($pin),*);
+                $(
-        $(
            $pin.set_as_af($pin.af_num(), AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up));
        )*
    };
@@ -92,12 +91,12 @@ macro_rules! fmc_sdram_constructor {
    )) => {
        /// Create a new FMC instance.
        pub fn $name<CHIP: stm32_fmc::SdramChip>(
-            _instance: impl Peripheral<P = T> + 'd,
+            _instance: Peri<'d, T>,
-            $($addr_pin_name: impl Peripheral<P = impl $addr_signal<T>> + 'd),*,
+            $($addr_pin_name: Peri<'d, impl $addr_signal<T>>),*,
-            $($ba_pin_name: impl Peripheral<P = impl $ba_signal<T>> + 'd),*,
+            $($ba_pin_name: Peri<'d, impl $ba_signal<T>>),*,
-            $($d_pin_name: impl Peripheral<P = impl $d_signal<T>> + 'd),*,
+            $($d_pin_name: Peri<'d, impl $d_signal<T>>),*,
-            $($nbl_pin_name: impl Peripheral<P = impl $nbl_signal<T>> + 'd),*,
+            $($nbl_pin_name: Peri<'d, impl $nbl_signal<T>>),*,
-            $($ctrl_pin_name: impl Peripheral<P = impl $ctrl_signal<T>> + 'd),*,
+            $($ctrl_pin_name: Peri<'d, impl $ctrl_signal<T>>),*,
            chip: CHIP
        ) -> stm32_fmc::Sdram<Fmc<'d, T>, CHIP> {
@@ -245,7 +244,7 @@ trait SealedInstance: crate::rcc::RccPeripheral {
 /// FMC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 foreach_peripheral!(
    (fmc, $inst:ident) => {
diff --git a/embassy-stm32/src/fmt.rs b/embassy-stm32/src/fmt.rs
index 8ca61bc39..b6ae24ee8 100644
--- a/embassy-stm32/src/fmt.rs
+++ b/embassy-stm32/src/fmt.rs
@@ -7,6 +7,28 @@ use core::fmt::{Debug, Display, LowerHex};
 compile_error!("You may not enable both `defmt` and `log` features.");
 #[collapse_debuginfo(yes)]
+macro_rules! rcc_assert {
+    ($($x:tt)*) => {
+        {
+            #[cfg(not(feature = "unchecked-overclocking"))]
+            {
+                #[cfg(not(feature = "defmt"))]
+                ::core::assert!($($x)*);
+                #[cfg(feature = "defmt")]
+                ::defmt::assert!($($x)*);
+            }
+            #[cfg(feature = "unchecked-overclocking")]
+            {
+                #[cfg(feature = "log")]
+                ::log::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
+                #[cfg(feature = "defmt")]
+                ::defmt::warn!("`rcc_assert!` skipped: `unchecked-overclocking` feature is enabled.");
+            }
+        }
+    };
+}
+#[collapse_debuginfo(yes)]
 macro_rules! assert {
    ($($x:tt)*) => {
        {
diff --git a/embassy-stm32/src/gpio.rs b/embassy-stm32/src/gpio.rs
index 87519f51e..bb37c4194 100644
--- a/embassy-stm32/src/gpio.rs
+++ b/embassy-stm32/src/gpio.rs
@@ -4,10 +4,10 @@
 use core::convert::Infallible;
 use critical_section::CriticalSection;
-use embassy_hal_internal::{impl_peripheral, into_ref, PeripheralRef};
+use embassy_hal_internal::{impl_peripheral, Peri, PeripheralType};
 use crate::pac::gpio::{self, vals};
-use crate::{pac, peripherals, Peripheral};
+use crate::peripherals;
 /// GPIO flexible pin.
 ///
@@ -15,7 +15,7 @@ use crate::{pac, peripherals, Peripheral};
 /// set while not in output mode, so the pin's level will be 'remembered' when it is not in output
 /// mode.
 pub struct Flex<'d> {
-    pub(crate) pin: PeripheralRef<'d, AnyPin>,
+    pub(crate) pin: Peri<'d, AnyPin>,
 }
 impl<'d> Flex<'d> {
@@ -25,10 +25,9 @@ impl<'d> Flex<'d> {
    /// before the pin is put into output mode.
    ///
    #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>) -> Self {
-        into_ref!(pin);
        // Pin will be in disconnected state.
-        Self { pin: pin.map_into() }
+        Self { pin: pin.into() }
    }
    /// Put the pin into input mode.
@@ -61,7 +60,7 @@ impl<'d> Flex<'d> {
            #[cfg(gpio_v2)]
            {
                r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
-                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
+                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
                r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
            }
        });
@@ -82,13 +81,13 @@ impl<'d> Flex<'d> {
            {
                r.cr(n / 8).modify(|w| {
                    w.set_mode(n % 8, speed.to_mode());
-                    w.set_cnf_out(n % 8, vals::CnfOut::PUSHPULL);
+                    w.set_cnf_out(n % 8, vals::CnfOut::PUSH_PULL);
                });
            }
            #[cfg(gpio_v2)]
            {
                r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
-                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
+                r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSH_PULL));
                r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
                r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
            }
@@ -112,7 +111,7 @@ impl<'d> Flex<'d> {
            let r = self.pin.block();
            let n = self.pin.pin() as usize;
            r.cr(n / 8).modify(|w| w.set_mode(n % 8, speed.to_mode()));
-            r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPENDRAIN));
+            r.cr(n / 8).modify(|w| w.set_cnf_out(n % 8, vals::CnfOut::OPEN_DRAIN));
        });
        #[cfg(gpio_v2)]
@@ -130,7 +129,7 @@ impl<'d> Flex<'d> {
            let r = self.pin.block();
            let n = self.pin.pin() as usize;
            r.pupdr().modify(|w| w.set_pupdr(n, pull.to_pupdr()));
-            r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPENDRAIN));
+            r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPEN_DRAIN));
            r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
            r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
        });
@@ -253,8 +252,8 @@ impl Pull {
    const fn to_pupdr(self) -> vals::Pupdr {
        match self {
            Pull::None => vals::Pupdr::FLOATING,
-            Pull::Up => vals::Pupdr::PULLUP,
+            Pull::Up => vals::Pupdr::PULL_UP,
-            Pull::Down => vals::Pupdr::PULLDOWN,
+            Pull::Down => vals::Pupdr::PULL_DOWN,
        }
    }
 }
@@ -293,11 +292,11 @@ impl Speed {
    #[cfg(gpio_v2)]
    const fn to_ospeedr(self: Speed) -> vals::Ospeedr {
        match self {
-            Speed::Low => vals::Ospeedr::LOWSPEED,
+            Speed::Low => vals::Ospeedr::LOW_SPEED,
-            Speed::Medium => vals::Ospeedr::MEDIUMSPEED,
+            Speed::Medium => vals::Ospeedr::MEDIUM_SPEED,
            #[cfg(not(syscfg_f0))]
-            Speed::High => vals::Ospeedr::HIGHSPEED,
+            Speed::High => vals::Ospeedr::HIGH_SPEED,
-            Speed::VeryHigh => vals::Ospeedr::VERYHIGHSPEED,
+            Speed::VeryHigh => vals::Ospeedr::VERY_HIGH_SPEED,
        }
    }
 }
@@ -310,7 +309,7 @@ pub struct Input<'d> {
 impl<'d> Input<'d> {
    /// Create GPIO input driver for a [Pin] with the provided [Pull] configuration.
    #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, pull: Pull) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, pull: Pull) -> Self {
        let mut pin = Flex::new(pin);
        pin.set_as_input(pull);
        Self { pin }
@@ -375,7 +374,7 @@ pub struct Output<'d> {
 impl<'d> Output<'d> {
    /// Create GPIO output driver for a [Pin] with the provided [Level] and [Speed] configuration.
    #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed) -> Self {
        let mut pin = Flex::new(pin);
        match initial_output {
            Level::High => pin.set_high(),
@@ -440,7 +439,7 @@ pub struct OutputOpenDrain<'d> {
 impl<'d> OutputOpenDrain<'d> {
    /// Create a new GPIO open drain output driver for a [Pin] with the provided [Level] and [Speed].
    #[inline]
-    pub fn new(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed) -> Self {
+    pub fn new(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed) -> Self {
        let mut pin = Flex::new(pin);
        match initial_output {
            Level::High => pin.set_high(),
@@ -454,7 +453,7 @@ impl<'d> OutputOpenDrain<'d> {
    /// and [Pull].
    #[inline]
    #[cfg(gpio_v2)]
-    pub fn new_pull(pin: impl Peripheral<P = impl Pin> + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
+    pub fn new_pull(pin: Peri<'d, impl Pin>, initial_output: Level, speed: Speed, pull: Pull) -> Self {
        let mut pin = Flex::new(pin);
        match initial_output {
            Level::High => pin.set_high(),
@@ -539,16 +538,16 @@ impl OutputType {
    #[cfg(gpio_v1)]
    const fn to_cnf_out(self) -> vals::CnfOut {
        match self {
-            OutputType::PushPull => vals::CnfOut::ALTPUSHPULL,
+            OutputType::PushPull => vals::CnfOut::ALT_PUSH_PULL,
-            OutputType::OpenDrain => vals::CnfOut::ALTOPENDRAIN,
+            OutputType::OpenDrain => vals::CnfOut::ALT_OPEN_DRAIN,
        }
    }
    #[cfg(gpio_v2)]
    const fn to_ot(self) -> vals::Ot {
        match self {
-            OutputType::PushPull => vals::Ot::PUSHPULL,
+            OutputType::PushPull => vals::Ot::PUSH_PULL,
-            OutputType::OpenDrain => vals::Ot::OPENDRAIN,
+            OutputType::OpenDrain => vals::Ot::OPEN_DRAIN,
        }
    }
 }
@@ -624,8 +623,8 @@ impl AfType {
    pub const fn input(pull: Pull) -> Self {
        Self {
            pupdr: pull.to_pupdr(),
-            ot: vals::Ot::PUSHPULL,
+            ot: vals::Ot::PUSH_PULL,
-            ospeedr: vals::Ospeedr::LOWSPEED,
+            ospeedr: vals::Ospeedr::LOW_SPEED,
        }
    }
@@ -659,6 +658,16 @@ fn set_as_af(pin_port: u8, af_num: u8, af_type: AfType) {
 }
 #[inline(never)]
+#[cfg(gpio_v2)]
+fn set_speed(pin_port: u8, speed: Speed) {
+    let pin = unsafe { AnyPin::steal(pin_port) };
+    let r = pin.block();
+    let n = pin._pin() as usize;
+    r.ospeedr().modify(|w| w.set_ospeedr(n, speed.to_ospeedr()));
+}
+#[inline(never)]
 fn set_as_analog(pin_port: u8) {
    let pin = unsafe { AnyPin::steal(pin_port) };
    let r = pin.block();
@@ -695,8 +704,8 @@ fn get_pull(pin_port: u8) -> Pull {
    #[cfg(gpio_v2)]
    return match r.pupdr().read().pupdr(n) {
        vals::Pupdr::FLOATING => Pull::None,
-        vals::Pupdr::PULLDOWN => Pull::Down,
+        vals::Pupdr::PULL_DOWN => Pull::Down,
-        vals::Pupdr::PULLUP => Pull::Up,
+        vals::Pupdr::PULL_UP => Pull::Up,
        vals::Pupdr::_RESERVED_3 => Pull::None,
    };
 }
@@ -716,7 +725,7 @@ pub(crate) trait SealedPin {
    #[inline]
    fn block(&self) -> gpio::Gpio {
-        pac::GPIO(self._port() as _)
+        crate::_generated::gpio_block(self._port() as _)
    }
    /// Set the output as high.
@@ -739,6 +748,12 @@ pub(crate) trait SealedPin {
    }
    #[inline]
+    #[cfg(gpio_v2)]
+    fn set_speed(&self, speed: Speed) {
+        set_speed(self.pin_port(), speed)
+    }
+    #[inline]
    fn set_as_analog(&self) {
        set_as_analog(self.pin_port());
    }
@@ -764,7 +779,7 @@ pub(crate) trait SealedPin {
 /// GPIO pin trait.
 #[allow(private_bounds)]
-pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + SealedPin + Sized + 'static {
+pub trait Pin: PeripheralType + Into<AnyPin> + SealedPin + Sized + 'static {
    /// EXTI channel assigned to this pin.
    ///
    /// For example, PC4 uses EXTI4.
@@ -782,18 +797,6 @@ pub trait Pin: Peripheral<P = Self> + Into<AnyPin> + SealedPin + Sized + 'static
    fn port(&self) -> u8 {
        self._port()
    }
-    /// Type-erase (degrade) this pin into an `AnyPin`.
-    ///
-    /// This converts pin singletons (`PA5`, `PB6`, ...), which
-    /// are all different types, into the same type. It is useful for
-    /// creating arrays of pins, or avoiding generics.
-    #[inline]
-    fn degrade(self) -> AnyPin {
-        AnyPin {
-            pin_port: self.pin_port(),
-        }
-    }
 }
 /// Type-erased GPIO pin
@@ -806,8 +809,8 @@ impl AnyPin {
    ///
    /// `pin_port` is `port_num * 16 + pin_num`, where `port_num` is 0 for port `A`, 1 for port `B`, etc...
    #[inline]
-    pub unsafe fn steal(pin_port: u8) -> Self {
+    pub unsafe fn steal(pin_port: u8) -> Peri<'static, Self> {
-        Self { pin_port }
+        Peri::new_unchecked(Self { pin_port })
    }
    #[inline]
@@ -819,7 +822,7 @@ impl AnyPin {
    #[cfg(feature = "unstable-pac")]
    #[inline]
    pub fn block(&self) -> gpio::Gpio {
-        pac::GPIO(self._port() as _)
+        crate::_generated::gpio_block(self._port() as _)
    }
 }
@@ -851,8 +854,10 @@ foreach_pin!(
        }
        impl From<peripherals::$pin_name> for AnyPin {
-            fn from(x: peripherals::$pin_name) -> Self {
+            fn from(val: peripherals::$pin_name) -> Self {
-                x.degrade()
+                Self {
+                    pin_port: val.pin_port(),
+                }
            }
        }
    };
diff --git a/embassy-stm32/src/hash/mod.rs b/embassy-stm32/src/hash/mod.rs
index 4d4a8ec5b..e62151bb5 100644
--- a/embassy-stm32/src/hash/mod.rs
+++ b/embassy-stm32/src/hash/mod.rs
@@ -8,16 +8,18 @@ use core::ptr;
 #[cfg(hash_v2)]
 use core::task::Poll;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use stm32_metapac::hash::regs::*;
-use crate::dma::NoDma;
 #[cfg(hash_v2)]
-use crate::dma::Transfer;
+use crate::dma::ChannelAndRequest;
 use crate::interrupt::typelevel::Interrupt;
+#[cfg(hash_v2)]
+use crate::mode::Async;
+use crate::mode::{Blocking, Mode};
 use crate::peripherals::HASH;
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::{interrupt, pac, peripherals, rcc, Peri};
 #[cfg(hash_v1)]
 const NUM_CONTEXT_REGS: usize = 51;
@@ -99,6 +101,7 @@ pub enum DataType {
 /// Stores the state of the HASH peripheral for suspending/resuming
 /// digest calculation.
+#[derive(Clone)]
 pub struct Context<'c> {
    first_word_sent: bool,
    key_sent: bool,
@@ -116,24 +119,25 @@ pub struct Context<'c> {
 type HmacKey<'k> = Option<&'k [u8]>;
 /// HASH driver.
-pub struct Hash<'d, T: Instance, D = NoDma> {
+pub struct Hash<'d, T: Instance, M: Mode> {
-    _peripheral: PeripheralRef<'d, T>,
+    _peripheral: Peri<'d, T>,
-    #[allow(dead_code)]
+    _phantom: PhantomData<M>,
-    dma: PeripheralRef<'d, D>,
+    #[cfg(hash_v2)]
+    dma: Option<ChannelAndRequest<'d>>,
 }
-impl<'d, T: Instance, D> Hash<'d, T, D> {
+impl<'d, T: Instance> Hash<'d, T, Blocking> {
    /// Instantiates, resets, and enables the HASH peripheral.
-    pub fn new(
+    pub fn new_blocking(
-        peripheral: impl Peripheral<P = T> + 'd,
+        peripheral: Peri<'d, T>,
-        dma: impl Peripheral<P = D> + 'd,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
        rcc::enable_and_reset::<HASH>();
-        into_ref!(peripheral, dma);
        let instance = Self {
            _peripheral: peripheral,
-            dma: dma,
+            _phantom: PhantomData,
+            #[cfg(hash_v2)]
+            dma: None,
        };
        T::Interrupt::unpend();
@@ -141,7 +145,9 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
        instance
    }
+}
+impl<'d, T: Instance, M: Mode> Hash<'d, T, M> {
    /// Starts computation of a new hash and returns the saved peripheral state.
    pub fn start<'c>(&mut self, algorithm: Algorithm, format: DataType, key: HmacKey<'c>) -> Context<'c> {
        // Define a context for this new computation.
@@ -282,14 +288,135 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
        self.store_context(ctx);
    }
+    /// Computes a digest for the given context.
+    /// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
+    /// The largest returned digest size is 128 bytes for SHA-512.
+    /// Panics if the supplied digest buffer is too short.
+    pub fn finish_blocking<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize {
+        // Restore the peripheral state.
+        self.load_context(&ctx);
+        // Hash the leftover bytes, if any.
+        self.accumulate_blocking(&ctx.buffer[0..ctx.buflen]);
+        ctx.buflen = 0;
+        //Start the digest calculation.
+        T::regs().str().write(|w| w.set_dcal(true));
+        // Load the HMAC key if provided.
+        if let Some(key) = ctx.key {
+            while !T::regs().sr().read().dinis() {}
+            self.accumulate_blocking(key);
+            T::regs().str().write(|w| w.set_dcal(true));
+        }
+        // Block until digest computation is complete.
+        while !T::regs().sr().read().dcis() {}
+        // Return the digest.
+        let digest_words = match ctx.algo {
+            Algorithm::SHA1 => 5,
+            #[cfg(any(hash_v1, hash_v2, hash_v4))]
+            Algorithm::MD5 => 4,
+            Algorithm::SHA224 => 7,
+            Algorithm::SHA256 => 8,
+            #[cfg(hash_v3)]
+            Algorithm::SHA384 => 12,
+            #[cfg(hash_v3)]
+            Algorithm::SHA512_224 => 7,
+            #[cfg(hash_v3)]
+            Algorithm::SHA512_256 => 8,
+            #[cfg(hash_v3)]
+            Algorithm::SHA512 => 16,
+        };
+        let digest_len_bytes = digest_words * 4;
+        // Panics if the supplied digest buffer is too short.
+        if digest.len() < digest_len_bytes {
+            panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
+        }
+        let mut i = 0;
+        while i < digest_words {
+            let word = T::regs().hr(i).read();
+            digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
+            i += 1;
+        }
+        digest_len_bytes
+    }
+    /// Push data into the hash core.
+    fn accumulate_blocking(&mut self, input: &[u8]) {
+        // Set the number of valid bits.
+        let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
+        T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
+        let mut i = 0;
+        while i < input.len() {
+            let mut word: [u8; 4] = [0; 4];
+            let copy_idx = min(i + 4, input.len());
+            word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
+            T::regs().din().write_value(u32::from_ne_bytes(word));
+            i += 4;
+        }
+    }
+    /// Save the peripheral state to a context.
+    fn store_context<'c>(&mut self, ctx: &mut Context<'c>) {
+        // Block waiting for data in ready.
+        while !T::regs().sr().read().dinis() {}
+        // Store peripheral context.
+        ctx.imr = T::regs().imr().read().0;
+        ctx.str = T::regs().str().read().0;
+        ctx.cr = T::regs().cr().read().0;
+        let mut i = 0;
+        while i < NUM_CONTEXT_REGS {
+            ctx.csr[i] = T::regs().csr(i).read();
+            i += 1;
+        }
+    }
+    /// Restore the peripheral state from a context.
+    fn load_context(&mut self, ctx: &Context) {
+        // Restore the peripheral state from the context.
+        T::regs().imr().write_value(Imr { 0: ctx.imr });
+        T::regs().str().write_value(Str { 0: ctx.str });
+        T::regs().cr().write_value(Cr { 0: ctx.cr });
+        T::regs().cr().modify(|w| w.set_init(true));
+        let mut i = 0;
+        while i < NUM_CONTEXT_REGS {
+            T::regs().csr(i).write_value(ctx.csr[i]);
+            i += 1;
+        }
+    }
+}
+#[cfg(hash_v2)]
+impl<'d, T: Instance> Hash<'d, T, Async> {
+    /// Instantiates, resets, and enables the HASH peripheral.
+    pub fn new(
+        peripheral: Peri<'d, T>,
+        dma: Peri<'d, impl Dma<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+    ) -> Self {
+        rcc::enable_and_reset::<HASH>();
+        let instance = Self {
+            _peripheral: peripheral,
+            _phantom: PhantomData,
+            dma: new_dma!(dma),
+        };
+        T::Interrupt::unpend();
+        unsafe { T::Interrupt::enable() };
+        instance
+    }
    /// Restores the peripheral state using the given context,
    /// then updates the state with the provided data.
    /// Peripheral state is saved upon return.
-    #[cfg(hash_v2)]
+    pub async fn update(&mut self, ctx: &mut Context<'_>, input: &[u8]) {
-    pub async fn update<'c>(&mut self, ctx: &mut Context<'c>, input: &[u8])
-    where
-        D: crate::hash::Dma<T>,
-    {
        // Restore the peripheral state.
        self.load_context(&ctx);
@@ -353,68 +480,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
    /// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
    /// The largest returned digest size is 128 bytes for SHA-512.
    /// Panics if the supplied digest buffer is too short.
-    pub fn finish_blocking<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize {
+    pub async fn finish<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize {
-        // Restore the peripheral state.
-        self.load_context(&ctx);
-        // Hash the leftover bytes, if any.
-        self.accumulate_blocking(&ctx.buffer[0..ctx.buflen]);
-        ctx.buflen = 0;
-        //Start the digest calculation.
-        T::regs().str().write(|w| w.set_dcal(true));
-        // Load the HMAC key if provided.
-        if let Some(key) = ctx.key {
-            while !T::regs().sr().read().dinis() {}
-            self.accumulate_blocking(key);
-            T::regs().str().write(|w| w.set_dcal(true));
-        }
-        // Block until digest computation is complete.
-        while !T::regs().sr().read().dcis() {}
-        // Return the digest.
-        let digest_words = match ctx.algo {
-            Algorithm::SHA1 => 5,
-            #[cfg(any(hash_v1, hash_v2, hash_v4))]
-            Algorithm::MD5 => 4,
-            Algorithm::SHA224 => 7,
-            Algorithm::SHA256 => 8,
-            #[cfg(hash_v3)]
-            Algorithm::SHA384 => 12,
-            #[cfg(hash_v3)]
-            Algorithm::SHA512_224 => 7,
-            #[cfg(hash_v3)]
-            Algorithm::SHA512_256 => 8,
-            #[cfg(hash_v3)]
-            Algorithm::SHA512 => 16,
-        };
-        let digest_len_bytes = digest_words * 4;
-        // Panics if the supplied digest buffer is too short.
-        if digest.len() < digest_len_bytes {
-            panic!("Digest buffer must be at least {} bytes long.", digest_words * 4);
-        }
-        let mut i = 0;
-        while i < digest_words {
-            let word = T::regs().hr(i).read();
-            digest[(i * 4)..((i * 4) + 4)].copy_from_slice(word.to_be_bytes().as_slice());
-            i += 1;
-        }
-        digest_len_bytes
-    }
-    /// Computes a digest for the given context.
-    /// The digest buffer must be large enough to accomodate a digest for the selected algorithm.
-    /// The largest returned digest size is 128 bytes for SHA-512.
-    /// Panics if the supplied digest buffer is too short.
-    #[cfg(hash_v2)]
-    pub async fn finish<'c>(&mut self, mut ctx: Context<'c>, digest: &mut [u8]) -> usize
-    where
-        D: crate::hash::Dma<T>,
-    {
        // Restore the peripheral state.
        self.load_context(&ctx);
@@ -483,27 +549,7 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
    }
    /// Push data into the hash core.
-    fn accumulate_blocking(&mut self, input: &[u8]) {
+    async fn accumulate(&mut self, input: &[u8]) {
-        // Set the number of valid bits.
-        let num_valid_bits: u8 = (8 * (input.len() % 4)) as u8;
-        T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
-        let mut i = 0;
-        while i < input.len() {
-            let mut word: [u8; 4] = [0; 4];
-            let copy_idx = min(i + 4, input.len());
-            word[0..copy_idx - i].copy_from_slice(&input[i..copy_idx]);
-            T::regs().din().write_value(u32::from_ne_bytes(word));
-            i += 4;
-        }
-    }
-    /// Push data into the hash core.
-    #[cfg(hash_v2)]
-    async fn accumulate(&mut self, input: &[u8])
-    where
-        D: crate::hash::Dma<T>,
-    {
        // Ignore an input length of 0.
        if input.len() == 0 {
            return;
@@ -514,50 +560,20 @@ impl<'d, T: Instance, D> Hash<'d, T, D> {
        T::regs().str().modify(|w| w.set_nblw(num_valid_bits));
        // Configure DMA to transfer input to hash core.
-        let dma_request = self.dma.request();
+        let dst_ptr: *mut u32 = T::regs().din().as_ptr();
-        let dst_ptr = T::regs().din().as_ptr();
        let mut num_words = input.len() / 4;
        if input.len() % 4 > 0 {
            num_words += 1;
        }
-        let src_ptr = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
+        let src_ptr: *const [u8] = ptr::slice_from_raw_parts(input.as_ptr().cast(), num_words);
-        let dma_transfer =
-            unsafe { Transfer::new_write_raw(&mut self.dma, dma_request, src_ptr, dst_ptr, Default::default()) };
+        let dma = self.dma.as_mut().unwrap();
+        let dma_transfer = unsafe { dma.write_raw(src_ptr, dst_ptr as *mut u32, Default::default()) };
        T::regs().cr().modify(|w| w.set_dmae(true));
        // Wait for the transfer to complete.
        dma_transfer.await;
    }
-    /// Save the peripheral state to a context.
-    fn store_context<'c>(&mut self, ctx: &mut Context<'c>) {
-        // Block waiting for data in ready.
-        while !T::regs().sr().read().dinis() {}
-        // Store peripheral context.
-        ctx.imr = T::regs().imr().read().0;
-        ctx.str = T::regs().str().read().0;
-        ctx.cr = T::regs().cr().read().0;
-        let mut i = 0;
-        while i < NUM_CONTEXT_REGS {
-            ctx.csr[i] = T::regs().csr(i).read();
-            i += 1;
-        }
-    }
-    /// Restore the peripheral state from a context.
-    fn load_context(&mut self, ctx: &Context) {
-        // Restore the peripheral state from the context.
-        T::regs().imr().write_value(Imr { 0: ctx.imr });
-        T::regs().str().write_value(Str { 0: ctx.str });
-        T::regs().cr().write_value(Cr { 0: ctx.cr });
-        T::regs().cr().modify(|w| w.set_init(true));
-        let mut i = 0;
-        while i < NUM_CONTEXT_REGS {
-            T::regs().csr(i).write_value(ctx.csr[i]);
-            i += 1;
-        }
-    }
 }
 trait SealedInstance {
@@ -566,7 +582,7 @@ trait SealedInstance {
 /// HASH instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
    /// Interrupt for this HASH instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/hrtim/mod.rs b/embassy-stm32/src/hrtim/mod.rs
index 13343fc2a..1d0594125 100644
--- a/embassy-stm32/src/hrtim/mod.rs
+++ b/embassy-stm32/src/hrtim/mod.rs
@@ -4,12 +4,12 @@ mod traits;
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::Peri;
 pub use traits::Instance;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::rcc;
 use crate::time::Hertz;
-use crate::{rcc, Peripheral};
 /// HRTIM burst controller instance.
 pub struct BurstController<T: Instance> {
@@ -62,13 +62,13 @@ pub trait AdvancedChannel<T: Instance>: SealedAdvancedChannel<T> {}
 /// HRTIM PWM pin.
 pub struct PwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, C)>,
 }
 /// HRTIM complementary PWM pin.
 pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, C)>,
 }
@@ -76,8 +76,7 @@ macro_rules! advanced_channel_impl {
    ($new_chx:ident, $channel:tt, $ch_num:expr, $pin_trait:ident, $complementary_pin_trait:ident) => {
        impl<'d, T: Instance> PwmPin<'d, T, $channel<T>> {
            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
-                into_ref!(pin);
                critical_section::with(|_| {
                    pin.set_low();
                    pin.set_as_af(
@@ -86,7 +85,7 @@ macro_rules! advanced_channel_impl {
                    );
                });
                PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -94,8 +93,7 @@ macro_rules! advanced_channel_impl {
        impl<'d, T: Instance> ComplementaryPwmPin<'d, T, $channel<T>> {
            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $complementary_pin_trait<T>> + 'd) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $complementary_pin_trait<T>>) -> Self {
-                into_ref!(pin);
                critical_section::with(|_| {
                    pin.set_low();
                    pin.set_as_af(
@@ -104,7 +102,7 @@ macro_rules! advanced_channel_impl {
                    );
                });
                ComplementaryPwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -129,7 +127,7 @@ advanced_channel_impl!(new_chf, ChF, 5, ChannelFPin, ChannelFComplementaryPin);
 /// Struct used to divide a high resolution timer into multiple channels
 pub struct AdvancedPwm<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
    /// Master instance.
    pub master: Master<T>,
    /// Burst controller.
@@ -154,7 +152,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
    ///
    /// This splits the HRTIM into its constituent parts, which you can then use individually.
    pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
        _cha: Option<PwmPin<'d, T, ChA<T>>>,
        _chan: Option<ComplementaryPwmPin<'d, T, ChA<T>>>,
        _chb: Option<PwmPin<'d, T, ChB<T>>>,
@@ -171,9 +169,7 @@ impl<'d, T: Instance> AdvancedPwm<'d, T> {
        Self::new_inner(tim)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
+    fn new_inner(tim: Peri<'d, T>) -> Self {
-        into_ref!(tim);
        rcc::enable_and_reset::<T>();
        #[cfg(stm32f334)]
@@ -236,8 +232,6 @@ pub struct BridgeConverter<T: Instance, C: AdvancedChannel<T>> {
 impl<T: Instance, C: AdvancedChannel<T>> BridgeConverter<T, C> {
    /// Create a new HRTIM bridge converter driver.
    pub fn new(_channel: C, frequency: Hertz) -> Self {
-        use crate::pac::hrtim::vals::{Activeeffect, Inactiveeffect};
        T::set_channel_frequency(C::raw(), frequency);
        // Always enable preload
@@ -258,28 +252,16 @@ impl<T: Instance, C: AdvancedChannel<T>> BridgeConverter<T, C> {
        // Therefore, software-implemented dead time must be used when setting the duty cycles
        // Set output 1 to active on a period event
-        T::regs()
+        T::regs().tim(C::raw()).setr(0).modify(|w| w.set_per(true));
-            .tim(C::raw())
-            .setr(0)
-            .modify(|w| w.set_per(Activeeffect::SETACTIVE));
        // Set output 1 to inactive on a compare 1 event
-        T::regs()
+        T::regs().tim(C::raw()).rstr(0).modify(|w| w.set_cmp(0, true));
-            .tim(C::raw())
-            .rstr(0)
-            .modify(|w| w.set_cmp(0, Inactiveeffect::SETINACTIVE));
        // Set output 2 to active on a compare 2 event
-        T::regs()
+        T::regs().tim(C::raw()).setr(1).modify(|w| w.set_cmp(1, true));
-            .tim(C::raw())
-            .setr(1)
-            .modify(|w| w.set_cmp(1, Activeeffect::SETACTIVE));
        // Set output 2 to inactive on a compare 3 event
-        T::regs()
+        T::regs().tim(C::raw()).rstr(1).modify(|w| w.set_cmp(2, true));
-            .tim(C::raw())
-            .rstr(1)
-            .modify(|w| w.set_cmp(2, Inactiveeffect::SETINACTIVE));
        Self {
            timer: PhantomData,
diff --git a/embassy-stm32/src/hrtim/traits.rs b/embassy-stm32/src/hrtim/traits.rs
index 75f9971e2..6c0661146 100644
--- a/embassy-stm32/src/hrtim/traits.rs
+++ b/embassy-stm32/src/hrtim/traits.rs
@@ -1,3 +1,5 @@
+use embassy_hal_internal::PeripheralType;
 use crate::rcc::RccPeripheral;
 use crate::time::Hertz;
@@ -153,7 +155,7 @@ pub(crate) trait SealedInstance: RccPeripheral {
 /// HRTIM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 foreach_interrupt! {
    ($inst:ident, hrtim, HRTIM, MASTER, $irq:ident) => {
diff --git a/embassy-stm32/src/hsem/mod.rs b/embassy-stm32/src/hsem/mod.rs
index 06ab7a9bc..31527bcdb 100644
--- a/embassy-stm32/src/hsem/mod.rs
+++ b/embassy-stm32/src/hsem/mod.rs
@@ -1,13 +1,14 @@
 //! Hardware Semaphore (HSEM)
+use embassy_hal_internal::PeripheralType;
+use crate::pac;
+use crate::rcc::RccPeripheral;
 // TODO: This code works for all HSEM implemenations except for the STM32WBA52/4/5xx MCUs.
 // Those MCUs have a different HSEM implementation (Secure semaphore lock support,
 // Privileged / unprivileged semaphore lock support, Semaphore lock protection via semaphore attribute),
 // which is not yet supported by this code.
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use crate::Peri;
-use crate::rcc::RccPeripheral;
-use crate::{pac, Peripheral};
 /// HSEM error.
 #[derive(Debug)]
@@ -73,13 +74,12 @@ fn core_id_to_index(core: CoreId) -> usize {
 /// HSEM driver
 pub struct HardwareSemaphore<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
 }
 impl<'d, T: Instance> HardwareSemaphore<'d, T> {
    /// Creates a new HardwareSemaphore instance.
-    pub fn new(peripheral: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(peripheral: Peri<'d, T>) -> Self {
-        into_ref!(peripheral);
        HardwareSemaphore { _peri: peripheral }
    }
@@ -177,7 +177,7 @@ trait SealedInstance {
 /// HSEM instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + Send + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + Send + 'static {}
 impl SealedInstance for crate::peripherals::HSEM {
    fn regs() -> crate::pac::hsem::Hsem {
diff --git a/embassy-stm32/src/hspi/enums.rs b/embassy-stm32/src/hspi/enums.rs
new file mode 100644
index 000000000..83a88f4d9
--- /dev/null
+++ b/embassy-stm32/src/hspi/enums.rs
@@ -0,0 +1,422 @@
+//! Enums used in Hspi configuration.
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub(crate) enum HspiMode {
+    IndirectWrite,
+    IndirectRead,
+    AutoPolling,
+    MemoryMapped,
+}
+impl Into<u8> for HspiMode {
+    fn into(self) -> u8 {
+        match self {
+            HspiMode::IndirectWrite => 0b00,
+            HspiMode::IndirectRead => 0b01,
+            HspiMode::AutoPolling => 0b10,
+            HspiMode::MemoryMapped => 0b11,
+        }
+    }
+}
+/// Hspi lane width
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum HspiWidth {
+    /// None
+    NONE,
+    /// Single lane
+    SING,
+    /// Dual lanes
+    DUAL,
+    /// Quad lanes
+    QUAD,
+    /// Eight lanes
+    OCTO,
+    /// Sixteen lanes
+    HEXADECA,
+}
+impl Into<u8> for HspiWidth {
+    fn into(self) -> u8 {
+        match self {
+            HspiWidth::NONE => 0b00,
+            HspiWidth::SING => 0b01,
+            HspiWidth::DUAL => 0b10,
+            HspiWidth::QUAD => 0b11,
+            HspiWidth::OCTO => 0b100,
+            HspiWidth::HEXADECA => 0b101,
+        }
+    }
+}
+/// Flash bank selection
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum FlashSelection {
+    /// Bank 1
+    Flash1,
+    /// Bank 2
+    Flash2,
+}
+impl Into<bool> for FlashSelection {
+    fn into(self) -> bool {
+        match self {
+            FlashSelection::Flash1 => false,
+            FlashSelection::Flash2 => true,
+        }
+    }
+}
+/// Wrap Size
+#[allow(dead_code)]
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum WrapSize {
+    None,
+    _16Bytes,
+    _32Bytes,
+    _64Bytes,
+    _128Bytes,
+}
+impl Into<u8> for WrapSize {
+    fn into(self) -> u8 {
+        match self {
+            WrapSize::None => 0x00,
+            WrapSize::_16Bytes => 0x02,
+            WrapSize::_32Bytes => 0x03,
+            WrapSize::_64Bytes => 0x04,
+            WrapSize::_128Bytes => 0x05,
+        }
+    }
+}
+/// Memory Type
+#[allow(missing_docs)]
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum MemoryType {
+    Micron,
+    Macronix,
+    Standard,
+    MacronixRam,
+    HyperBusMemory,
+    HyperBusRegister,
+}
+impl Into<u8> for MemoryType {
+    fn into(self) -> u8 {
+        match self {
+            MemoryType::Micron => 0x00,
+            MemoryType::Macronix => 0x01,
+            MemoryType::Standard => 0x02,
+            MemoryType::MacronixRam => 0x03,
+            MemoryType::HyperBusMemory => 0x04,
+            MemoryType::HyperBusRegister => 0x04,
+        }
+    }
+}
+/// Hspi memory size.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum MemorySize {
+    _1KiB,
+    _2KiB,
+    _4KiB,
+    _8KiB,
+    _16KiB,
+    _32KiB,
+    _64KiB,
+    _128KiB,
+    _256KiB,
+    _512KiB,
+    _1MiB,
+    _2MiB,
+    _4MiB,
+    _8MiB,
+    _16MiB,
+    _32MiB,
+    _64MiB,
+    _128MiB,
+    _256MiB,
+    _512MiB,
+    _1GiB,
+    _2GiB,
+    _4GiB,
+    Other(u8),
+}
+impl Into<u8> for MemorySize {
+    fn into(self) -> u8 {
+        match self {
+            MemorySize::_1KiB => 6,
+            MemorySize::_2KiB => 7,
+            MemorySize::_4KiB => 8,
+            MemorySize::_8KiB => 9,
+            MemorySize::_16KiB => 10,
+            MemorySize::_32KiB => 11,
+            MemorySize::_64KiB => 12,
+            MemorySize::_128KiB => 13,
+            MemorySize::_256KiB => 14,
+            MemorySize::_512KiB => 15,
+            MemorySize::_1MiB => 16,
+            MemorySize::_2MiB => 17,
+            MemorySize::_4MiB => 18,
+            MemorySize::_8MiB => 19,
+            MemorySize::_16MiB => 20,
+            MemorySize::_32MiB => 21,
+            MemorySize::_64MiB => 22,
+            MemorySize::_128MiB => 23,
+            MemorySize::_256MiB => 24,
+            MemorySize::_512MiB => 25,
+            MemorySize::_1GiB => 26,
+            MemorySize::_2GiB => 27,
+            MemorySize::_4GiB => 28,
+            MemorySize::Other(val) => val,
+        }
+    }
+}
+/// Hspi Address size
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum AddressSize {
+    /// 8-bit address
+    _8Bit,
+    /// 16-bit address
+    _16Bit,
+    /// 24-bit address
+    _24Bit,
+    /// 32-bit address
+    _32Bit,
+}
+impl Into<u8> for AddressSize {
+    fn into(self) -> u8 {
+        match self {
+            AddressSize::_8Bit => 0b00,
+            AddressSize::_16Bit => 0b01,
+            AddressSize::_24Bit => 0b10,
+            AddressSize::_32Bit => 0b11,
+        }
+    }
+}
+/// Time the Chip Select line stays high.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum ChipSelectHighTime {
+    _1Cycle,
+    _2Cycle,
+    _3Cycle,
+    _4Cycle,
+    _5Cycle,
+    _6Cycle,
+    _7Cycle,
+    _8Cycle,
+}
+impl Into<u8> for ChipSelectHighTime {
+    fn into(self) -> u8 {
+        match self {
+            ChipSelectHighTime::_1Cycle => 0,
+            ChipSelectHighTime::_2Cycle => 1,
+            ChipSelectHighTime::_3Cycle => 2,
+            ChipSelectHighTime::_4Cycle => 3,
+            ChipSelectHighTime::_5Cycle => 4,
+            ChipSelectHighTime::_6Cycle => 5,
+            ChipSelectHighTime::_7Cycle => 6,
+            ChipSelectHighTime::_8Cycle => 7,
+        }
+    }
+}
+/// FIFO threshold.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum FIFOThresholdLevel {
+    _1Bytes,
+    _2Bytes,
+    _3Bytes,
+    _4Bytes,
+    _5Bytes,
+    _6Bytes,
+    _7Bytes,
+    _8Bytes,
+    _9Bytes,
+    _10Bytes,
+    _11Bytes,
+    _12Bytes,
+    _13Bytes,
+    _14Bytes,
+    _15Bytes,
+    _16Bytes,
+    _17Bytes,
+    _18Bytes,
+    _19Bytes,
+    _20Bytes,
+    _21Bytes,
+    _22Bytes,
+    _23Bytes,
+    _24Bytes,
+    _25Bytes,
+    _26Bytes,
+    _27Bytes,
+    _28Bytes,
+    _29Bytes,
+    _30Bytes,
+    _31Bytes,
+    _32Bytes,
+}
+impl Into<u8> for FIFOThresholdLevel {
+    fn into(self) -> u8 {
+        match self {
+            FIFOThresholdLevel::_1Bytes => 0,
+            FIFOThresholdLevel::_2Bytes => 1,
+            FIFOThresholdLevel::_3Bytes => 2,
+            FIFOThresholdLevel::_4Bytes => 3,
+            FIFOThresholdLevel::_5Bytes => 4,
+            FIFOThresholdLevel::_6Bytes => 5,
+            FIFOThresholdLevel::_7Bytes => 6,
+            FIFOThresholdLevel::_8Bytes => 7,
+            FIFOThresholdLevel::_9Bytes => 8,
+            FIFOThresholdLevel::_10Bytes => 9,
+            FIFOThresholdLevel::_11Bytes => 10,
+            FIFOThresholdLevel::_12Bytes => 11,
+            FIFOThresholdLevel::_13Bytes => 12,
+            FIFOThresholdLevel::_14Bytes => 13,
+            FIFOThresholdLevel::_15Bytes => 14,
+            FIFOThresholdLevel::_16Bytes => 15,
+            FIFOThresholdLevel::_17Bytes => 16,
+            FIFOThresholdLevel::_18Bytes => 17,
+            FIFOThresholdLevel::_19Bytes => 18,
+            FIFOThresholdLevel::_20Bytes => 19,
+            FIFOThresholdLevel::_21Bytes => 20,
+            FIFOThresholdLevel::_22Bytes => 21,
+            FIFOThresholdLevel::_23Bytes => 22,
+            FIFOThresholdLevel::_24Bytes => 23,
+            FIFOThresholdLevel::_25Bytes => 24,
+            FIFOThresholdLevel::_26Bytes => 25,
+            FIFOThresholdLevel::_27Bytes => 26,
+            FIFOThresholdLevel::_28Bytes => 27,
+            FIFOThresholdLevel::_29Bytes => 28,
+            FIFOThresholdLevel::_30Bytes => 29,
+            FIFOThresholdLevel::_31Bytes => 30,
+            FIFOThresholdLevel::_32Bytes => 31,
+        }
+    }
+}
+/// Dummy cycle count
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum DummyCycles {
+    _0,
+    _1,
+    _2,
+    _3,
+    _4,
+    _5,
+    _6,
+    _7,
+    _8,
+    _9,
+    _10,
+    _11,
+    _12,
+    _13,
+    _14,
+    _15,
+    _16,
+    _17,
+    _18,
+    _19,
+    _20,
+    _21,
+    _22,
+    _23,
+    _24,
+    _25,
+    _26,
+    _27,
+    _28,
+    _29,
+    _30,
+    _31,
+}
+impl Into<u8> for DummyCycles {
+    fn into(self) -> u8 {
+        match self {
+            DummyCycles::_0 => 0,
+            DummyCycles::_1 => 1,
+            DummyCycles::_2 => 2,
+            DummyCycles::_3 => 3,
+            DummyCycles::_4 => 4,
+            DummyCycles::_5 => 5,
+            DummyCycles::_6 => 6,
+            DummyCycles::_7 => 7,
+            DummyCycles::_8 => 8,
+            DummyCycles::_9 => 9,
+            DummyCycles::_10 => 10,
+            DummyCycles::_11 => 11,
+            DummyCycles::_12 => 12,
+            DummyCycles::_13 => 13,
+            DummyCycles::_14 => 14,
+            DummyCycles::_15 => 15,
+            DummyCycles::_16 => 16,
+            DummyCycles::_17 => 17,
+            DummyCycles::_18 => 18,
+            DummyCycles::_19 => 19,
+            DummyCycles::_20 => 20,
+            DummyCycles::_21 => 21,
+            DummyCycles::_22 => 22,
+            DummyCycles::_23 => 23,
+            DummyCycles::_24 => 24,
+            DummyCycles::_25 => 25,
+            DummyCycles::_26 => 26,
+            DummyCycles::_27 => 27,
+            DummyCycles::_28 => 28,
+            DummyCycles::_29 => 29,
+            DummyCycles::_30 => 30,
+            DummyCycles::_31 => 31,
+        }
+    }
+}
+/// Functional mode
+#[allow(missing_docs)]
+#[allow(dead_code)]
+#[derive(Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum FunctionalMode {
+    IndirectWrite,
+    IndirectRead,
+    AutoStatusPolling,
+    MemoryMapped,
+}
+impl Into<u8> for FunctionalMode {
+    fn into(self) -> u8 {
+        match self {
+            FunctionalMode::IndirectWrite => 0x00,
+            FunctionalMode::IndirectRead => 0x01,
+            FunctionalMode::AutoStatusPolling => 0x02,
+            FunctionalMode::MemoryMapped => 0x03,
+        }
+    }
+}
diff --git a/embassy-stm32/src/hspi/mod.rs b/embassy-stm32/src/hspi/mod.rs
new file mode 100644
index 000000000..62bc0e979
--- /dev/null
+++ b/embassy-stm32/src/hspi/mod.rs
@@ -0,0 +1,1007 @@
+//! HSPI Serial Peripheral Interface
+//!
+// NOTE: This is a partial implementation of the HSPI driver.
+// It implements only Single and Octal SPI modes, but additional
+// modes can be added as needed following the same pattern and
+// using ospi/mod.rs as a reference.
+#![macro_use]
+pub mod enums;
+use core::marker::PhantomData;
+use embassy_embedded_hal::{GetConfig, SetConfig};
+use embassy_hal_internal::{Peri, PeripheralType};
+pub use enums::*;
+use crate::dma::{word, ChannelAndRequest};
+use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
+use crate::mode::{Async, Blocking, Mode as PeriMode};
+use crate::pac::hspi::Hspi as Regs;
+use crate::peripherals;
+use crate::rcc::{self, RccPeripheral};
+/// HSPI driver config.
+#[derive(Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct Config {
+    /// Fifo threshold used by the peripheral to generate the interrupt indicating data
+    /// or space is available in the FIFO
+    pub fifo_threshold: FIFOThresholdLevel,
+    /// Indicates the type of external device connected
+    pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface
+    /// Defines the size of the external device connected to the HSPI corresponding
+    /// to the number of address bits required to access the device
+    pub device_size: MemorySize,
+    /// Sets the minimum number of clock cycles that the chip select signal must be held high
+    /// between commands
+    pub chip_select_high_time: ChipSelectHighTime,
+    /// Enables the free running clock
+    pub free_running_clock: bool,
+    /// Sets the clock level when the device is not selected
+    pub clock_mode: bool,
+    /// Indicates the wrap size corresponding to the external device configuration
+    pub wrap_size: WrapSize,
+    /// Specified the prescaler factor used for generating the external clock based
+    /// on the AHB clock
+    pub clock_prescaler: u8,
+    /// Allows the delay of 1/2 cycle the data sampling to account for external
+    /// signal delays
+    pub sample_shifting: bool,
+    /// Allows hold to 1/4 cycle the data
+    pub delay_hold_quarter_cycle: bool,
+    /// Enables the transaction boundary feature and defines the boundary to release
+    /// the chip select
+    pub chip_select_boundary: u8,
+    /// Enables the delay block bypass so the sampling is not affected by the delay block
+    pub delay_block_bypass: bool,
+    /// Enables communication regulation feature. Chip select is released when the other
+    /// HSPI requests access to the bus
+    pub max_transfer: u8,
+    /// Enables the refresh feature, chip select is released every refresh + 1 clock cycles
+    pub refresh: u32,
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            fifo_threshold: FIFOThresholdLevel::_16Bytes,
+            memory_type: MemoryType::Micron,
+            device_size: MemorySize::Other(0),
+            chip_select_high_time: ChipSelectHighTime::_5Cycle,
+            free_running_clock: false,
+            clock_mode: false,
+            wrap_size: WrapSize::None,
+            clock_prescaler: 0,
+            sample_shifting: false,
+            delay_hold_quarter_cycle: false,
+            chip_select_boundary: 0, // Acceptable range 0 to 31
+            delay_block_bypass: true,
+            max_transfer: 0,
+            refresh: 0,
+        }
+    }
+}
+/// HSPI transfer configuration.
+pub struct TransferConfig {
+    /// Instruction width (IMODE)
+    pub iwidth: HspiWidth,
+    /// Instruction Id
+    pub instruction: Option<u32>,
+    /// Number of Instruction Bytes
+    pub isize: AddressSize,
+    /// Instruction Double Transfer rate enable
+    pub idtr: bool,
+    /// Address width (ADMODE)
+    pub adwidth: HspiWidth,
+    /// Device memory address
+    pub address: Option<u32>,
+    /// Number of Address Bytes
+    pub adsize: AddressSize,
+    /// Address Double Transfer rate enable
+    pub addtr: bool,
+    /// Alternate bytes width (ABMODE)
+    pub abwidth: HspiWidth,
+    /// Alternate Bytes
+    pub alternate_bytes: Option<u32>,
+    /// Number of Alternate Bytes
+    pub absize: AddressSize,
+    /// Alternate Bytes Double Transfer rate enable
+    pub abdtr: bool,
+    /// Data width (DMODE)
+    pub dwidth: HspiWidth,
+    /// Data buffer
+    pub ddtr: bool,
+    /// Number of dummy cycles (DCYC)
+    pub dummy: DummyCycles,
+}
+impl Default for TransferConfig {
+    fn default() -> Self {
+        Self {
+            iwidth: HspiWidth::NONE,
+            instruction: None,
+            isize: AddressSize::_8Bit,
+            idtr: false,
+            adwidth: HspiWidth::NONE,
+            address: None,
+            adsize: AddressSize::_8Bit,
+            addtr: false,
+            abwidth: HspiWidth::NONE,
+            alternate_bytes: None,
+            absize: AddressSize::_8Bit,
+            abdtr: false,
+            dwidth: HspiWidth::NONE,
+            ddtr: false,
+            dummy: DummyCycles::_0,
+        }
+    }
+}
+/// Error used for HSPI implementation
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum HspiError {
+    /// Peripheral configuration is invalid
+    InvalidConfiguration,
+    /// Operation configuration is invalid
+    InvalidCommand,
+    /// Size zero buffer passed to instruction
+    EmptyBuffer,
+}
+/// HSPI driver.
+pub struct Hspi<'d, T: Instance, M: PeriMode> {
+    _peri: Peri<'d, T>,
+    sck: Option<Peri<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
+    d8: Option<Peri<'d, AnyPin>>,
+    d9: Option<Peri<'d, AnyPin>>,
+    d10: Option<Peri<'d, AnyPin>>,
+    d11: Option<Peri<'d, AnyPin>>,
+    d12: Option<Peri<'d, AnyPin>>,
+    d13: Option<Peri<'d, AnyPin>>,
+    d14: Option<Peri<'d, AnyPin>>,
+    d15: Option<Peri<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
+    dqs0: Option<Peri<'d, AnyPin>>,
+    dqs1: Option<Peri<'d, AnyPin>>,
+    dma: Option<ChannelAndRequest<'d>>,
+    _phantom: PhantomData<M>,
+    config: Config,
+    width: HspiWidth,
+}
+impl<'d, T: Instance, M: PeriMode> Hspi<'d, T, M> {
+    /// Enter memory mode.
+    /// The Input `read_config` is used to configure the read operation in memory mode
+    pub fn enable_memory_mapped_mode(
+        &mut self,
+        read_config: TransferConfig,
+        write_config: TransferConfig,
+    ) -> Result<(), HspiError> {
+        // Use configure command to set read config
+        self.configure_command(&read_config, None)?;
+        // Set writing configurations, there are separate registers for write configurations in memory mapped mode
+        T::REGS.wccr().modify(|w| {
+            w.set_imode(write_config.iwidth.into());
+            w.set_idtr(write_config.idtr);
+            w.set_isize(write_config.isize.into());
+            w.set_admode(write_config.adwidth.into());
+            w.set_addtr(write_config.idtr);
+            w.set_adsize(write_config.adsize.into());
+            w.set_dmode(write_config.dwidth.into());
+            w.set_ddtr(write_config.ddtr);
+            w.set_abmode(write_config.abwidth.into());
+            w.set_dqse(true);
+        });
+        T::REGS.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
+        // Enable memory mapped mode
+        T::REGS.cr().modify(|r| {
+            r.set_fmode(FunctionalMode::MemoryMapped.into());
+            r.set_tcen(false);
+        });
+        Ok(())
+    }
+    /// Quit from memory mapped mode
+    pub fn disable_memory_mapped_mode(&mut self) {
+        T::REGS.cr().modify(|r| {
+            r.set_fmode(FunctionalMode::IndirectWrite.into());
+            r.set_abort(true);
+            r.set_dmaen(false);
+            r.set_en(false);
+        });
+        // Clear transfer complete flag
+        T::REGS.fcr().write(|w| w.set_ctcf(true));
+        // Re-enable HSPI
+        T::REGS.cr().modify(|r| {
+            r.set_en(true);
+        });
+    }
+    fn new_inner(
+        peri: Peri<'d, T>,
+        d0: Option<Peri<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
+        d8: Option<Peri<'d, AnyPin>>,
+        d9: Option<Peri<'d, AnyPin>>,
+        d10: Option<Peri<'d, AnyPin>>,
+        d11: Option<Peri<'d, AnyPin>>,
+        d12: Option<Peri<'d, AnyPin>>,
+        d13: Option<Peri<'d, AnyPin>>,
+        d14: Option<Peri<'d, AnyPin>>,
+        d15: Option<Peri<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
+        dqs0: Option<Peri<'d, AnyPin>>,
+        dqs1: Option<Peri<'d, AnyPin>>,
+        dma: Option<ChannelAndRequest<'d>>,
+        config: Config,
+        width: HspiWidth,
+        dual_memory_mode: bool,
+    ) -> Self {
+        // System configuration
+        rcc::enable_and_reset::<T>();
+        // Call this function just to check that the clock for HSPI1 is properly setup
+        let _ = T::frequency();
+        while T::REGS.sr().read().busy() {}
+        Self::configure_registers(&config, Some(dual_memory_mode));
+        Self {
+            _peri: peri,
+            sck,
+            d0,
+            d1,
+            d2,
+            d3,
+            d4,
+            d5,
+            d6,
+            d7,
+            d8,
+            d9,
+            d10,
+            d11,
+            d12,
+            d13,
+            d14,
+            d15,
+            nss,
+            dqs0,
+            dqs1,
+            dma,
+            _phantom: PhantomData,
+            config,
+            width,
+        }
+    }
+    fn configure_registers(config: &Config, dual_memory_mode: Option<bool>) {
+        // Device configuration
+        T::REGS.dcr1().modify(|w| {
+            w.set_mtyp(config.memory_type.into());
+            w.set_devsize(config.device_size.into());
+            w.set_csht(config.chip_select_high_time.into());
+            w.set_frck(false);
+            w.set_ckmode(config.clock_mode);
+            w.set_dlybyp(config.delay_block_bypass);
+        });
+        T::REGS.dcr2().modify(|w| {
+            w.set_wrapsize(config.wrap_size.into());
+        });
+        T::REGS.dcr3().modify(|w| {
+            w.set_csbound(config.chip_select_boundary);
+            w.set_maxtran(config.max_transfer);
+        });
+        T::REGS.dcr4().modify(|w| {
+            w.set_refresh(config.refresh);
+        });
+        T::REGS.cr().modify(|w| {
+            w.set_fthres(config.fifo_threshold.into());
+        });
+        // Wait for busy flag to clear
+        while T::REGS.sr().read().busy() {}
+        T::REGS.dcr2().modify(|w| {
+            w.set_prescaler(config.clock_prescaler);
+        });
+        // The configuration of clock prescaler trigger automatically a calibration process
+        // So it is necessary to wait the calibration is complete
+        while T::REGS.sr().read().busy() {}
+        if let Some(dual_memory_mode) = dual_memory_mode {
+            T::REGS.cr().modify(|w| {
+                w.set_dmm(dual_memory_mode);
+            });
+        }
+        T::REGS.tcr().modify(|w| {
+            w.set_sshift(config.sample_shifting);
+            w.set_dhqc(config.delay_hold_quarter_cycle);
+        });
+        // Enable peripheral
+        T::REGS.cr().modify(|w| {
+            w.set_en(true);
+        });
+        // Free running clock needs to be set after peripheral enable
+        if config.free_running_clock {
+            T::REGS.dcr1().modify(|w| {
+                w.set_frck(config.free_running_clock);
+            });
+        }
+    }
+    // Function to configure the peripheral for the requested command
+    fn configure_command(&mut self, command: &TransferConfig, data_len: Option<usize>) -> Result<(), HspiError> {
+        // Check that transaction doesn't use more than hardware initialized pins
+        if <enums::HspiWidth as Into<u8>>::into(command.iwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
+            || <enums::HspiWidth as Into<u8>>::into(command.adwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
+            || <enums::HspiWidth as Into<u8>>::into(command.abwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
+            || <enums::HspiWidth as Into<u8>>::into(command.dwidth) > <enums::HspiWidth as Into<u8>>::into(self.width)
+        {
+            return Err(HspiError::InvalidCommand);
+        }
+        while T::REGS.sr().read().busy() {}
+        T::REGS.cr().modify(|w| {
+            w.set_fmode(0.into());
+        });
+        // Configure alternate bytes
+        if let Some(ab) = command.alternate_bytes {
+            T::REGS.abr().write(|v| v.set_alternate(ab));
+            T::REGS.ccr().modify(|w| {
+                w.set_abmode(command.abwidth.into());
+                w.set_abdtr(command.abdtr);
+                w.set_absize(command.absize.into());
+            })
+        }
+        // Configure dummy cycles
+        T::REGS.tcr().modify(|w| {
+            w.set_dcyc(command.dummy.into());
+        });
+        // Configure data
+        if let Some(data_length) = data_len {
+            T::REGS.dlr().write(|v| {
+                v.set_dl((data_length - 1) as u32);
+            })
+        } else {
+            T::REGS.dlr().write(|v| {
+                v.set_dl((0) as u32);
+            })
+        }
+        // Configure instruction/address/data modes
+        T::REGS.ccr().modify(|w| {
+            w.set_imode(command.iwidth.into());
+            w.set_idtr(command.idtr);
+            w.set_isize(command.isize.into());
+            w.set_admode(command.adwidth.into());
+            w.set_addtr(command.addtr);
+            w.set_adsize(command.adsize.into());
+            w.set_dmode(command.dwidth.into());
+            w.set_ddtr(command.ddtr);
+        });
+        // Configure DQS
+        T::REGS.ccr().modify(|w| {
+            w.set_dqse(command.ddtr && command.instruction.unwrap_or(0) != 0x12ED);
+        });
+        // Set information required to initiate transaction
+        if let Some(instruction) = command.instruction {
+            if let Some(address) = command.address {
+                T::REGS.ir().write(|v| {
+                    v.set_instruction(instruction);
+                });
+                T::REGS.ar().write(|v| {
+                    v.set_address(address);
+                });
+            } else {
+                T::REGS.ir().write(|v| {
+                    v.set_instruction(instruction);
+                });
+            }
+        } else {
+            if let Some(address) = command.address {
+                T::REGS.ar().write(|v| {
+                    v.set_address(address);
+                });
+            } else {
+                // The only single phase transaction supported is instruction only
+                return Err(HspiError::InvalidCommand);
+            }
+        }
+        Ok(())
+    }
+    /// Function used to control or configure the target device without data transfer
+    pub fn blocking_command(&mut self, command: &TransferConfig) -> Result<(), HspiError> {
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        // Need additional validation that command configuration doesn't have data set
+        self.configure_command(command, None)?;
+        // Transaction initiated by setting final configuration, i.e the instruction register
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|w| {
+            w.set_ctcf(true);
+        });
+        Ok(())
+    }
+    /// Blocking read with byte by byte data transfer
+    pub fn blocking_read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        // Ensure DMA is not enabled for this transaction
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        self.configure_command(&transaction, Some(buf.len()))?;
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
+        if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        for idx in 0..buf.len() {
+            while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
+            buf[idx] = unsafe { (T::REGS.dr().as_ptr() as *mut W).read_volatile() };
+        }
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|v| v.set_ctcf(true));
+        Ok(())
+    }
+    /// Blocking write with byte by byte data transfer
+    pub fn blocking_write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
+        for idx in 0..buf.len() {
+            while !T::REGS.sr().read().ftf() {}
+            unsafe { (T::REGS.dr().as_ptr() as *mut W).write_volatile(buf[idx]) };
+        }
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|v| v.set_ctcf(true));
+        Ok(())
+    }
+    /// Set new bus configuration
+    pub fn set_config(&mut self, config: &Config) {
+        // Wait for busy flag to clear
+        while T::REGS.sr().read().busy() {}
+        // Disable DMA channel while configuring the peripheral
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        Self::configure_registers(config, None);
+        self.config = *config;
+    }
+    /// Get current configuration
+    pub fn get_config(&self) -> Config {
+        self.config
+    }
+}
+impl<'d, T: Instance> Hspi<'d, T, Blocking> {
+    /// Create new blocking HSPI driver for single spi external chip
+    pub fn new_blocking_singlespi(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::input(Pull::None)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            config,
+            HspiWidth::SING,
+            false,
+        )
+    }
+    /// Create new blocking HSPI driver for octospi external chip
+    pub fn new_blocking_octospi(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs0: Peri<'d, impl DQS0Pin<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            new_pin!(dqs0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            config,
+            HspiWidth::OCTO,
+            false,
+        )
+    }
+}
+impl<'d, T: Instance> Hspi<'d, T, Async> {
+    /// Create new HSPI driver for a single spi external chip
+    pub fn new_singlespi(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dma: Peri<'d, impl HspiDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::input(Pull::None)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            HspiWidth::SING,
+            false,
+        )
+    }
+    /// Create new HSPI driver for octospi external chip
+    pub fn new_octospi(
+        peri: Peri<'d, T>,
+        sck: Peri<'d, impl SckPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        nss: Peri<'d, impl NSSPin<T>>,
+        dqs0: Peri<'d, impl DQS0Pin<T>>,
+        dma: Peri<'d, impl HspiDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(sck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(
+                nss,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            new_pin!(dqs0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            new_dma!(dma),
+            config,
+            HspiWidth::OCTO,
+            false,
+        )
+    }
+    /// Blocking read with DMA transfer
+    pub fn blocking_read_dma<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
+        if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.blocking_wait();
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Blocking write with DMA transfer
+    pub fn blocking_write_dma<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.blocking_wait();
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Asynchronous read from external device
+    pub async fn read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectRead.into()));
+        if T::REGS.ccr().read().admode() == HspiWidth::NONE.into() {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.await;
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Asynchronous write to external device
+    pub async fn write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), HspiError> {
+        if buf.is_empty() {
+            return Err(HspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(FunctionalMode::IndirectWrite.into()));
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.await;
+        finish_dma(T::REGS);
+        Ok(())
+    }
+}
+impl<'d, T: Instance, M: PeriMode> Drop for Hspi<'d, T, M> {
+    fn drop(&mut self) {
+        self.sck.as_ref().map(|x| x.set_as_disconnected());
+        self.d0.as_ref().map(|x| x.set_as_disconnected());
+        self.d1.as_ref().map(|x| x.set_as_disconnected());
+        self.d2.as_ref().map(|x| x.set_as_disconnected());
+        self.d3.as_ref().map(|x| x.set_as_disconnected());
+        self.d4.as_ref().map(|x| x.set_as_disconnected());
+        self.d5.as_ref().map(|x| x.set_as_disconnected());
+        self.d6.as_ref().map(|x| x.set_as_disconnected());
+        self.d7.as_ref().map(|x| x.set_as_disconnected());
+        self.d8.as_ref().map(|x| x.set_as_disconnected());
+        self.d9.as_ref().map(|x| x.set_as_disconnected());
+        self.d10.as_ref().map(|x| x.set_as_disconnected());
+        self.d11.as_ref().map(|x| x.set_as_disconnected());
+        self.d12.as_ref().map(|x| x.set_as_disconnected());
+        self.d13.as_ref().map(|x| x.set_as_disconnected());
+        self.d14.as_ref().map(|x| x.set_as_disconnected());
+        self.d15.as_ref().map(|x| x.set_as_disconnected());
+        self.nss.as_ref().map(|x| x.set_as_disconnected());
+        self.dqs0.as_ref().map(|x| x.set_as_disconnected());
+        self.dqs1.as_ref().map(|x| x.set_as_disconnected());
+        rcc::disable::<T>();
+    }
+}
+fn finish_dma(regs: Regs) {
+    while !regs.sr().read().tcf() {}
+    regs.fcr().write(|v| v.set_ctcf(true));
+    regs.cr().modify(|w| {
+        w.set_dmaen(false);
+    });
+}
+/// HSPI instance trait.
+pub(crate) trait SealedInstance {
+    const REGS: Regs;
+}
+/// HSPI instance trait.
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
+pin_trait!(SckPin, Instance);
+pin_trait!(NckPin, Instance);
+pin_trait!(D0Pin, Instance);
+pin_trait!(D1Pin, Instance);
+pin_trait!(D2Pin, Instance);
+pin_trait!(D3Pin, Instance);
+pin_trait!(D4Pin, Instance);
+pin_trait!(D5Pin, Instance);
+pin_trait!(D6Pin, Instance);
+pin_trait!(D7Pin, Instance);
+pin_trait!(D8Pin, Instance);
+pin_trait!(D9Pin, Instance);
+pin_trait!(D10Pin, Instance);
+pin_trait!(D11Pin, Instance);
+pin_trait!(D12Pin, Instance);
+pin_trait!(D13Pin, Instance);
+pin_trait!(D14Pin, Instance);
+pin_trait!(D15Pin, Instance);
+pin_trait!(DQS0Pin, Instance);
+pin_trait!(DQS1Pin, Instance);
+pin_trait!(NSSPin, Instance);
+dma_trait!(HspiDma, Instance);
+foreach_peripheral!(
+    (hspi, $inst:ident) => {
+        impl SealedInstance for peripherals::$inst {
+            const REGS: Regs = crate::pac::$inst;
+        }
+        impl Instance for peripherals::$inst {}
+    };
+);
+impl<'d, T: Instance, M: PeriMode> SetConfig for Hspi<'d, T, M> {
+    type Config = Config;
+    type ConfigError = ();
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
+        self.set_config(config);
+        Ok(())
+    }
+}
+impl<'d, T: Instance, M: PeriMode> GetConfig for Hspi<'d, T, M> {
+    type Config = Config;
+    fn get_config(&self) -> Self::Config {
+        self.get_config()
+    }
+}
+/// Word sizes usable for HSPI.
+#[allow(private_bounds)]
+pub trait Word: word::Word {}
+macro_rules! impl_word {
+    ($T:ty) => {
+        impl Word for $T {}
+    };
+}
+impl_word!(u8);
+impl_word!(u16);
+impl_word!(u32);
diff --git a/embassy-stm32/src/i2c/mod.rs b/embassy-stm32/src/i2c/mod.rs
index 2ff21702b..825dd240c 100644
--- a/embassy-stm32/src/i2c/mod.rs
+++ b/embassy-stm32/src/i2c/mod.rs
@@ -12,7 +12,7 @@ use core::iter;
 use core::marker::PhantomData;
 pub use config::*;
-use embassy_hal_internal::{Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(feature = "time")]
 use embassy_time::{Duration, Instant};
@@ -47,6 +47,24 @@ pub enum Error {
    ZeroLengthTransfer,
 }
+impl core::fmt::Display for Error {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let message = match self {
+            Self::Bus => "Bus Error",
+            Self::Arbitration => "Arbitration Lost",
+            Self::Nack => "ACK Not Received",
+            Self::Timeout => "Request Timed Out",
+            Self::Crc => "CRC Mismatch",
+            Self::Overrun => "Buffer Overrun",
+            Self::ZeroLengthTransfer => "Zero-Length Transfers are not allowed",
+        };
+        write!(f, "{}", message)
+    }
+}
+impl core::error::Error for Error {}
 /// I2C modes
 pub mod mode {
    trait SealedMode {}
@@ -99,8 +117,8 @@ pub enum SendStatus {
 struct I2CDropGuard<'d> {
    info: &'static Info,
-    scl: Option<PeripheralRef<'d, AnyPin>>,
+    scl: Option<Peri<'d, AnyPin>>,
-    sda: Option<PeripheralRef<'d, AnyPin>>,
+    sda: Option<Peri<'d, AnyPin>>,
 }
 impl<'d> Drop for I2CDropGuard<'d> {
    fn drop(&mut self) {
@@ -132,14 +150,14 @@ pub struct I2c<'d, M: Mode, IM: MasterMode> {
 impl<'d> I2c<'d, Async, Master> {
    /// Create a new I2C driver.
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        scl: impl Peripheral<P = impl SclPin<T>> + 'd,
+        scl: Peri<'d, impl SclPin<T>>,
-        sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
+        sda: Peri<'d, impl SdaPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
            + interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
            + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        freq: Hertz,
        config: Config,
    ) -> Self {
@@ -158,9 +176,9 @@ impl<'d> I2c<'d, Async, Master> {
 impl<'d> I2c<'d, Blocking, Master> {
    /// Create a new blocking I2C driver.
    pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        scl: impl Peripheral<P = impl SclPin<T>> + 'd,
+        scl: Peri<'d, impl SclPin<T>>,
-        sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
+        sda: Peri<'d, impl SdaPin<T>>,
        freq: Hertz,
        config: Config,
    ) -> Self {
@@ -179,9 +197,9 @@ impl<'d> I2c<'d, Blocking, Master> {
 impl<'d, M: Mode> I2c<'d, M, Master> {
    /// Create a new I2C driver.
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        scl: Option<PeripheralRef<'d, AnyPin>>,
+        scl: Option<Peri<'d, AnyPin>>,
-        sda: Option<PeripheralRef<'d, AnyPin>>,
+        sda: Option<Peri<'d, AnyPin>>,
        tx_dma: Option<ChannelAndRequest<'d>>,
        rx_dma: Option<ChannelAndRequest<'d>>,
        freq: Hertz,
diff --git a/embassy-stm32/src/i2c/v2.rs b/embassy-stm32/src/i2c/v2.rs
index 64ccd24c7..990ce7d21 100644
--- a/embassy-stm32/src/i2c/v2.rs
+++ b/embassy-stm32/src/i2c/v2.rs
@@ -40,7 +40,7 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
    let regs = T::info().regs;
    let isr = regs.isr().read();
-    if isr.tcr() || isr.tc() || isr.addr() || isr.stopf() {
+    if isr.tcr() || isr.tc() || isr.addr() || isr.stopf() || isr.nackf() || isr.berr() || isr.arlo() || isr.ovr() {
        T::state().waker.wake();
    }
@@ -48,10 +48,11 @@ pub(crate) unsafe fn on_interrupt<T: Instance>() {
        regs.cr1().modify(|w| {
            w.set_addrie(false);
            w.set_stopie(false);
+              // The flag can only be cleared by writting to nbytes, we won't do that here
            w.set_tcie(false);
-            // The flag can only be cleared by writting to nbytes, we won't do that here, so disable
+            // Error flags are to be read in the routines, so we also don't clear them here
-            // the interrupt
+            w.set_nackie(false);
-            w.set_tcie(false);
+            w.set_errie(false);
        });
    });
 }
@@ -107,7 +108,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        // is BUSY or I2C is in slave mode.
        let reload = if reload {
-            i2c::vals::Reload::NOTCOMPLETED
+            i2c::vals::Reload::NOT_COMPLETED
        } else {
            i2c::vals::Reload::COMPLETED
        };
@@ -148,7 +149,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        }
        let reload = if reload {
-            i2c::vals::Reload::NOTCOMPLETED
+            i2c::vals::Reload::NOT_COMPLETED
        } else {
            i2c::vals::Reload::COMPLETED
        };
@@ -177,7 +178,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
        }
        let will_reload = if will_reload {
-            i2c::vals::Reload::NOTCOMPLETED
+            i2c::vals::Reload::NOT_COMPLETED
        } else {
            i2c::vals::Reload::COMPLETED
        };
@@ -483,6 +484,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        write: &[u8],
        first_slice: bool,
        last_slice: bool,
+        send_stop: bool,
        timeout: Timeout,
    ) -> Result<(), Error> {
        let total_len = write.len();
@@ -494,6 +496,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
                if first_slice {
                    w.set_tcie(true);
                }
+                w.set_nackie(true);
+                w.set_errie(true);
            });
            let dst = regs.txdr().as_ptr() as *mut u8;
@@ -504,18 +508,41 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        let on_drop = OnDrop::new(|| {
            let regs = self.info.regs;
+            let isr = regs.isr().read();
            regs.cr1().modify(|w| {
-                if last_slice {
+                if last_slice || isr.nackf() || isr.arlo() || isr.berr() || isr.ovr() {
                    w.set_txdmaen(false);
                }
                w.set_tcie(false);
-            })
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
        });
        poll_fn(|cx| {
            self.state.waker.register(cx.waker());
            let isr = self.info.regs.isr().read();
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
            if remaining_len == total_len {
                if first_slice {
                    Self::master_write(
@@ -550,10 +577,12 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        .await?;
        dma_transfer.await;
        if last_slice {
            // This should be done already
            self.wait_tc(timeout)?;
+        }
+        if last_slice & send_stop {
            self.master_stop();
        }
@@ -576,6 +605,8 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            regs.cr1().modify(|w| {
                w.set_rxdmaen(true);
                w.set_tcie(true);
+                w.set_nackie(true);
+                w.set_errie(true);
            });
            let src = regs.rxdr().as_ptr() as *mut u8;
@@ -589,34 +620,62 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            regs.cr1().modify(|w| {
                w.set_rxdmaen(false);
                w.set_tcie(false);
-            })
+                w.set_nackie(false);
+                w.set_errie(false);
+            });
+            regs.icr().write(|w| {
+                w.set_nackcf(true);
+                w.set_berrcf(true);
+                w.set_arlocf(true);
+                w.set_ovrcf(true);
+            });
        });
        poll_fn(|cx| {
            self.state.waker.register(cx.waker());
            let isr = self.info.regs.isr().read();
+            if isr.nackf() {
+                return Poll::Ready(Err(Error::Nack));
+            }
+            if isr.arlo() {
+                return Poll::Ready(Err(Error::Arbitration));
+            }
+            if isr.berr() {
+                return Poll::Ready(Err(Error::Bus));
+            }
+            if isr.ovr() {
+                return Poll::Ready(Err(Error::Overrun));
+            }
            if remaining_len == total_len {
                Self::master_read(
                    self.info,
                    address,
                    total_len.min(255),
-                    Stop::Software,
+                    Stop::Automatic,
                    total_len > 255,
                    restart,
                    timeout,
                )?;
-            } else if !(isr.tcr() || isr.tc()) {
+                if total_len <= 255 {
+                    return Poll::Ready(Ok(()));
+                }
+            } else if isr.tcr() {
                // poll_fn was woken without an interrupt present
                return Poll::Pending;
-            } else if remaining_len == 0 {
-                return Poll::Ready(Ok(()));
            } else {
                let last_piece = remaining_len <= 255;
                if let Err(e) = Self::reload(self.info, remaining_len.min(255), !last_piece, timeout) {
                    return Poll::Ready(Err(e));
                }
+                // Return here if we are on last chunk,
+                // end of transfer will be awaited with the DMA below
+                if last_piece {
+                    return Poll::Ready(Ok(()));
+                }
                self.info.regs.cr1().modify(|w| w.set_tcie(true));
            }
@@ -626,11 +685,6 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        .await?;
        dma_transfer.await;
-        // This should be done already
-        self.wait_tc(timeout)?;
-        self.master_stop();
        drop(on_drop);
        Ok(())
@@ -645,7 +699,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            self.write_internal(address.into(), write, true, timeout)
        } else {
            timeout
-                .with(self.write_dma_internal(address.into(), write, true, true, timeout))
+                .with(self.write_dma_internal(address.into(), write, true, true, true, timeout))
                .await
        }
    }
@@ -667,7 +721,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
            let next = iter.next();
            let is_last = next.is_none();
-            let fut = self.write_dma_internal(address, c, first, is_last, timeout);
+            let fut = self.write_dma_internal(address, c, first, is_last, is_last, timeout);
            timeout.with(fut).await?;
            first = false;
            current = next;
@@ -694,7 +748,7 @@ impl<'d, IM: MasterMode> I2c<'d, Async, IM> {
        if write.is_empty() {
            self.write_internal(address.into(), write, false, timeout)?;
        } else {
-            let fut = self.write_dma_internal(address.into(), write, true, true, timeout);
+            let fut = self.write_dma_internal(address.into(), write, true, true, false, timeout);
            timeout.with(fut).await?;
        }
@@ -1202,7 +1256,12 @@ impl<'d, M: Mode> SetConfig for I2c<'d, M, Master> {
    type Config = Hertz;
    type ConfigError = ();
    fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(false);
+        });
        let timings = Timings::new(self.kernel_clock, *config);
        self.info.regs.timingr().write(|reg| {
            reg.set_presc(timings.prescale);
            reg.set_scll(timings.scll);
@@ -1211,6 +1270,10 @@ impl<'d, M: Mode> SetConfig for I2c<'d, M, Master> {
            reg.set_scldel(timings.scldel);
        });
+        self.info.regs.cr1().modify(|reg| {
+            reg.set_pe(true);
+        });
        Ok(())
    }
 }
@@ -1232,3 +1295,4 @@ impl<'d, M: Mode> SetConfig for I2c<'d, M, MultiMaster> {
        Ok(())
    }
 }
diff --git a/embassy-stm32/src/i2s.rs b/embassy-stm32/src/i2s.rs
index 094de2461..5005a5cdb 100644
--- a/embassy-stm32/src/i2s.rs
+++ b/embassy-stm32/src/i2s.rs
@@ -1,14 +1,14 @@
 //! Inter-IC Sound (I2S)
-use embassy_hal_internal::into_ref;
+use embassy_futures::join::join;
+use stm32_metapac::spi::vals;
-use crate::dma::ChannelAndRequest;
+use crate::dma::{ringbuffer, ChannelAndRequest, ReadableRingBuffer, TransferOptions, WritableRingBuffer};
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
 use crate::mode::Async;
-use crate::pac::spi::vals;
+use crate::spi::{Config as SpiConfig, RegsExt as _, *};
-use crate::spi::{Config as SpiConfig, *};
 use crate::time::Hertz;
-use crate::{Peripheral, PeripheralRef};
+use crate::Peri;
 /// I2S mode
 #[derive(Copy, Clone)]
@@ -19,6 +19,19 @@ pub enum Mode {
    Slave,
 }
+/// I2S function
+#[derive(Copy, Clone)]
+#[allow(dead_code)]
+enum Function {
+    /// Transmit audio data
+    Transmit,
+    /// Receive audio data
+    Receive,
+    #[cfg(spi_v3)]
+    /// Transmit and Receive audio data
+    FullDuplex,
+}
 /// I2C standard
 #[derive(Copy, Clone)]
 pub enum Standard {
@@ -34,6 +47,30 @@ pub enum Standard {
    PcmShortSync,
 }
+/// SAI error
+#[derive(Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Error {
+    /// `write` called on a SAI in receive mode.
+    NotATransmitter,
+    /// `read` called on a SAI in transmit mode.
+    NotAReceiver,
+    /// Overrun
+    Overrun,
+}
+impl From<ringbuffer::Error> for Error {
+    fn from(#[allow(unused)] err: ringbuffer::Error) -> Self {
+        #[cfg(feature = "defmt")]
+        {
+            if err == ringbuffer::Error::DmaUnsynced {
+                defmt::error!("Ringbuffer broken invariants detected!");
+            }
+        }
+        Self::Overrun
+    }
+}
 impl Standard {
    #[cfg(any(spi_v1, spi_v3, spi_f1))]
    const fn i2sstd(&self) -> vals::I2sstd {
@@ -103,8 +140,8 @@ impl ClockPolarity {
    #[cfg(any(spi_v1, spi_v3, spi_f1))]
    const fn ckpol(&self) -> vals::Ckpol {
        match self {
-            ClockPolarity::IdleHigh => vals::Ckpol::IDLEHIGH,
+            ClockPolarity::IdleHigh => vals::Ckpol::IDLE_HIGH,
-            ClockPolarity::IdleLow => vals::Ckpol::IDLELOW,
+            ClockPolarity::IdleLow => vals::Ckpol::IDLE_LOW,
        }
    }
 }
@@ -142,50 +179,107 @@ impl Default for Config {
    }
 }
-/// I2S driver.
+/// I2S driver writer. Useful for moving write functionality across tasks.
-pub struct I2S<'d> {
+pub struct Writer<'s, 'd, W: Word>(&'s mut WritableRingBuffer<'d, W>);
-    _peri: Spi<'d, Async>,
-    txsd: Option<PeripheralRef<'d, AnyPin>>,
+impl<'s, 'd, W: Word> Writer<'s, 'd, W> {
-    rxsd: Option<PeripheralRef<'d, AnyPin>>,
+    /// Write data to the I2S ringbuffer.
-    ws: Option<PeripheralRef<'d, AnyPin>>,
+    /// This appends the data to the buffer and returns immediately. The data will be transmitted in the background.
-    ck: Option<PeripheralRef<'d, AnyPin>>,
+    /// If thfre’s no space in the buffer, this waits until there is.
-    mck: Option<PeripheralRef<'d, AnyPin>>,
+    pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
+        self.0.write_exact(data).await?;
+        Ok(())
+    }
+    /// Reset the ring buffer to its initial state.
+    /// Can be used to recover from overrun.
+    /// The ringbuffer will always auto-reset on Overrun in any case.
+    pub fn reset(&mut self) {
+        self.0.clear();
+    }
 }
-/// I2S function
+/// I2S driver reader. Useful for moving read functionality across tasks.
-#[derive(Copy, Clone)]
+pub struct Reader<'s, 'd, W: Word>(&'s mut ReadableRingBuffer<'d, W>);
-#[allow(dead_code)]
-enum Function {
+impl<'s, 'd, W: Word> Reader<'s, 'd, W> {
-    /// Transmit audio data
+    /// Read data from the I2S ringbuffer.
-    Transmit,
+    /// SAI is always receiving data in the background. This function pops already-received data from the buffer.
-    /// Receive audio data
+    /// If there’s less than data.len() data in the buffer, this waits until there is.
-    Receive,
+    pub async fn read(&mut self, data: &mut [W]) -> Result<(), Error> {
-    #[cfg(spi_v3)]
+        self.0.read_exact(data).await?;
-    /// Transmit and Receive audio data
+        Ok(())
-    FullDuplex,
+    }
+    /// Reset the ring buffer to its initial state.
+    /// Can be used to prevent overrun.
+    /// The ringbuffer will always auto-reset on Overrun in any case.
+    pub fn reset(&mut self) {
+        self.0.clear();
+    }
+}
+/// I2S driver.
+pub struct I2S<'d, W: Word> {
+    #[allow(dead_code)]
+    mode: Mode,
+    spi: Spi<'d, Async>,
+    txsd: Option<Peri<'d, AnyPin>>,
+    rxsd: Option<Peri<'d, AnyPin>>,
+    ws: Option<Peri<'d, AnyPin>>,
+    ck: Option<Peri<'d, AnyPin>>,
+    mck: Option<Peri<'d, AnyPin>>,
+    tx_ring_buffer: Option<WritableRingBuffer<'d, W>>,
+    rx_ring_buffer: Option<ReadableRingBuffer<'d, W>>,
 }
-impl<'d> I2S<'d> {
+impl<'d, W: Word> I2S<'d, W> {
-    /// Create a transmitter driver
+    /// Create a transmitter driver.
    pub fn new_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        sd: Peri<'d, impl MosiPin<T>>,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
+        ws: Peri<'d, impl WsPin<T>>,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
+        ck: Peri<'d, impl CkPin<T>>,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
+        mck: Peri<'d, impl MckPin<T>>,
-        txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        txdma: Peri<'d, impl TxDma<T>>,
+        txdma_buf: &'d mut [W],
+        freq: Hertz,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            ws,
+            ck,
+            new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_dma!(txdma).map(|d| (d, txdma_buf)),
+            None,
+            freq,
+            config,
+            Function::Transmit,
+        )
+    }
+    /// Create a transmitter driver without a master clock pin.
+    pub fn new_txonly_nomck<T: Instance>(
+        peri: Peri<'d, T>,
+        sd: Peri<'d, impl MosiPin<T>>,
+        ws: Peri<'d, impl WsPin<T>>,
+        ck: Peri<'d, impl CkPin<T>>,
+        txdma: Peri<'d, impl TxDma<T>>,
+        txdma_buf: &'d mut [W],
        freq: Hertz,
        config: Config,
    ) -> Self {
-        into_ref!(sd);
        Self::new_inner(
            peri,
            new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
            None,
            ws,
            ck,
-            mck,
+            None,
-            new_dma!(txdma),
+            new_dma!(txdma).map(|d| (d, txdma_buf)),
            None,
            freq,
            config,
@@ -193,120 +287,210 @@ impl<'d> I2S<'d> {
        )
    }
-    /// Create a receiver driver
+    /// Create a receiver driver.
    pub fn new_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sd: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        sd: Peri<'d, impl MisoPin<T>>,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
+        ws: Peri<'d, impl WsPin<T>>,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
+        ck: Peri<'d, impl CkPin<T>>,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
+        mck: Peri<'d, impl MckPin<T>>,
-        #[cfg(not(spi_v3))] txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        rxdma: Peri<'d, impl RxDma<T>>,
-        rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rxdma_buf: &'d mut [W],
        freq: Hertz,
        config: Config,
    ) -> Self {
-        into_ref!(sd);
        Self::new_inner(
            peri,
            None,
            new_pin!(sd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
            ws,
            ck,
-            mck,
+            new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            #[cfg(not(spi_v3))]
-            new_dma!(txdma),
-            #[cfg(spi_v3)]
            None,
-            new_dma!(rxdma),
+            new_dma!(rxdma).map(|d| (d, rxdma_buf)),
            freq,
            config,
-            #[cfg(not(spi_v3))]
-            Function::Transmit,
-            #[cfg(spi_v3)]
            Function::Receive,
        )
    }
    #[cfg(spi_v3)]
-    /// Create a full duplex transmitter driver
+    /// Create a full duplex driver.
    pub fn new_full_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        txsd: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        txsd: Peri<'d, impl MosiPin<T>>,
-        rxsd: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        rxsd: Peri<'d, impl MisoPin<T>>,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
+        ws: Peri<'d, impl WsPin<T>>,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
+        ck: Peri<'d, impl CkPin<T>>,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
+        mck: Peri<'d, impl MckPin<T>>,
-        txdma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        txdma: Peri<'d, impl TxDma<T>>,
-        rxdma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        txdma_buf: &'d mut [W],
+        rxdma: Peri<'d, impl RxDma<T>>,
+        rxdma_buf: &'d mut [W],
        freq: Hertz,
        config: Config,
    ) -> Self {
-        into_ref!(txsd, rxsd);
        Self::new_inner(
            peri,
            new_pin!(txsd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
            new_pin!(rxsd, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
            ws,
            ck,
-            mck,
+            new_pin!(mck, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
-            new_dma!(txdma),
+            new_dma!(txdma).map(|d| (d, txdma_buf)),
-            new_dma!(rxdma),
+            new_dma!(rxdma).map(|d| (d, rxdma_buf)),
            freq,
            config,
            Function::FullDuplex,
        )
    }
-    /// Write audio data.
+    /// Start I2S driver.
-    pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
+    pub fn start(&mut self) {
-        self._peri.read(data).await
+        self.spi.info.regs.cr1().modify(|w| {
+            w.set_spe(false);
+        });
+        self.spi.set_word_size(W::CONFIG);
+        if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
+            tx_ring_buffer.start();
+            set_txdmaen(self.spi.info.regs, true);
+        }
+        if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
+            rx_ring_buffer.start();
+            // SPIv3 clears rxfifo on SPE=0
+            #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
+            flush_rx_fifo(self.spi.info.regs);
+            set_rxdmaen(self.spi.info.regs, true);
+        }
+        self.spi.info.regs.cr1().modify(|w| {
+            w.set_spe(true);
+        });
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        self.spi.info.regs.cr1().modify(|w| {
+            w.set_cstart(true);
+        });
    }
-    /// Write audio data.
+    /// Reset the ring buffer to its initial state.
-    pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
+    /// Can be used to recover from overrun.
-        self._peri.write(data).await
+    pub fn clear(&mut self) {
+        if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
+            rx_ring_buffer.clear();
+        }
+        if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
+            tx_ring_buffer.clear();
+        }
    }
-    /// Transfer audio data.
+    /// Stop I2S driver.
-    pub async fn transfer<W: Word>(&mut self, read: &mut [W], write: &[W]) -> Result<(), Error> {
+    pub async fn stop(&mut self) {
-        self._peri.transfer(read, write).await
+        let regs = self.spi.info.regs;
+        let tx_f = async {
+            if let Some(tx_ring_buffer) = &mut self.tx_ring_buffer {
+                tx_ring_buffer.stop().await;
+                set_txdmaen(regs, false);
+            }
+        };
+        let rx_f = async {
+            if let Some(rx_ring_buffer) = &mut self.rx_ring_buffer {
+                rx_ring_buffer.stop().await;
+                set_rxdmaen(regs, false);
+            }
+        };
+        join(rx_f, tx_f).await;
+        #[cfg(any(spi_v3, spi_v4, spi_v5))]
+        {
+            if let Mode::Master = self.mode {
+                regs.cr1().modify(|w| {
+                    w.set_csusp(true);
+                });
+                while regs.cr1().read().cstart() {}
+            }
+        }
+        regs.cr1().modify(|w| {
+            w.set_spe(false);
+        });
+        self.clear();
+    }
+    /// Split the driver into a Reader/Writer pair.
+    /// Useful for splitting the reader/writer functionality across tasks or
+    /// for calling the read/write methods in parallel.
+    pub fn split<'s>(&'s mut self) -> Result<(Reader<'s, 'd, W>, Writer<'s, 'd, W>), Error> {
+        match (&mut self.rx_ring_buffer, &mut self.tx_ring_buffer) {
+            (None, _) => Err(Error::NotAReceiver),
+            (_, None) => Err(Error::NotATransmitter),
+            (Some(rx_ring), Some(tx_ring)) => Ok((Reader(rx_ring), Writer(tx_ring))),
+        }
    }
-    /// Transfer audio data in place.
+    /// Read data from the I2S ringbuffer.
-    pub async fn transfer_in_place<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
+    /// SAI is always receiving data in the background. This function pops already-received data from the buffer.
-        self._peri.transfer_in_place(data).await
+    /// If there’s less than data.len() data in the buffer, this waits until there is.
+    pub async fn read(&mut self, data: &mut [W]) -> Result<(), Error> {
+        match &mut self.rx_ring_buffer {
+            Some(ring) => Reader(ring).read(data).await,
+            _ => Err(Error::NotAReceiver),
+        }
+    }
+    /// Write data to the I2S ringbuffer.
+    /// This appends the data to the buffer and returns immediately. The data will be transmitted in the background.
+    /// If thfre’s no space in the buffer, this waits until there is.
+    pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
+        match &mut self.tx_ring_buffer {
+            Some(ring) => Writer(ring).write(data).await,
+            _ => Err(Error::NotATransmitter),
+        }
+    }
+    /// Write data directly to the raw I2S ringbuffer.
+    /// This can be used to fill the buffer before starting the DMA transfer.
+    pub async fn write_immediate(&mut self, data: &[W]) -> Result<(usize, usize), Error> {
+        match &mut self.tx_ring_buffer {
+            Some(ring) => Ok(ring.write_immediate(data)?),
+            _ => return Err(Error::NotATransmitter),
+        }
    }
    fn new_inner<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        txsd: Option<PeripheralRef<'d, AnyPin>>,
+        txsd: Option<Peri<'d, AnyPin>>,
-        rxsd: Option<PeripheralRef<'d, AnyPin>>,
+        rxsd: Option<Peri<'d, AnyPin>>,
-        ws: impl Peripheral<P = impl WsPin<T>> + 'd,
+        ws: Peri<'d, impl WsPin<T>>,
-        ck: impl Peripheral<P = impl CkPin<T>> + 'd,
+        ck: Peri<'d, impl CkPin<T>>,
-        mck: impl Peripheral<P = impl MckPin<T>> + 'd,
+        mck: Option<Peri<'d, AnyPin>>,
-        txdma: Option<ChannelAndRequest<'d>>,
+        txdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
-        rxdma: Option<ChannelAndRequest<'d>>,
+        rxdma: Option<(ChannelAndRequest<'d>, &'d mut [W])>,
        freq: Hertz,
        config: Config,
        function: Function,
    ) -> Self {
-        into_ref!(ws, ck, mck);
        ws.set_as_af(ws.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
        ck.set_as_af(ck.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
-        mck.set_as_af(mck.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
-        let mut spi_cfg = SpiConfig::default();
+        let spi = Spi::new_internal(peri, None, None, {
-        spi_cfg.frequency = freq;
+            let mut config = SpiConfig::default();
+            config.frequency = freq;
-        let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
+            config
+        });
        let regs = T::info().regs;
-        // TODO move i2s to the new mux infra.
+        #[cfg(all(rcc_f4, not(stm32f410)))]
-        //#[cfg(all(rcc_f4, not(stm32f410)))]
+        let pclk = unsafe { crate::rcc::get_freqs() }.plli2s1_r.to_hertz().unwrap();
-        //let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
+        #[cfg(not(all(rcc_f4, not(stm32f410))))]
-        //#[cfg(stm32f410)]
        let pclk = T::frequency();
        let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
@@ -376,36 +560,43 @@ impl<'d> I2S<'d> {
                w.set_chlen(config.format.chlen());
                w.set_i2scfg(match (config.mode, function) {
-                    (Mode::Master, Function::Transmit) => I2scfg::MASTERTX,
+                    (Mode::Master, Function::Transmit) => I2scfg::MASTER_TX,
-                    (Mode::Master, Function::Receive) => I2scfg::MASTERRX,
+                    (Mode::Master, Function::Receive) => I2scfg::MASTER_RX,
                    #[cfg(spi_v3)]
-                    (Mode::Master, Function::FullDuplex) => I2scfg::MASTERFULLDUPLEX,
+                    (Mode::Master, Function::FullDuplex) => I2scfg::MASTER_FULL_DUPLEX,
-                    (Mode::Slave, Function::Transmit) => I2scfg::SLAVETX,
+                    (Mode::Slave, Function::Transmit) => I2scfg::SLAVE_TX,
-                    (Mode::Slave, Function::Receive) => I2scfg::SLAVERX,
+                    (Mode::Slave, Function::Receive) => I2scfg::SLAVE_RX,
                    #[cfg(spi_v3)]
-                    (Mode::Slave, Function::FullDuplex) => I2scfg::SLAVEFULLDUPLEX,
+                    (Mode::Slave, Function::FullDuplex) => I2scfg::SLAVE_FULL_DUPLEX,
                });
                #[cfg(any(spi_v1, spi_f1))]
                w.set_i2se(true);
            });
-            #[cfg(spi_v3)]
+            let mut opts = TransferOptions::default();
-            regs.cr1().modify(|w| w.set_spe(true));
+            opts.half_transfer_ir = true;
-        }
+            Self {
-        Self {
+                mode: config.mode,
-            _peri: spi,
+                spi,
-            txsd: txsd.map(|w| w.map_into()),
+                txsd: txsd.map(|w| w.into()),
-            rxsd: rxsd.map(|w| w.map_into()),
+                rxsd: rxsd.map(|w| w.into()),
-            ws: Some(ws.map_into()),
+                ws: Some(ws.into()),
-            ck: Some(ck.map_into()),
+                ck: Some(ck.into()),
-            mck: Some(mck.map_into()),
+                mck: mck.map(|w| w.into()),
+                tx_ring_buffer: txdma.map(|(ch, buf)| unsafe {
+                    WritableRingBuffer::new(ch.channel, ch.request, regs.tx_ptr(), buf, opts)
+                }),
+                rx_ring_buffer: rxdma.map(|(ch, buf)| unsafe {
+                    ReadableRingBuffer::new(ch.channel, ch.request, regs.rx_ptr(), buf, opts)
+                }),
+            }
        }
    }
 }
-impl<'d> Drop for I2S<'d> {
+impl<'d, W: Word> Drop for I2S<'d, W> {
    fn drop(&mut self) {
        self.txsd.as_ref().map(|x| x.set_as_disconnected());
        self.rxsd.as_ref().map(|x| x.set_as_disconnected());
diff --git a/embassy-stm32/src/ipcc.rs b/embassy-stm32/src/ipcc.rs
index 6c8347311..20cd20dca 100644
--- a/embassy-stm32/src/ipcc.rs
+++ b/embassy-stm32/src/ipcc.rs
@@ -229,11 +229,9 @@ struct State {
 impl State {
    const fn new() -> Self {
-        const WAKER: AtomicWaker = AtomicWaker::new();
        Self {
-            rx_wakers: [WAKER; 6],
+            rx_wakers: [const { AtomicWaker::new() }; 6],
-            tx_wakers: [WAKER; 6],
+            tx_wakers: [const { AtomicWaker::new() }; 6],
        }
    }
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 12ebbae2d..973acc9bb 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -68,6 +68,8 @@ pub mod dac;
 pub mod dcmi;
 #[cfg(dsihost)]
 pub mod dsihost;
+#[cfg(dts)]
+pub mod dts;
 #[cfg(eth)]
 pub mod eth;
 #[cfg(feature = "exti")]
@@ -81,6 +83,8 @@ pub mod hash;
 pub mod hrtim;
 #[cfg(hsem)]
 pub mod hsem;
+#[cfg(hspi)]
+pub mod hspi;
 #[cfg(i2c)]
 pub mod i2c;
 #[cfg(any(all(spi_v1, rcc_f4), spi_v3))]
@@ -89,6 +93,8 @@ pub mod i2s;
 pub mod ipcc;
 #[cfg(feature = "low-power")]
 pub mod low_power;
+#[cfg(lptim)]
+pub mod lptim;
 #[cfg(ltdc)]
 pub mod ltdc;
 #[cfg(opamp)]
@@ -105,6 +111,8 @@ pub mod rtc;
 pub mod sai;
 #[cfg(sdmmc)]
 pub mod sdmmc;
+#[cfg(spdifrx)]
+pub mod spdifrx;
 #[cfg(spi)]
 pub mod spi;
 #[cfg(tsc)]
@@ -119,6 +127,8 @@ pub mod usart;
 pub mod usb;
 #[cfg(iwdg)]
 pub mod wdg;
+#[cfg(xspi)]
+pub mod xspi;
 // This must go last, so that it sees all the impl_foo! macros defined earlier.
 pub(crate) mod _generated {
@@ -153,39 +163,63 @@ pub use crate::_generated::interrupt;
 /// ```rust,ignore
 /// use embassy_stm32::{bind_interrupts, i2c, peripherals};
 ///
-/// bind_interrupts!(struct Irqs {
+/// bind_interrupts!(
-///     I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
+///     /// Binds the I2C interrupts.
-///     I2C2_3 => i2c::EventInterruptHandler<peripherals::I2C2>, i2c::ErrorInterruptHandler<peripherals::I2C2>,
+///     struct Irqs {
-///         i2c::EventInterruptHandler<peripherals::I2C3>, i2c::ErrorInterruptHandler<peripherals::I2C3>;
+///         I2C1 => i2c::EventInterruptHandler<peripherals::I2C1>, i2c::ErrorInterruptHandler<peripherals::I2C1>;
-/// });
+///         I2C2_3 => i2c::EventInterruptHandler<peripherals::I2C2>, i2c::ErrorInterruptHandler<peripherals::I2C2>,
+///             i2c::EventInterruptHandler<peripherals::I2C3>, i2c::ErrorInterruptHandler<peripherals::I2C3>;
+///     }
+/// );
 /// ```
 // developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
 #[macro_export]
 macro_rules! bind_interrupts {
-    ($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
+    ($(#[$outer:meta])* $vis:vis struct $name:ident {
+        $(
+            $(#[$inner:meta])*
+            $(#[cfg($cond_irq:meta)])?
+            $irq:ident => $(
+                $(#[cfg($cond_handler:meta)])?
+                $handler:ty
+            ),*;
+        )*
+    }) => {
        #[derive(Copy, Clone)]
+        $(#[$outer])*
        $vis struct $name;
        $(
            #[allow(non_snake_case)]
            #[no_mangle]
+            $(#[cfg($cond_irq)])?
+            $(#[$inner])*
            unsafe extern "C" fn $irq() {
                $(
+                    $(#[cfg($cond_handler)])?
                    <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
                )*
            }
-            $(
+            $(#[cfg($cond_irq)])?
-                unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
+            $crate::bind_interrupts!(@inner
-            )*
+                $(
+                    $(#[cfg($cond_handler)])?
+                    unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
+                )*
+            );
        )*
    };
+    (@inner $($t:tt)*) => {
+        $($t)*
+    }
 }
 // Reexports
 pub use _generated::{peripherals, Peripherals};
-pub use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+pub use embassy_hal_internal::{Peri, PeripheralType};
 #[cfg(feature = "unstable-pac")]
 pub use stm32_metapac as pac;
 #[cfg(not(feature = "unstable-pac"))]
@@ -197,6 +231,7 @@ pub use crate::pac::NVIC_PRIO_BITS;
 /// `embassy-stm32` global configuration.
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    /// RCC config.
    pub rcc: rcc::Config,
@@ -215,6 +250,10 @@ pub struct Config {
    #[cfg(any(stm32l4, stm32l5, stm32u5))]
    pub enable_independent_io_supply: bool,
+    /// On the U5 series all analog peripherals are powered by a separate supply.
+    #[cfg(stm32u5)]
+    pub enable_independent_analog_supply: bool,
    /// BDMA interrupt priority.
    ///
    /// Defaults to P0 (highest).
@@ -254,6 +293,8 @@ impl Default for Config {
            enable_debug_during_sleep: true,
            #[cfg(any(stm32l4, stm32l5, stm32u5))]
            enable_independent_io_supply: true,
+            #[cfg(stm32u5)]
+            enable_independent_analog_supply: true,
            #[cfg(bdma)]
            bdma_interrupt_priority: Priority::P0,
            #[cfg(dma)]
@@ -293,6 +334,9 @@ mod dual_core {
    /// It cannot be initialized by the user. The intended use is:
    ///
    /// ```
+    /// use core::mem::MaybeUninit;
+    /// use embassy_stm32::{init_secondary, SharedData};
+    ///
    /// #[link_section = ".ram_d3"]
    /// static SHARED_DATA: MaybeUninit<SharedData> = MaybeUninit::uninit();
    ///
@@ -300,9 +344,11 @@ mod dual_core {
    /// ```
    ///
    /// This static must be placed in the same position for both cores. How and where this is done is left to the user.
+    #[repr(C)]
    pub struct SharedData {
        init_flag: AtomicUsize,
        clocks: UnsafeCell<MaybeUninit<Clocks>>,
+        config: UnsafeCell<MaybeUninit<SharedConfig>>,
    }
    unsafe impl Sync for SharedData {}
@@ -322,9 +368,16 @@ mod dual_core {
    pub fn init_primary(config: Config, shared_data: &'static MaybeUninit<SharedData>) -> Peripherals {
        let shared_data = unsafe { shared_data.assume_init_ref() };
+        // Write the flag as soon as possible. Reading this flag uninitialized in the `init_secondary`
+        // is maybe unsound? Unclear. If it is indeed unsound, writing it sooner doesn't fix it all,
+        // but improves the odds of it going right
+        shared_data.init_flag.store(0, Ordering::SeqCst);
        rcc::set_freqs_ptr(shared_data.clocks.get());
        let p = init_hw(config);
+        unsafe { *shared_data.config.get() }.write(config.into());
        shared_data.init_flag.store(INIT_DONE_FLAG, Ordering::SeqCst);
        p
@@ -372,15 +425,63 @@ mod dual_core {
    fn init_secondary_hw(shared_data: &'static SharedData) -> Peripherals {
        rcc::set_freqs_ptr(shared_data.clocks.get());
+        let config = unsafe { (*shared_data.config.get()).assume_init() };
        // We use different timers on the different cores, so we have to still initialize one here
-        #[cfg(feature = "_time-driver")]
        critical_section::with(|cs| {
+            unsafe {
+                dma::init(
+                    cs,
+                    #[cfg(bdma)]
+                    config.bdma_interrupt_priority,
+                    #[cfg(dma)]
+                    config.dma_interrupt_priority,
+                    #[cfg(gpdma)]
+                    config.gpdma_interrupt_priority,
+                )
+            }
+            #[cfg(feature = "_time-driver")]
            // must be after rcc init
            time_driver::init(cs);
        });
        Peripherals::take()
    }
+    #[repr(C)]
+    #[derive(Clone, Copy)]
+    struct SharedConfig {
+        #[cfg(bdma)]
+        bdma_interrupt_priority: Priority,
+        #[cfg(dma)]
+        dma_interrupt_priority: Priority,
+        #[cfg(gpdma)]
+        gpdma_interrupt_priority: Priority,
+    }
+    impl From<Config> for SharedConfig {
+        fn from(value: Config) -> Self {
+            let Config {
+                #[cfg(bdma)]
+                bdma_interrupt_priority,
+                #[cfg(dma)]
+                dma_interrupt_priority,
+                #[cfg(gpdma)]
+                gpdma_interrupt_priority,
+                ..
+            } = value;
+            SharedConfig {
+                #[cfg(bdma)]
+                bdma_interrupt_priority,
+                #[cfg(dma)]
+                dma_interrupt_priority,
+                #[cfg(gpdma)]
+                gpdma_interrupt_priority,
+            }
+        }
+    }
 }
 #[cfg(feature = "_dual-core")]
@@ -397,7 +498,7 @@ fn init_hw(config: Config) -> Peripherals {
                cr.set_stop(config.enable_debug_during_sleep);
                cr.set_standby(config.enable_debug_during_sleep);
            }
-            #[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u5, dbgmcu_wba, dbgmcu_l5))]
+            #[cfg(any(dbgmcu_f0, dbgmcu_c0, dbgmcu_g0, dbgmcu_u0, dbgmcu_u5, dbgmcu_wba, dbgmcu_l5))]
            {
                cr.set_dbg_stop(config.enable_debug_during_sleep);
                cr.set_dbg_standby(config.enable_debug_during_sleep);
@@ -444,6 +545,20 @@ fn init_hw(config: Config) -> Peripherals {
            crate::pac::PWR.svmcr().modify(|w| {
                w.set_io2sv(config.enable_independent_io_supply);
            });
+            if config.enable_independent_analog_supply {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(true);
+                });
+                while !crate::pac::PWR.svmsr().read().vdda1rdy() {}
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_asv(true);
+                });
+            } else {
+                crate::pac::PWR.svmcr().modify(|w| {
+                    w.set_avm1en(false);
+                    w.set_avm2en(false);
+                });
+            }
        }
        // dead battery functionality is still present on these
@@ -491,17 +606,7 @@ fn init_hw(config: Config) -> Peripherals {
            #[cfg(feature = "exti")]
            exti::init(cs);
-            rcc::init(config.rcc);
+            rcc::init_rcc(cs, config.rcc);
-            // must be after rcc init
-            #[cfg(feature = "_time-driver")]
-            time_driver::init(cs);
-            #[cfg(feature = "low-power")]
-            {
-                crate::rcc::REFCOUNT_STOP2 = 0;
-                crate::rcc::REFCOUNT_STOP1 = 0;
-            }
        }
        p
diff --git a/embassy-stm32/src/low_power.rs b/embassy-stm32/src/low_power.rs
index 604bdf416..7734365f1 100644
--- a/embassy-stm32/src/low_power.rs
+++ b/embassy-stm32/src/low_power.rs
@@ -51,6 +51,9 @@
 //! }
 //! ```
+// TODO: Usage of `static mut` here is unsound. Fix then remove this `allow`.`
+#![allow(static_mut_refs)]
 use core::arch::asm;
 use core::marker::PhantomData;
 use core::sync::atomic::{compiler_fence, Ordering};
@@ -67,6 +70,7 @@ use crate::rtc::Rtc;
 static mut EXECUTOR: Option<Executor> = None;
+#[cfg(not(stm32u0))]
 foreach_interrupt! {
    (RTC, rtc, $block:ident, WKUP, $irq:ident) => {
        #[interrupt]
@@ -77,6 +81,17 @@ foreach_interrupt! {
    };
 }
+#[cfg(stm32u0)]
+foreach_interrupt! {
+    (RTC, rtc, $block:ident, TAMP, $irq:ident) => {
+        #[interrupt]
+        #[allow(non_snake_case)]
+        unsafe fn $irq() {
+            EXECUTOR.as_mut().unwrap().on_wakeup_irq();
+        }
+    };
+}
 #[allow(dead_code)]
 pub(crate) unsafe fn on_wakeup_irq() {
    EXECUTOR.as_mut().unwrap().on_wakeup_irq();
@@ -109,10 +124,10 @@ pub enum StopMode {
    Stop2,
 }
-#[cfg(stm32l5)]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
 use stm32_metapac::pwr::vals::Lpms;
-#[cfg(stm32l5)]
+#[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
 impl Into<Lpms> for StopMode {
    fn into(self) -> Lpms {
        match self {
@@ -152,7 +167,9 @@ impl Executor {
                time_driver: get_driver(),
            });
-            EXECUTOR.as_mut().unwrap()
+            let executor = EXECUTOR.as_mut().unwrap();
+            executor
        })
    }
@@ -181,7 +198,7 @@ impl Executor {
    #[allow(unused_variables)]
    fn configure_stop(&mut self, stop_mode: StopMode) {
-        #[cfg(stm32l5)]
+        #[cfg(any(stm32l4, stm32l5, stm32u5, stm32u0))]
        crate::pac::PWR.cr1().modify(|m| m.set_lpms(stop_mode.into()));
        #[cfg(stm32h5)]
        crate::pac::PWR.pmcr().modify(|v| {
@@ -238,11 +255,12 @@ impl Executor {
    ///
    /// This function never returns.
    pub fn run(&'static mut self, init: impl FnOnce(Spawner)) -> ! {
-        init(unsafe { EXECUTOR.as_mut().unwrap() }.inner.spawner());
+        let executor = unsafe { EXECUTOR.as_mut().unwrap() };
+        init(executor.inner.spawner());
        loop {
            unsafe {
-                EXECUTOR.as_mut().unwrap().inner.poll();
+                executor.inner.poll();
                self.configure_pwr();
                asm!("wfe");
            };
diff --git a/embassy-stm32/src/lptim/channel.rs b/embassy-stm32/src/lptim/channel.rs
new file mode 100644
index 000000000..17fc2fb86
--- /dev/null
+++ b/embassy-stm32/src/lptim/channel.rs
@@ -0,0 +1,18 @@
+/// Timer channel.
+#[derive(Clone, Copy)]
+pub enum Channel {
+    /// Channel 1.
+    Ch1,
+    /// Channel 2.
+    Ch2,
+}
+impl Channel {
+    /// Get the channel index (0..1)
+    pub fn index(&self) -> usize {
+        match self {
+            Channel::Ch1 => 0,
+            Channel::Ch2 => 1,
+        }
+    }
+}
diff --git a/embassy-stm32/src/lptim/mod.rs b/embassy-stm32/src/lptim/mod.rs
new file mode 100644
index 000000000..e0ddba1c7
--- /dev/null
+++ b/embassy-stm32/src/lptim/mod.rs
@@ -0,0 +1,49 @@
+//! Low-power timer (LPTIM)
+pub mod pwm;
+pub mod timer;
+use crate::rcc::RccPeripheral;
+/// Timer channel.
+#[cfg(any(lptim_v2a, lptim_v2b))]
+mod channel;
+#[cfg(any(lptim_v2a, lptim_v2b))]
+pub use channel::Channel;
+use embassy_hal_internal::PeripheralType;
+pin_trait!(OutputPin, BasicInstance);
+pin_trait!(Channel1Pin, BasicInstance);
+pin_trait!(Channel2Pin, BasicInstance);
+pub(crate) trait SealedInstance: RccPeripheral {
+    fn regs() -> crate::pac::lptim::Lptim;
+}
+pub(crate) trait SealedBasicInstance: RccPeripheral {}
+/// LPTIM basic instance trait.
+#[allow(private_bounds)]
+pub trait BasicInstance: PeripheralType + SealedBasicInstance + 'static {}
+/// LPTIM instance trait.
+#[allow(private_bounds)]
+pub trait Instance: BasicInstance + SealedInstance + 'static {}
+foreach_interrupt! {
+    ($inst:ident, lptim, LPTIM, GLOBAL, $irq:ident) => {
+        impl SealedInstance for crate::peripherals::$inst {
+            fn regs() -> crate::pac::lptim::Lptim {
+                crate::pac::$inst
+            }
+        }
+        impl SealedBasicInstance for crate::peripherals::$inst {
+        }
+        impl BasicInstance for crate::peripherals::$inst {}
+        impl Instance for crate::peripherals::$inst {}
+    };
+    ($inst:ident, lptim, LPTIM_BASIC, GLOBAL, $irq:ident) => {
+        impl SealedBasicInstance for crate::peripherals::$inst {
+        }
+        impl BasicInstance for crate::peripherals::$inst {}
+    };
+}
diff --git a/embassy-stm32/src/lptim/pwm.rs b/embassy-stm32/src/lptim/pwm.rs
new file mode 100644
index 000000000..2f2d7ba01
--- /dev/null
+++ b/embassy-stm32/src/lptim/pwm.rs
@@ -0,0 +1,198 @@
+//! PWM driver.
+use core::marker::PhantomData;
+use embassy_hal_internal::Peri;
+use super::timer::Timer;
+#[cfg(not(any(lptim_v2a, lptim_v2b)))]
+use super::OutputPin;
+#[cfg(any(lptim_v2a, lptim_v2b))]
+use super::{channel::Channel, timer::ChannelDirection, Channel1Pin, Channel2Pin};
+use super::{BasicInstance, Instance};
+#[cfg(gpio_v2)]
+use crate::gpio::Pull;
+use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::time::Hertz;
+/// Output marker type.
+pub enum Output {}
+/// Channel 1 marker type.
+pub enum Ch1 {}
+/// Channel 2 marker type.
+pub enum Ch2 {}
+/// PWM pin wrapper.
+///
+/// This wraps a pin to make it usable with PWM.
+pub struct PwmPin<'d, T, C> {
+    _pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<(T, C)>,
+}
+/// PWM pin config
+///
+/// This configures the pwm pin settings
+pub struct PwmPinConfig {
+    /// PWM Pin output type
+    pub output_type: OutputType,
+    /// PWM Pin speed
+    pub speed: Speed,
+    /// PWM Pin pull type
+    #[cfg(gpio_v2)]
+    pub pull: Pull,
+}
+macro_rules! channel_impl {
+    ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
+        impl<'d, T: BasicInstance> PwmPin<'d, T, $channel> {
+            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    pin.set_as_af(
+                        pin.af_num(),
+                        AfType::output(OutputType::PushPull, Speed::VeryHigh),
+                    );
+                });
+                PwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
+            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
+            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    pin.set_as_af(
+                        pin.af_num(),
+                        #[cfg(gpio_v1)]
+                        AfType::output(pin_config.output_type, pin_config.speed),
+                        #[cfg(gpio_v2)]
+                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+                    );
+                });
+                PwmPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
+        }
+    };
+}
+#[cfg(not(any(lptim_v2a, lptim_v2b)))]
+channel_impl!(new, new_with_config, Output, OutputPin);
+#[cfg(any(lptim_v2a, lptim_v2b))]
+channel_impl!(new_ch1, new_ch1_with_config, Ch1, Channel1Pin);
+#[cfg(any(lptim_v2a, lptim_v2b))]
+channel_impl!(new_ch2, new_ch2_with_config, Ch2, Channel2Pin);
+/// PWM driver.
+pub struct Pwm<'d, T: Instance> {
+    inner: Timer<'d, T>,
+}
+#[cfg(not(any(lptim_v2a, lptim_v2b)))]
+impl<'d, T: Instance> Pwm<'d, T> {
+    /// Create a new PWM driver.
+    pub fn new(tim: Peri<'d, T>, _output_pin: PwmPin<'d, T, Output>, freq: Hertz) -> Self {
+        Self::new_inner(tim, freq)
+    }
+    /// Set the duty.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
+    pub fn set_duty(&mut self, duty: u16) {
+        assert!(duty <= self.get_max_duty());
+        self.inner.set_compare_value(duty)
+    }
+    /// Get the duty.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
+    pub fn get_duty(&self) -> u16 {
+        self.inner.get_compare_value()
+    }
+    fn post_init(&mut self) {}
+}
+#[cfg(any(lptim_v2a, lptim_v2b))]
+impl<'d, T: Instance> Pwm<'d, T> {
+    /// Create a new PWM driver.
+    pub fn new(
+        tim: Peri<'d, T>,
+        _ch1_pin: Option<PwmPin<'d, T, Ch1>>,
+        _ch2_pin: Option<PwmPin<'d, T, Ch2>>,
+        freq: Hertz,
+    ) -> Self {
+        Self::new_inner(tim, freq)
+    }
+    /// Enable the given channel.
+    pub fn enable(&mut self, channel: Channel) {
+        self.inner.enable_channel(channel, true);
+    }
+    /// Disable the given channel.
+    pub fn disable(&mut self, channel: Channel) {
+        self.inner.enable_channel(channel, false);
+    }
+    /// Check whether given channel is enabled
+    pub fn is_enabled(&self, channel: Channel) -> bool {
+        self.inner.get_channel_enable_state(channel)
+    }
+    /// Set the duty for a given channel.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
+    pub fn set_duty(&mut self, channel: Channel, duty: u16) {
+        assert!(duty <= self.get_max_duty());
+        self.inner.set_compare_value(channel, duty)
+    }
+    /// Get the duty for a given channel.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
+    pub fn get_duty(&self, channel: Channel) -> u16 {
+        self.inner.get_compare_value(channel)
+    }
+    fn post_init(&mut self) {
+        [Channel::Ch1, Channel::Ch2].iter().for_each(|&channel| {
+            self.inner.set_channel_direction(channel, ChannelDirection::OutputPwm);
+        });
+    }
+}
+impl<'d, T: Instance> Pwm<'d, T> {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz) -> Self {
+        let mut this = Self { inner: Timer::new(tim) };
+        this.inner.enable();
+        this.set_frequency(freq);
+        this.post_init();
+        this.inner.continuous_mode_start();
+        this
+    }
+    /// Set PWM frequency.
+    ///
+    /// Note: when you call this, the max duty value changes, so you will have to
+    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
+    pub fn set_frequency(&mut self, frequency: Hertz) {
+        self.inner.set_frequency(frequency);
+    }
+    /// Get max duty value.
+    ///
+    /// This value depends on the configured frequency and the timer's clock rate from RCC.
+    pub fn get_max_duty(&self) -> u16 {
+        self.inner.get_max_compare_value() + 1
+    }
+}
diff --git a/embassy-stm32/src/lptim/timer/channel_direction.rs b/embassy-stm32/src/lptim/timer/channel_direction.rs
new file mode 100644
index 000000000..e4af8f45f
--- /dev/null
+++ b/embassy-stm32/src/lptim/timer/channel_direction.rs
@@ -0,0 +1,18 @@
+use crate::pac::lptim::vals;
+/// Direction of a low-power timer channel
+pub enum ChannelDirection {
+    /// Use channel as a PWM output
+    OutputPwm,
+    /// Use channel as an input capture
+    InputCapture,
+}
+impl From<ChannelDirection> for vals::Ccsel {
+    fn from(direction: ChannelDirection) -> Self {
+        match direction {
+            ChannelDirection::OutputPwm => vals::Ccsel::OUTPUT_COMPARE,
+            ChannelDirection::InputCapture => vals::Ccsel::INPUT_CAPTURE,
+        }
+    }
+}
diff --git a/embassy-stm32/src/lptim/timer/mod.rs b/embassy-stm32/src/lptim/timer/mod.rs
new file mode 100644
index 000000000..a629be62b
--- /dev/null
+++ b/embassy-stm32/src/lptim/timer/mod.rs
@@ -0,0 +1,131 @@
+//! Low-level timer driver.
+mod prescaler;
+use embassy_hal_internal::Peri;
+#[cfg(any(lptim_v2a, lptim_v2b))]
+use super::channel::Channel;
+#[cfg(any(lptim_v2a, lptim_v2b))]
+mod channel_direction;
+#[cfg(any(lptim_v2a, lptim_v2b))]
+pub use channel_direction::ChannelDirection;
+use prescaler::Prescaler;
+use super::Instance;
+use crate::rcc;
+use crate::time::Hertz;
+/// Low-level timer driver.
+pub struct Timer<'d, T: Instance> {
+    _tim: Peri<'d, T>,
+}
+impl<'d, T: Instance> Timer<'d, T> {
+    /// Create a new timer driver.
+    pub fn new(tim: Peri<'d, T>) -> Self {
+        rcc::enable_and_reset::<T>();
+        Self { _tim: tim }
+    }
+    /// Enable the timer.
+    pub fn enable(&self) {
+        T::regs().cr().modify(|w| w.set_enable(true));
+    }
+    /// Disable the timer.
+    pub fn disable(&self) {
+        T::regs().cr().modify(|w| w.set_enable(false));
+    }
+    /// Start the timer in single pulse mode.
+    pub fn single_mode_start(&self) {
+        T::regs().cr().modify(|w| w.set_sngstrt(true));
+    }
+    /// Start the timer in continuous mode.
+    pub fn continuous_mode_start(&self) {
+        T::regs().cr().modify(|w| w.set_cntstrt(true));
+    }
+    /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
+    pub fn set_frequency(&self, frequency: Hertz) {
+        let f = frequency.0;
+        assert!(f > 0);
+        let pclk_f = T::frequency().0;
+        let pclk_ticks_per_timer_period = pclk_f / f;
+        let psc = Prescaler::from_ticks(pclk_ticks_per_timer_period);
+        let arr = psc.scale_down(pclk_ticks_per_timer_period);
+        T::regs().cfgr().modify(|r| r.set_presc((&psc).into()));
+        T::regs().arr().modify(|r| r.set_arr(arr.into()));
+    }
+    /// Get the timer frequency.
+    pub fn get_frequency(&self) -> Hertz {
+        let pclk_f = T::frequency();
+        let arr = T::regs().arr().read().arr();
+        let psc = Prescaler::from(T::regs().cfgr().read().presc());
+        pclk_f / psc.scale_up(arr)
+    }
+    /// Get the clock frequency of the timer (before prescaler is applied).
+    pub fn get_clock_frequency(&self) -> Hertz {
+        T::frequency()
+    }
+    /// Get max compare value. This depends on the timer frequency and the clock frequency from RCC.
+    pub fn get_max_compare_value(&self) -> u16 {
+        T::regs().arr().read().arr()
+    }
+}
+#[cfg(any(lptim_v2a, lptim_v2b))]
+impl<'d, T: Instance> Timer<'d, T> {
+    /// Enable/disable a channel.
+    pub fn enable_channel(&self, channel: Channel, enable: bool) {
+        T::regs().ccmr(0).modify(|w| {
+            w.set_cce(channel.index(), enable);
+        });
+    }
+    /// Get enable/disable state of a channel
+    pub fn get_channel_enable_state(&self, channel: Channel) -> bool {
+        T::regs().ccmr(0).read().cce(channel.index())
+    }
+    /// Set compare value for a channel.
+    pub fn set_compare_value(&self, channel: Channel, value: u16) {
+        T::regs().ccr(channel.index()).modify(|w| w.set_ccr(value));
+    }
+    /// Get compare value for a channel.
+    pub fn get_compare_value(&self, channel: Channel) -> u16 {
+        T::regs().ccr(channel.index()).read().ccr()
+    }
+    /// Set channel direction.
+    #[cfg(any(lptim_v2a, lptim_v2b))]
+    pub fn set_channel_direction(&self, channel: Channel, direction: ChannelDirection) {
+        T::regs()
+            .ccmr(0)
+            .modify(|w| w.set_ccsel(channel.index(), direction.into()));
+    }
+}
+#[cfg(not(any(lptim_v2a, lptim_v2b)))]
+impl<'d, T: Instance> Timer<'d, T> {
+    /// Set compare value for a channel.
+    pub fn set_compare_value(&self, value: u16) {
+        T::regs().cmp().modify(|w| w.set_cmp(value));
+    }
+    /// Get compare value for a channel.
+    pub fn get_compare_value(&self) -> u16 {
+        T::regs().cmp().read().cmp()
+    }
+}
diff --git a/embassy-stm32/src/lptim/timer/prescaler.rs b/embassy-stm32/src/lptim/timer/prescaler.rs
new file mode 100644
index 000000000..5d2326faf
--- /dev/null
+++ b/embassy-stm32/src/lptim/timer/prescaler.rs
@@ -0,0 +1,90 @@
+//! Low-level timer driver.
+use crate::pac::lptim::vals;
+pub enum Prescaler {
+    Div1,
+    Div2,
+    Div4,
+    Div8,
+    Div16,
+    Div32,
+    Div64,
+    Div128,
+}
+impl From<&Prescaler> for vals::Presc {
+    fn from(prescaler: &Prescaler) -> Self {
+        match prescaler {
+            Prescaler::Div1 => vals::Presc::DIV1,
+            Prescaler::Div2 => vals::Presc::DIV2,
+            Prescaler::Div4 => vals::Presc::DIV4,
+            Prescaler::Div8 => vals::Presc::DIV8,
+            Prescaler::Div16 => vals::Presc::DIV16,
+            Prescaler::Div32 => vals::Presc::DIV32,
+            Prescaler::Div64 => vals::Presc::DIV64,
+            Prescaler::Div128 => vals::Presc::DIV128,
+        }
+    }
+}
+impl From<vals::Presc> for Prescaler {
+    fn from(prescaler: vals::Presc) -> Self {
+        match prescaler {
+            vals::Presc::DIV1 => Prescaler::Div1,
+            vals::Presc::DIV2 => Prescaler::Div2,
+            vals::Presc::DIV4 => Prescaler::Div4,
+            vals::Presc::DIV8 => Prescaler::Div8,
+            vals::Presc::DIV16 => Prescaler::Div16,
+            vals::Presc::DIV32 => Prescaler::Div32,
+            vals::Presc::DIV64 => Prescaler::Div64,
+            vals::Presc::DIV128 => Prescaler::Div128,
+        }
+    }
+}
+impl From<&Prescaler> for u32 {
+    fn from(prescaler: &Prescaler) -> Self {
+        match prescaler {
+            Prescaler::Div1 => 1,
+            Prescaler::Div2 => 2,
+            Prescaler::Div4 => 4,
+            Prescaler::Div8 => 8,
+            Prescaler::Div16 => 16,
+            Prescaler::Div32 => 32,
+            Prescaler::Div64 => 64,
+            Prescaler::Div128 => 128,
+        }
+    }
+}
+impl From<u32> for Prescaler {
+    fn from(prescaler: u32) -> Self {
+        match prescaler {
+            1 => Prescaler::Div1,
+            2 => Prescaler::Div2,
+            4 => Prescaler::Div4,
+            8 => Prescaler::Div8,
+            16 => Prescaler::Div16,
+            32 => Prescaler::Div32,
+            64 => Prescaler::Div64,
+            128 => Prescaler::Div128,
+            _ => unreachable!(),
+        }
+    }
+}
+impl Prescaler {
+    pub fn from_ticks(ticks: u32) -> Self {
+        // We need to scale down to a 16-bit range
+        (ticks >> 16).next_power_of_two().into()
+    }
+    pub fn scale_down(&self, ticks: u32) -> u16 {
+        (ticks / u32::from(self)).try_into().unwrap()
+    }
+    pub fn scale_up(&self, ticks: u16) -> u32 {
+        u32::from(self) * ticks as u32
+    }
+}
diff --git a/embassy-stm32/src/ltdc.rs b/embassy-stm32/src/ltdc.rs
index 4c5239971..0f6ef569c 100644
--- a/embassy-stm32/src/ltdc.rs
+++ b/embassy-stm32/src/ltdc.rs
@@ -6,7 +6,7 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use stm32_metapac::ltdc::regs::Dccr;
 use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
@@ -14,7 +14,7 @@ use stm32_metapac::ltdc::vals::{Bf1, Bf2, Cfuif, Clif, Crrif, Cterrif, Pf, Vbr};
 use crate::gpio::{AfType, OutputType, Speed};
 use crate::interrupt::typelevel::Interrupt;
 use crate::interrupt::{self};
-use crate::{peripherals, rcc, Peripheral};
+use crate::{peripherals, rcc, Peri};
 static LTDC_WAKER: AtomicWaker = AtomicWaker::new();
@@ -83,7 +83,7 @@ pub enum PolarityActive {
 /// LTDC driver.
 pub struct Ltdc<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
 }
 /// LTDC interrupt handler.
@@ -178,47 +178,45 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 impl<'d, T: Instance> Ltdc<'d, T> {
    // Create a new LTDC driver without specifying color and control pins. This is typically used if you want to drive a display though a DsiHost
    /// Note: Full-Duplex modes are not supported at this time
-    pub fn new(peri: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(peri: Peri<'d, T>) -> Self {
        Self::setup_clocks();
-        into_ref!(peri);
        Self { _peri: peri }
    }
    /// Create a new LTDC driver. 8 pins per color channel for blue, green and red
    #[allow(clippy::too_many_arguments)]
    pub fn new_with_pins(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl ClkPin<T>> + 'd,
+        clk: Peri<'d, impl ClkPin<T>>,
-        hsync: impl Peripheral<P = impl HsyncPin<T>> + 'd,
+        hsync: Peri<'d, impl HsyncPin<T>>,
-        vsync: impl Peripheral<P = impl VsyncPin<T>> + 'd,
+        vsync: Peri<'d, impl VsyncPin<T>>,
-        b0: impl Peripheral<P = impl B0Pin<T>> + 'd,
+        b0: Peri<'d, impl B0Pin<T>>,
-        b1: impl Peripheral<P = impl B1Pin<T>> + 'd,
+        b1: Peri<'d, impl B1Pin<T>>,
-        b2: impl Peripheral<P = impl B2Pin<T>> + 'd,
+        b2: Peri<'d, impl B2Pin<T>>,
-        b3: impl Peripheral<P = impl B3Pin<T>> + 'd,
+        b3: Peri<'d, impl B3Pin<T>>,
-        b4: impl Peripheral<P = impl B4Pin<T>> + 'd,
+        b4: Peri<'d, impl B4Pin<T>>,
-        b5: impl Peripheral<P = impl B5Pin<T>> + 'd,
+        b5: Peri<'d, impl B5Pin<T>>,
-        b6: impl Peripheral<P = impl B6Pin<T>> + 'd,
+        b6: Peri<'d, impl B6Pin<T>>,
-        b7: impl Peripheral<P = impl B7Pin<T>> + 'd,
+        b7: Peri<'d, impl B7Pin<T>>,
-        g0: impl Peripheral<P = impl G0Pin<T>> + 'd,
+        g0: Peri<'d, impl G0Pin<T>>,
-        g1: impl Peripheral<P = impl G1Pin<T>> + 'd,
+        g1: Peri<'d, impl G1Pin<T>>,
-        g2: impl Peripheral<P = impl G2Pin<T>> + 'd,
+        g2: Peri<'d, impl G2Pin<T>>,
-        g3: impl Peripheral<P = impl G3Pin<T>> + 'd,
+        g3: Peri<'d, impl G3Pin<T>>,
-        g4: impl Peripheral<P = impl G4Pin<T>> + 'd,
+        g4: Peri<'d, impl G4Pin<T>>,
-        g5: impl Peripheral<P = impl G5Pin<T>> + 'd,
+        g5: Peri<'d, impl G5Pin<T>>,
-        g6: impl Peripheral<P = impl G6Pin<T>> + 'd,
+        g6: Peri<'d, impl G6Pin<T>>,
-        g7: impl Peripheral<P = impl G7Pin<T>> + 'd,
+        g7: Peri<'d, impl G7Pin<T>>,
-        r0: impl Peripheral<P = impl R0Pin<T>> + 'd,
+        r0: Peri<'d, impl R0Pin<T>>,
-        r1: impl Peripheral<P = impl R1Pin<T>> + 'd,
+        r1: Peri<'d, impl R1Pin<T>>,
-        r2: impl Peripheral<P = impl R2Pin<T>> + 'd,
+        r2: Peri<'d, impl R2Pin<T>>,
-        r3: impl Peripheral<P = impl R3Pin<T>> + 'd,
+        r3: Peri<'d, impl R3Pin<T>>,
-        r4: impl Peripheral<P = impl R4Pin<T>> + 'd,
+        r4: Peri<'d, impl R4Pin<T>>,
-        r5: impl Peripheral<P = impl R5Pin<T>> + 'd,
+        r5: Peri<'d, impl R5Pin<T>>,
-        r6: impl Peripheral<P = impl R6Pin<T>> + 'd,
+        r6: Peri<'d, impl R6Pin<T>>,
-        r7: impl Peripheral<P = impl R7Pin<T>> + 'd,
+        r7: Peri<'d, impl R7Pin<T>>,
    ) -> Self {
        Self::setup_clocks();
-        into_ref!(peri);
        new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh));
        new_pin!(hsync, AfType::output(OutputType::PushPull, Speed::VeryHigh));
        new_pin!(vsync, AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -261,23 +259,23 @@ impl<'d, T: Instance> Ltdc<'d, T> {
        // configure the HS, VS, DE and PC polarity
        ltdc.gcr().modify(|w| {
            w.set_hspol(match config.h_sync_polarity {
-                PolarityActive::ActiveHigh => Hspol::ACTIVEHIGH,
+                PolarityActive::ActiveHigh => Hspol::ACTIVE_HIGH,
-                PolarityActive::ActiveLow => Hspol::ACTIVELOW,
+                PolarityActive::ActiveLow => Hspol::ACTIVE_LOW,
            });
            w.set_vspol(match config.v_sync_polarity {
-                PolarityActive::ActiveHigh => Vspol::ACTIVEHIGH,
+                PolarityActive::ActiveHigh => Vspol::ACTIVE_HIGH,
-                PolarityActive::ActiveLow => Vspol::ACTIVELOW,
+                PolarityActive::ActiveLow => Vspol::ACTIVE_LOW,
            });
            w.set_depol(match config.data_enable_polarity {
-                PolarityActive::ActiveHigh => Depol::ACTIVEHIGH,
+                PolarityActive::ActiveHigh => Depol::ACTIVE_HIGH,
-                PolarityActive::ActiveLow => Depol::ACTIVELOW,
+                PolarityActive::ActiveLow => Depol::ACTIVE_LOW,
            });
            w.set_pcpol(match config.pixel_clock_polarity {
-                PolarityEdge::RisingEdge => Pcpol::RISINGEDGE,
+                PolarityEdge::RisingEdge => Pcpol::RISING_EDGE,
-                PolarityEdge::FallingEdge => Pcpol::FALLINGEDGE,
+                PolarityEdge::FallingEdge => Pcpol::FALLING_EDGE,
            });
        });
@@ -395,7 +393,10 @@ impl<'d, T: Instance> Ltdc<'d, T> {
        // framebuffer pitch and line length
        layer.cfblr().modify(|w| {
            w.set_cfbp(width * bytes_per_pixel);
+            #[cfg(not(stm32u5))]
            w.set_cfbll(width * bytes_per_pixel + 7);
+            #[cfg(stm32u5)]
+            w.set_cfbll(width * bytes_per_pixel + 3);
        });
        // framebuffer line number
@@ -526,7 +527,7 @@ trait SealedInstance: crate::rcc::SealedRccPeripheral {
 /// LTDC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
    /// Interrupt for this LTDC instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/macros.rs b/embassy-stm32/src/macros.rs
index ae53deb08..7526bb180 100644
--- a/embassy-stm32/src/macros.rs
+++ b/embassy-stm32/src/macros.rs
@@ -14,7 +14,7 @@ macro_rules! peri_trait {
        /// Peripheral instance trait.
        #[allow(private_bounds)]
-        pub trait Instance: crate::Peripheral<P = Self> + SealedInstance + crate::rcc::RccPeripheral {
+        pub trait Instance: SealedInstance + crate::PeripheralType  + crate::rcc::RccPeripheral {
            $($(
                /// Interrupt for this peripheral.
                type $irq: crate::interrupt::typelevel::Interrupt;
@@ -60,6 +60,17 @@ macro_rules! pin_trait_impl {
    };
 }
+#[allow(unused_macros)]
+macro_rules! sel_trait_impl {
+    (crate::$mod:ident::$trait:ident$(<$mode:ident>)?, $instance:ident, $pin:ident, $sel:expr) => {
+        impl crate::$mod::$trait<crate::peripherals::$instance $(, crate::$mod::$mode)?> for crate::peripherals::$pin {
+            fn sel(&self) -> u8 {
+                $sel
+            }
+        }
+    };
+}
 // ====================
 macro_rules! dma_trait {
@@ -85,12 +96,24 @@ macro_rules! dma_trait_impl {
    };
 }
+#[allow(unused)]
+macro_rules! new_dma_nonopt {
+    ($name:ident) => {{
+        let dma = $name;
+        let request = dma.request();
+        crate::dma::ChannelAndRequest {
+            channel: dma.into(),
+            request,
+        }
+    }};
+}
 macro_rules! new_dma {
    ($name:ident) => {{
-        let dma = $name.into_ref();
+        let dma = $name;
        let request = dma.request();
        Some(crate::dma::ChannelAndRequest {
-            channel: dma.map_into(),
+            channel: dma.into(),
            request,
        })
    }};
@@ -98,8 +121,8 @@ macro_rules! new_dma {
 macro_rules! new_pin {
    ($name:ident, $af_type:expr) => {{
-        let pin = $name.into_ref();
+        let pin = $name;
        pin.set_as_af(pin.af_num(), $af_type);
-        Some(pin.map_into())
+        Some(pin.into())
    }};
 }
diff --git a/embassy-stm32/src/opamp.rs b/embassy-stm32/src/opamp.rs
index c86c18e22..2eb2e61c1 100644
--- a/embassy-stm32/src/opamp.rs
+++ b/embassy-stm32/src/opamp.rs
@@ -1,40 +1,48 @@
 //! Operational Amplifier (OPAMP)
 #![macro_use]
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use crate::pac::opamp::vals::*;
-use crate::Peripheral;
+use crate::Peri;
+/// Performs a busy-wait delay for a specified number of microseconds.
+#[cfg(opamp_g4)]
+fn blocking_delay_ms(ms: u32) {
+    #[cfg(feature = "time")]
+    embassy_time::block_for(embassy_time::Duration::from_millis(ms as u64));
+    #[cfg(not(feature = "time"))]
+    cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000 * ms);
+}
 /// Gain
 #[allow(missing_docs)]
 #[derive(Clone, Copy)]
 pub enum OpAmpGain {
-    Mul1,
    Mul2,
    Mul4,
    Mul8,
    Mul16,
+    #[cfg(opamp_g4)]
+    Mul32,
+    #[cfg(opamp_g4)]
+    Mul64,
+}
+#[cfg(opamp_g4)]
+enum OpAmpDifferentialPair {
+    P,
+    N,
 }
 /// Speed
 #[allow(missing_docs)]
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, PartialEq)]
 pub enum OpAmpSpeed {
    Normal,
    HighSpeed,
 }
-#[cfg(opamp_g4)]
-impl From<OpAmpSpeed> for crate::pac::opamp::vals::Opahsm {
-    fn from(v: OpAmpSpeed) -> Self {
-        match v {
-            OpAmpSpeed::Normal => crate::pac::opamp::vals::Opahsm::NORMAL,
-            OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::Opahsm::HIGHSPEED,
-        }
-    }
-}
 /// OpAmp external outputs, wired to a GPIO pad.
 ///
 /// This struct can also be used as an ADC input.
@@ -52,19 +60,17 @@ pub struct OpAmpInternalOutput<'d, T: Instance> {
 /// OpAmp driver.
 pub struct OpAmp<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
 }
 impl<'d, T: Instance> OpAmp<'d, T> {
    /// Create a new driver instance.
    ///
    /// Does not enable the opamp, but does set the speed mode on some families.
-    pub fn new(opamp: impl Peripheral<P = T> + 'd, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
+    pub fn new(opamp: Peri<'d, T>, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
-        into_ref!(opamp);
        #[cfg(opamp_g4)]
        T::regs().csr().modify(|w| {
-            w.set_opahsm(speed.into());
+            w.set_opahsm(speed == OpAmpSpeed::HighSpeed);
        });
        Self { _inner: opamp }
@@ -82,35 +88,81 @@ impl<'d, T: Instance> OpAmp<'d, T> {
    /// [`OpAmpOutput`] is dropped.
    pub fn buffer_ext(
        &mut self,
-        in_pin: impl Peripheral<P = impl NonInvertingPin<T> + crate::gpio::Pin>,
+        in_pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
-        out_pin: impl Peripheral<P = impl OutputPin<T> + crate::gpio::Pin>,
+        out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpOutput<'_, T> {
+        in_pin.set_as_analog();
+        out_pin.set_as_analog();
+        #[cfg(opamp_g4)]
+        let vm_sel = VmSel::OUTPUT;
+        #[cfg(not(opamp_g4))]
+        let vm_sel = VmSel::from_bits(0b11);
+        T::regs().csr().modify(|w| {
+            w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
+            w.set_vm_sel(vm_sel);
+            #[cfg(opamp_g4)]
+            w.set_opaintoen(false);
+            w.set_opampen(true);
+        });
+        OpAmpOutput { _inner: self }
+    }
+    /// Configure the OpAmp as a PGA for the provided input pin,
+    /// outputting to the provided output pin, and enable the opamp.
+    ///
+    /// The input pin is configured for analogue mode but not consumed,
+    /// so it may subsequently be used for ADC or comparator inputs.
+    ///
+    /// The output pin is held within the returned [`OpAmpOutput`] struct,
+    /// preventing it being used elsewhere. The `OpAmpOutput` can then be
+    /// directly used as an ADC input. The opamp will be disabled when the
+    /// [`OpAmpOutput`] is dropped.
+    pub fn pga_ext(
+        &mut self,
+        in_pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
+        out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>,
        gain: OpAmpGain,
    ) -> OpAmpOutput<'_, T> {
-        into_ref!(in_pin);
-        into_ref!(out_pin);
        in_pin.set_as_analog();
        out_pin.set_as_analog();
-        // PGA_GAIN value may have different meaning in different MCU serials, use with caution.
+        #[cfg(opamp_g4)]
-        let (vm_sel, pga_gain) = match gain {
+        let vm_sel = VmSel::PGA;
-            OpAmpGain::Mul1 => (0b11, 0b00),
+        #[cfg(not(opamp_g4))]
-            OpAmpGain::Mul2 => (0b10, 0b00),
+        let vm_sel = VmSel::from_bits(0b10);
-            OpAmpGain::Mul4 => (0b10, 0b01),
-            OpAmpGain::Mul8 => (0b10, 0b10),
+        #[cfg(opamp_g4)]
-            OpAmpGain::Mul16 => (0b10, 0b11),
+        let pga_gain = match gain {
+            OpAmpGain::Mul2 => PgaGain::GAIN2,
+            OpAmpGain::Mul4 => PgaGain::GAIN4,
+            OpAmpGain::Mul8 => PgaGain::GAIN8,
+            OpAmpGain::Mul16 => PgaGain::GAIN16,
+            OpAmpGain::Mul32 => PgaGain::GAIN32,
+            OpAmpGain::Mul64 => PgaGain::GAIN64,
        };
+        #[cfg(not(opamp_g4))]
+        let pga_gain = PgaGain::from_bits(match gain {
+            OpAmpGain::Mul2 => 0b00,
+            OpAmpGain::Mul4 => 0b01,
+            OpAmpGain::Mul8 => 0b10,
+            OpAmpGain::Mul16 => 0b11,
+        });
        T::regs().csr().modify(|w| {
            w.set_vp_sel(VpSel::from_bits(in_pin.channel()));
-            w.set_vm_sel(VmSel::from_bits(vm_sel));
+            w.set_vm_sel(vm_sel);
-            w.set_pga_gain(PgaGain::from_bits(pga_gain));
+            w.set_pga_gain(pga_gain);
            #[cfg(opamp_g4)]
-            w.set_opaintoen(Opaintoen::OUTPUTPIN);
+            w.set_opaintoen(false);
            w.set_opampen(true);
        });
        OpAmpOutput { _inner: self }
    }
    /// Configure the OpAmp as a buffer for the DAC it is connected to,
    /// outputting to the provided output pin, and enable the opamp.
    ///
@@ -119,11 +171,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
    /// directly used as an ADC input. The opamp will be disabled when the
    /// [`OpAmpOutput`] is dropped.
    #[cfg(opamp_g4)]
-    pub fn buffer_dac(
+    pub fn buffer_dac(&mut self, out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>) -> OpAmpOutput<'_, T> {
-        &mut self,
-        out_pin: impl Peripheral<P = impl OutputPin<T> + crate::gpio::Pin>,
-    ) -> OpAmpOutput<'_, T> {
-        into_ref!(out_pin);
        out_pin.set_as_analog();
        T::regs().csr().modify(|w| {
@@ -131,7 +179,7 @@ impl<'d, T: Instance> OpAmp<'d, T> {
            w.set_vm_sel(VmSel::OUTPUT);
            w.set_vp_sel(VpSel::DAC3_CH1);
-            w.set_opaintoen(Opaintoen::OUTPUTPIN);
+            w.set_opaintoen(false);
            w.set_opampen(true);
        });
@@ -149,32 +197,259 @@ impl<'d, T: Instance> OpAmp<'d, T> {
    #[cfg(opamp_g4)]
    pub fn buffer_int(
        &mut self,
-        pin: impl Peripheral<P = impl NonInvertingPin<T> + crate::gpio::Pin>,
+        pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpInternalOutput<'_, T> {
+        pin.set_as_analog();
+        T::regs().csr().modify(|w| {
+            w.set_vp_sel(VpSel::from_bits(pin.channel()));
+            w.set_vm_sel(VmSel::OUTPUT);
+            #[cfg(opamp_g4)]
+            w.set_opaintoen(true);
+            w.set_opampen(true);
+        });
+        OpAmpInternalOutput { _inner: self }
+    }
+    /// Configure the OpAmp as a PGA for the provided input pin,
+    /// with the output only used internally, and enable the opamp.
+    ///
+    /// The input pin is configured for analogue mode but not consumed,
+    /// so it may be subsequently used for ADC or comparator inputs.
+    ///
+    /// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
+    /// The opamp output will be disabled when it is dropped.
+    #[cfg(opamp_g4)]
+    pub fn pga_int(
+        &mut self,
+        pin: Peri<'_, impl NonInvertingPin<T> + crate::gpio::Pin>,
        gain: OpAmpGain,
    ) -> OpAmpInternalOutput<'_, T> {
-        into_ref!(pin);
        pin.set_as_analog();
-        // PGA_GAIN value may have different meaning in different MCU serials, use with caution.
+        let pga_gain = match gain {
-        let (vm_sel, pga_gain) = match gain {
+            OpAmpGain::Mul2 => PgaGain::GAIN2,
-            OpAmpGain::Mul1 => (0b11, 0b00),
+            OpAmpGain::Mul4 => PgaGain::GAIN4,
-            OpAmpGain::Mul2 => (0b10, 0b00),
+            OpAmpGain::Mul8 => PgaGain::GAIN8,
-            OpAmpGain::Mul4 => (0b10, 0b01),
+            OpAmpGain::Mul16 => PgaGain::GAIN16,
-            OpAmpGain::Mul8 => (0b10, 0b10),
+            OpAmpGain::Mul32 => PgaGain::GAIN32,
-            OpAmpGain::Mul16 => (0b10, 0b11),
+            OpAmpGain::Mul64 => PgaGain::GAIN64,
        };
        T::regs().csr().modify(|w| {
-            use crate::pac::opamp::vals::*;
            w.set_vp_sel(VpSel::from_bits(pin.channel()));
-            w.set_vm_sel(VmSel::from_bits(vm_sel));
+            w.set_vm_sel(VmSel::PGA);
-            w.set_pga_gain(PgaGain::from_bits(pga_gain));
+            w.set_pga_gain(pga_gain);
-            w.set_opaintoen(Opaintoen::ADCCHANNEL);
+            w.set_opaintoen(true);
+            w.set_opampen(true);
+        });
+        OpAmpInternalOutput { _inner: self }
+    }
+    /// Configure the OpAmp as a standalone DAC with the inverting input
+    /// connected to the provided pin, and the output is connected
+    /// internally to an ADC channel.
+    ///
+    /// The input pin is configured for analogue mode but not consumed,
+    /// so it may be subsequently used for ADC or comparator inputs.
+    ///
+    /// The returned `OpAmpInternalOutput` struct may be used as an ADC
+    /// input. The opamp output will be disabled when it is dropped.
+    #[cfg(opamp_g4)]
+    pub fn standalone_dac_int(
+        &mut self,
+        m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpInternalOutput<'_, T> {
+        m_pin.set_as_analog();
+        T::regs().csr().modify(|w| {
+            use crate::pac::opamp::vals::*;
+            w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
+            w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
+            w.set_opaintoen(true);
            w.set_opampen(true);
        });
        OpAmpInternalOutput { _inner: self }
    }
+    /// Configure the OpAmp as a standalone DAC with the inverting input
+    /// connected to the provided pin, and the output connected to the
+    /// provided pin.
+    ///
+    /// The input pin is configured for analogue mode but not consumed,
+    /// so it may be subsequently used for ADC or comparator inputs.
+    ///
+    /// The output pin is held within the returned [`OpAmpOutput`] struct,
+    /// preventing it being used elsewhere. The opamp will be disabled when
+    /// the [`OpAmpOutput`] is dropped.
+    #[cfg(opamp_g4)]
+    pub fn standalone_dac_ext(
+        &mut self,
+        m_pin: Peri<'_, impl InvertingPin<T> + crate::gpio::Pin>,
+        out_pin: Peri<'_, impl OutputPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpOutput<'_, T> {
+        m_pin.set_as_analog();
+        out_pin.set_as_analog();
+        T::regs().csr().modify(|w| {
+            use crate::pac::opamp::vals::*;
+            w.set_vp_sel(VpSel::DAC3_CH1); // Actually DAC3_CHx
+            w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
+            w.set_opaintoen(false);
+            w.set_opampen(true);
+        });
+        OpAmpOutput { _inner: self }
+    }
+    /// Configure the OpAmp in standalone mode with the non-inverting input
+    /// connected to the provided `p_pin`, the inverting input connected to
+    /// the `m_pin`, and output to the provided `out_pin`.
+    ///
+    /// The input pins are configured for analogue mode but not consumed,
+    /// allowing their subsequent use for ADC or comparator inputs.
+    ///
+    /// The output pin is held within the returned [`OpAmpOutput`] struct,
+    /// preventing it being used elsewhere. The opamp will be disabled when
+    /// the [`OpAmpOutput`] is dropped.
+    #[cfg(opamp_g4)]
+    pub fn standalone_ext(
+        &mut self,
+        p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
+        m_pin: Peri<'d, impl InvertingPin<T> + crate::gpio::Pin>,
+        out_pin: Peri<'d, impl OutputPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpOutput<'_, T> {
+        p_pin.set_as_analog();
+        m_pin.set_as_analog();
+        out_pin.set_as_analog();
+        T::regs().csr().modify(|w| {
+            use crate::pac::opamp::vals::*;
+            w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
+            w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
+            w.set_opaintoen(false);
+            w.set_opampen(true);
+        });
+        OpAmpOutput { _inner: self }
+    }
+    /// Configure the OpAmp in standalone mode with the non-inverting input
+    /// connected to the provided `p_pin`, the inverting input connected to
+    /// the `m_pin`, and output is connected to the DAC.
+    ///
+    /// The input pins are configured for analogue mode but not consumed,
+    /// allowing their subsequent use for ADC or comparator inputs.
+    ///
+    /// The returned `OpAmpOutput` struct may be used as an ADC
+    /// input. The opamp output will be disabled when it is dropped.
+    #[cfg(opamp_g4)]
+    pub fn standalone_int(
+        &mut self,
+        p_pin: Peri<'d, impl NonInvertingPin<T> + crate::gpio::Pin>,
+        m_pin: Peri<'d, impl InvertingPin<T> + crate::gpio::Pin>,
+    ) -> OpAmpOutput<'_, T> {
+        p_pin.set_as_analog();
+        m_pin.set_as_analog();
+        T::regs().csr().modify(|w| {
+            use crate::pac::opamp::vals::*;
+            w.set_vp_sel(VpSel::from_bits(p_pin.channel()));
+            w.set_vm_sel(VmSel::from_bits(m_pin.channel()));
+            w.set_opaintoen(true);
+            w.set_opampen(true);
+        });
+        OpAmpOutput { _inner: self }
+    }
+    /// Calibrates the operational amplifier.
+    ///
+    /// This function enables the opamp and sets the user trim mode for calibration.
+    /// Depending on the speed mode of the opamp, it calibrates the differential pair inputs.
+    /// For normal speed, both the P and N differential pairs are calibrated,
+    /// while for high-speed mode, only the P differential pair is calibrated.
+    ///
+    /// Calibrating a differential pair requires waiting 12ms in the worst case (binary method).
+    #[cfg(opamp_g4)]
+    pub fn calibrate(&mut self) {
+        T::regs().csr().modify(|w| {
+            w.set_opampen(true);
+            w.set_calon(true);
+            w.set_usertrim(true);
+        });
+        if T::regs().csr().read().opahsm() {
+            self.calibrate_differential_pair(OpAmpDifferentialPair::P);
+        } else {
+            self.calibrate_differential_pair(OpAmpDifferentialPair::P);
+            self.calibrate_differential_pair(OpAmpDifferentialPair::N);
+        }
+        T::regs().csr().modify(|w| {
+            w.set_calon(false);
+            w.set_opampen(false);
+        });
+    }
+    /// Calibrate differential pair.
+    ///
+    /// The calibration is done by trying different offset values and
+    /// measuring the outcal bit.
+    ///
+    /// The calibration range is from 0 to 31.
+    ///
+    /// The result is stored in the OPAMP_CSR register.
+    #[cfg(opamp_g4)]
+    fn calibrate_differential_pair(&mut self, pair: OpAmpDifferentialPair) {
+        let mut low = 0;
+        let mut high = 31;
+        let calsel = match pair {
+            OpAmpDifferentialPair::P => Calsel::PERCENT10,
+            OpAmpDifferentialPair::N => Calsel::PERCENT90,
+        };
+        T::regs().csr().modify(|w| {
+            w.set_calsel(calsel);
+        });
+        while low <= high {
+            let mid = (low + high) / 2;
+            T::regs().csr().modify(|w| match pair {
+                OpAmpDifferentialPair::P => {
+                    #[cfg(feature = "defmt")]
+                    defmt::debug!("opamp p calibration. offset: {}", mid);
+                    w.set_trimoffsetp(mid);
+                }
+                OpAmpDifferentialPair::N => {
+                    #[cfg(feature = "defmt")]
+                    defmt::debug!("opamp n calibration. offset: {}", mid);
+                    w.set_trimoffsetn(mid);
+                }
+            });
+            // The closer the trimming value is to the optimum trimming value, the longer it takes to stabilize
+            // (with a maximum stabilization time remaining below 2 ms in any case) -- RM0440 25.3.7
+            blocking_delay_ms(2);
+            if !T::regs().csr().read().calout() {
+                if mid == 0 {
+                    break;
+                }
+                high = mid - 1;
+            } else {
+                if mid == 31 {
+                    break;
+                }
+                low = mid + 1;
+            }
+        }
+    }
 }
 impl<'d, T: Instance> Drop for OpAmpOutput<'d, T> {
@@ -211,7 +486,7 @@ pub(crate) trait SealedOutputPin<T: Instance> {}
 /// Opamp instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + 'static {}
+pub trait Instance: SealedInstance + PeripheralType + 'static {}
 /// Non-inverting pin trait.
 #[allow(private_bounds)]
 pub trait NonInvertingPin<T: Instance>: SealedNonInvertingPin<T> {}
@@ -251,10 +526,12 @@ foreach_peripheral!(
        impl_opamp_external_output!(OPAMP2, ADC2, 3);
    };
    (opamp, OPAMP3) => {
+        impl_opamp_external_output!(OPAMP3, ADC1, 12);
        impl_opamp_external_output!(OPAMP3, ADC3, 1);
    };
    // OPAMP4 only in STM32G4 Cat 3 devices
    (opamp, OPAMP4) => {
+        impl_opamp_external_output!(OPAMP4, ADC1, 11);
        impl_opamp_external_output!(OPAMP4, ADC4, 3);
    };
    // OPAMP5 only in STM32G4 Cat 3 devices
@@ -264,6 +541,7 @@ foreach_peripheral!(
    // OPAMP6 only in STM32G4 Cat 3/4 devices
    (opamp, OPAMP6) => {
        impl_opamp_external_output!(OPAMP6, ADC1, 14);
+        impl_opamp_external_output!(OPAMP6, ADC2, 14);
    };
 );
@@ -345,6 +623,18 @@ macro_rules! impl_opamp_vp_pin {
 }
 #[allow(unused_macros)]
+macro_rules! impl_opamp_vn_pin {
+    ($inst:ident, $pin:ident, $ch:expr) => {
+        impl crate::opamp::InvertingPin<peripherals::$inst> for crate::peripherals::$pin {}
+        impl crate::opamp::SealedInvertingPin<peripherals::$inst> for crate::peripherals::$pin {
+            fn channel(&self) -> u8 {
+                $ch
+            }
+        }
+    };
+}
+#[allow(unused_macros)]
 macro_rules! impl_opamp_vout_pin {
    ($inst:ident, $pin:ident) => {
        impl crate::opamp::OutputPin<peripherals::$inst> for crate::peripherals::$pin {}
diff --git a/embassy-stm32/src/ospi/mod.rs b/embassy-stm32/src/ospi/mod.rs
index 289bfa672..74edfd5e4 100644
--- a/embassy-stm32/src/ospi/mod.rs
+++ b/embassy-stm32/src/ospi/mod.rs
@@ -8,7 +8,7 @@ pub mod enums;
 use core::marker::PhantomData;
 use embassy_embedded_hal::{GetConfig, SetConfig};
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 pub use enums::*;
 use stm32_metapac::octospi::vals::{PhaseMode, SizeInBits};
@@ -16,8 +16,10 @@ use crate::dma::{word, ChannelAndRequest};
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::octospi::{vals, Octospi as Regs};
+#[cfg(octospim_v1)]
+use crate::pac::octospim::Octospim;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 /// OPSI driver config.
 #[derive(Clone, Copy)]
@@ -50,7 +52,7 @@ pub struct Config {
    /// Enables the transaction boundary feature and defines the boundary to release
    /// the chip select
    pub chip_select_boundary: u8,
-    /// Enbales the delay block bypass so the sampling is not affected by the delay block
+    /// Enables the delay block bypass so the sampling is not affected by the delay block
    pub delay_block_bypass: bool,
    /// Enables communication regulation feature. Chip select is released when the other
    /// OctoSpi requests access to the bus
@@ -158,18 +160,18 @@ pub enum OspiError {
 /// OSPI driver.
 pub struct Ospi<'d, T: Instance, M: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
-    d0: Option<PeripheralRef<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
-    d4: Option<PeripheralRef<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
-    d5: Option<PeripheralRef<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
-    d6: Option<PeripheralRef<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
-    d7: Option<PeripheralRef<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
-    nss: Option<PeripheralRef<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
-    dqs: Option<PeripheralRef<'d, AnyPin>>,
+    dqs: Option<Peri<'d, AnyPin>>,
    dma: Option<ChannelAndRequest<'d>>,
    _phantom: PhantomData<M>,
    config: Config,
@@ -177,25 +179,165 @@ pub struct Ospi<'d, T: Instance, M: PeriMode> {
 }
 impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
+    /// Enter memory mode.
+    /// The Input `read_config` is used to configure the read operation in memory mode
+    pub fn enable_memory_mapped_mode(
+        &mut self,
+        read_config: TransferConfig,
+        write_config: TransferConfig,
+    ) -> Result<(), OspiError> {
+        // Use configure command to set read config
+        self.configure_command(&read_config, None)?;
+        let reg = T::REGS;
+        while reg.sr().read().busy() {}
+        reg.ccr().modify(|r| {
+            r.set_dqse(false);
+            r.set_sioo(true);
+        });
+        // Set wrting configurations, there are separate registers for write configurations in memory mapped mode
+        reg.wccr().modify(|w| {
+            w.set_imode(PhaseMode::from_bits(write_config.iwidth.into()));
+            w.set_idtr(write_config.idtr);
+            w.set_isize(SizeInBits::from_bits(write_config.isize.into()));
+            w.set_admode(PhaseMode::from_bits(write_config.adwidth.into()));
+            w.set_addtr(write_config.idtr);
+            w.set_adsize(SizeInBits::from_bits(write_config.adsize.into()));
+            w.set_dmode(PhaseMode::from_bits(write_config.dwidth.into()));
+            w.set_ddtr(write_config.ddtr);
+            w.set_abmode(PhaseMode::from_bits(write_config.abwidth.into()));
+            w.set_dqse(true);
+        });
+        reg.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
+        // Enable memory mapped mode
+        reg.cr().modify(|r| {
+            r.set_fmode(crate::ospi::vals::FunctionalMode::MEMORY_MAPPED);
+            r.set_tcen(false);
+        });
+        Ok(())
+    }
+    /// Quit from memory mapped mode
+    pub fn disable_memory_mapped_mode(&mut self) {
+        let reg = T::REGS;
+        reg.cr().modify(|r| {
+            r.set_fmode(crate::ospi::vals::FunctionalMode::INDIRECT_WRITE);
+            r.set_abort(true);
+            r.set_dmaen(false);
+            r.set_en(false);
+        });
+        // Clear transfer complete flag
+        reg.fcr().write(|w| w.set_ctcf(true));
+        // Re-enable ospi
+        reg.cr().modify(|r| {
+            r.set_en(true);
+        });
+    }
    fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: Option<PeripheralRef<'d, AnyPin>>,
+        d0: Option<Peri<'d, AnyPin>>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
-        d4: Option<PeripheralRef<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
-        d5: Option<PeripheralRef<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
-        d6: Option<PeripheralRef<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
-        d7: Option<PeripheralRef<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
-        nss: Option<PeripheralRef<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
-        dqs: Option<PeripheralRef<'d, AnyPin>>,
+        dqs: Option<Peri<'d, AnyPin>>,
        dma: Option<ChannelAndRequest<'d>>,
        config: Config,
        width: OspiWidth,
        dual_quad: bool,
    ) -> Self {
-        into_ref!(peri);
+        #[cfg(octospim_v1)]
+        {
+            // RCC for octospim should be enabled before writing register
+            #[cfg(stm32l4)]
+            crate::pac::RCC.ahb2smenr().modify(|w| w.set_octospimsmen(true));
+            #[cfg(stm32u5)]
+            crate::pac::RCC.ahb2enr1().modify(|w| w.set_octospimen(true));
+            #[cfg(not(any(stm32l4, stm32u5)))]
+            crate::pac::RCC.ahb3enr().modify(|w| w.set_iomngren(true));
+            // Disable OctoSPI peripheral first
+            T::REGS.cr().modify(|w| {
+                w.set_en(false);
+            });
+            // OctoSPI IO Manager has been enabled before
+            T::OCTOSPIM_REGS.cr().modify(|w| {
+                w.set_muxen(false);
+                w.set_req2ack_time(0xff);
+            });
+            // Clear config
+            T::OCTOSPIM_REGS.p1cr().modify(|w| {
+                w.set_clksrc(false);
+                w.set_dqssrc(false);
+                w.set_ncssrc(false);
+                w.set_clken(false);
+                w.set_dqsen(false);
+                w.set_ncsen(false);
+                w.set_iolsrc(0);
+                w.set_iohsrc(0);
+            });
+            T::OCTOSPIM_REGS.p1cr().modify(|w| {
+                let octospi_src = if T::OCTOSPI_IDX == 1 { false } else { true };
+                w.set_ncsen(true);
+                w.set_ncssrc(octospi_src);
+                w.set_clken(true);
+                w.set_clksrc(octospi_src);
+                if dqs.is_some() {
+                    w.set_dqsen(true);
+                    w.set_dqssrc(octospi_src);
+                }
+                // Set OCTOSPIM IOL and IOH according to the index of OCTOSPI instance
+                if T::OCTOSPI_IDX == 1 {
+                    w.set_iolen(true);
+                    w.set_iolsrc(0);
+                    // Enable IOH in octo and dual quad mode
+                    if let OspiWidth::OCTO = width {
+                        w.set_iohen(true);
+                        w.set_iohsrc(0b01);
+                    } else if dual_quad {
+                        w.set_iohen(true);
+                        w.set_iohsrc(0b00);
+                    } else {
+                        w.set_iohen(false);
+                        w.set_iohsrc(0b00);
+                    }
+                } else {
+                    w.set_iolen(true);
+                    w.set_iolsrc(0b10);
+                    // Enable IOH in octo and dual quad mode
+                    if let OspiWidth::OCTO = width {
+                        w.set_iohen(true);
+                        w.set_iohsrc(0b11);
+                    } else if dual_quad {
+                        w.set_iohen(true);
+                        w.set_iohsrc(0b10);
+                    } else {
+                        w.set_iohen(false);
+                        w.set_iohsrc(0b00);
+                    }
+                }
+            });
+        }
        // System configuration
        rcc::enable_and_reset::<T>();
@@ -228,7 +370,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        });
        T::REGS.cr().modify(|w| {
-            w.set_fthres(vals::Threshold(config.fifo_threshold.into()));
+            w.set_fthres(vals::Threshold::from_bits(config.fifo_threshold.into()));
        });
        // Wait for busy flag to clear
@@ -244,7 +386,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        T::REGS.tcr().modify(|w| {
            w.set_sshift(match config.sample_shifting {
-                true => vals::SampleShift::HALFCYCLE,
+                true => vals::SampleShift::HALF_CYCLE,
                false => vals::SampleShift::NONE,
            });
            w.set_dhqc(config.delay_hold_quarter_cycle);
@@ -376,7 +518,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
    }
    /// Function used to control or configure the target device without data transfer
-    pub async fn command(&mut self, command: &TransferConfig) -> Result<(), OspiError> {
+    pub fn blocking_command(&mut self, command: &TransferConfig) -> Result<(), OspiError> {
        // Wait for peripheral to be free
        while T::REGS.sr().read().busy() {}
@@ -412,7 +554,9 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        let current_instruction = T::REGS.ir().read().instruction();
        // For a indirect read transaction, the transaction begins when the instruction/address is set
-        T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD));
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
        if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
        } else {
@@ -447,7 +591,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        T::REGS
            .cr()
-            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE));
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
        for idx in 0..buf.len() {
            while !T::REGS.sr().read().ftf() {}
@@ -497,7 +641,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        });
        T::REGS.cr().modify(|w| {
-            w.set_fthres(vals::Threshold(config.fifo_threshold.into()));
+            w.set_fthres(vals::Threshold::from_bits(config.fifo_threshold.into()));
        });
        // Wait for busy flag to clear
@@ -509,7 +653,7 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
        T::REGS.tcr().modify(|w| {
            w.set_sshift(match config.sample_shifting {
-                true => vals::SampleShift::HALFCYCLE,
+                true => vals::SampleShift::HALF_CYCLE,
                false => vals::SampleShift::NONE,
            });
            w.set_dhqc(config.delay_hold_quarter_cycle);
@@ -539,11 +683,11 @@ impl<'d, T: Instance, M: PeriMode> Ospi<'d, T, M> {
 impl<'d, T: Instance> Ospi<'d, T, Blocking> {
    /// Create new blocking OSPI driver for a single spi external chip
    pub fn new_blocking_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -571,11 +715,11 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
    /// Create new blocking OSPI driver for a dualspi external chip
    pub fn new_blocking_dualspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -603,13 +747,13 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
    /// Create new blocking OSPI driver for a quadspi external chip
    pub fn new_blocking_quadspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -637,17 +781,17 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
    /// Create new blocking OSPI driver for two quadspi external chips
    pub fn new_blocking_dualquadspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -675,17 +819,17 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
    /// Create new blocking OSPI driver for octospi external chips
    pub fn new_blocking_octospi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -715,12 +859,12 @@ impl<'d, T: Instance> Ospi<'d, T, Blocking> {
 impl<'d, T: Instance> Ospi<'d, T, Async> {
    /// Create new blocking OSPI driver for a single spi external chip
    pub fn new_singlespi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        dma: Peri<'d, impl OctoDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -748,12 +892,12 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
    /// Create new blocking OSPI driver for a dualspi external chip
    pub fn new_dualspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        dma: Peri<'d, impl OctoDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -781,14 +925,14 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
    /// Create new blocking OSPI driver for a quadspi external chip
    pub fn new_quadspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        dma: Peri<'d, impl OctoDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -816,18 +960,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
    /// Create new blocking OSPI driver for two quadspi external chips
    pub fn new_dualquadspi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        dma: Peri<'d, impl OctoDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -855,18 +999,18 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
    /// Create new blocking OSPI driver for octospi external chips
    pub fn new_octospi(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
-        d4: impl Peripheral<P = impl D4Pin<T>> + 'd,
+        d4: Peri<'d, impl D4Pin<T>>,
-        d5: impl Peripheral<P = impl D5Pin<T>> + 'd,
+        d5: Peri<'d, impl D5Pin<T>>,
-        d6: impl Peripheral<P = impl D6Pin<T>> + 'd,
+        d6: Peri<'d, impl D6Pin<T>>,
-        d7: impl Peripheral<P = impl D7Pin<T>> + 'd,
+        d7: Peri<'d, impl D7Pin<T>>,
-        nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
+        nss: Peri<'d, impl NSSPin<T>>,
-        dma: impl Peripheral<P = impl OctoDma<T>> + 'd,
+        dma: Peri<'d, impl OctoDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -907,7 +1051,9 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
        let current_instruction = T::REGS.ir().read().instruction();
        // For a indirect read transaction, the transaction begins when the instruction/address is set
-        T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD));
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
        if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
        } else {
@@ -942,7 +1088,7 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
        self.configure_command(&transaction, Some(buf.len()))?;
        T::REGS
            .cr()
-            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE));
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
        let transfer = unsafe {
            self.dma
@@ -975,7 +1121,9 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
        let current_instruction = T::REGS.ir().read().instruction();
        // For a indirect read transaction, the transaction begins when the instruction/address is set
-        T::REGS.cr().modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTREAD));
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_READ));
        if T::REGS.ccr().read().admode() == vals::PhaseMode::NONE {
            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
        } else {
@@ -1010,7 +1158,7 @@ impl<'d, T: Instance> Ospi<'d, T, Async> {
        self.configure_command(&transaction, Some(buf.len()))?;
        T::REGS
            .cr()
-            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECTWRITE));
+            .modify(|v| v.set_fmode(vals::FunctionalMode::INDIRECT_WRITE));
        let transfer = unsafe {
            self.dma
@@ -1056,13 +1204,27 @@ fn finish_dma(regs: Regs) {
    });
 }
+#[cfg(octospim_v1)]
+/// OctoSPI I/O manager instance trait.
+pub(crate) trait SealedOctospimInstance {
+    const OCTOSPIM_REGS: Octospim;
+    const OCTOSPI_IDX: u8;
+}
+/// OctoSPI instance trait.
 pub(crate) trait SealedInstance {
    const REGS: Regs;
 }
 /// OSPI instance trait.
+#[cfg(octospim_v1)]
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + SealedOctospimInstance {}
+/// OSPI instance trait.
+#[cfg(not(octospim_v1))]
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 pin_trait!(SckPin, Instance);
 pin_trait!(NckPin, Instance);
@@ -1078,6 +1240,31 @@ pin_trait!(DQSPin, Instance);
 pin_trait!(NSSPin, Instance);
 dma_trait!(OctoDma, Instance);
+// Hard-coded the octospi index, for OCTOSPIM
+#[cfg(octospim_v1)]
+impl SealedOctospimInstance for peripherals::OCTOSPI1 {
+    const OCTOSPIM_REGS: Octospim = crate::pac::OCTOSPIM;
+    const OCTOSPI_IDX: u8 = 1;
+}
+#[cfg(all(octospim_v1, peri_octospi2))]
+impl SealedOctospimInstance for peripherals::OCTOSPI2 {
+    const OCTOSPIM_REGS: Octospim = crate::pac::OCTOSPIM;
+    const OCTOSPI_IDX: u8 = 2;
+}
+#[cfg(octospim_v1)]
+foreach_peripheral!(
+    (octospi, $inst:ident) => {
+        impl SealedInstance for peripherals::$inst {
+            const REGS: Regs = crate::pac::$inst;
+        }
+        impl Instance for peripherals::$inst {}
+    };
+);
+#[cfg(not(octospim_v1))]
 foreach_peripheral!(
    (octospi, $inst:ident) => {
        impl SealedInstance for peripherals::$inst {
diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index ecade9b1a..9ec4c1b43 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -9,9 +9,9 @@ pub(crate) enum QspiMode {
    MemoryMapped,
 }
-impl Into<u8> for QspiMode {
+impl From<QspiMode> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: QspiMode) -> Self {
-        match self {
+        match val {
            QspiMode::IndirectWrite => 0b00,
            QspiMode::IndirectRead => 0b01,
            QspiMode::AutoPolling => 0b10,
@@ -34,9 +34,9 @@ pub enum QspiWidth {
    QUAD,
 }
-impl Into<u8> for QspiWidth {
+impl From<QspiWidth> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: QspiWidth) -> Self {
-        match self {
+        match val {
            QspiWidth::NONE => 0b00,
            QspiWidth::SING => 0b01,
            QspiWidth::DUAL => 0b10,
@@ -55,9 +55,9 @@ pub enum FlashSelection {
    Flash2,
 }
-impl Into<bool> for FlashSelection {
+impl From<FlashSelection> for bool {
-    fn into(self) -> bool {
+    fn from(val: FlashSelection) -> Self {
-        match self {
+        match val {
            FlashSelection::Flash1 => false,
            FlashSelection::Flash2 => true,
        }
@@ -94,9 +94,9 @@ pub enum MemorySize {
    Other(u8),
 }
-impl Into<u8> for MemorySize {
+impl From<MemorySize> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: MemorySize) -> Self {
-        match self {
+        match val {
            MemorySize::_1KiB => 9,
            MemorySize::_2KiB => 10,
            MemorySize::_4KiB => 11,
@@ -138,9 +138,9 @@ pub enum AddressSize {
    _32bit,
 }
-impl Into<u8> for AddressSize {
+impl From<AddressSize> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: AddressSize) -> Self {
-        match self {
+        match val {
            AddressSize::_8Bit => 0b00,
            AddressSize::_16Bit => 0b01,
            AddressSize::_24bit => 0b10,
@@ -163,9 +163,9 @@ pub enum ChipSelectHighTime {
    _8Cycle,
 }
-impl Into<u8> for ChipSelectHighTime {
+impl From<ChipSelectHighTime> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: ChipSelectHighTime) -> Self {
-        match self {
+        match val {
            ChipSelectHighTime::_1Cycle => 0,
            ChipSelectHighTime::_2Cycle => 1,
            ChipSelectHighTime::_3Cycle => 2,
@@ -216,9 +216,9 @@ pub enum FIFOThresholdLevel {
    _32Bytes,
 }
-impl Into<u8> for FIFOThresholdLevel {
+impl From<FIFOThresholdLevel> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: FIFOThresholdLevel) -> Self {
-        match self {
+        match val {
            FIFOThresholdLevel::_1Bytes => 0,
            FIFOThresholdLevel::_2Bytes => 1,
            FIFOThresholdLevel::_3Bytes => 2,
@@ -293,9 +293,9 @@ pub enum DummyCycles {
    _31,
 }
-impl Into<u8> for DummyCycles {
+impl From<DummyCycles> for u8 {
-    fn into(self) -> u8 {
+    fn from(val: DummyCycles) -> Self {
-        match self {
+        match val {
            DummyCycles::_0 => 0,
            DummyCycles::_1 => 1,
            DummyCycles::_2 => 2,
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 308947e99..0df057c53 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -6,7 +6,7 @@ pub mod enums;
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use enums::*;
 use crate::dma::ChannelAndRequest;
@@ -14,11 +14,11 @@ use crate::gpio::{AfType, AnyPin, OutputType, Pull, Speed};
 use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::quadspi::Quadspi as Regs;
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 /// QSPI transfer configuration.
 pub struct TransferConfig {
-    /// Instraction width (IMODE)
+    /// Instruction width (IMODE)
    pub iwidth: QspiWidth,
    /// Address width (ADMODE)
    pub awidth: QspiWidth,
@@ -75,13 +75,13 @@ impl Default for Config {
 /// QSPI driver.
 #[allow(dead_code)]
 pub struct Qspi<'d, T: Instance, M: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
-    d0: Option<PeripheralRef<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
-    nss: Option<PeripheralRef<'d, AnyPin>>,
+    nss: Option<Peri<'d, AnyPin>>,
    dma: Option<ChannelAndRequest<'d>>,
    _phantom: PhantomData<M>,
    config: Config,
@@ -89,19 +89,17 @@ pub struct Qspi<'d, T: Instance, M: PeriMode> {
 impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
    fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: Option<PeripheralRef<'d, AnyPin>>,
+        d0: Option<Peri<'d, AnyPin>>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
-        nss: Option<PeripheralRef<'d, AnyPin>>,
+        nss: Option<Peri<'d, AnyPin>>,
        dma: Option<ChannelAndRequest<'d>>,
        config: Config,
        fsel: FlashSelection,
    ) -> Self {
-        into_ref!(peri);
        rcc::enable_and_reset::<T>();
        while T::REGS.sr().read().busy() {}
@@ -148,7 +146,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
    }
    /// Do a QSPI command.
-    pub fn command(&mut self, transaction: TransferConfig) {
+    pub fn blocking_command(&mut self, transaction: TransferConfig) {
        #[cfg(not(stm32h7))]
        T::REGS.cr().modify(|v| v.set_dmaen(false));
        self.setup_transaction(QspiMode::IndirectWrite, &transaction, None);
@@ -172,7 +170,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
        });
        for b in buf {
-            while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
+            while !T::REGS.sr().read().tcf() && (T::REGS.sr().read().flevel() == 0) {}
            *b = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() };
        }
@@ -201,7 +199,42 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
        T::REGS.fcr().modify(|v| v.set_ctcf(true));
    }
+    /// Enable memory map mode
+    pub fn enable_memory_map(&mut self, transaction: &TransferConfig) {
+        T::REGS.fcr().modify(|v| {
+            v.set_csmf(true);
+            v.set_ctcf(true);
+            v.set_ctef(true);
+            v.set_ctof(true);
+        });
+        T::REGS.ccr().write(|v| {
+            v.set_fmode(QspiMode::MemoryMapped.into());
+            v.set_imode(transaction.iwidth.into());
+            v.set_instruction(transaction.instruction);
+            v.set_admode(transaction.awidth.into());
+            v.set_adsize(self.config.address_size.into());
+            v.set_dmode(transaction.dwidth.into());
+            v.set_abmode(QspiWidth::NONE.into());
+            v.set_dcyc(transaction.dummy.into());
+        });
+    }
    fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig, data_len: Option<usize>) {
+        match (transaction.address, transaction.awidth) {
+            (Some(_), QspiWidth::NONE) => panic!("QSPI address can't be sent with an address width of NONE"),
+            (Some(_), _) => {}
+            (None, QspiWidth::NONE) => {}
+            (None, _) => panic!("QSPI address is not set, so the address width should be NONE"),
+        }
+        match (data_len, transaction.dwidth) {
+            (Some(0), _) => panic!("QSPI data must be at least one byte"),
+            (Some(_), QspiWidth::NONE) => panic!("QSPI data can't be sent with a data width of NONE"),
+            (Some(_), _) => {}
+            (None, QspiWidth::NONE) => {}
+            (None, _) => panic!("QSPI data is empty, so the data width should be NONE"),
+        }
        T::REGS.fcr().modify(|v| {
            v.set_csmf(true);
            v.set_ctcf(true);
@@ -237,13 +270,13 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
 impl<'d, T: Instance> Qspi<'d, T, Blocking> {
    /// Create a new QSPI driver for bank 1, in blocking mode.
    pub fn new_blocking_bank1(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
+        d0: Peri<'d, impl BK1D0Pin<T>>,
-        d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
+        d1: Peri<'d, impl BK1D1Pin<T>>,
-        d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
+        d2: Peri<'d, impl BK1D2Pin<T>>,
-        d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
+        d3: Peri<'d, impl BK1D3Pin<T>>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
+        nss: Peri<'d, impl BK1NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -265,13 +298,13 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
    /// Create a new QSPI driver for bank 2, in blocking mode.
    pub fn new_blocking_bank2(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
+        d0: Peri<'d, impl BK2D0Pin<T>>,
-        d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
+        d1: Peri<'d, impl BK2D1Pin<T>>,
-        d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
+        d2: Peri<'d, impl BK2D2Pin<T>>,
-        d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
+        d3: Peri<'d, impl BK2D3Pin<T>>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
+        nss: Peri<'d, impl BK2NSSPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -295,14 +328,14 @@ impl<'d, T: Instance> Qspi<'d, T, Blocking> {
 impl<'d, T: Instance> Qspi<'d, T, Async> {
    /// Create a new QSPI driver for bank 1.
    pub fn new_bank1(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: impl Peripheral<P = impl BK1D0Pin<T>> + 'd,
+        d0: Peri<'d, impl BK1D0Pin<T>>,
-        d1: impl Peripheral<P = impl BK1D1Pin<T>> + 'd,
+        d1: Peri<'d, impl BK1D1Pin<T>>,
-        d2: impl Peripheral<P = impl BK1D2Pin<T>> + 'd,
+        d2: Peri<'d, impl BK1D2Pin<T>>,
-        d3: impl Peripheral<P = impl BK1D3Pin<T>> + 'd,
+        d3: Peri<'d, impl BK1D3Pin<T>>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        nss: impl Peripheral<P = impl BK1NSSPin<T>> + 'd,
+        nss: Peri<'d, impl BK1NSSPin<T>>,
-        dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
+        dma: Peri<'d, impl QuadDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -324,14 +357,14 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
    /// Create a new QSPI driver for bank 2.
    pub fn new_bank2(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        d0: impl Peripheral<P = impl BK2D0Pin<T>> + 'd,
+        d0: Peri<'d, impl BK2D0Pin<T>>,
-        d1: impl Peripheral<P = impl BK2D1Pin<T>> + 'd,
+        d1: Peri<'d, impl BK2D1Pin<T>>,
-        d2: impl Peripheral<P = impl BK2D2Pin<T>> + 'd,
+        d2: Peri<'d, impl BK2D2Pin<T>>,
-        d3: impl Peripheral<P = impl BK2D3Pin<T>> + 'd,
+        d3: Peri<'d, impl BK2D3Pin<T>>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        nss: impl Peripheral<P = impl BK2NSSPin<T>> + 'd,
+        nss: Peri<'d, impl BK2NSSPin<T>>,
-        dma: impl Peripheral<P = impl QuadDma<T>> + 'd,
+        dma: Peri<'d, impl QuadDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -353,6 +386,21 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
    /// Blocking read data, using DMA.
    pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
+        let transfer = self.start_read_transfer(transaction, buf);
+        transfer.blocking_wait();
+    }
+    /// Async read data, using DMA.
+    pub async fn read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig) {
+        let transfer = self.start_read_transfer(transaction, buf);
+        transfer.await;
+    }
+    fn start_read_transfer<'a>(
+        &'a mut self,
+        transaction: TransferConfig,
+        buf: &'a mut [u8],
+    ) -> crate::dma::Transfer<'a> {
        self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
        T::REGS.ccr().modify(|v| {
@@ -373,12 +421,22 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
        // STM32H7 does not have dmaen
        #[cfg(not(stm32h7))]
        T::REGS.cr().modify(|v| v.set_dmaen(true));
+        transfer
-        transfer.blocking_wait();
    }
    /// Blocking write data, using DMA.
    pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
+        let transfer = self.start_write_transfer(transaction, buf);
+        transfer.blocking_wait();
+    }
+    /// Async write data, using DMA.
+    pub async fn write_dma(&mut self, buf: &[u8], transaction: TransferConfig) {
+        let transfer = self.start_write_transfer(transaction, buf);
+        transfer.await;
+    }
+    fn start_write_transfer<'a>(&'a mut self, transaction: TransferConfig, buf: &'a [u8]) -> crate::dma::Transfer<'a> {
        self.setup_transaction(QspiMode::IndirectWrite, &transaction, Some(buf.len()));
        T::REGS.ccr().modify(|v| {
@@ -395,8 +453,7 @@ impl<'d, T: Instance> Qspi<'d, T, Async> {
        // STM32H7 does not have dmaen
        #[cfg(not(stm32h7))]
        T::REGS.cr().modify(|v| v.set_dmaen(true));
+        transfer
-        transfer.blocking_wait();
    }
 }
@@ -406,7 +463,7 @@ trait SealedInstance {
 /// QSPI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 pin_trait!(SckPin, Instance);
 pin_trait!(BK1D0Pin, Instance);
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 4e9c18594..e2c704405 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -16,9 +16,13 @@ pub enum LseMode {
    Bypass,
 }
+#[derive(Clone, Copy)]
 pub struct LseConfig {
    pub frequency: Hertz,
    pub mode: LseMode,
+    /// If peripherals other than RTC/TAMP or RCC functions need the lse this bit must be set
+    #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
+    pub peripherals_clocked: bool,
 }
 #[allow(dead_code)]
@@ -41,8 +45,8 @@ impl From<LseDrive> for crate::pac::rcc::vals::Lsedrv {
        match value {
            #[cfg(not(stm32h5))] // ES0565: LSE Low drive mode is not functional
            LseDrive::Low => Lsedrv::LOW,
-            LseDrive::MediumLow => Lsedrv::MEDIUMLOW,
+            LseDrive::MediumLow => Lsedrv::MEDIUM_LOW,
-            LseDrive::MediumHigh => Lsedrv::MEDIUMHIGH,
+            LseDrive::MediumHigh => Lsedrv::MEDIUM_HIGH,
            LseDrive::High => Lsedrv::HIGH,
        }
    }
@@ -80,6 +84,7 @@ fn bdcr() -> Reg<Bdcr, RW> {
    return crate::pac::RCC.csr1();
 }
+#[derive(Clone, Copy)]
 pub struct LsConfig {
    pub rtc: RtcClockSource,
    pub lsi: bool,
@@ -87,12 +92,25 @@ pub struct LsConfig {
 }
 impl LsConfig {
+    /// Creates an [`LsConfig`] using the LSI when possible.
+    pub const fn new() -> Self {
+        // on L5, just the fact that LSI is enabled makes things crash.
+        // TODO: investigate.
+        #[cfg(not(stm32l5))]
+        return Self::default_lsi();
+        #[cfg(stm32l5)]
+        return Self::off();
+    }
    pub const fn default_lse() -> Self {
        Self {
            rtc: RtcClockSource::LSE,
            lse: Some(LseConfig {
                frequency: Hertz(32_768),
                mode: LseMode::Oscillator(LseDrive::MediumHigh),
+                #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
+                peripherals_clocked: false,
            }),
            lsi: false,
        }
@@ -117,13 +135,7 @@ impl LsConfig {
 impl Default for LsConfig {
    fn default() -> Self {
-        // on L5, just the fact that LSI is enabled makes things crash.
+        Self::new()
-        // TODO: investigate.
-        #[cfg(not(stm32l5))]
-        return Self::default_lsi();
-        #[cfg(stm32l5)]
-        return Self::off();
    }
 }
@@ -146,6 +158,15 @@ impl LsConfig {
            },
            None => (false, false, None),
        };
+        #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba))]
+        let lse_sysen = if let Some(lse) = self.lse {
+            Some(lse.peripherals_clocked)
+        } else {
+            None
+        };
+        #[cfg(rcc_u0)]
+        let lse_sysen = Some(lse_en);
        _ = lse_drv; // not all chips have it.
        // Disable backup domain write protection
@@ -186,6 +207,10 @@ impl LsConfig {
        }
        ok &= reg.lseon() == lse_en;
        ok &= reg.lsebyp() == lse_byp;
+        #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
+        if let Some(lse_sysen) = lse_sysen {
+            ok &= reg.lsesysen() == lse_sysen;
+        }
        #[cfg(not(any(rcc_f1, rcc_f1cl, rcc_f100, rcc_f2, rcc_f4, rcc_f410, rcc_l1)))]
        if let Some(lse_drv) = lse_drv {
            ok &= reg.lsedrv() == lse_drv.into();
@@ -233,6 +258,17 @@ impl LsConfig {
            });
            while !bdcr().read().lserdy() {}
+            #[cfg(any(rcc_l5, rcc_u5, rcc_wle, rcc_wl5, rcc_wba, rcc_u0))]
+            if let Some(lse_sysen) = lse_sysen {
+                bdcr().modify(|w| {
+                    w.set_lsesysen(lse_sysen);
+                });
+                if lse_sysen {
+                    while !bdcr().read().lsesysrdy() {}
+                }
+            }
        }
        if self.rtc != RtcClockSource::DISABLE {
diff --git a/embassy-stm32/src/rcc/c0.rs b/embassy-stm32/src/rcc/c0.rs
index 5adf37941..cac2a9149 100644
--- a/embassy-stm32/src/rcc/c0.rs
+++ b/embassy-stm32/src/rcc/c0.rs
@@ -3,6 +3,7 @@ pub use crate::pac::rcc::vals::{
    Hpre as AHBPrescaler, Hsidiv as HsiSysDiv, Hsikerdiv as HsiKerDiv, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::{FLASH, RCC};
+use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 /// HSI speed
@@ -37,6 +38,7 @@ pub struct Hsi {
 /// Clocks configutation
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    /// HSI Configuration
    pub hsi: Option<Hsi>,
@@ -57,9 +59,8 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    #[inline]
+    pub const fn new() -> Self {
-    fn default() -> Config {
        Config {
            hsi: Some(Hsi {
                sys_div: HsiSysDiv::DIV4,
@@ -69,12 +70,18 @@ impl Default for Config {
            sys: Sysclk::HSISYS,
            ahb_pre: AHBPrescaler::DIV1,
            apb1_pre: APBPrescaler::DIV1,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Config {
+        Self::new()
+    }
+}
 pub(crate) unsafe fn init(config: Config) {
    // Turn on the HSI
    match config.hsi {
@@ -109,8 +116,8 @@ pub(crate) unsafe fn init(config: Config) {
        }
        Some(hse) => {
            match hse.mode {
-                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
-                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+                HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
            }
            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -120,20 +127,27 @@ pub(crate) unsafe fn init(config: Config) {
        }
    };
+    let rtc = config.ls.init();
    let sys = match config.sys {
        Sysclk::HSISYS => unwrap!(hsisys),
        Sysclk::HSE => unwrap!(hse),
+        Sysclk::LSI => {
+            assert!(config.ls.lsi);
+            LSI_FREQ
+        }
+        Sysclk::LSE => unwrap!(config.ls.lse).frequency,
        _ => unreachable!(),
    };
-    assert!(max::SYSCLK.contains(&sys));
+    rcc_assert!(max::SYSCLK.contains(&sys));
    // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
    let hclk = sys / config.ahb_pre;
-    assert!(max::HCLK.contains(&hclk));
+    rcc_assert!(max::HCLK.contains(&hclk));
    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
-    assert!(max::PCLK.contains(&pclk1));
+    rcc_assert!(max::PCLK.contains(&pclk1));
    let latency = match hclk.0 {
        ..=24_000_000 => Latency::WS0,
@@ -161,8 +175,6 @@ pub(crate) unsafe fn init(config: Config) {
        RCC.cr().modify(|w| w.set_hsion(false));
    }
-    let rtc = config.ls.init();
    config.mux.init();
    set_clocks!(
@@ -179,6 +191,9 @@ pub(crate) unsafe fn init(config: Config) {
        lsi: None,
        lse: None,
    );
+    RCC.ccipr()
+        .modify(|w| w.set_adc1sel(stm32_metapac::rcc::vals::Adcsel::SYS));
 }
 mod max {
diff --git a/embassy-stm32/src/rcc/f013.rs b/embassy-stm32/src/rcc/f013.rs
index 63dc27bdd..1155b6acd 100644
--- a/embassy-stm32/src/rcc/f013.rs
+++ b/embassy-stm32/src/rcc/f013.rs
@@ -4,11 +4,13 @@ pub use crate::pac::rcc::vals::Adcpre as ADCPrescaler;
 #[cfg(stm32f3)]
 pub use crate::pac::rcc::vals::Adcpres as AdcPllPrescaler;
 use crate::pac::rcc::vals::Pllsrc;
-#[cfg(stm32f1)]
+#[cfg(all(stm32f1, not(stm32f107)))]
 pub use crate::pac::rcc::vals::Pllxtpre as PllPreDiv;
 #[cfg(any(stm32f0, stm32f3))]
 pub use crate::pac::rcc::vals::Prediv as PllPreDiv;
 pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Pllmul as PllMul, Ppre as APBPrescaler, Sw as Sysclk};
+#[cfg(stm32f107)]
+pub use crate::pac::rcc::vals::{I2s2src, Pll2mul as Pll2Mul, Prediv1 as PllPreDiv, Prediv1src, Usbpre as UsbPre};
 use crate::pac::{FLASH, RCC};
 use crate::time::Hertz;
@@ -37,6 +39,8 @@ pub enum PllSource {
    HSI,
    #[cfg(rcc_f0v4)]
    HSI48,
+    #[cfg(stm32f107)]
+    PLL2,
 }
 #[derive(Clone, Copy)]
@@ -52,6 +56,12 @@ pub struct Pll {
    pub mul: PllMul,
 }
+#[cfg(stm32f107)]
+#[derive(Clone, Copy)]
+pub struct Pll2Or3 {
+    pub mul: Pll2Mul,
+}
 #[cfg(all(stm32f3, not(rcc_f37)))]
 #[derive(Clone, Copy)]
 pub enum AdcClockSource {
@@ -76,6 +86,7 @@ pub enum HrtimClockSource {
 /// Clocks configutation
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    pub hsi: bool,
    pub hse: Option<Hse>,
@@ -84,6 +95,12 @@ pub struct Config {
    pub sys: Sysclk,
    pub pll: Option<Pll>,
+    #[cfg(stm32f107)]
+    pub pll2: Option<Pll2Or3>,
+    #[cfg(stm32f107)]
+    pub pll3: Option<Pll2Or3>,
+    #[cfg(stm32f107)]
+    pub prediv2: PllPreDiv,
    pub ahb_pre: AHBPrescaler,
    pub apb1_pre: APBPrescaler,
@@ -98,26 +115,39 @@ pub struct Config {
    #[cfg(all(stm32f3, not(rcc_f37), any(peri_adc3_common, peri_adc34_common)))]
    pub adc34: AdcClockSource,
+    #[cfg(stm32f107)]
+    pub i2s2_src: I2s2src,
+    #[cfg(stm32f107)]
+    pub i2s3_src: I2s2src,
    /// Per-peripheral kernel clock selection muxes
    pub mux: super::mux::ClockMux,
    pub ls: super::LsConfig,
 }
-impl Default for Config {
+impl Config {
-    fn default() -> Self {
+    pub const fn new() -> Self {
        Self {
            hsi: true,
            hse: None,
            #[cfg(crs)]
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
            sys: Sysclk::HSI,
            pll: None,
+            #[cfg(stm32f107)]
+            pll2: None,
+            #[cfg(stm32f107)]
+            pll3: None,
+            #[cfg(stm32f107)]
+            prediv2: PllPreDiv::DIV1,
            ahb_pre: AHBPrescaler::DIV1,
            apb1_pre: APBPrescaler::DIV1,
            #[cfg(not(stm32f0))]
            apb2_pre: APBPrescaler::DIV1,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            #[cfg(stm32f1)]
            // ensure ADC is not out of range by default even if APB2 is maxxed out (36mhz)
@@ -128,11 +158,22 @@ impl Default for Config {
            #[cfg(all(stm32f3, not(rcc_f37), any(peri_adc3_common, peri_adc34_common)))]
            adc34: AdcClockSource::Hclk(AdcHclkPrescaler::Div1),
-            mux: Default::default(),
+            #[cfg(stm32f107)]
+            i2s2_src: I2s2src::SYS,
+            #[cfg(stm32f107)]
+            i2s3_src: I2s2src::SYS,
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
 /// Initialize and Set the clock frequencies
 pub(crate) unsafe fn init(config: Config) {
    // Turn on the HSI
@@ -157,8 +198,8 @@ pub(crate) unsafe fn init(config: Config) {
        }
        Some(hse) => {
            match hse.mode {
-                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
-                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+                HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
            }
            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -174,6 +215,28 @@ pub(crate) unsafe fn init(config: Config) {
    #[cfg(not(crs))]
    let hsi48: Option<Hertz> = None;
+    // PLL2 and PLL3
+    // Configure this before PLL since PLL2 can be the source for PLL.
+    #[cfg(stm32f107)]
+    {
+        // Common prediv for PLL2 and PLL3
+        RCC.cfgr2().modify(|w| w.set_prediv2(config.prediv2));
+        // Configure PLL2
+        if let Some(pll2) = config.pll2 {
+            RCC.cfgr2().modify(|w| w.set_pll2mul(pll2.mul));
+            RCC.cr().modify(|w| w.set_pll2on(true));
+            while !RCC.cr().read().pll2rdy() {}
+        }
+        // Configure PLL3
+        if let Some(pll3) = config.pll3 {
+            RCC.cfgr2().modify(|w| w.set_pll3mul(pll3.mul));
+            RCC.cr().modify(|w| w.set_pll3on(true));
+            while !RCC.cr().read().pll3rdy() {}
+        }
+    }
    // Enable PLL
    let pll = config.pll.map(|pll| {
        let (src_val, src_freq) = match pll.src {
@@ -186,21 +249,44 @@ pub(crate) unsafe fn init(config: Config) {
                }
                (Pllsrc::HSI_DIV2, unwrap!(hsi))
            }
-            PllSource::HSE => (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse)),
+            PllSource::HSE => {
+                #[cfg(stm32f107)]
+                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::HSE));
+                (Pllsrc::HSE_DIV_PREDIV, unwrap!(hse))
+            }
            #[cfg(rcc_f0v4)]
            PllSource::HSI48 => (Pllsrc::HSI48_DIV_PREDIV, unwrap!(hsi48)),
+            #[cfg(stm32f107)]
+            PllSource::PLL2 => {
+                if config.pll2.is_none() {
+                    panic!("if PLL source is PLL2, Config::pll2 must also be set.");
+                }
+                RCC.cfgr2().modify(|w| w.set_prediv1src(Prediv1src::PLL2));
+                let pll2 = unwrap!(config.pll2);
+                let in_freq = hse.unwrap() / config.prediv2;
+                let pll2freq = in_freq * pll2.mul;
+                (Pllsrc::HSE_DIV_PREDIV, pll2freq)
+            }
        };
        let in_freq = src_freq / pll.prediv;
-        assert!(max::PLL_IN.contains(&in_freq));
+        rcc_assert!(max::PLL_IN.contains(&in_freq));
        let out_freq = in_freq * pll.mul;
-        assert!(max::PLL_OUT.contains(&out_freq));
+        rcc_assert!(max::PLL_OUT.contains(&out_freq));
        #[cfg(not(stm32f1))]
        RCC.cfgr2().modify(|w| w.set_prediv(pll.prediv));
+        #[cfg(stm32f107)]
+        RCC.cfgr2().modify(|w| w.set_prediv1(pll.prediv));
        RCC.cfgr().modify(|w| {
            w.set_pllmul(pll.mul);
            w.set_pllsrc(src_val);
-            #[cfg(stm32f1)]
+            #[cfg(all(stm32f1, not(stm32f107)))]
            w.set_pllxtpre(pll.prediv);
        });
        RCC.cr().modify(|w| w.set_pllon(true));
@@ -209,10 +295,7 @@ pub(crate) unsafe fn init(config: Config) {
        out_freq
    });
-    #[cfg(stm32f3)]
+    #[cfg(any(rcc_f1, rcc_f1cl, stm32f3, stm32f107))]
-    let pll_mul_2 = pll.map(|pll| pll * 2u32);
-    #[cfg(any(rcc_f1, rcc_f1cl, stm32f3))]
    let usb = match pll {
        Some(Hertz(72_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1_5),
        Some(Hertz(48_000_000)) => Some(crate::pac::rcc::vals::Usbpre::DIV1),
@@ -228,6 +311,9 @@ pub(crate) unsafe fn init(config: Config) {
        Sysclk::HSI => unwrap!(hsi),
        Sysclk::HSE => unwrap!(hse),
        Sysclk::PLL1_P => unwrap!(pll),
+        #[cfg(crs)]
+        Sysclk::HSI48 => unwrap!(hsi48),
+        #[cfg(not(crs))]
        _ => unreachable!(),
    };
@@ -238,15 +324,15 @@ pub(crate) unsafe fn init(config: Config) {
    #[cfg(stm32f0)]
    let (pclk2, pclk2_tim) = (pclk1, pclk1_tim);
-    assert!(max::HCLK.contains(&hclk));
+    rcc_assert!(max::HCLK.contains(&hclk));
-    assert!(max::PCLK1.contains(&pclk1));
+    rcc_assert!(max::PCLK1.contains(&pclk1));
    #[cfg(not(stm32f0))]
-    assert!(max::PCLK2.contains(&pclk2));
+    rcc_assert!(max::PCLK2.contains(&pclk2));
    #[cfg(stm32f1)]
    let adc = pclk2 / config.adc_pre;
    #[cfg(stm32f1)]
-    assert!(max::ADC.contains(&adc));
+    rcc_assert!(max::ADC.contains(&adc));
    // Set latency based on HCLK frquency
    #[cfg(stm32f0)]
@@ -289,6 +375,13 @@ pub(crate) unsafe fn init(config: Config) {
        w.set_adcpre(config.adc_pre);
    });
+    // I2S2 and I2S3
+    #[cfg(stm32f107)]
+    {
+        RCC.cfgr2().modify(|w| w.set_i2s2src(config.i2s2_src));
+        RCC.cfgr2().modify(|w| w.set_i2s3src(config.i2s3_src));
+    }
    // Wait for the new prescalers to kick in
    // "The clocks are divided with the new prescaler factor from
    //  1 to 16 AHB cycles after write"
@@ -328,9 +421,9 @@ pub(crate) unsafe fn init(config: Config) {
                assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
                let (div, ckmode) = match adcpres {
-                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNC_DIV1),
-                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNC_DIV2),
-                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNC_DIV4),
                };
                common.ccr().modify(|w| w.set_ckmode(ckmode));
@@ -357,9 +450,9 @@ pub(crate) unsafe fn init(config: Config) {
                assert!(!(adcpres == AdcHclkPrescaler::Div1 && config.ahb_pre != AHBPrescaler::DIV1));
                let (div, ckmode) = match adcpres {
-                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNCDIV1),
+                    AdcHclkPrescaler::Div1 => (1u32, Ckmode::SYNC_DIV1),
-                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNCDIV2),
+                    AdcHclkPrescaler::Div2 => (2u32, Ckmode::SYNC_DIV2),
-                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNCDIV4),
+                    AdcHclkPrescaler::Div4 => (4u32, Ckmode::SYNC_DIV4),
                };
                common.ccr().modify(|w| w.set_ckmode(ckmode));
@@ -393,9 +486,6 @@ pub(crate) unsafe fn init(config: Config) {
        hsi: hsi,
        hse: hse,
        pll1_p: pll,
-        #[cfg(stm32f3)]
-        pll1_p_mul_2: pll_mul_2,
-        hsi_div_244: hsi.map(|h| h / 244u32),
        sys: Some(sys),
        pclk1: Some(pclk1),
        pclk2: Some(pclk2),
diff --git a/embassy-stm32/src/rcc/f247.rs b/embassy-stm32/src/rcc/f247.rs
index 61f687d30..8f2e8db5f 100644
--- a/embassy-stm32/src/rcc/f247.rs
+++ b/embassy-stm32/src/rcc/f247.rs
@@ -1,5 +1,7 @@
 use stm32_metapac::flash::vals::Latency;
+#[cfg(any(stm32f413, stm32f423, stm32f412))]
+pub use crate::pac::rcc::vals::Plli2ssrc as Plli2sSource;
 pub use crate::pac::rcc::vals::{
    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
@@ -63,6 +65,7 @@ pub struct Pll {
 /// Used to calculate flash waitstates. See
 /// RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock frequency
 #[cfg(stm32f2)]
+#[derive(Clone, Copy)]
 pub enum VoltageScale {
    /// 2.7 to 3.6 V
    Range0,
@@ -76,12 +79,15 @@ pub enum VoltageScale {
 /// Configuration of the core clocks
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    pub hsi: bool,
    pub hse: Option<Hse>,
    pub sys: Sysclk,
    pub pll_src: PllSource,
+    #[cfg(any(stm32f412, stm32f413, stm32f423))]
+    pub external_i2s_clock: Option<Hertz>,
    pub pll: Option<Pll>,
    #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
@@ -102,13 +108,15 @@ pub struct Config {
    pub voltage: VoltageScale,
 }
-impl Default for Config {
+impl Config {
-    fn default() -> Self {
+    pub const fn new() -> Self {
        Self {
            hsi: true,
            hse: None,
            sys: Sysclk::HSI,
            pll_src: PllSource::HSI,
+            #[cfg(any(stm32f412, stm32f413, stm32f423))]
+            external_i2s_clock: None,
            pll: None,
            #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
            plli2s: None,
@@ -119,15 +127,21 @@ impl Default for Config {
            apb1_pre: APBPrescaler::DIV1,
            apb2_pre: APBPrescaler::DIV1,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            #[cfg(stm32f2)]
            voltage: VoltageScale::Range3,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
 pub(crate) unsafe fn init(config: Config) {
    // set VOS to SCALE1, if use PLL
    // TODO: check real clock speed before set VOS
@@ -168,8 +182,8 @@ pub(crate) unsafe fn init(config: Config) {
        }
        Some(hse) => {
            match hse.mode {
-                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
-                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+                HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
            }
            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -183,6 +197,8 @@ pub(crate) unsafe fn init(config: Config) {
    let pll_input = PllInput {
        hse,
        hsi,
+        #[cfg(any(stm32f412, stm32f413, stm32f423))]
+        external: config.external_i2s_clock,
        source: config.pll_src,
    };
    let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
@@ -203,10 +219,10 @@ pub(crate) unsafe fn init(config: Config) {
    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
-    assert!(max::SYSCLK.contains(&sys));
+    rcc_assert!(max::SYSCLK.contains(&sys));
-    assert!(max::HCLK.contains(&hclk));
+    rcc_assert!(max::HCLK.contains(&hclk));
-    assert!(max::PCLK1.contains(&pclk1));
+    rcc_assert!(max::PCLK1.contains(&pclk1));
-    assert!(max::PCLK2.contains(&pclk2));
+    rcc_assert!(max::PCLK2.contains(&pclk2));
    let rtc = config.ls.init();
@@ -306,7 +322,6 @@ pub(crate) unsafe fn init(config: Config) {
        #[cfg(dsihost)]
        dsi_phy: None, // DSI PLL clock not supported, don't call `RccPeripheral::frequency()` in the drivers
-        hsi_div488: hsi.map(|hsi| hsi/488u32),
        hsi_hse: None,
        afif: None,
    );
@@ -316,6 +331,8 @@ struct PllInput {
    source: PllSource,
    hsi: Option<Hertz>,
    hse: Option<Hertz>,
+    #[cfg(any(stm32f412, stm32f413, stm32f423))]
+    external: Option<Hertz>,
 }
 #[derive(Default)]
@@ -360,10 +377,17 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
    let Some(pll) = config else { return PllOutput::default() };
+    #[cfg(not(any(stm32f412, stm32f413, stm32f423)))]
    let pll_src = match input.source {
        PllSource::HSE => input.hse,
        PllSource::HSI => input.hsi,
    };
+    #[cfg(any(stm32f412, stm32f413, stm32f423))]
+    let pll_src = match (input.source, input.external) {
+        (PllSource::HSE, None) => input.hse,
+        (PllSource::HSI, None) => input.hsi,
+        (_, Some(ext)) => Some(ext),
+    };
    let pll_src = pll_src.unwrap();
@@ -412,6 +436,17 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
        }),
        #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
        PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
+            #[cfg(any(stm32f411, stm32f412, stm32f413, stm32f423, stm32f446))]
+            w.set_pllm(pll.prediv);
+            #[cfg(any(stm32f412, stm32f413, stm32f423))]
+            {
+                let plli2ssource = match input.external {
+                    Some(_) => Plli2sSource::EXTERNAL,
+                    None => Plli2sSource::HSE_HSI,
+                };
+                w.set_plli2ssrc(plli2ssource);
+            }
            write_fields!(w);
        }),
        #[cfg(stm32f2)]
diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index c2fa0ca39..ce6398afd 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -1,10 +1,11 @@
 use crate::pac::flash::vals::Latency;
 pub use crate::pac::pwr::vals::Vos as VoltageRange;
 pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
+    Hpre as AHBPrescaler, Hsidiv as HsiSysDiv, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
-    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
+    Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::{FLASH, PWR, RCC};
+use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 /// HSI speed
@@ -28,11 +29,18 @@ pub struct Hse {
    pub mode: HseMode,
 }
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+    /// Division factor for HSISYS clock. Default is 1.
+    pub sys_div: HsiSysDiv,
+}
 /// PLL Configuration
 ///
 /// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
 /// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
 /// frequency ranges for each of these settings.
+#[derive(Clone, Copy)]
 pub struct Pll {
    /// PLL Source clock selection.
    pub source: PllSource,
@@ -55,9 +63,10 @@ pub struct Pll {
 /// Clocks configutation
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
-    /// HSI Enable
+    /// HSI Configuration
-    pub hsi: bool,
+    pub hsi: Option<Hsi>,
    /// HSE Configuration
    pub hse: Option<Hse>,
@@ -88,26 +97,33 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    #[inline]
+    pub const fn new() -> Self {
-    fn default() -> Config {
        Config {
-            hsi: true,
+            hsi: Some(Hsi {
+                sys_div: HsiSysDiv::DIV1,
+            }),
            hse: None,
            sys: Sysclk::HSI,
            #[cfg(crs)]
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
            pll: None,
            ahb_pre: AHBPrescaler::DIV1,
            apb1_pre: APBPrescaler::DIV1,
            low_power_run: false,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            voltage_range: VoltageRange::RANGE1,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Config {
+        Self::new()
+    }
+}
 #[derive(Default)]
 pub struct PllFreq {
    pub pll_p: Option<Hertz>,
@@ -117,7 +133,12 @@ pub struct PllFreq {
 pub(crate) unsafe fn init(config: Config) {
    // Turn on the HSI
-    RCC.cr().modify(|w| w.set_hsion(true));
+    RCC.cr().modify(|w| {
+        w.set_hsion(true);
+        if let Some(hsi) = config.hsi {
+            w.set_hsidiv(hsi.sys_div);
+        }
+    });
    while !RCC.cr().read().hsirdy() {}
    // Use the HSI clock as system clock during the actual clock setup
@@ -125,9 +146,9 @@ pub(crate) unsafe fn init(config: Config) {
    while RCC.cfgr().read().sws() != Sysclk::HSI {}
    // Configure HSI
-    let hsi = match config.hsi {
+    let (hsi, hsisys) = match config.hsi {
-        false => None,
+        None => (None, None),
-        true => Some(HSI_FREQ),
+        Some(hsi) => (Some(HSI_FREQ), Some(HSI_FREQ / hsi.sys_div)),
    };
    // Configure HSE
@@ -138,8 +159,8 @@ pub(crate) unsafe fn init(config: Config) {
        }
        Some(hse) => {
            match hse.mode {
-                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
-                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+                HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
            }
            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -167,10 +188,9 @@ pub(crate) unsafe fn init(config: Config) {
            while RCC.cr().read().pllrdy() {}
            let in_freq = src_freq / pll_config.prediv;
-            assert!(max::PLL_IN.contains(&in_freq));
+            rcc_assert!(max::PLL_IN.contains(&in_freq));
            let internal_freq = in_freq * pll_config.mul;
+            rcc_assert!(max::PLL_VCO.contains(&internal_freq));
-            assert!(max::PLL_VCO.contains(&internal_freq));
            RCC.pllcfgr().write(|w| {
                w.set_plln(pll_config.mul);
@@ -184,7 +204,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllpen(true);
                });
                let freq = internal_freq / div_p;
-                assert!(max::PLL_P.contains(&freq));
+                rcc_assert!(max::PLL_P.contains(&freq));
                freq
            });
@@ -194,7 +214,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllqen(true);
                });
                let freq = internal_freq / div_q;
-                assert!(max::PLL_Q.contains(&freq));
+                rcc_assert!(max::PLL_Q.contains(&freq));
                freq
            });
@@ -204,7 +224,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllren(true);
                });
                let freq = internal_freq / div_r;
-                assert!(max::PLL_R.contains(&freq));
+                rcc_assert!(max::PLL_R.contains(&freq));
                freq
            });
@@ -220,21 +240,28 @@ pub(crate) unsafe fn init(config: Config) {
        })
        .unwrap_or_default();
+    let rtc = config.ls.init();
    let sys = match config.sys {
-        Sysclk::HSI => unwrap!(hsi),
+        Sysclk::HSI => unwrap!(hsisys),
        Sysclk::HSE => unwrap!(hse),
        Sysclk::PLL1_R => unwrap!(pll.pll_r),
+        Sysclk::LSI => {
+            assert!(config.ls.lsi);
+            LSI_FREQ
+        }
+        Sysclk::LSE => unwrap!(config.ls.lse).frequency,
        _ => unreachable!(),
    };
-    assert!(max::SYSCLK.contains(&sys));
+    rcc_assert!(max::SYSCLK.contains(&sys));
    // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
    let hclk = sys / config.ahb_pre;
-    assert!(max::HCLK.contains(&hclk));
+    rcc_assert!(max::HCLK.contains(&hclk));
    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
-    assert!(max::PCLK.contains(&pclk1));
+    rcc_assert!(max::PCLK.contains(&pclk1));
    let latency = match (config.voltage_range, hclk.0) {
        (VoltageRange::RANGE1, ..=24_000_000) => Latency::WS0,
@@ -263,7 +290,7 @@ pub(crate) unsafe fn init(config: Config) {
    while RCC.cfgr().read().sws() != config.sys {}
    // Disable HSI if not used
-    if !config.hsi {
+    if config.hsi.is_none() {
        RCC.cr().modify(|w| w.set_hsion(false));
    }
@@ -272,8 +299,6 @@ pub(crate) unsafe fn init(config: Config) {
        PWR.cr1().modify(|w| w.set_lpr(true));
    }
-    let rtc = config.ls.init();
    config.mux.init();
    set_clocks!(
@@ -289,8 +314,6 @@ pub(crate) unsafe fn init(config: Config) {
        #[cfg(crs)]
        hsi48: hsi48,
        rtc: rtc,
-        hsi_div_8: hsi.map(|h| h / 8u32),
-        hsi_div_488: hsi.map(|h| h / 488u32),
        // TODO
        lsi: None,
diff --git a/embassy-stm32/src/rcc/g4.rs b/embassy-stm32/src/rcc/g4.rs
index c261c0fed..da13e16aa 100644
--- a/embassy-stm32/src/rcc/g4.rs
+++ b/embassy-stm32/src/rcc/g4.rs
@@ -32,6 +32,7 @@ pub struct Hse {
 /// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
 /// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
 /// frequency ranges for each of these settings.
+#[derive(Clone, Copy)]
 pub struct Pll {
    /// PLL Source clock selection.
    pub source: PllSource,
@@ -54,6 +55,7 @@ pub struct Pll {
 /// Clocks configutation
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    /// HSI Enable
    pub hsi: bool,
@@ -89,26 +91,31 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    #[inline]
+    pub const fn new() -> Self {
-    fn default() -> Config {
        Config {
            hsi: true,
            hse: None,
            sys: Sysclk::HSI,
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
            pll: None,
            ahb_pre: AHBPrescaler::DIV1,
            apb1_pre: APBPrescaler::DIV1,
            apb2_pre: APBPrescaler::DIV1,
            low_power_run: false,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            boost: false,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Config {
+        Self::new()
+    }
+}
 #[derive(Default)]
 pub struct PllFreq {
    pub pll_p: Option<Hertz>,
@@ -139,8 +146,8 @@ pub(crate) unsafe fn init(config: Config) {
        }
        Some(hse) => {
            match hse.mode {
-                HseMode::Bypass => assert!(max::HSE_BYP.contains(&hse.freq)),
+                HseMode::Bypass => rcc_assert!(max::HSE_BYP.contains(&hse.freq)),
-                HseMode::Oscillator => assert!(max::HSE_OSC.contains(&hse.freq)),
+                HseMode::Oscillator => rcc_assert!(max::HSE_OSC.contains(&hse.freq)),
            }
            RCC.cr().modify(|w| w.set_hsebyp(hse.mode != HseMode::Oscillator));
@@ -167,10 +174,10 @@ pub(crate) unsafe fn init(config: Config) {
            while RCC.cr().read().pllrdy() {}
            let in_freq = src_freq / pll_config.prediv;
-            assert!(max::PLL_IN.contains(&in_freq));
+            rcc_assert!(max::PLL_IN.contains(&in_freq));
            let internal_freq = in_freq * pll_config.mul;
-            assert!(max::PLL_VCO.contains(&internal_freq));
+            rcc_assert!(max::PLL_VCO.contains(&internal_freq));
            RCC.pllcfgr().write(|w| {
                w.set_plln(pll_config.mul);
@@ -184,7 +191,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllpen(true);
                });
                let freq = internal_freq / div_p;
-                assert!(max::PLL_P.contains(&freq));
+                rcc_assert!(max::PLL_P.contains(&freq));
                freq
            });
@@ -194,7 +201,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllqen(true);
                });
                let freq = internal_freq / div_q;
-                assert!(max::PLL_Q.contains(&freq));
+                rcc_assert!(max::PLL_Q.contains(&freq));
                freq
            });
@@ -204,7 +211,7 @@ pub(crate) unsafe fn init(config: Config) {
                    w.set_pllren(true);
                });
                let freq = internal_freq / div_r;
-                assert!(max::PLL_R.contains(&freq));
+                rcc_assert!(max::PLL_R.contains(&freq));
                freq
            });
@@ -227,16 +234,16 @@ pub(crate) unsafe fn init(config: Config) {
        _ => unreachable!(),
    };
-    assert!(max::SYSCLK.contains(&sys));
+    rcc_assert!(max::SYSCLK.contains(&sys));
    // Calculate the AHB frequency (HCLK), among other things so we can calculate the correct flash read latency.
    let hclk = sys / config.ahb_pre;
-    assert!(max::HCLK.contains(&hclk));
+    rcc_assert!(max::HCLK.contains(&hclk));
    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk, config.apb1_pre);
    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk, config.apb2_pre);
-    assert!(max::PCLK.contains(&pclk2));
+    rcc_assert!(max::PCLK.contains(&pclk1));
-    assert!(max::PCLK.contains(&pclk2));
+    rcc_assert!(max::PCLK.contains(&pclk2));
    // Configure Core Boost mode ([RM0440] p234 – inverted because setting r1mode to 0 enables boost mode!)
    if config.boost {
@@ -318,6 +325,8 @@ pub(crate) unsafe fn init(config: Config) {
        hse: hse,
        hsi48: hsi48,
        rtc: rtc,
+        lsi: None,
+        lse: None,
    );
 }
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index e3c7dd158..383f48874 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -34,8 +34,10 @@ pub enum VoltageScale {
    Scale2,
    Scale3,
 }
-#[cfg(any(stm32h7rs))]
+#[cfg(stm32h7rs)]
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
+#[cfg(all(stm32h7rs, peri_usb_otg_hs))]
+pub use crate::pac::rcc::vals::{Usbphycsel, Usbrefcksel};
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
@@ -111,8 +113,8 @@ pub enum TimerPrescaler {
 impl From<TimerPrescaler> for Timpre {
    fn from(value: TimerPrescaler) -> Self {
        match value {
-            TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2,
+            TimerPrescaler::DefaultX2 => Timpre::DEFAULT_X2,
-            TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4,
+            TimerPrescaler::DefaultX4 => Timpre::DEFAULT_X4,
        }
    }
 }
@@ -120,7 +122,7 @@ impl From<TimerPrescaler> for Timpre {
 /// Power supply configuration
 /// See RM0433 Rev 4 7.4
 #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
-#[derive(PartialEq)]
+#[derive(Clone, Copy, PartialEq)]
 pub enum SupplyConfig {
    /// Default power supply configuration.
    /// V CORE Power Domains are supplied from the LDO according to VOS.
@@ -180,6 +182,7 @@ pub enum SMPSSupplyVoltage {
 /// Configuration of the core clocks
 #[non_exhaustive]
+#[derive(Clone, Copy)]
 pub struct Config {
    pub hsi: Option<HSIPrescaler>,
    pub hse: Option<Hse>,
@@ -215,13 +218,13 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    fn default() -> Self {
+    pub const fn new() -> Self {
        Self {
            hsi: Some(HSIPrescaler::DIV1),
            hse: None,
            csi: false,
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
            sys: Sysclk::HSI,
            pll1: None,
            pll2: None,
@@ -245,16 +248,22 @@ impl Default for Config {
            voltage_scale: VoltageScale::Scale0,
            #[cfg(rcc_h7rs)]
            voltage_scale: VoltageScale::HIGH,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
            supply_config: SupplyConfig::LDO,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
 pub(crate) unsafe fn init(config: Config) {
    #[cfg(any(stm32h7))]
    let pwr_reg = PWR.cr3();
@@ -556,6 +565,27 @@ pub(crate) unsafe fn init(config: Config) {
    let rtc = config.ls.init();
+    #[cfg(all(stm32h7rs, peri_usb_otg_hs))]
+    let usb_refck = match config.mux.usbphycsel {
+        Usbphycsel::HSE => hse,
+        Usbphycsel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
+        Usbphycsel::PLL3_Q => pll3.q,
+        _ => None,
+    };
+    #[cfg(all(stm32h7rs, peri_usb_otg_hs))]
+    let usb_refck_sel = match usb_refck {
+        Some(clk_val) => match clk_val {
+            Hertz(16_000_000) => Usbrefcksel::MHZ16,
+            Hertz(19_200_000) => Usbrefcksel::MHZ19_2,
+            Hertz(20_000_000) => Usbrefcksel::MHZ20,
+            Hertz(24_000_000) => Usbrefcksel::MHZ24,
+            Hertz(26_000_000) => Usbrefcksel::MHZ26,
+            Hertz(32_000_000) => Usbrefcksel::MHZ32,
+            _ => panic!("cannot select USBPHYC reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+        },
+        None => Usbrefcksel::MHZ24,
+    };
    #[cfg(stm32h7)]
    {
        RCC.d1cfgr().modify(|w| {
@@ -592,6 +622,11 @@ pub(crate) unsafe fn init(config: Config) {
            w.set_ppre4(config.apb4_pre);
            w.set_ppre5(config.apb5_pre);
        });
+        #[cfg(peri_usb_otg_hs)]
+        RCC.ahbperckselr().modify(|w| {
+            w.set_usbrefcksel(usb_refck_sel);
+        });
    }
    #[cfg(stm32h5)]
    {
@@ -658,7 +693,6 @@ pub(crate) unsafe fn init(config: Config) {
        hsi: hsi,
        hsi48: hsi48,
        csi: csi,
-        csi_div_122: csi.map(|c| c / 122u32),
        hse: hse,
        lse: None,
@@ -697,7 +731,9 @@ pub(crate) unsafe fn init(config: Config) {
        #[cfg(stm32h7rs)]
        clk48mohci: None, // TODO
        #[cfg(stm32h7rs)]
-        usb: None, // TODO
+        usb: Some(Hertz(48_000_000)),
+        #[cfg(stm32h5)]
+        hse_div_rtcpre: None, // TODO
    );
 }
@@ -748,7 +784,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
        ..=3_999_999 => Pllrge::RANGE2,
        ..=7_999_999 => Pllrge::RANGE4,
        ..=16_000_000 => Pllrge::RANGE8,
-        x => panic!("pll ref_clk out of range: {} mhz", x),
+        x => panic!("pll ref_clk out of range: {} hz", x),
    };
    // The smaller range (150 to 420 MHz) must
@@ -757,18 +793,18 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
    let vco_clk = ref_clk * config.mul;
    let vco_range = if VCO_RANGE.contains(&vco_clk) {
-        Pllvcosel::MEDIUMVCO
+        Pllvcosel::MEDIUM_VCO
    } else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk) {
-        Pllvcosel::WIDEVCO
+        Pllvcosel::WIDE_VCO
    } else {
-        panic!("pll vco_clk out of range: {} hz", vco_clk.0)
+        panic!("pll vco_clk out of range: {}", vco_clk)
    };
    let p = config.divp.map(|div| {
        if num == 0 {
            // on PLL1, DIVP must be even for most series.
            // The enum value is 1 less than the divider, so check it's odd.
-            #[cfg(not(pwr_h7rm0468))]
+            #[cfg(not(any(pwr_h7rm0468, stm32h7rs)))]
            assert!(div.to_bits() % 2 == 1);
            #[cfg(pwr_h7rm0468)]
            assert!(div.to_bits() % 2 == 1 || div.to_bits() == 0);
diff --git a/embassy-stm32/src/rcc/hsi48.rs b/embassy-stm32/src/rcc/hsi48.rs
index efabd059f..3ea5c96c9 100644
--- a/embassy-stm32/src/rcc/hsi48.rs
+++ b/embassy-stm32/src/rcc/hsi48.rs
@@ -18,9 +18,15 @@ pub struct Hsi48Config {
    pub sync_from_usb: bool,
 }
+impl Hsi48Config {
+    pub const fn new() -> Self {
+        Self { sync_from_usb: false }
+    }
+}
 impl Default for Hsi48Config {
    fn default() -> Self {
-        Self { sync_from_usb: false }
+        Self::new()
    }
 }
diff --git a/embassy-stm32/src/rcc/l.rs b/embassy-stm32/src/rcc/l.rs
index e9266c65b..81b89046e 100644
--- a/embassy-stm32/src/rcc/l.rs
+++ b/embassy-stm32/src/rcc/l.rs
@@ -5,6 +5,7 @@ use crate::pac::rcc::regs::Cfgr;
 pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
 pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as Sysclk};
 use crate::pac::{FLASH, RCC};
+use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 /// HSI speed
@@ -30,6 +31,7 @@ pub struct Hse {
 }
 /// Clocks configuration
+#[derive(Clone, Copy)]
 pub struct Config {
    // base clock sources
    pub msi: Option<MSIRange>,
@@ -66,9 +68,8 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    #[inline]
+    pub const fn new() -> Self {
-    fn default() -> Config {
        Config {
            hse: None,
            hsi: false,
@@ -88,15 +89,21 @@ impl Default for Config {
            #[cfg(any(stm32l47x, stm32l48x, stm32l49x, stm32l4ax, rcc_l4plus, stm32l5))]
            pllsai2: None,
            #[cfg(crs)]
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            #[cfg(any(stm32l0, stm32l1))]
            voltage_scale: VoltageScale::RANGE1,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Config {
+        Self::new()
+    }
+}
 #[cfg(stm32wb)]
 pub const WPAN_DEFAULT: Config = Config {
    hse: Some(Hse {
@@ -181,6 +188,9 @@ pub(crate) unsafe fn init(config: Config) {
    let rtc = config.ls.init();
+    let lse = config.ls.lse.map(|l| l.frequency);
+    let lsi = config.ls.lsi.then_some(LSI_FREQ);
    let msi = config.msi.map(|range| {
        msi_enable(range);
        msirange_to_hertz(range)
@@ -391,7 +401,7 @@ pub(crate) unsafe fn init(config: Config) {
        hsi48: hsi48,
        #[cfg(any(stm32l0, stm32l1))]
-        pll1_vco_div_2: pll.vco.map(|c| c/2u32),
+        pll1_vco: pll.vco,
        #[cfg(not(any(stm32l0, stm32l1)))]
        pll1_p: pll.p,
@@ -424,12 +434,12 @@ pub(crate) unsafe fn init(config: Config) {
        dsi_phy: None, // DSI PLL clock not supported, don't call `RccPeripheral::frequency()` in the drivers
        rtc: rtc,
+        lse: lse,
+        lsi: lsi,
        // TODO
        sai1_extclk: None,
        sai2_extclk: None,
-        lsi: None,
-        lse: None,
    );
 }
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index d1ce14c86..c50e071fb 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -1,6 +1,6 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use crate::gpio::{AfType, OutputType, Speed};
 #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
@@ -32,7 +32,7 @@ pub use crate::pac::rcc::vals::Mcosel as McoSource;
 ))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::pac::RCC;
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 #[cfg(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37))]
 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
@@ -43,7 +43,7 @@ pub enum McoPrescaler {
 pub(crate) trait SealedMcoInstance {}
 #[allow(private_bounds)]
-pub trait McoInstance: SealedMcoInstance + 'static {
+pub trait McoInstance: PeripheralType + SealedMcoInstance + 'static {
    type Source;
    #[doc(hidden)]
@@ -91,14 +91,7 @@ pub struct Mco<'d, T: McoInstance> {
 impl<'d, T: McoInstance> Mco<'d, T> {
    /// Create a new MCO instance.
-    pub fn new(
+    pub fn new(_peri: Peri<'d, T>, pin: Peri<'d, impl McoPin<T>>, source: T::Source, prescaler: McoPrescaler) -> Self {
-        _peri: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl McoPin<T>> + 'd,
-        source: T::Source,
-        prescaler: McoPrescaler,
-    ) -> Self {
-        into_ref!(pin);
        critical_section::with(|_| unsafe {
            T::_apply_clock_settings(source, prescaler);
            pin.set_as_af(pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index 8022a35a4..c41f81816 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -86,7 +86,7 @@ pub(crate) unsafe fn set_freqs(freqs: Clocks) {
 #[cfg(not(feature = "_dual-core"))]
 /// Safety: Reads a mutable global.
 pub(crate) unsafe fn get_freqs() -> &'static Clocks {
-    CLOCK_FREQS.assume_init_ref()
+    (*core::ptr::addr_of_mut!(CLOCK_FREQS)).assume_init_ref()
 }
 #[cfg(feature = "_dual-core")]
@@ -95,8 +95,19 @@ pub(crate) unsafe fn get_freqs() -> &'static Clocks {
    unwrap!(CLOCK_FREQS_PTR.load(core::sync::atomic::Ordering::SeqCst).as_ref()).assume_init_ref()
 }
+/// Get the current clock configuration of the chip.
+pub fn clocks<'a>(_rcc: &'a crate::Peri<'a, crate::peripherals::RCC>) -> &'a Clocks {
+    // Safety: the existence of a `Peri<RCC>` means that `rcc::init()`
+    // has already been called, so `CLOCK_FREQS` must be initialized.
+    // The clocks could be modified again by `reinit()`, but reinit
+    // (for this reason) requires an exclusive reference to `Peri<RCC>`.
+    unsafe { get_freqs() }
+}
 pub(crate) trait SealedRccPeripheral {
    fn frequency() -> Hertz;
+    #[allow(dead_code)]
+    fn bus_frequency() -> Hertz;
    const RCC_INFO: RccInfo;
 }
@@ -171,7 +182,9 @@ impl RccInfo {
            // Use .get_mut instead of []-operator so that we control how bounds checks happen.
            // Otherwise, core::fmt will be pulled in here in order to format the integer in the
            // out-of-bounds error.
-            if let Some(refcount) = unsafe { crate::_generated::REFCOUNTS.get_mut(refcount_idx) } {
+            if let Some(refcount) =
+                unsafe { (*core::ptr::addr_of_mut!(crate::_generated::REFCOUNTS)).get_mut(refcount_idx) }
+            {
                *refcount += 1;
                if *refcount > 1 {
                    return;
@@ -235,7 +248,9 @@ impl RccInfo {
            // Use .get_mut instead of []-operator so that we control how bounds checks happen.
            // Otherwise, core::fmt will be pulled in here in order to format the integer in the
            // out-of-bounds error.
-            if let Some(refcount) = unsafe { crate::_generated::REFCOUNTS.get_mut(refcount_idx) } {
+            if let Some(refcount) =
+                unsafe { (*core::ptr::addr_of_mut!(crate::_generated::REFCOUNTS)).get_mut(refcount_idx) }
+            {
                *refcount -= 1;
                if *refcount > 0 {
                    return;
@@ -365,3 +380,32 @@ pub fn enable_and_reset<T: RccPeripheral>() {
 pub fn disable<T: RccPeripheral>() {
    T::RCC_INFO.disable();
 }
+/// Re-initialize the `embassy-stm32` clock configuration with the provided configuration.
+///
+/// This is useful when you need to alter the CPU clock after configuring peripherals.
+/// For instance, configure an external clock via spi or i2c.
+///
+/// Please not this only re-configures the rcc and the time driver (not GPIO, EXTI, etc).
+///
+/// This should only be called after `init`.
+#[cfg(not(feature = "_dual-core"))]
+pub fn reinit<'a>(config: Config, _rcc: &'a mut crate::Peri<'a, crate::peripherals::RCC>) {
+    critical_section::with(|cs| init_rcc(cs, config))
+}
+pub(crate) fn init_rcc(_cs: CriticalSection, config: Config) {
+    unsafe {
+        init(config);
+        // must be after rcc init
+        #[cfg(feature = "_time-driver")]
+        crate::time_driver::init(_cs);
+        #[cfg(feature = "low-power")]
+        {
+            REFCOUNT_STOP2 = 0;
+            REFCOUNT_STOP1 = 0;
+        }
+    }
+}
diff --git a/embassy-stm32/src/rcc/u5.rs b/embassy-stm32/src/rcc/u5.rs
index d6331f512..97eb2eb6d 100644
--- a/embassy-stm32/src/rcc/u5.rs
+++ b/embassy-stm32/src/rcc/u5.rs
@@ -1,10 +1,15 @@
 pub use crate::pac::pwr::vals::Vos as VoltageScale;
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::rcc::vals::Otghssel;
 pub use crate::pac::rcc::vals::{
    Hpre as AHBPrescaler, Msirange, Msirange as MSIRange, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul,
    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::rcc::vals::{Hseext, Msirgsel, Pllmboost, Pllrge};
+#[cfg(all(peri_usb_otg_hs))]
+pub use crate::pac::{syscfg::vals::Usbrefcksel, SYSCFG};
 use crate::pac::{FLASH, PWR, RCC};
+use crate::rcc::LSI_FREQ;
 use crate::time::Hertz;
 /// HSI speed
@@ -59,9 +64,11 @@ pub struct Pll {
    pub divr: Option<PllDiv>,
 }
+#[derive(Clone, Copy)]
 pub struct Config {
    // base clock sources
-    pub msi: Option<MSIRange>,
+    pub msis: Option<MSIRange>,
+    pub msik: Option<MSIRange>,
    pub hsi: bool,
    pub hse: Option<Hse>,
    pub hsi48: Option<super::Hsi48Config>,
@@ -90,13 +97,14 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    fn default() -> Self {
+    pub const fn new() -> Self {
        Self {
-            msi: Some(Msirange::RANGE_4MHZ),
+            msis: Some(Msirange::RANGE_4MHZ),
+            msik: Some(Msirange::RANGE_4MHZ),
            hse: None,
            hsi: false,
-            hsi48: Some(Default::default()),
+            hsi48: Some(crate::rcc::Hsi48Config::new()),
            pll1: None,
            pll2: None,
            pll3: None,
@@ -106,18 +114,24 @@ impl Default for Config {
            apb2_pre: APBPrescaler::DIV1,
            apb3_pre: APBPrescaler::DIV1,
            voltage_range: VoltageScale::RANGE1,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Self {
+        Self::new()
+    }
+}
 pub(crate) unsafe fn init(config: Config) {
    // Set the requested power mode
    PWR.vosr().modify(|w| w.set_vos(config.voltage_range));
    while !PWR.vosr().read().vosrdy() {}
-    let msi = config.msi.map(|range| {
+    let msis = config.msis.map(|range| {
        // Check MSI output per RM0456 § 11.4.10
        match config.voltage_range {
            VoltageScale::RANGE4 => {
@@ -146,8 +160,36 @@ pub(crate) unsafe fn init(config: Config) {
        msirange_to_hertz(range)
    });
+    let msik = config.msik.map(|range| {
+        // Check MSI output per RM0456 § 11.4.10
+        match config.voltage_range {
+            VoltageScale::RANGE4 => {
+                assert!(msirange_to_hertz(range).0 <= 24_000_000);
+            }
+            _ => {}
+        }
+        // RM0456 § 11.8.2: spin until MSIS is off or MSIS is ready before setting its range
+        loop {
+            let cr = RCC.cr().read();
+            if cr.msikon() == false || cr.msikrdy() == true {
+                break;
+            }
+        }
+        RCC.icscr1().modify(|w| {
+            w.set_msikrange(range);
+            w.set_msirgsel(Msirgsel::ICSCR1);
+        });
+        RCC.cr().modify(|w| {
+            w.set_msikon(true);
+        });
+        while !RCC.cr().read().msikrdy() {}
+        msirange_to_hertz(range)
+    });
    let hsi = config.hsi.then(|| {
-        RCC.cr().write(|w| w.set_hsion(true));
+        RCC.cr().modify(|w| w.set_hsion(true));
        while !RCC.cr().read().hsirdy() {}
        HSI_FREQ
@@ -165,7 +207,7 @@ pub(crate) unsafe fn init(config: Config) {
        }
        // Enable HSE, and wait for it to stabilize
-        RCC.cr().write(|w| {
+        RCC.cr().modify(|w| {
            w.set_hseon(true);
            w.set_hsebyp(hse.mode != HseMode::Oscillator);
            w.set_hseext(match hse.mode {
@@ -180,7 +222,7 @@ pub(crate) unsafe fn init(config: Config) {
    let hsi48 = config.hsi48.map(super::init_hsi48);
-    let pll_input = PllInput { hse, hsi, msi };
+    let pll_input = PllInput { hse, hsi, msi: msis };
    let pll1 = init_pll(PllInstance::Pll1, config.pll1, &pll_input, config.voltage_range);
    let pll2 = init_pll(PllInstance::Pll2, config.pll2, &pll_input, config.voltage_range);
    let pll3 = init_pll(PllInstance::Pll3, config.pll3, &pll_input, config.voltage_range);
@@ -188,7 +230,7 @@ pub(crate) unsafe fn init(config: Config) {
    let sys_clk = match config.sys {
        Sysclk::HSE => hse.unwrap(),
        Sysclk::HSI => hsi.unwrap(),
-        Sysclk::MSIS => msi.unwrap(),
+        Sysclk::MSIS => msis.unwrap(),
        Sysclk::PLL1_R => pll1.r.unwrap(),
    };
@@ -263,6 +305,34 @@ pub(crate) unsafe fn init(config: Config) {
    let rtc = config.ls.init();
+    #[cfg(all(stm32u5, peri_usb_otg_hs))]
+    let usb_refck = match config.mux.otghssel {
+        Otghssel::HSE => hse,
+        Otghssel::HSE_DIV_2 => hse.map(|hse_val| hse_val / 2u8),
+        Otghssel::PLL1_P => pll1.p,
+        Otghssel::PLL1_P_DIV_2 => pll1.p.map(|pll1p_val| pll1p_val / 2u8),
+    };
+    #[cfg(all(stm32u5, peri_usb_otg_hs))]
+    let usb_refck_sel = match usb_refck {
+        Some(clk_val) => match clk_val {
+            Hertz(16_000_000) => Usbrefcksel::MHZ16,
+            Hertz(19_200_000) => Usbrefcksel::MHZ19_2,
+            Hertz(20_000_000) => Usbrefcksel::MHZ20,
+            Hertz(24_000_000) => Usbrefcksel::MHZ24,
+            Hertz(26_000_000) => Usbrefcksel::MHZ26,
+            Hertz(32_000_000) => Usbrefcksel::MHZ32,
+            _ => panic!("cannot select OTG_HS reference clock with source frequency of {}, must be one of 16, 19.2, 20, 24, 26, 32 MHz", clk_val),
+        },
+        None => Usbrefcksel::MHZ24,
+    };
+    #[cfg(all(stm32u5, peri_usb_otg_hs))]
+    SYSCFG.otghsphycr().modify(|w| {
+        w.set_clksel(usb_refck_sel);
+    });
+    let lse = config.ls.lse.map(|l| l.frequency);
+    let lsi = config.ls.lsi.then_some(LSI_FREQ);
    config.mux.init();
    set_clocks!(
@@ -275,8 +345,11 @@ pub(crate) unsafe fn init(config: Config) {
        pclk3: Some(pclk3),
        pclk1_tim: Some(pclk1_tim),
        pclk2_tim: Some(pclk2_tim),
+        msik: msik,
        hsi48: hsi48,
        rtc: rtc,
+        lse: lse,
+        lsi: lsi,
        hse: hse,
        hsi: hsi,
        pll1_p: pll1.p,
@@ -294,12 +367,7 @@ pub(crate) unsafe fn init(config: Config) {
        // TODO
        audioclk: None,
-        hsi48_div_2: None,
-        lse: None,
-        lsi: None,
-        msik: None,
        shsi: None,
-        shsi_div_2: None,
    );
 }
diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 8e1779d7c..b9fc4e423 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -15,6 +15,7 @@ pub struct Hse {
 }
 /// Clocks configuration
+#[derive(Clone, Copy)]
 pub struct Config {
    // base clock sources
    pub hsi: bool,
@@ -36,9 +37,8 @@ pub struct Config {
    pub mux: super::mux::ClockMux,
 }
-impl Default for Config {
+impl Config {
-    #[inline]
+    pub const fn new() -> Self {
-    fn default() -> Config {
        Config {
            hse: None,
            hsi: true,
@@ -47,13 +47,19 @@ impl Default for Config {
            apb1_pre: APBPrescaler::DIV1,
            apb2_pre: APBPrescaler::DIV1,
            apb7_pre: APBPrescaler::DIV1,
-            ls: Default::default(),
+            ls: crate::rcc::LsConfig::new(),
            voltage_scale: VoltageScale::RANGE2,
-            mux: Default::default(),
+            mux: super::mux::ClockMux::default(),
        }
    }
 }
+impl Default for Config {
+    fn default() -> Config {
+        Self::new()
+    }
+}
 fn hsi_enable() {
    RCC.cr().modify(|w| w.set_hsion(true));
    while !RCC.cr().read().hsirdy() {}
diff --git a/embassy-stm32/src/rng.rs b/embassy-stm32/src/rng.rs
index 6f4c81c8a..312f343b9 100644
--- a/embassy-stm32/src/rng.rs
+++ b/embassy-stm32/src/rng.rs
@@ -5,12 +5,11 @@ use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::task::Poll;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
-use rand_core::{CryptoRng, RngCore};
 use crate::interrupt::typelevel::Interrupt;
-use crate::{interrupt, pac, peripherals, rcc, Peripheral};
+use crate::{interrupt, pac, peripherals, rcc, Peri};
 static RNG_WAKER: AtomicWaker = AtomicWaker::new();
@@ -43,17 +42,16 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
 /// RNG driver.
 pub struct Rng<'d, T: Instance> {
-    _inner: PeripheralRef<'d, T>,
+    _inner: Peri<'d, T>,
 }
 impl<'d, T: Instance> Rng<'d, T> {
    /// Create a new RNG driver.
    pub fn new(
-        inner: impl Peripheral<P = T> + 'd,
+        inner: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
    ) -> Self {
        rcc::enable_and_reset::<T>();
-        into_ref!(inner);
        let mut random = Self { _inner: inner };
        random.reset();
@@ -88,10 +86,10 @@ impl<'d, T: Instance> Rng<'d, T> {
            reg.set_nistc(pac::rng::vals::Nistc::CUSTOM);
            // set RNG config "A" according to reference manual
            // this has to be written within the same write access as setting the CONDRST bit
-            reg.set_rng_config1(pac::rng::vals::RngConfig1::CONFIGA);
+            reg.set_rng_config1(pac::rng::vals::RngConfig1::CONFIG_A);
-            reg.set_clkdiv(pac::rng::vals::Clkdiv::NODIV);
+            reg.set_clkdiv(pac::rng::vals::Clkdiv::NO_DIV);
-            reg.set_rng_config2(pac::rng::vals::RngConfig2::CONFIGA_B);
+            reg.set_rng_config2(pac::rng::vals::RngConfig2::CONFIG_A_B);
-            reg.set_rng_config3(pac::rng::vals::RngConfig3::CONFIGA);
+            reg.set_rng_config3(pac::rng::vals::RngConfig3::CONFIG_A);
            reg.set_ced(true);
            reg.set_ie(false);
            reg.set_rngen(true);
@@ -185,10 +183,9 @@ impl<'d, T: Instance> Rng<'d, T> {
        Ok(())
    }
-}
-impl<'d, T: Instance> RngCore for Rng<'d, T> {
+    /// Get a random u32
-    fn next_u32(&mut self) -> u32 {
+    pub fn next_u32(&mut self) -> u32 {
        loop {
            let sr = T::regs().sr().read();
            if sr.seis() | sr.ceis() {
@@ -199,13 +196,15 @@ impl<'d, T: Instance> RngCore for Rng<'d, T> {
        }
    }
-    fn next_u64(&mut self) -> u64 {
+    /// Get a random u64
+    pub fn next_u64(&mut self) -> u64 {
        let mut rand = self.next_u32() as u64;
        rand |= (self.next_u32() as u64) << 32;
        rand
    }
-    fn fill_bytes(&mut self, dest: &mut [u8]) {
+    /// Fill a slice with random bytes
+    pub fn fill_bytes(&mut self, dest: &mut [u8]) {
        for chunk in dest.chunks_mut(4) {
            let rand = self.next_u32();
            for (slot, num) in chunk.iter_mut().zip(rand.to_ne_bytes().iter()) {
@@ -213,14 +212,53 @@ impl<'d, T: Instance> RngCore for Rng<'d, T> {
            }
        }
    }
+}
+impl<'d, T: Instance> Drop for Rng<'d, T> {
+    fn drop(&mut self) {
+        T::regs().cr().modify(|reg| {
+            reg.set_rngen(false);
+        });
+        rcc::disable::<T>();
+    }
+}
+impl<'d, T: Instance> rand_core_06::RngCore for Rng<'d, T> {
+    fn next_u32(&mut self) -> u32 {
+        self.next_u32()
+    }
+    fn next_u64(&mut self) -> u64 {
+        self.next_u64()
+    }
-    fn try_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), rand_core::Error> {
+    fn fill_bytes(&mut self, dest: &mut [u8]) {
+        self.fill_bytes(dest);
+    }
+    fn try_fill_bytes(&mut self, dest: &mut [u8]) -> Result<(), rand_core_06::Error> {
        self.fill_bytes(dest);
        Ok(())
    }
 }
-impl<'d, T: Instance> CryptoRng for Rng<'d, T> {}
+impl<'d, T: Instance> rand_core_06::CryptoRng for Rng<'d, T> {}
+impl<'d, T: Instance> rand_core_09::RngCore for Rng<'d, T> {
+    fn next_u32(&mut self) -> u32 {
+        self.next_u32()
+    }
+    fn next_u64(&mut self) -> u64 {
+        self.next_u64()
+    }
+    fn fill_bytes(&mut self, dest: &mut [u8]) {
+        self.fill_bytes(dest);
+    }
+}
+impl<'d, T: Instance> rand_core_09::CryptoRng for Rng<'d, T> {}
 trait SealedInstance {
    fn regs() -> pac::rng::Rng;
@@ -228,7 +266,7 @@ trait SealedInstance {
 /// RNG instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + Peripheral<P = Self> + crate::rcc::RccPeripheral + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + crate::rcc::RccPeripheral + 'static + Send {
    /// Interrupt for this RNG instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/rtc/datetime.rs b/embassy-stm32/src/rtc/datetime.rs
index 32732e96e..8b420bb6e 100644
--- a/embassy-stm32/src/rtc/datetime.rs
+++ b/embassy-stm32/src/rtc/datetime.rs
@@ -3,6 +3,7 @@ use chrono::{Datelike, NaiveDate, Timelike, Weekday};
 /// Errors regarding the [`DateTime`] struct.
 #[derive(Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
    /// The [DateTime] contains an invalid year value. Must be between `0..=4095`.
    InvalidYear,
@@ -21,9 +22,12 @@ pub enum Error {
    InvalidMinute,
    /// The [DateTime] contains an invalid second value. Must be between `0..=59`.
    InvalidSecond,
+    /// The [DateTime] contains an invalid microsecond value. Must be between `0..=999_999`.
+    InvalidMicrosecond,
 }
 /// Structure containing date and time information
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct DateTime {
    /// 0..4095
    year: u16,
@@ -39,6 +43,8 @@ pub struct DateTime {
    minute: u8,
    /// 0..59
    second: u8,
+    /// 0..999_999
+    usecond: u32,
 }
 impl DateTime {
@@ -77,6 +83,11 @@ impl DateTime {
        self.second
    }
+    /// Get the microsecond (0..=999_999)
+    pub const fn microsecond(&self) -> u32 {
+        self.usecond
+    }
    /// Create a new DateTime with the given information.
    pub fn from(
        year: u16,
@@ -86,6 +97,7 @@ impl DateTime {
        hour: u8,
        minute: u8,
        second: u8,
+        usecond: u32,
    ) -> Result<Self, Error> {
        if year > 4095 {
            Err(Error::InvalidYear)
@@ -99,6 +111,8 @@ impl DateTime {
            Err(Error::InvalidMinute)
        } else if second > 59 {
            Err(Error::InvalidSecond)
+        } else if usecond > 999_999 {
+            Err(Error::InvalidMicrosecond)
        } else {
            Ok(Self {
                year,
@@ -108,6 +122,7 @@ impl DateTime {
                hour,
                minute,
                second,
+                usecond,
            })
        }
    }
@@ -124,6 +139,7 @@ impl From<chrono::NaiveDateTime> for DateTime {
            hour: date_time.hour() as u8,
            minute: date_time.minute() as u8,
            second: date_time.second() as u8,
+            usecond: date_time.and_utc().timestamp_subsec_micros(),
        }
    }
 }
@@ -133,7 +149,12 @@ impl From<DateTime> for chrono::NaiveDateTime {
    fn from(date_time: DateTime) -> Self {
        NaiveDate::from_ymd_opt(date_time.year as i32, date_time.month as u32, date_time.day as u32)
            .unwrap()
-            .and_hms_opt(date_time.hour as u32, date_time.minute as u32, date_time.second as u32)
+            .and_hms_micro_opt(
+                date_time.hour as u32,
+                date_time.minute as u32,
+                date_time.second as u32,
+                date_time.usecond,
+            )
            .unwrap()
    }
 }
@@ -141,6 +162,7 @@ impl From<DateTime> for chrono::NaiveDateTime {
 /// A day of the week
 #[repr(u8)]
 #[derive(Copy, Clone, Debug, PartialEq, Eq, Ord, PartialOrd, Hash)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[allow(missing_docs)]
 pub enum DayOfWeek {
    Monday = 1,
diff --git a/embassy-stm32/src/rtc/low_power.rs b/embassy-stm32/src/rtc/low_power.rs
index b9aaa63b9..cd075f3de 100644
--- a/embassy-stm32/src/rtc/low_power.rs
+++ b/embassy-stm32/src/rtc/low_power.rs
@@ -65,7 +65,9 @@ pub(crate) enum WakeupPrescaler {
    Div16 = 16,
 }
-#[cfg(any(stm32f4, stm32l0, stm32g4, stm32l5, stm32wb, stm32h5, stm32g0))]
+#[cfg(any(
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+))]
 impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
    fn from(val: WakeupPrescaler) -> Self {
        use crate::pac::rtc::vals::Wucksel;
@@ -79,7 +81,9 @@ impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
    }
 }
-#[cfg(any(stm32f4, stm32l0, stm32g4, stm32l5, stm32wb, stm32h5, stm32g0))]
+#[cfg(any(
+    stm32f4, stm32l0, stm32g4, stm32l4, stm32l5, stm32wb, stm32h5, stm32g0, stm32u5, stm32u0
+))]
 impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
        use crate::pac::rtc::vals::Wucksel;
@@ -219,12 +223,29 @@ impl Rtc {
    pub(crate) fn enable_wakeup_line(&self) {
        use crate::interrupt::typelevel::Interrupt;
-        use crate::pac::EXTI;
        <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::unpend();
        unsafe { <RTC as crate::rtc::SealedInstance>::WakeupInterrupt::enable() };
-        EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+        #[cfg(not(any(stm32u5, stm32u0)))]
-        EXTI.imr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+        {
+            use crate::pac::EXTI;
+            EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+            #[cfg(not(stm32wb))]
+            {
+                EXTI.imr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+            }
+            #[cfg(stm32wb)]
+            {
+                EXTI.cpu(0).imr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+            }
+        }
+        #[cfg(stm32u5)]
+        {
+            use crate::pac::RCC;
+            RCC.srdamr().modify(|w| w.set_rtcapbamen(true));
+            RCC.apb3smenr().modify(|w| w.set_rtcapbsmen(true));
+        }
    }
 }
diff --git a/embassy-stm32/src/rtc/mod.rs b/embassy-stm32/src/rtc/mod.rs
index fe57cfe66..49f423f37 100644
--- a/embassy-stm32/src/rtc/mod.rs
+++ b/embassy-stm32/src/rtc/mod.rs
@@ -25,17 +25,18 @@ use crate::time::Hertz;
    ),
    path = "v2.rs"
 )]
-#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5), path = "v3.rs")]
+#[cfg_attr(any(rtc_v3, rtc_v3u5, rtc_v3l5, rtc_v3h7rs), path = "v3.rs")]
 mod _version;
 #[allow(unused_imports)]
 pub use _version::*;
-use embassy_hal_internal::Peripheral;
 use crate::peripherals::RTC;
+use crate::Peri;
 /// Errors that can occur on methods on [RtcClock]
 #[non_exhaustive]
 #[derive(Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum RtcError {
    /// An invalid DateTime was given or stored on the hardware.
    InvalidDateTime(DateTimeError),
@@ -59,7 +60,7 @@ impl RtcTimeProvider {
    ///
    /// Will return an `RtcError::InvalidDateTime` if the stored value in the system is not a valid [`DayOfWeek`].
    pub fn now(&self) -> Result<DateTime, RtcError> {
-        self.read(|dr, tr, _| {
+        self.read(|dr, tr, _ss| {
            let second = bcd2_to_byte((tr.st(), tr.su()));
            let minute = bcd2_to_byte((tr.mnt(), tr.mnu()));
            let hour = bcd2_to_byte((tr.ht(), tr.hu()));
@@ -69,7 +70,17 @@ impl RtcTimeProvider {
            let month = bcd2_to_byte((dr.mt() as u8, dr.mu()));
            let year = bcd2_to_byte((dr.yt(), dr.yu())) as u16 + 2000_u16;
-            DateTime::from(year, month, day, weekday, hour, minute, second).map_err(RtcError::InvalidDateTime)
+            // Calculate second fraction and multiply to microseconds
+            // Formula from RM0410
+            #[cfg(not(rtc_v2f2))]
+            let us = {
+                let prediv = RTC::regs().prer().read().prediv_s() as f32;
+                (((prediv - _ss as f32) / (prediv + 1.0)) * 1e6).min(999_999.0) as u32
+            };
+            #[cfg(rtc_v2f2)]
+            let us = 0;
+            DateTime::from(year, month, day, weekday, hour, minute, second, us).map_err(RtcError::InvalidDateTime)
        })
    }
@@ -140,7 +151,7 @@ pub enum RtcCalibrationCyclePeriod {
 impl Rtc {
    /// Create a new RTC instance.
-    pub fn new(_rtc: impl Peripheral<P = RTC>, rtc_config: RtcConfig) -> Self {
+    pub fn new(_rtc: Peri<'static, RTC>, rtc_config: RtcConfig) -> Self {
        #[cfg(not(any(stm32l0, stm32f3, stm32l1, stm32f0, stm32f2)))]
        crate::rcc::enable_and_reset::<RTC>();
@@ -285,6 +296,7 @@ trait SealedInstance {
    const BACKUP_REGISTER_COUNT: usize;
    #[cfg(feature = "low-power")]
+    #[cfg(not(any(stm32u5, stm32u0)))]
    const EXTI_WAKEUP_LINE: usize;
    #[cfg(feature = "low-power")]
diff --git a/embassy-stm32/src/rtc/v2.rs b/embassy-stm32/src/rtc/v2.rs
index cdc1cb299..28380a3c0 100644
--- a/embassy-stm32/src/rtc/v2.rs
+++ b/embassy-stm32/src/rtc/v2.rs
@@ -77,7 +77,7 @@ impl super::Rtc {
                    // When the offset is positive (0 to 512), the opposite of
                    // the offset (512 - offset) is masked, i.e. for the
                    // maximum offset (512), 0 pulses are masked.
-                    w.set_calp(stm32_metapac::rtc::vals::Calp::INCREASEFREQ);
+                    w.set_calp(stm32_metapac::rtc::vals::Calp::INCREASE_FREQ);
                    w.set_calm(512 - clock_drift as u16);
                } else {
                    // Minimum (about -510.7) rounds to -511.
@@ -86,7 +86,7 @@ impl super::Rtc {
                    // When the offset is negative or zero (-511 to 0),
                    // the absolute offset is masked, i.e. for the minimum
                    // offset (-511), 511 pulses are masked.
-                    w.set_calp(stm32_metapac::rtc::vals::Calp::NOCHANGE);
+                    w.set_calp(stm32_metapac::rtc::vals::Calp::NO_CHANGE);
                    w.set_calm((clock_drift * -1.0) as u16);
                }
            });
@@ -131,10 +131,16 @@ impl SealedInstance for crate::peripherals::RTC {
    #[cfg(all(feature = "low-power", stm32f4))]
    const EXTI_WAKEUP_LINE: usize = 22;
+    #[cfg(all(feature = "low-power", stm32l4))]
+    const EXTI_WAKEUP_LINE: usize = 20;
    #[cfg(all(feature = "low-power", stm32l0))]
    const EXTI_WAKEUP_LINE: usize = 20;
-    #[cfg(all(feature = "low-power", stm32f4))]
+    #[cfg(all(feature = "low-power", stm32wb))]
+    const EXTI_WAKEUP_LINE: usize = 19;
+    #[cfg(all(feature = "low-power", any(stm32f4, stm32l4, stm32wb)))]
    type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
    #[cfg(all(feature = "low-power", stm32l0))]
diff --git a/embassy-stm32/src/rtc/v3.rs b/embassy-stm32/src/rtc/v3.rs
index 02fd5272e..39aa6c5cb 100644
--- a/embassy-stm32/src/rtc/v3.rs
+++ b/embassy-stm32/src/rtc/v3.rs
@@ -12,7 +12,7 @@ impl super::Rtc {
        self.write(true, |rtc| {
            rtc.cr().modify(|w| {
                w.set_bypshad(true);
-                w.set_fmt(Fmt::TWENTYFOURHOUR);
+                w.set_fmt(Fmt::TWENTY_FOUR_HOUR);
                w.set_osel(Osel::DISABLED);
                w.set_pol(Pol::HIGH);
            });
@@ -25,7 +25,7 @@ impl super::Rtc {
            // TODO: configuration for output pins
            rtc.cr().modify(|w| {
                w.set_out2en(false);
-                w.set_tampalrm_type(TampalrmType::PUSHPULL);
+                w.set_tampalrm_type(TampalrmType::PUSH_PULL);
                w.set_tampalrm_pu(false);
            });
        });
@@ -56,10 +56,10 @@ impl super::Rtc {
            rtc.calr().write(|w| {
                match period {
                    RtcCalibrationCyclePeriod::Seconds8 => {
-                        w.set_calw8(Calw8::EIGHTSECONDS);
+                        w.set_calw8(Calw8::EIGHT_SECONDS);
                    }
                    RtcCalibrationCyclePeriod::Seconds16 => {
-                        w.set_calw16(Calw16::SIXTEENSECONDS);
+                        w.set_calw16(Calw16::SIXTEEN_SECONDS);
                    }
                    RtcCalibrationCyclePeriod::Seconds32 => {
                        // Set neither `calw8` nor `calw16` to use 32 seconds
@@ -79,7 +79,7 @@ impl super::Rtc {
                    // When the offset is positive (0 to 512), the opposite of
                    // the offset (512 - offset) is masked, i.e. for the
                    // maximum offset (512), 0 pulses are masked.
-                    w.set_calp(Calp::INCREASEFREQ);
+                    w.set_calp(Calp::INCREASE_FREQ);
                    w.set_calm(512 - clock_drift as u16);
                } else {
                    // Minimum (about -510.7) rounds to -511.
@@ -88,7 +88,7 @@ impl super::Rtc {
                    // When the offset is negative or zero (-511 to 0),
                    // the absolute offset is masked, i.e. for the minimum
                    // offset (-511), 511 pulses are masked.
-                    w.set_calp(Calp::NOCHANGE);
+                    w.set_calp(Calp::NO_CHANGE);
                    w.set_calm((clock_drift * -1.0) as u16);
                }
            });
@@ -133,12 +133,20 @@ impl SealedInstance for crate::peripherals::RTC {
    cfg_if::cfg_if!(
        if #[cfg(stm32g4)] {
            const EXTI_WAKEUP_LINE: usize = 20;
-            type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
        } else if #[cfg(stm32g0)] {
            const EXTI_WAKEUP_LINE: usize = 19;
-            type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
        } else if #[cfg(any(stm32l5, stm32h5))] {
            const EXTI_WAKEUP_LINE: usize = 17;
+        }
+    );
+    #[cfg(feature = "low-power")]
+    cfg_if::cfg_if!(
+        if #[cfg(stm32g4)] {
+            type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
+        } else if #[cfg(any(stm32g0, stm32u0))] {
+            type WakeupInterrupt = crate::interrupt::typelevel::RTC_TAMP;
+        } else if #[cfg(any(stm32l5, stm32h5, stm32u5))] {
            type WakeupInterrupt = crate::interrupt::typelevel::RTC;
        }
    );
diff --git a/embassy-stm32/src/sai/mod.rs b/embassy-stm32/src/sai/mod.rs
index c48d81b5f..0c9c27797 100644
--- a/embassy-stm32/src/sai/mod.rs
+++ b/embassy-stm32/src/sai/mod.rs
@@ -4,7 +4,7 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::PeripheralType;
 pub use crate::dma::word;
 #[cfg(not(gpdma))]
@@ -12,7 +12,7 @@ use crate::dma::{ringbuffer, Channel, ReadableRingBuffer, Request, TransferOptio
 use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::pac::sai::{vals, Sai as Regs};
 use crate::rcc::{self, RccPeripheral};
-use crate::{peripherals, Peripheral};
+use crate::{peripherals, Peri};
 /// SAI error
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -27,8 +27,14 @@ pub enum Error {
 }
 #[cfg(not(gpdma))]
-impl From<ringbuffer::OverrunError> for Error {
+impl From<ringbuffer::Error> for Error {
-    fn from(_: ringbuffer::OverrunError) -> Self {
+    fn from(#[allow(unused)] err: ringbuffer::Error) -> Self {
+        #[cfg(feature = "defmt")]
+        {
+            if err == ringbuffer::Error::DmaUnsynced {
+                defmt::error!("Ringbuffer broken invariants detected!");
+            }
+        }
        Self::Overrun
    }
 }
@@ -46,12 +52,12 @@ impl Mode {
    const fn mode(&self, tx_rx: TxRx) -> vals::Mode {
        match tx_rx {
            TxRx::Transmitter => match self {
-                Mode::Master => vals::Mode::MASTERTX,
+                Mode::Master => vals::Mode::MASTER_TX,
-                Mode::Slave => vals::Mode::SLAVETX,
+                Mode::Slave => vals::Mode::SLAVE_TX,
            },
            TxRx::Receiver => match self {
-                Mode::Master => vals::Mode::MASTERRX,
+                Mode::Master => vals::Mode::MASTER_RX,
-                Mode::Slave => vals::Mode::SLAVERX,
+                Mode::Slave => vals::Mode::SLAVE_RX,
            },
        }
    }
@@ -80,7 +86,7 @@ impl SlotSize {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn slotsz(&self) -> vals::Slotsz {
        match self {
-            SlotSize::DataSize => vals::Slotsz::DATASIZE,
+            SlotSize::DataSize => vals::Slotsz::DATA_SIZE,
            SlotSize::Channel16 => vals::Slotsz::BIT16,
            SlotSize::Channel32 => vals::Slotsz::BIT32,
        }
@@ -149,8 +155,8 @@ impl MuteValue {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn muteval(&self) -> vals::Muteval {
        match self {
-            MuteValue::Zero => vals::Muteval::SENDZERO,
+            MuteValue::Zero => vals::Muteval::SEND_ZERO,
-            MuteValue::LastValue => vals::Muteval::SENDLAST,
+            MuteValue::LastValue => vals::Muteval::SEND_LAST,
        }
    }
 }
@@ -184,7 +190,7 @@ pub enum SyncInput {
    /// Syncs with the other A/B sub-block within the SAI unit
    Internal,
    /// Syncs with a sub-block in the other SAI unit
-    #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
+    #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    External(SyncInputInstance),
 }
@@ -193,14 +199,14 @@ impl SyncInput {
        match self {
            SyncInput::None => vals::Syncen::ASYNCHRONOUS,
            SyncInput::Internal => vals::Syncen::INTERNAL,
-            #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
+            #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
            SyncInput::External(_) => vals::Syncen::EXTERNAL,
        }
    }
 }
 /// SAI instance to sync from.
-#[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
+#[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
 #[derive(Copy, Clone, PartialEq)]
 #[allow(missing_docs)]
 pub enum SyncInputInstance {
@@ -245,8 +251,8 @@ impl BitOrder {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn lsbfirst(&self) -> vals::Lsbfirst {
        match self {
-            BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
+            BitOrder::LsbFirst => vals::Lsbfirst::LSB_FIRST,
-            BitOrder::MsbFirst => vals::Lsbfirst::MSBFIRST,
+            BitOrder::MsbFirst => vals::Lsbfirst::MSB_FIRST,
        }
    }
 }
@@ -264,8 +270,8 @@ impl FrameSyncOffset {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn fsoff(&self) -> vals::Fsoff {
        match self {
-            FrameSyncOffset::OnFirstBit => vals::Fsoff::ONFIRST,
+            FrameSyncOffset::OnFirstBit => vals::Fsoff::ON_FIRST,
-            FrameSyncOffset::BeforeFirstBit => vals::Fsoff::BEFOREFIRST,
+            FrameSyncOffset::BeforeFirstBit => vals::Fsoff::BEFORE_FIRST,
        }
    }
 }
@@ -283,8 +289,8 @@ impl FrameSyncPolarity {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn fspol(&self) -> vals::Fspol {
        match self {
-            FrameSyncPolarity::ActiveLow => vals::Fspol::FALLINGEDGE,
+            FrameSyncPolarity::ActiveLow => vals::Fspol::FALLING_EDGE,
-            FrameSyncPolarity::ActiveHigh => vals::Fspol::RISINGEDGE,
+            FrameSyncPolarity::ActiveHigh => vals::Fspol::RISING_EDGE,
        }
    }
 }
@@ -319,8 +325,8 @@ impl ClockStrobe {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn ckstr(&self) -> vals::Ckstr {
        match self {
-            ClockStrobe::Falling => vals::Ckstr::FALLINGEDGE,
+            ClockStrobe::Falling => vals::Ckstr::FALLING_EDGE,
-            ClockStrobe::Rising => vals::Ckstr::RISINGEDGE,
+            ClockStrobe::Rising => vals::Ckstr::RISING_EDGE,
        }
    }
 }
@@ -337,8 +343,8 @@ impl ComplementFormat {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn cpl(&self) -> vals::Cpl {
        match self {
-            ComplementFormat::OnesComplement => vals::Cpl::ONESCOMPLEMENT,
+            ComplementFormat::OnesComplement => vals::Cpl::ONES_COMPLEMENT,
-            ComplementFormat::TwosComplement => vals::Cpl::TWOSCOMPLEMENT,
+            ComplementFormat::TwosComplement => vals::Cpl::TWOS_COMPLEMENT,
        }
    }
 }
@@ -356,8 +362,8 @@ impl Companding {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn comp(&self) -> vals::Comp {
        match self {
-            Companding::None => vals::Comp::NOCOMPANDING,
+            Companding::None => vals::Comp::NO_COMPANDING,
-            Companding::MuLaw => vals::Comp::MULAW,
+            Companding::MuLaw => vals::Comp::MU_LAW,
            Companding::ALaw => vals::Comp::ALAW,
        }
    }
@@ -375,7 +381,7 @@ impl OutputDrive {
    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    const fn outdriv(&self) -> vals::Outdriv {
        match self {
-            OutputDrive::OnStart => vals::Outdriv::ONSTART,
+            OutputDrive::OnStart => vals::Outdriv::ON_START,
            OutputDrive::Immediately => vals::Outdriv::IMMEDIATELY,
        }
    }
@@ -661,19 +667,19 @@ fn get_af_types(mode: Mode, tx_rx: TxRx) -> (AfType, AfType) {
        //sd is defined by tx/rx mode
        match tx_rx {
            TxRx::Transmitter => AfType::output(OutputType::PushPull, Speed::VeryHigh),
-            TxRx::Receiver => AfType::input(Pull::None),
+            TxRx::Receiver => AfType::input(Pull::Down), // Ensure mute level when no input is connected.
        },
        //clocks (mclk, sck and fs) are defined by master/slave
        match mode {
            Mode::Master => AfType::output(OutputType::PushPull, Speed::VeryHigh),
-            Mode::Slave => AfType::input(Pull::None),
+            Mode::Slave => AfType::input(Pull::Down), // Ensure no clocks when no input is connected.
        },
    )
 }
 #[cfg(not(gpdma))]
 fn get_ring_buffer<'d, T: Instance, W: word::Word>(
-    dma: impl Peripheral<P = impl Channel> + 'd,
+    dma: Peri<'d, impl Channel>,
    dma_buf: &'d mut [W],
    request: Request,
    sub_block: WhichSubBlock,
@@ -698,12 +704,12 @@ fn update_synchronous_config(config: &mut Config) {
    config.mode = Mode::Slave;
    config.sync_output = false;
-    #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm))]
+    #[cfg(any(sai_v1, sai_v2))]
    {
        config.sync_input = SyncInput::Internal;
    }
-    #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
+    #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
    {
        //this must either be Internal or External
        //The asynchronous sub-block on the same SAI needs to enable sync_output
@@ -712,16 +718,15 @@ fn update_synchronous_config(config: &mut Config) {
 }
 /// SAI subblock instance.
-pub struct SubBlock<'d, T, S: SubBlockInstance> {
+pub struct SubBlock<'d, T: Instance, S: SubBlockInstance> {
-    peri: PeripheralRef<'d, T>,
+    peri: Peri<'d, T>,
    _phantom: PhantomData<S>,
 }
 /// Split the main SAIx peripheral into the two subblocks.
 ///
 /// You can then create a [`Sai`] driver for each each half.
-pub fn split_subblocks<'d, T: Instance>(peri: impl Peripheral<P = T> + 'd) -> (SubBlock<'d, T, A>, SubBlock<'d, T, B>) {
+pub fn split_subblocks<'d, T: Instance>(peri: Peri<'d, T>) -> (SubBlock<'d, T, A>, SubBlock<'d, T, B>) {
-    into_ref!(peri);
    rcc::enable_and_reset::<T>();
    (
@@ -738,11 +743,11 @@ pub fn split_subblocks<'d, T: Instance>(peri: impl Peripheral<P = T> + 'd) -> (S
 /// SAI sub-block driver.
 pub struct Sai<'d, T: Instance, W: word::Word> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
-    sd: Option<PeripheralRef<'d, AnyPin>>,
+    sd: Option<Peri<'d, AnyPin>>,
-    fs: Option<PeripheralRef<'d, AnyPin>>,
+    fs: Option<Peri<'d, AnyPin>>,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
-    mclk: Option<PeripheralRef<'d, AnyPin>>,
+    mclk: Option<Peri<'d, AnyPin>>,
    #[cfg(gpdma)]
    ring_buffer: PhantomData<W>,
    #[cfg(not(gpdma))]
@@ -757,16 +762,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    /// You can obtain the [`SubBlock`] with [`split_subblocks`].
    pub fn new_asynchronous_with_mclk<S: SubBlockInstance>(
        peri: SubBlock<'d, T, S>,
-        sck: impl Peripheral<P = impl SckPin<T, S>> + 'd,
+        sck: Peri<'d, impl SckPin<T, S>>,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
+        sd: Peri<'d, impl SdPin<T, S>>,
-        fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
+        fs: Peri<'d, impl FsPin<T, S>>,
-        mclk: impl Peripheral<P = impl MclkPin<T, S>> + 'd,
+        mclk: Peri<'d, impl MclkPin<T, S>>,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
        dma_buf: &'d mut [W],
        mut config: Config,
    ) -> Self {
-        into_ref!(mclk);
        let (_sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
        mclk.set_as_af(mclk.af_num(), ck_af_type);
@@ -782,15 +785,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    /// You can obtain the [`SubBlock`] with [`split_subblocks`].
    pub fn new_asynchronous<S: SubBlockInstance>(
        peri: SubBlock<'d, T, S>,
-        sck: impl Peripheral<P = impl SckPin<T, S>> + 'd,
+        sck: Peri<'d, impl SckPin<T, S>>,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
+        sd: Peri<'d, impl SdPin<T, S>>,
-        fs: impl Peripheral<P = impl FsPin<T, S>> + 'd,
+        fs: Peri<'d, impl FsPin<T, S>>,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
        dma_buf: &'d mut [W],
        config: Config,
    ) -> Self {
        let peri = peri.peri;
-        into_ref!(peri, dma, sck, sd, fs);
        let (sd_af_type, ck_af_type) = get_af_types(config.mode, config.tx_rx);
        sd.set_as_af(sd.af_num(), sd_af_type);
@@ -803,10 +805,10 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
        Self::new_inner(
            peri,
            sub_block,
-            Some(sck.map_into()),
+            Some(sck.into()),
            None,
-            Some(sd.map_into()),
+            Some(sd.into()),
-            Some(fs.map_into()),
+            Some(fs.into()),
            get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
            config,
        )
@@ -817,15 +819,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    /// You can obtain the [`SubBlock`] with [`split_subblocks`].
    pub fn new_synchronous<S: SubBlockInstance>(
        peri: SubBlock<'d, T, S>,
-        sd: impl Peripheral<P = impl SdPin<T, S>> + 'd,
+        sd: Peri<'d, impl SdPin<T, S>>,
-        dma: impl Peripheral<P = impl Channel + Dma<T, S>> + 'd,
+        dma: Peri<'d, impl Channel + Dma<T, S>>,
        dma_buf: &'d mut [W],
        mut config: Config,
    ) -> Self {
        update_synchronous_config(&mut config);
        let peri = peri.peri;
-        into_ref!(dma, peri, sd);
        let (sd_af_type, _ck_af_type) = get_af_types(config.mode, config.tx_rx);
        sd.set_as_af(sd.af_num(), sd_af_type);
@@ -838,7 +839,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
            sub_block,
            None,
            None,
-            Some(sd.map_into()),
+            Some(sd.into()),
            None,
            get_ring_buffer::<T, W>(dma, dma_buf, request, sub_block, config.tx_rx),
            config,
@@ -846,22 +847,25 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    }
    fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        sub_block: WhichSubBlock,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
-        mclk: Option<PeripheralRef<'d, AnyPin>>,
+        mclk: Option<Peri<'d, AnyPin>>,
-        sd: Option<PeripheralRef<'d, AnyPin>>,
+        sd: Option<Peri<'d, AnyPin>>,
-        fs: Option<PeripheralRef<'d, AnyPin>>,
+        fs: Option<Peri<'d, AnyPin>>,
        ring_buffer: RingBuffer<'d, W>,
        config: Config,
    ) -> Self {
+        let ch = T::REGS.ch(sub_block as usize);
        #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
        {
-            let ch = T::REGS.ch(sub_block as usize);
            ch.cr1().modify(|w| w.set_saien(false));
        }
-        #[cfg(any(sai_v4_2pdm, sai_v4_4pdm))]
+        ch.cr2().modify(|w| w.set_fflush(true));
+        #[cfg(any(sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
        {
            if let SyncInput::External(i) = config.sync_input {
                T::REGS.gcr().modify(|w| {
@@ -882,7 +886,6 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
        #[cfg(any(sai_v1, sai_v2, sai_v3_2pdm, sai_v3_4pdm, sai_v4_2pdm, sai_v4_4pdm))]
        {
-            let ch = T::REGS.ch(sub_block as usize);
            ch.cr1().modify(|w| {
                w.set_mode(config.mode.mode(if Self::is_transmitter(&ring_buffer) {
                    TxRx::Transmitter
@@ -899,9 +902,9 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
                w.set_mckdiv(config.master_clock_divider.mckdiv());
                w.set_nodiv(
                    if config.master_clock_divider == MasterClockDivider::MasterClockDisabled {
-                        vals::Nodiv::NODIV
+                        vals::Nodiv::NO_DIV
                    } else {
-                        vals::Nodiv::MASTERCLOCK
+                        vals::Nodiv::MASTER_CLOCK
                    },
                );
                w.set_dmaen(true);
@@ -928,7 +931,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
                w.set_nbslot(config.slot_count.0 as u8 - 1);
                w.set_slotsz(config.slot_size.slotsz());
                w.set_fboff(config.first_bit_offset.0 as u8);
-                w.set_sloten(vals::Sloten(config.slot_enable as u16));
+                w.set_sloten(vals::Sloten::from_bits(config.slot_enable as u16));
            });
            ch.cr1().modify(|w| w.set_saien(true));
@@ -939,7 +942,7 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
        }
        Self {
-            _peri: peri.into_ref(),
+            _peri: peri,
            sub_block,
            sck,
            mclk,
@@ -950,13 +953,14 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    }
    /// Start the SAI driver.
-    pub fn start(&mut self) {
+    ///
+    /// Only receivers can be started. Transmitters are started on the first writing operation.
+    pub fn start(&mut self) -> Result<(), Error> {
        match self.ring_buffer {
-            RingBuffer::Writable(ref mut rb) => {
+            RingBuffer::Writable(_) => Err(Error::NotAReceiver),
-                rb.start();
-            }
            RingBuffer::Readable(ref mut rb) => {
                rb.start();
+                Ok(())
            }
        }
    }
@@ -973,22 +977,48 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
        rcc::enable_and_reset::<T>();
    }
-    /// Flush.
-    pub fn flush(&mut self) {
-        let ch = T::REGS.ch(self.sub_block as usize);
-        ch.cr1().modify(|w| w.set_saien(false));
-        ch.cr2().modify(|w| w.set_fflush(true));
-        ch.cr1().modify(|w| w.set_saien(true));
-    }
    /// Enable or disable mute.
    pub fn set_mute(&mut self, value: bool) {
        let ch = T::REGS.ch(self.sub_block as usize);
        ch.cr2().modify(|w| w.set_mute(value));
    }
+    /// Determine the mute state of the receiver.
+    ///
+    /// Clears the mute state flag in the status register.
+    pub fn is_muted(&self) -> Result<bool, Error> {
+        match &self.ring_buffer {
+            RingBuffer::Readable(_) => {
+                let ch = T::REGS.ch(self.sub_block as usize);
+                let mute_state = ch.sr().read().mutedet();
+                ch.clrfr().write(|w| w.set_cmutedet(true));
+                Ok(mute_state)
+            }
+            _ => Err(Error::NotAReceiver),
+        }
+    }
+    /// Wait until any SAI write error occurs.
+    ///
+    /// One useful application for this is stopping playback as soon as the SAI
+    /// experiences an overrun of the ring buffer. Then, instead of letting
+    /// the SAI peripheral play the last written buffer over and over again, SAI
+    /// can be muted or dropped instead.
+    pub async fn wait_write_error(&mut self) -> Result<(), Error> {
+        match &mut self.ring_buffer {
+            RingBuffer::Writable(buffer) => {
+                buffer.wait_write_error().await?;
+                Ok(())
+            }
+            _ => return Err(Error::NotATransmitter),
+        }
+    }
    /// Write data to the SAI ringbuffer.
    ///
+    /// The first write starts the DMA after filling the ring buffer with the provided data.
+    /// This ensures that the DMA does not run before data is available in the ring buffer.
+    ///
    /// This appends the data to the buffer and returns immediately. The
    /// data will be transmitted in the background.
    ///
@@ -996,7 +1026,12 @@ impl<'d, T: Instance, W: word::Word> Sai<'d, T, W> {
    pub async fn write(&mut self, data: &[W]) -> Result<(), Error> {
        match &mut self.ring_buffer {
            RingBuffer::Writable(buffer) => {
-                buffer.write_exact(data).await?;
+                if buffer.is_running() {
+                    buffer.write_exact(data).await?;
+                } else {
+                    buffer.write_immediate(data)?;
+                    buffer.start();
+                }
                Ok(())
            }
            _ => return Err(Error::NotATransmitter),
@@ -1024,6 +1059,7 @@ impl<'d, T: Instance, W: word::Word> Drop for Sai<'d, T, W> {
    fn drop(&mut self) {
        let ch = T::REGS.ch(self.sub_block as usize);
        ch.cr1().modify(|w| w.set_saien(false));
+        ch.cr2().modify(|w| w.set_fflush(true));
        self.fs.as_ref().map(|x| x.set_as_disconnected());
        self.sd.as_ref().map(|x| x.set_as_disconnected());
        self.sck.as_ref().map(|x| x.set_as_disconnected());
@@ -1065,7 +1101,7 @@ impl SubBlockInstance for B {}
 /// SAI instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {}
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
 pin_trait!(SckPin, Instance, SubBlockInstance);
 pin_trait!(FsPin, Instance, SubBlockInstance);
diff --git a/embassy-stm32/src/sdmmc/mod.rs b/embassy-stm32/src/sdmmc/mod.rs
index 44ff9fcd5..6a02aae70 100644
--- a/embassy-stm32/src/sdmmc/mod.rs
+++ b/embassy-stm32/src/sdmmc/mod.rs
@@ -8,11 +8,15 @@ use core::ops::{Deref, DerefMut};
 use core::task::Poll;
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+use embassy_hal_internal::{Peri, PeripheralType};
 use embassy_sync::waitqueue::AtomicWaker;
-use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID, CSD, OCR, SCR};
+use sdio_host::common_cmd::{self, Resp, ResponseLen};
+use sdio_host::emmc::{ExtCSD, EMMC};
+use sdio_host::sd::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CIC, CID, CSD, OCR, RCA, SCR, SD};
+use sdio_host::{emmc_cmd, sd_cmd, Cmd};
-use crate::dma::NoDma;
+#[cfg(sdmmc_v1)]
+use crate::dma::ChannelAndRequest;
 #[cfg(gpio_v2)]
 use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, SealedPin, Speed};
@@ -20,7 +24,7 @@ use crate::interrupt::typelevel::Interrupt;
 use crate::pac::sdmmc::Sdmmc as RegBlock;
 use crate::rcc::{self, RccPeripheral};
 use crate::time::Hertz;
-use crate::{interrupt, peripherals, Peripheral};
+use crate::{interrupt, peripherals};
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -135,51 +139,59 @@ pub enum Error {
    UnsupportedCardVersion,
    /// Unsupported card type.
    UnsupportedCardType,
+    /// Unsupported voltage.
+    UnsupportedVoltage,
    /// CRC error.
    Crc,
    /// No card inserted.
    NoCard,
+    /// 8-lane buses are not supported for SD cards.
+    BusWidth,
    /// Bad clock supplied to the SDMMC peripheral.
    BadClock,
    /// Signaling switch failed.
    SignalingSwitchFailed,
+    /// Underrun error
+    Underrun,
    /// ST bit error.
    #[cfg(sdmmc_v1)]
    StBitErr,
 }
-/// A SD command
-struct Cmd {
-    cmd: u8,
-    arg: u32,
-    resp: Response,
-}
 #[derive(Clone, Copy, Debug, Default)]
 /// SD Card
 pub struct Card {
    /// The type of this card
    pub card_type: CardCapacity,
    /// Operation Conditions Register
-    pub ocr: OCR,
+    pub ocr: OCR<SD>,
    /// Relative Card Address
-    pub rca: u32,
+    pub rca: u16,
    /// Card ID
-    pub cid: CID,
+    pub cid: CID<SD>,
    /// Card Specific Data
-    pub csd: CSD,
+    pub csd: CSD<SD>,
    /// SD CARD Configuration Register
    pub scr: SCR,
    /// SD Status
    pub status: SDStatus,
 }
-impl Card {
+#[derive(Clone, Copy, Debug, Default)]
-    /// Size in bytes
+/// eMMC storage
-    pub fn size(&self) -> u64 {
+pub struct Emmc {
-        // SDHC / SDXC / SDUC
+    /// The capacity of this card
-        u64::from(self.csd.block_count()) * 512
+    pub capacity: CardCapacity,
-    }
+    /// Operation Conditions Register
+    pub ocr: OCR<EMMC>,
+    /// Relative Card Address
+    pub rca: u16,
+    /// Card ID
+    pub cid: CID<EMMC>,
+    /// Card Specific Data
+    pub csd: CSD<EMMC>,
+    /// Extended Card Specific Data
+    pub ext_csd: ExtCSD,
 }
 #[repr(u8)]
@@ -188,22 +200,12 @@ enum PowerCtrl {
    On = 0b11,
 }
-#[repr(u32)]
+fn get_waitresp_val(rlen: ResponseLen) -> u8 {
-#[allow(dead_code)]
+    match rlen {
-#[allow(non_camel_case_types)]
+        common_cmd::ResponseLen::Zero => 0,
-enum CmdAppOper {
+        common_cmd::ResponseLen::R48 => 1,
-    VOLTAGE_WINDOW_SD = 0x8010_0000,
+        common_cmd::ResponseLen::R136 => 3,
-    HIGH_CAPACITY = 0x4000_0000,
+    }
-    SDMMC_STD_CAPACITY = 0x0000_0000,
-    SDMMC_CHECK_PATTERN = 0x0000_01AA,
-    SD_SWITCH_1_8V_CAPACITY = 0x0100_0000,
-}
-#[derive(Eq, PartialEq, Copy, Clone)]
-enum Response {
-    None = 0,
-    Short = 1,
-    Long = 3,
 }
 /// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
@@ -300,18 +302,77 @@ impl Default for Config {
    }
 }
+/// Peripheral that can be operated over SDMMC
+#[derive(Clone, Copy, Debug)]
+pub enum SdmmcPeripheral {
+    /// SD Card
+    SdCard(Card),
+    /// eMMC memory
+    Emmc(Emmc),
+}
+impl SdmmcPeripheral {
+    /// Get this peripheral's address on the SDMMC bus
+    fn get_address(&self) -> u16 {
+        match self {
+            Self::SdCard(c) => c.rca,
+            Self::Emmc(e) => e.rca,
+        }
+    }
+    /// Is this a standard or high capacity peripheral?
+    fn get_capacity(&self) -> CardCapacity {
+        match self {
+            Self::SdCard(c) => c.card_type,
+            Self::Emmc(e) => e.capacity,
+        }
+    }
+    /// Size in bytes
+    fn size(&self) -> u64 {
+        match self {
+            // SDHC / SDXC / SDUC
+            Self::SdCard(c) => u64::from(c.csd.block_count()) * 512,
+            // capacity > 2GB
+            Self::Emmc(e) => u64::from(e.ext_csd.sector_count()) * 512,
+        }
+    }
+    /// Get a mutable reference to the SD Card.
+    ///
+    /// Panics if there is another peripheral instead.
+    fn get_sd_card(&mut self) -> &mut Card {
+        match *self {
+            Self::SdCard(ref mut c) => c,
+            _ => unreachable!("SD only"),
+        }
+    }
+    /// Get a mutable reference to the eMMC.
+    ///
+    /// Panics if there is another peripheral instead.
+    fn get_emmc(&mut self) -> &mut Emmc {
+        match *self {
+            Self::Emmc(ref mut e) => e,
+            _ => unreachable!("eMMC only"),
+        }
+    }
+}
 /// Sdmmc device
-pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
+pub struct Sdmmc<'d, T: Instance> {
-    _peri: PeripheralRef<'d, T>,
+    _peri: Peri<'d, T>,
-    #[allow(unused)]
+    #[cfg(sdmmc_v1)]
-    dma: PeripheralRef<'d, Dma>,
+    dma: ChannelAndRequest<'d>,
-    clk: PeripheralRef<'d, AnyPin>,
+    clk: Peri<'d, AnyPin>,
-    cmd: PeripheralRef<'d, AnyPin>,
+    cmd: Peri<'d, AnyPin>,
-    d0: PeripheralRef<'d, AnyPin>,
+    d0: Peri<'d, AnyPin>,
-    d1: Option<PeripheralRef<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
-    d2: Option<PeripheralRef<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
-    d3: Option<PeripheralRef<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
    config: Config,
    /// Current clock to card
@@ -319,7 +380,7 @@ pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
    /// Current signalling scheme to card
    signalling: Signalling,
    /// Card
-    card: Option<Card>,
+    card: Option<SdmmcPeripheral>,
    /// An optional buffer to be used for commands
    /// This should be used if there are special memory location requirements for dma
@@ -334,19 +395,17 @@ const CMD_AF: AfType = AfType::output_pull(OutputType::PushPull, Speed::VeryHigh
 const DATA_AF: AfType = CMD_AF;
 #[cfg(sdmmc_v1)]
-impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
+impl<'d, T: Instance> Sdmmc<'d, T> {
    /// Create a new SDMMC driver, with 1 data lane.
    pub fn new_1bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, impl SdmmcDma<T>>,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
+        cmd: Peri<'d, impl CmdPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(clk, cmd, d0);
        critical_section::with(|_| {
            clk.set_as_af(clk.af_num(), CLK_AF);
            cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -355,10 +414,14 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
        Self::new_inner(
            sdmmc,
-            dma,
+            new_dma_nonopt!(dma),
-            clk.map_into(),
+            clk.into(),
-            cmd.map_into(),
+            cmd.into(),
-            d0.map_into(),
+            d0.into(),
+            None,
+            None,
+            None,
+            None,
            None,
            None,
            None,
@@ -368,19 +431,63 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
    /// Create a new SDMMC driver, with 4 data lanes.
    pub fn new_4bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dma: impl Peripheral<P = Dma> + 'd,
+        dma: Peri<'d, impl SdmmcDma<T>>,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
+        cmd: Peri<'d, impl CmdPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(clk, cmd, d0, d1, d2, d3);
+        critical_section::with(|_| {
+            clk.set_as_af(clk.af_num(), CLK_AF);
+            cmd.set_as_af(cmd.af_num(), CMD_AF);
+            d0.set_as_af(d0.af_num(), DATA_AF);
+            d1.set_as_af(d1.af_num(), DATA_AF);
+            d2.set_as_af(d2.af_num(), DATA_AF);
+            d3.set_as_af(d3.af_num(), DATA_AF);
+        });
+        Self::new_inner(
+            sdmmc,
+            new_dma_nonopt!(dma),
+            clk.into(),
+            cmd.into(),
+            d0.into(),
+            Some(d1.into()),
+            Some(d2.into()),
+            Some(d3.into()),
+            None,
+            None,
+            None,
+            None,
+            config,
+        )
+    }
+}
+#[cfg(sdmmc_v1)]
+impl<'d, T: Instance> Sdmmc<'d, T> {
+    /// Create a new SDMMC driver, with 8 data lanes.
+    pub fn new_8bit(
+        sdmmc: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        dma: Peri<'d, impl SdmmcDma<T>>,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        config: Config,
+    ) -> Self {
        critical_section::with(|_| {
            clk.set_as_af(clk.af_num(), CLK_AF);
            cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -388,35 +495,41 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
            d1.set_as_af(d1.af_num(), DATA_AF);
            d2.set_as_af(d2.af_num(), DATA_AF);
            d3.set_as_af(d3.af_num(), DATA_AF);
+            d4.set_as_af(d4.af_num(), DATA_AF);
+            d5.set_as_af(d5.af_num(), DATA_AF);
+            d6.set_as_af(d6.af_num(), DATA_AF);
+            d7.set_as_af(d7.af_num(), DATA_AF);
        });
        Self::new_inner(
            sdmmc,
-            dma,
+            new_dma_nonopt!(dma),
-            clk.map_into(),
+            clk.into(),
-            cmd.map_into(),
+            cmd.into(),
-            d0.map_into(),
+            d0.into(),
-            Some(d1.map_into()),
+            Some(d1.into()),
-            Some(d2.map_into()),
+            Some(d2.into()),
-            Some(d3.map_into()),
+            Some(d3.into()),
+            Some(d4.into()),
+            Some(d5.into()),
+            Some(d6.into()),
+            Some(d7.into()),
            config,
        )
    }
 }
 #[cfg(sdmmc_v2)]
-impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
+impl<'d, T: Instance> Sdmmc<'d, T> {
    /// Create a new SDMMC driver, with 1 data lane.
    pub fn new_1bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
+        cmd: Peri<'d, impl CmdPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(clk, cmd, d0);
        critical_section::with(|_| {
            clk.set_as_af(clk.af_num(), CLK_AF);
            cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -425,10 +538,13 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
        Self::new_inner(
            sdmmc,
-            NoDma.into_ref(),
+            clk.into(),
-            clk.map_into(),
+            cmd.into(),
-            cmd.map_into(),
+            d0.into(),
-            d0.map_into(),
+            None,
+            None,
+            None,
+            None,
            None,
            None,
            None,
@@ -438,18 +554,60 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
    /// Create a new SDMMC driver, with 4 data lanes.
    pub fn new_4bit(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        clk: impl Peripheral<P = impl CkPin<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
-        cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
+        cmd: Peri<'d, impl CmdPin<T>>,
-        d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
+        d0: Peri<'d, impl D0Pin<T>>,
-        d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
+        d1: Peri<'d, impl D1Pin<T>>,
-        d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
+        d2: Peri<'d, impl D2Pin<T>>,
-        d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
+        d3: Peri<'d, impl D3Pin<T>>,
        config: Config,
    ) -> Self {
-        into_ref!(clk, cmd, d0, d1, d2, d3);
+        critical_section::with(|_| {
+            clk.set_as_af(clk.af_num(), CLK_AF);
+            cmd.set_as_af(cmd.af_num(), CMD_AF);
+            d0.set_as_af(d0.af_num(), DATA_AF);
+            d1.set_as_af(d1.af_num(), DATA_AF);
+            d2.set_as_af(d2.af_num(), DATA_AF);
+            d3.set_as_af(d3.af_num(), DATA_AF);
+        });
+        Self::new_inner(
+            sdmmc,
+            clk.into(),
+            cmd.into(),
+            d0.into(),
+            Some(d1.into()),
+            Some(d2.into()),
+            Some(d3.into()),
+            None,
+            None,
+            None,
+            None,
+            config,
+        )
+    }
+}
+#[cfg(sdmmc_v2)]
+impl<'d, T: Instance> Sdmmc<'d, T> {
+    /// Create a new SDMMC driver, with 8 data lanes.
+    pub fn new_8bit(
+        sdmmc: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        clk: Peri<'d, impl CkPin<T>>,
+        cmd: Peri<'d, impl CmdPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        config: Config,
+    ) -> Self {
        critical_section::with(|_| {
            clk.set_as_af(clk.af_num(), CLK_AF);
            cmd.set_as_af(cmd.af_num(), CMD_AF);
@@ -457,36 +615,45 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
            d1.set_as_af(d1.af_num(), DATA_AF);
            d2.set_as_af(d2.af_num(), DATA_AF);
            d3.set_as_af(d3.af_num(), DATA_AF);
+            d4.set_as_af(d4.af_num(), DATA_AF);
+            d5.set_as_af(d5.af_num(), DATA_AF);
+            d6.set_as_af(d6.af_num(), DATA_AF);
+            d7.set_as_af(d7.af_num(), DATA_AF);
        });
        Self::new_inner(
            sdmmc,
-            NoDma.into_ref(),
+            clk.into(),
-            clk.map_into(),
+            cmd.into(),
-            cmd.map_into(),
+            d0.into(),
-            d0.map_into(),
+            Some(d1.into()),
-            Some(d1.map_into()),
+            Some(d2.into()),
-            Some(d2.map_into()),
+            Some(d3.into()),
-            Some(d3.map_into()),
+            Some(d4.into()),
+            Some(d5.into()),
+            Some(d6.into()),
+            Some(d7.into()),
            config,
        )
    }
 }
-impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
+impl<'d, T: Instance> Sdmmc<'d, T> {
    fn new_inner(
-        sdmmc: impl Peripheral<P = T> + 'd,
+        sdmmc: Peri<'d, T>,
-        dma: impl Peripheral<P = Dma> + 'd,
+        #[cfg(sdmmc_v1)] dma: ChannelAndRequest<'d>,
-        clk: PeripheralRef<'d, AnyPin>,
+        clk: Peri<'d, AnyPin>,
-        cmd: PeripheralRef<'d, AnyPin>,
+        cmd: Peri<'d, AnyPin>,
-        d0: PeripheralRef<'d, AnyPin>,
+        d0: Peri<'d, AnyPin>,
-        d1: Option<PeripheralRef<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
-        d2: Option<PeripheralRef<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
-        d3: Option<PeripheralRef<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
        config: Config,
    ) -> Self {
-        into_ref!(sdmmc, dma);
        rcc::enable_and_reset::<T>();
        T::Interrupt::unpend();
@@ -514,6 +681,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        Self {
            _peri: sdmmc,
+            #[cfg(sdmmc_v1)]
            dma,
            clk,
@@ -522,6 +690,10 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
            d1,
            d2,
            d3,
+            d4,
+            d5,
+            d6,
+            d7,
            config,
            clock: SD_INIT_FREQ,
@@ -567,7 +739,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
    #[allow(unused_variables)]
    fn prepare_datapath_read<'a>(
        config: &Config,
-        dma: &'a mut PeripheralRef<'d, Dma>,
+        #[cfg(sdmmc_v1)] dma: &'a mut ChannelAndRequest<'d>,
        buffer: &'a mut [u32],
        length_bytes: u32,
        block_size: u8,
@@ -583,16 +755,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        regs.dlenr().write(|w| w.set_datalength(length_bytes));
        #[cfg(sdmmc_v1)]
-        let transfer = unsafe {
+        let transfer = unsafe { dma.read(regs.fifor().as_ptr() as *mut u32, buffer, DMA_TRANSFER_OPTIONS) };
-            let request = dma.request();
-            Transfer::new_read(
-                dma,
-                request,
-                regs.fifor().as_ptr() as *mut u32,
-                buffer,
-                DMA_TRANSFER_OPTIONS,
-            )
-        };
        #[cfg(sdmmc_v2)]
        let transfer = {
            regs.idmabase0r().write(|w| w.set_idmabase0(buffer.as_mut_ptr() as u32));
@@ -632,14 +795,8 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        #[cfg(sdmmc_v1)]
        let transfer = unsafe {
-            let request = self.dma.request();
+            self.dma
-            Transfer::new_write(
+                .write(buffer, regs.fifor().as_ptr() as *mut u32, DMA_TRANSFER_OPTIONS)
-                &mut self.dma,
-                request,
-                buffer,
-                regs.fifor().as_ptr() as *mut u32,
-                DMA_TRANSFER_OPTIONS,
-            )
        };
        #[cfg(sdmmc_v2)]
        let transfer = {
@@ -707,168 +864,29 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        Ok(())
    }
-    /// Switch mode using CMD6.
-    ///
-    /// Attempt to set a new signalling mode. The selected
-    /// signalling mode is returned. Expects the current clock
-    /// frequency to be > 12.5MHz.
-    async fn switch_signalling_mode(&mut self, signalling: Signalling) -> Result<Signalling, Error> {
-        // NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not
-        // necessary"
-        let set_function = 0x8000_0000
-            | match signalling {
-                // See PLSS v7_10 Table 4-11
-                Signalling::DDR50 => 0xFF_FF04,
-                Signalling::SDR104 => 0xFF_1F03,
-                Signalling::SDR50 => 0xFF_1F02,
-                Signalling::SDR25 => 0xFF_FF01,
-                Signalling::SDR12 => 0xFF_FF00,
-            };
-        let status = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let regs = T::regs();
-        let on_drop = OnDrop::new(|| Self::on_drop());
-        let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, status.as_mut(), 64, 6);
-        InterruptHandler::<T>::data_interrupts(true);
-        Self::cmd(Cmd::cmd6(set_function), true)?; // CMD6
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-            let status = regs.star().read();
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-            Poll::Pending
-        })
-        .await;
-        Self::clear_interrupt_flags();
-        // Host is allowed to use the new functions at least 8
-        // clocks after the end of the switch command
-        // transaction. We know the current clock period is < 80ns,
-        // so a total delay of 640ns is required here
-        for _ in 0..300 {
-            cortex_m::asm::nop();
-        }
-        match res {
-            Ok(_) => {
-                on_drop.defuse();
-                Self::stop_datapath();
-                drop(transfer);
-                // Function Selection of Function Group 1
-                let selection = (u32::from_be(status[4]) >> 24) & 0xF;
-                match selection {
-                    0 => Ok(Signalling::SDR12),
-                    1 => Ok(Signalling::SDR25),
-                    2 => Ok(Signalling::SDR50),
-                    3 => Ok(Signalling::SDR104),
-                    4 => Ok(Signalling::DDR50),
-                    _ => Err(Error::UnsupportedCardType),
-                }
-            }
-            Err(e) => Err(e),
-        }
-    }
    /// Query the card status (CMD13, returns R1)
-    fn read_status(&self, card: &Card) -> Result<CardStatus, Error> {
+    fn read_status<Ext>(&self, card: &SdmmcPeripheral) -> Result<CardStatus<Ext>, Error>
+    where
+        CardStatus<Ext>: From<u32>,
+    {
        let regs = T::regs();
-        let rca = card.rca;
+        let rca = card.get_address();
-        Self::cmd(Cmd::card_status(rca << 16), false)?; // CMD13
+        Self::cmd(common_cmd::card_status(rca, false), false)?; // CMD13
        let r1 = regs.respr(0).read().cardstatus();
        Ok(r1.into())
    }
-    /// Reads the SD Status (ACMD13)
-    async fn read_sd_status(&mut self) -> Result<(), Error> {
-        let card = self.card.as_mut().ok_or(Error::NoCard)?;
-        let rca = card.rca;
-        let cmd_block = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-        Self::cmd(Cmd::set_block_length(64), false)?; // CMD16
-        Self::cmd(Cmd::app_cmd(rca << 16), false)?; // APP
-        let status = cmd_block;
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let regs = T::regs();
-        let on_drop = OnDrop::new(|| Self::on_drop());
-        let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, status.as_mut(), 64, 6);
-        InterruptHandler::<T>::data_interrupts(true);
-        Self::cmd(Cmd::card_status(0), true)?;
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-            let status = regs.star().read();
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-            Poll::Pending
-        })
-        .await;
-        Self::clear_interrupt_flags();
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-            for byte in status.iter_mut() {
-                *byte = u32::from_be(*byte);
-            }
-            self.card.as_mut().unwrap().status = status.0.into();
-        }
-        res
-    }
    /// Select one card and place it into the _Tranfer State_
    ///
    /// If `None` is specifed for `card`, all cards are put back into
    /// _Stand-by State_
-    fn select_card(&self, card: Option<&Card>) -> Result<(), Error> {
+    fn select_card(&self, rca: Option<u16>) -> Result<(), Error> {
        // Determine Relative Card Address (RCA) of given card
-        let rca = card.map(|c| c.rca << 16).unwrap_or(0);
+        let rca = rca.unwrap_or(0);
-        let r = Self::cmd(Cmd::sel_desel_card(rca), false);
+        let r = Self::cmd(common_cmd::select_card(rca), false);
        match (r, rca) {
            (Err(Error::Timeout), 0) => Ok(()),
            _ => r,
@@ -909,63 +927,9 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        });
    }
-    async fn get_scr(&mut self, card: &mut Card) -> Result<(), Error> {
-        // Read the the 64-bit SCR register
-        Self::cmd(Cmd::set_block_length(8), false)?; // CMD16
-        Self::cmd(Cmd::app_cmd(card.rca << 16), false)?;
-        let cmd_block = match self.cmd_block.as_deref_mut() {
-            Some(x) => x,
-            None => &mut CmdBlock::new(),
-        };
-        let scr = &mut cmd_block.0[..2];
-        // Arm `OnDrop` after the buffer, so it will be dropped first
-        let regs = T::regs();
-        let on_drop = OnDrop::new(|| Self::on_drop());
-        let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, scr, 8, 3);
-        InterruptHandler::<T>::data_interrupts(true);
-        Self::cmd(Cmd::cmd51(), true)?;
-        let res = poll_fn(|cx| {
-            T::state().register(cx.waker());
-            let status = regs.star().read();
-            if status.dcrcfail() {
-                return Poll::Ready(Err(Error::Crc));
-            }
-            if status.dtimeout() {
-                return Poll::Ready(Err(Error::Timeout));
-            }
-            #[cfg(sdmmc_v1)]
-            if status.stbiterr() {
-                return Poll::Ready(Err(Error::StBitErr));
-            }
-            if status.dataend() {
-                return Poll::Ready(Ok(()));
-            }
-            Poll::Pending
-        })
-        .await;
-        Self::clear_interrupt_flags();
-        if res.is_ok() {
-            on_drop.defuse();
-            Self::stop_datapath();
-            drop(transfer);
-            unsafe {
-                let scr_bytes = &*(&scr as *const _ as *const [u8; 8]);
-                card.scr = SCR(u64::from_be_bytes(*scr_bytes));
-            }
-        }
-        res
-    }
    /// Send command to card
    #[allow(unused_variables)]
-    fn cmd(cmd: Cmd, data: bool) -> Result<(), Error> {
+    fn cmd<R: Resp>(cmd: Cmd<R>, data: bool) -> Result<(), Error> {
        let regs = T::regs();
        Self::clear_interrupt_flags();
@@ -978,7 +942,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        // Command index and start CP State Machine
        regs.cmdr().write(|w| {
            w.set_waitint(false);
-            w.set_waitresp(cmd.resp as u8);
+            w.set_waitresp(get_waitresp_val(cmd.response_len()));
            w.set_cmdindex(cmd.cmd);
            w.set_cpsmen(true);
@@ -993,7 +957,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        });
        let mut status;
-        if cmd.resp == Response::None {
+        if cmd.response_len() == ResponseLen::Zero {
            // Wait for CMDSENT or a timeout
            while {
                status = regs.star().read();
@@ -1029,7 +993,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
            // Command index and start CP State Machine
            regs.cmdr().write(|w| {
                w.set_waitint(false);
-                w.set_waitresp(Response::Short as u8);
+                w.set_waitresp(get_waitresp_val(ResponseLen::R48));
                w.set_cmdindex(12);
                w.set_cpsmen(true);
@@ -1048,175 +1012,113 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        Self::stop_datapath();
    }
-    /// Initializes card (if present) and sets the bus at the specified frequency.
+    /// Wait for a previously started datapath transfer to complete from an interrupt.
-    pub async fn init_card(&mut self, freq: Hertz) -> Result<(), Error> {
+    #[inline]
+    async fn complete_datapath_transfer() -> Result<(), Error> {
        let regs = T::regs();
-        let ker_ck = T::frequency();
-        let bus_width = match self.d3.is_some() {
+        let res = poll_fn(|cx| {
-            true => BusWidth::Four,
+            T::state().register(cx.waker());
-            false => BusWidth::One,
+            let status = regs.star().read();
-        };
-        // While the SD/SDIO card or eMMC is in identification mode,
-        // the SDMMC_CK frequency must be no more than 400 kHz.
-        let (_bypass, clkdiv, init_clock) = unwrap!(clk_div(ker_ck, SD_INIT_FREQ.0));
-        self.clock = init_clock;
-        // CPSMACT and DPSMACT must be 0 to set WIDBUS
-        Self::wait_idle();
-        regs.clkcr().modify(|w| {
+            if status.dcrcfail() {
-            w.set_widbus(0);
+                return Poll::Ready(Err(Error::Crc));
-            w.set_clkdiv(clkdiv);
+            }
+            if status.dtimeout() {
+                return Poll::Ready(Err(Error::Timeout));
+            }
+            if status.txunderr() {
+                return Poll::Ready(Err(Error::Underrun));
+            }
            #[cfg(sdmmc_v1)]
-            w.set_bypass(_bypass);
+            if status.stbiterr() {
-        });
+                return Poll::Ready(Err(Error::StBitErr));
-        regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
-        Self::cmd(Cmd::idle(), false)?;
-        // Check if cards supports CMD8 (with pattern)
-        Self::cmd(Cmd::hs_send_ext_csd(0x1AA), false)?;
-        let r1 = regs.respr(0).read().cardstatus();
-        let mut card = if r1 == 0x1AA {
-            // Card echoed back the pattern. Must be at least v2
-            Card::default()
-        } else {
-            return Err(Error::UnsupportedCardVersion);
-        };
-        let ocr = loop {
-            // Signal that next command is a app command
-            Self::cmd(Cmd::app_cmd(0), false)?; // CMD55
-            let arg = CmdAppOper::VOLTAGE_WINDOW_SD as u32
-                | CmdAppOper::HIGH_CAPACITY as u32
-                | CmdAppOper::SD_SWITCH_1_8V_CAPACITY as u32;
-            // Initialize card
-            match Self::cmd(Cmd::app_op_cmd(arg), false) {
-                // ACMD41
-                Ok(_) => (),
-                Err(Error::Crc) => (),
-                Err(err) => return Err(err),
            }
-            let ocr: OCR = regs.respr(0).read().cardstatus().into();
+            if status.dataend() {
-            if !ocr.is_busy() {
+                return Poll::Ready(Ok(()));
-                // Power up done
-                break ocr;
            }
-        };
+            Poll::Pending
+        })
-        if ocr.high_capacity() {
+        .await;
-            // Card is SDHC or SDXC or SDUC
-            card.card_type = CardCapacity::SDHC;
-        } else {
-            card.card_type = CardCapacity::SDSC;
-        }
-        card.ocr = ocr;
-        Self::cmd(Cmd::all_send_cid(), false)?; // CMD2
-        let cid0 = regs.respr(0).read().cardstatus() as u128;
-        let cid1 = regs.respr(1).read().cardstatus() as u128;
-        let cid2 = regs.respr(2).read().cardstatus() as u128;
-        let cid3 = regs.respr(3).read().cardstatus() as u128;
-        let cid = (cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3);
-        card.cid = cid.into();
-        Self::cmd(Cmd::send_rel_addr(), false)?;
+        Self::clear_interrupt_flags();
-        card.rca = regs.respr(0).read().cardstatus() >> 16;
-        Self::cmd(Cmd::send_csd(card.rca << 16), false)?;
+        res
-        let csd0 = regs.respr(0).read().cardstatus() as u128;
+    }
-        let csd1 = regs.respr(1).read().cardstatus() as u128;
-        let csd2 = regs.respr(2).read().cardstatus() as u128;
-        let csd3 = regs.respr(3).read().cardstatus() as u128;
-        let csd = (csd0 << 96) | (csd1 << 64) | (csd2 << 32) | (csd3);
-        card.csd = csd.into();
-        self.select_card(Some(&card))?;
+    /// Read a data block.
+    #[inline]
+    pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
+        let card_capacity = self.card()?.get_capacity();
-        self.get_scr(&mut card).await?;
+        // NOTE(unsafe) DataBlock uses align 4
+        let buffer = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) };
-        // Set bus width
+        // Always read 1 block of 512 bytes
-        let (width, acmd_arg) = match bus_width {
+        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-            BusWidth::Eight => unimplemented!(),
+        let address = match card_capacity {
-            BusWidth::Four if card.scr.bus_width_four() => (BusWidth::Four, 2),
+            CardCapacity::StandardCapacity => block_idx * 512,
-            _ => (BusWidth::One, 0),
+            _ => block_idx,
        };
-        Self::cmd(Cmd::app_cmd(card.rca << 16), false)?;
+        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
-        Self::cmd(Cmd::cmd6(acmd_arg), false)?;
-        // CPSMACT and DPSMACT must be 0 to set WIDBUS
-        Self::wait_idle();
-        regs.clkcr().modify(|w| {
-            w.set_widbus(match width {
-                BusWidth::One => 0,
-                BusWidth::Four => 1,
-                BusWidth::Eight => 2,
-                _ => panic!("Invalid Bus Width"),
-            })
-        });
-        // Set Clock
-        if freq.0 <= 25_000_000 {
-            // Final clock frequency
-            self.clkcr_set_clkdiv(freq.0, width)?;
-        } else {
-            // Switch to max clock for SDR12
-            self.clkcr_set_clkdiv(25_000_000, width)?;
-        }
-        self.card = Some(card);
+        let on_drop = OnDrop::new(|| Self::on_drop());
-        // Read status
-        self.read_sd_status().await?;
-        if freq.0 > 25_000_000 {
+        let transfer = Self::prepare_datapath_read(
-            // Switch to SDR25
+            &self.config,
-            self.signalling = self.switch_signalling_mode(Signalling::SDR25).await?;
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            buffer,
+            512,
+            9,
+        );
+        InterruptHandler::<T>::data_interrupts(true);
+        Self::cmd(common_cmd::read_single_block(address), true)?;
-            if self.signalling == Signalling::SDR25 {
+        let res = Self::complete_datapath_transfer().await;
-                // Set final clock frequency
-                self.clkcr_set_clkdiv(freq.0, width)?;
-                if self.read_status(&card)?.state() != CurrentState::Transfer {
+        if res.is_ok() {
-                    return Err(Error::SignalingSwitchFailed);
+            on_drop.defuse();
-                }
+            Self::stop_datapath();
-            }
+            drop(transfer);
        }
+        res
-        // Read status after signalling change
-        self.read_sd_status().await?;
-        Ok(())
    }
-    /// Read a data block.
+    /// Read multiple data blocks.
    #[inline]
-    pub async fn read_block(&mut self, block_idx: u32, buffer: &mut DataBlock) -> Result<(), Error> {
+    pub async fn read_blocks(&mut self, block_idx: u32, blocks: &mut [DataBlock]) -> Result<(), Error> {
-        let card_capacity = self.card()?.card_type;
+        let card_capacity = self.card()?.get_capacity();
-        // NOTE(unsafe) DataBlock uses align 4
+        // NOTE(unsafe) reinterpret buffer as &mut [u32]
-        let buffer = unsafe { &mut *((&mut buffer.0) as *mut [u8; 512] as *mut [u32; 128]) };
+        let buffer = unsafe {
+            let ptr = blocks.as_mut_ptr() as *mut u32;
+            let len = blocks.len() * 128;
+            core::slice::from_raw_parts_mut(ptr, len)
+        };
        // Always read 1 block of 512 bytes
        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
        let address = match card_capacity {
-            CardCapacity::SDSC => block_idx * 512,
+            CardCapacity::StandardCapacity => block_idx * 512,
            _ => block_idx,
        };
-        Self::cmd(Cmd::set_block_length(512), false)?; // CMD16
+        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
        let regs = T::regs();
        let on_drop = OnDrop::new(|| Self::on_drop());
-        let transfer = Self::prepare_datapath_read(&self.config, &mut self.dma, buffer, 512, 9);
+        let transfer = Self::prepare_datapath_read(
+            &self.config,
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            buffer,
+            512 * blocks.len() as u32,
+            9,
+        );
        InterruptHandler::<T>::data_interrupts(true);
-        Self::cmd(Cmd::read_single_block(address), true)?;
+        Self::cmd(common_cmd::read_multiple_blocks(address), true)?;
        let res = poll_fn(|cx| {
            T::state().register(cx.waker());
@@ -1238,6 +1140,8 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
            Poll::Pending
        })
        .await;
+        Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
        Self::clear_interrupt_flags();
        if res.is_ok() {
@@ -1256,28 +1160,92 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
        let buffer = unsafe { &*((&buffer.0) as *const [u8; 512] as *const [u32; 128]) };
        // Always read 1 block of 512 bytes
-        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        //  cards are byte addressed hence the blockaddress is in multiples of 512 bytes
-        let address = match card.card_type {
+        let address = match card.get_capacity() {
-            CardCapacity::SDSC => block_idx * 512,
+            CardCapacity::StandardCapacity => block_idx * 512,
            _ => block_idx,
        };
-        Self::cmd(Cmd::set_block_length(512), false)?; // CMD16
+        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
-        let regs = T::regs();
        let on_drop = OnDrop::new(|| Self::on_drop());
        // sdmmc_v1 uses different cmd/dma order than v2, but only for writes
        #[cfg(sdmmc_v1)]
-        Self::cmd(Cmd::write_single_block(address), true)?;
+        Self::cmd(common_cmd::write_single_block(address), true)?;
        let transfer = self.prepare_datapath_write(buffer, 512, 9);
        InterruptHandler::<T>::data_interrupts(true);
        #[cfg(sdmmc_v2)]
-        Self::cmd(Cmd::write_single_block(address), true)?;
+        Self::cmd(common_cmd::write_single_block(address), true)?;
+        let res = Self::complete_datapath_transfer().await;
+        match res {
+            Ok(_) => {
+                on_drop.defuse();
+                Self::stop_datapath();
+                drop(transfer);
+                // TODO: Make this configurable
+                let mut timeout: u32 = 0x00FF_FFFF;
+                let card = self.card.as_ref().unwrap();
+                while timeout > 0 {
+                    let ready_for_data = match card {
+                        SdmmcPeripheral::Emmc(_) => self.read_status::<EMMC>(card)?.ready_for_data(),
+                        SdmmcPeripheral::SdCard(_) => self.read_status::<SD>(card)?.ready_for_data(),
+                    };
+                    if ready_for_data {
+                        return Ok(());
+                    }
+                    timeout -= 1;
+                }
+                Err(Error::SoftwareTimeout)
+            }
+            Err(e) => Err(e),
+        }
+    }
+    /// Write multiple data blocks.
+    pub async fn write_blocks(&mut self, block_idx: u32, blocks: &[DataBlock]) -> Result<(), Error> {
+        let card = self.card.as_mut().ok_or(Error::NoCard)?;
+        // NOTE(unsafe) reinterpret buffer as &[u32]
+        let buffer = unsafe {
+            let ptr = blocks.as_ptr() as *const u32;
+            let len = blocks.len() * 128;
+            core::slice::from_raw_parts(ptr, len)
+        };
+        // Always read 1 block of 512 bytes
+        // SDSC cards are byte addressed hence the blockaddress is in multiples of 512 bytes
+        let address = match card.get_capacity() {
+            CardCapacity::StandardCapacity => block_idx * 512,
+            _ => block_idx,
+        };
+        Self::cmd(common_cmd::set_block_length(512), false)?; // CMD16
+        let block_count = blocks.len();
+        let regs = T::regs();
+        let on_drop = OnDrop::new(|| Self::on_drop());
+        #[cfg(sdmmc_v1)]
+        Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
+        // Setup write command
+        let transfer = self.prepare_datapath_write(buffer, 512 * block_count as u32, 9);
+        InterruptHandler::<T>::data_interrupts(true);
+        #[cfg(sdmmc_v2)]
+        Self::cmd(common_cmd::write_multiple_blocks(address), true)?; // CMD25
        let res = poll_fn(|cx| {
            T::state().register(cx.waker());
            let status = regs.star().read();
            if status.dcrcfail() {
@@ -1286,6 +1254,9 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
            if status.dtimeout() {
                return Poll::Ready(Err(Error::Timeout));
            }
+            if status.txunderr() {
+                return Poll::Ready(Err(Error::Underrun));
+            }
            #[cfg(sdmmc_v1)]
            if status.stbiterr() {
                return Poll::Ready(Err(Error::StBitErr));
@@ -1293,9 +1264,12 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
            if status.dataend() {
                return Poll::Ready(Ok(()));
            }
            Poll::Pending
        })
        .await;
+        Self::cmd(common_cmd::stop_transmission(), false)?; // CMD12
        Self::clear_interrupt_flags();
        match res {
@@ -1326,10 +1300,10 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
    ///
    /// # Errors
    ///
-    /// Returns Error::NoCard if [`init_card`](#method.init_card)
+    /// Returns Error::NoCard if [`init_sd_card`](#method.init_sd_card) or
-    /// has not previously succeeded
+    /// [`init_emmc`](#method.init_emmc) has not previously succeeded
    #[inline]
-    pub fn card(&self) -> Result<&Card, Error> {
+    pub fn card(&self) -> Result<&SdmmcPeripheral, Error> {
        self.card.as_ref().ok_or(Error::NoCard)
    }
@@ -1345,114 +1319,490 @@ impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Sdmmc<'d, T, Dma> {
    pub fn set_cmd_block(&mut self, cmd_block: &'d mut CmdBlock) {
        self.cmd_block = Some(cmd_block)
    }
-}
-impl<'d, T: Instance, Dma: SdmmcDma<T> + 'd> Drop for Sdmmc<'d, T, Dma> {
+    async fn init_internal(&mut self, freq: Hertz, mut card: SdmmcPeripheral) -> Result<(), Error> {
-    fn drop(&mut self) {
+        let regs = T::regs();
-        T::Interrupt::disable();
+        let ker_ck = T::frequency();
-        Self::on_drop();
-        critical_section::with(|_| {
+        let bus_width = match (self.d3.is_some(), self.d7.is_some()) {
-            self.clk.set_as_disconnected();
+            (true, true) => {
-            self.cmd.set_as_disconnected();
+                if matches!(card, SdmmcPeripheral::SdCard(_)) {
-            self.d0.set_as_disconnected();
+                    return Err(Error::BusWidth);
-            if let Some(x) = &mut self.d1 {
+                }
-                x.set_as_disconnected();
+                BusWidth::Eight
            }
-            if let Some(x) = &mut self.d2 {
+            (true, false) => BusWidth::Four,
-                x.set_as_disconnected();
+            _ => BusWidth::One,
+        };
+        // While the SD/SDIO card or eMMC is in identification mode,
+        // the SDMMC_CK frequency must be no more than 400 kHz.
+        let (_bypass, clkdiv, init_clock) = unwrap!(clk_div(ker_ck, SD_INIT_FREQ.0));
+        self.clock = init_clock;
+        // CPSMACT and DPSMACT must be 0 to set WIDBUS
+        Self::wait_idle();
+        regs.clkcr().modify(|w| {
+            w.set_widbus(0);
+            w.set_clkdiv(clkdiv);
+            #[cfg(sdmmc_v1)]
+            w.set_bypass(_bypass);
+        });
+        regs.power().modify(|w| w.set_pwrctrl(PowerCtrl::On as u8));
+        Self::cmd(common_cmd::idle(), false)?;
+        match card {
+            SdmmcPeripheral::SdCard(ref mut card) => {
+                // Check if cards supports CMD8 (with pattern)
+                Self::cmd(sd_cmd::send_if_cond(1, 0xAA), false)?;
+                let cic = CIC::from(regs.respr(0).read().cardstatus());
+                if cic.pattern() != 0xAA {
+                    return Err(Error::UnsupportedCardVersion);
+                }
+                if cic.voltage_accepted() & 1 == 0 {
+                    return Err(Error::UnsupportedVoltage);
+                }
+                let ocr = loop {
+                    // Signal that next command is a app command
+                    Self::cmd(common_cmd::app_cmd(0), false)?; // CMD55
+                    // 3.2-3.3V
+                    let voltage_window = 1 << 5;
+                    // Initialize card
+                    match Self::cmd(sd_cmd::sd_send_op_cond(true, false, true, voltage_window), false) {
+                        // ACMD41
+                        Ok(_) => (),
+                        Err(Error::Crc) => (),
+                        Err(err) => return Err(err),
+                    }
+                    let ocr: OCR<SD> = regs.respr(0).read().cardstatus().into();
+                    if !ocr.is_busy() {
+                        // Power up done
+                        break ocr;
+                    }
+                };
+                if ocr.high_capacity() {
+                    // Card is SDHC or SDXC or SDUC
+                    card.card_type = CardCapacity::HighCapacity;
+                } else {
+                    card.card_type = CardCapacity::StandardCapacity;
+                }
+                card.ocr = ocr;
            }
-            if let Some(x) = &mut self.d3 {
+            SdmmcPeripheral::Emmc(ref mut emmc) => {
-                x.set_as_disconnected();
+                let ocr = loop {
+                    let high_voltage = 0b0 << 7;
+                    let access_mode = 0b10 << 29;
+                    let op_cond = high_voltage | access_mode | 0b1_1111_1111 << 15;
+                    // Initialize card
+                    match Self::cmd(emmc_cmd::send_op_cond(op_cond), false) {
+                        Ok(_) => (),
+                        Err(Error::Crc) => (),
+                        Err(err) => return Err(err),
+                    }
+                    let ocr: OCR<EMMC> = regs.respr(0).read().cardstatus().into();
+                    if !ocr.is_busy() {
+                        // Power up done
+                        break ocr;
+                    }
+                };
+                emmc.capacity = if ocr.access_mode() == 0b10 {
+                    // Card is SDHC or SDXC or SDUC
+                    CardCapacity::HighCapacity
+                } else {
+                    CardCapacity::StandardCapacity
+                };
+                emmc.ocr = ocr;
            }
-        });
+        }
-    }
-}
-/// SD card Commands
+        Self::cmd(common_cmd::all_send_cid(), false)?; // CMD2
-impl Cmd {
+        let cid0 = regs.respr(0).read().cardstatus() as u128;
-    const fn new(cmd: u8, arg: u32, resp: Response) -> Cmd {
+        let cid1 = regs.respr(1).read().cardstatus() as u128;
-        Cmd { cmd, arg, resp }
+        let cid2 = regs.respr(2).read().cardstatus() as u128;
-    }
+        let cid3 = regs.respr(3).read().cardstatus() as u128;
+        let cid = (cid0 << 96) | (cid1 << 64) | (cid2 << 32) | (cid3);
-    /// CMD0: Idle
+        match card {
-    const fn idle() -> Cmd {
+            SdmmcPeripheral::SdCard(ref mut card) => {
-        Cmd::new(0, 0, Response::None)
+                card.cid = cid.into();
-    }
-    /// CMD2: Send CID
+                Self::cmd(sd_cmd::send_relative_address(), false)?;
-    const fn all_send_cid() -> Cmd {
+                let rca = RCA::<SD>::from(regs.respr(0).read().cardstatus());
-        Cmd::new(2, 0, Response::Long)
+                card.rca = rca.address();
-    }
+            }
+            SdmmcPeripheral::Emmc(ref mut emmc) => {
+                emmc.cid = cid.into();
-    /// CMD3: Send Relative Address
+                emmc.rca = 1u16.into();
-    const fn send_rel_addr() -> Cmd {
+                Self::cmd(emmc_cmd::assign_relative_address(emmc.rca), false)?;
-        Cmd::new(3, 0, Response::Short)
+            }
-    }
+        }
-    /// CMD6: Switch Function Command
+        Self::cmd(common_cmd::send_csd(card.get_address()), false)?;
-    /// ACMD6: Bus Width
+        let csd0 = regs.respr(0).read().cardstatus() as u128;
-    const fn cmd6(arg: u32) -> Cmd {
+        let csd1 = regs.respr(1).read().cardstatus() as u128;
-        Cmd::new(6, arg, Response::Short)
+        let csd2 = regs.respr(2).read().cardstatus() as u128;
-    }
+        let csd3 = regs.respr(3).read().cardstatus() as u128;
+        let csd = (csd0 << 96) | (csd1 << 64) | (csd2 << 32) | (csd3);
-    /// CMD7: Select one card and put it into the _Tranfer State_
+        self.select_card(Some(card.get_address()))?;
-    const fn sel_desel_card(rca: u32) -> Cmd {
-        Cmd::new(7, rca, Response::Short)
+        let bus_width = match card {
-    }
+            SdmmcPeripheral::SdCard(ref mut card) => {
+                card.csd = csd.into();
+                self.get_scr(card).await?;
+                if !card.scr.bus_width_four() {
+                    BusWidth::One
+                } else {
+                    BusWidth::Four
+                }
+            }
+            SdmmcPeripheral::Emmc(ref mut emmc) => {
+                emmc.csd = csd.into();
+                bus_width
+            }
+        };
-    /// CMD8:
+        // Set bus width
-    const fn hs_send_ext_csd(arg: u32) -> Cmd {
+        let widbus = match bus_width {
-        Cmd::new(8, arg, Response::Short)
+            BusWidth::Eight => 2,
+            BusWidth::Four => 1,
+            BusWidth::One => 0,
+            _ => unreachable!(),
+        };
+        match card {
+            SdmmcPeripheral::SdCard(ref mut card) => {
+                let acmd_arg = match bus_width {
+                    BusWidth::Four if card.scr.bus_width_four() => 2,
+                    _ => 0,
+                };
+                Self::cmd(common_cmd::app_cmd(card.rca), false)?;
+                Self::cmd(sd_cmd::cmd6(acmd_arg), false)?;
+            }
+            SdmmcPeripheral::Emmc(_) => {
+                // Write bus width to ExtCSD byte 183
+                Self::cmd(
+                    emmc_cmd::modify_ext_csd(emmc_cmd::AccessMode::WriteByte, 183, widbus),
+                    false,
+                )?;
+                // Wait for ready after R1b response
+                loop {
+                    let status = self.read_status::<EMMC>(&card)?;
+                    if status.ready_for_data() {
+                        break;
+                    }
+                }
+            }
+        }
+        // CPSMACT and DPSMACT must be 0 to set WIDBUS
+        Self::wait_idle();
+        regs.clkcr().modify(|w| w.set_widbus(widbus));
+        // Set Clock
+        if freq.0 <= 25_000_000 {
+            // Final clock frequency
+            self.clkcr_set_clkdiv(freq.0, bus_width)?;
+        } else {
+            // Switch to max clock for SDR12
+            self.clkcr_set_clkdiv(25_000_000, bus_width)?;
+        }
+        self.card = Some(card);
+        match card {
+            SdmmcPeripheral::SdCard(_) => {
+                // Read status
+                self.read_sd_status().await?;
+                if freq.0 > 25_000_000 {
+                    // Switch to SDR25
+                    self.signalling = self.switch_signalling_mode(Signalling::SDR25).await?;
+                    if self.signalling == Signalling::SDR25 {
+                        // Set final clock frequency
+                        self.clkcr_set_clkdiv(freq.0, bus_width)?;
+                        if self.read_status::<SD>(self.card.as_ref().unwrap())?.state() != CurrentState::Transfer {
+                            return Err(Error::SignalingSwitchFailed);
+                        }
+                    }
+                }
+                // Read status after signalling change
+                self.read_sd_status().await?;
+            }
+            SdmmcPeripheral::Emmc(_) => {
+                self.read_ext_csd().await?;
+            }
+        }
+        Ok(())
    }
-    /// CMD9:
+    /// Initializes card (if present) and sets the bus at the specified frequency.
-    const fn send_csd(rca: u32) -> Cmd {
+    ///
-        Cmd::new(9, rca, Response::Long)
+    /// SD only.
+    pub async fn init_sd_card(&mut self, freq: Hertz) -> Result<(), Error> {
+        self.init_internal(freq, SdmmcPeripheral::SdCard(Card::default())).await
    }
-    /// CMD12:
+    /// Switch mode using CMD6.
-    //const fn stop_transmission() -> Cmd {
+    ///
-    //    Cmd::new(12, 0, Response::Short)
+    /// Attempt to set a new signalling mode. The selected
-    //}
+    /// signalling mode is returned. Expects the current clock
+    /// frequency to be > 12.5MHz.
+    ///
+    /// SD only.
+    async fn switch_signalling_mode(&mut self, signalling: Signalling) -> Result<Signalling, Error> {
+        let _ = self.card.as_mut().ok_or(Error::NoCard)?.get_sd_card();
+        // NB PLSS v7_10 4.3.10.4: "the use of SET_BLK_LEN command is not
+        // necessary"
-    /// CMD13: Ask card to send status register
+        let set_function = 0x8000_0000
-    /// ACMD13: SD Status
+            | match signalling {
-    const fn card_status(rca: u32) -> Cmd {
+                // See PLSS v7_10 Table 4-11
-        Cmd::new(13, rca, Response::Short)
+                Signalling::DDR50 => 0xFF_FF04,
-    }
+                Signalling::SDR104 => 0xFF_1F03,
+                Signalling::SDR50 => 0xFF_1F02,
+                Signalling::SDR25 => 0xFF_FF01,
+                Signalling::SDR12 => 0xFF_FF00,
+            };
+        let status = match self.cmd_block.as_deref_mut() {
+            Some(x) => x,
+            None => &mut CmdBlock::new(),
+        };
+        // Arm `OnDrop` after the buffer, so it will be dropped first
+        let on_drop = OnDrop::new(|| Self::on_drop());
-    /// CMD16:
+        let transfer = Self::prepare_datapath_read(
-    const fn set_block_length(blocklen: u32) -> Cmd {
+            &self.config,
-        Cmd::new(16, blocklen, Response::Short)
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            status.as_mut(),
+            64,
+            6,
+        );
+        InterruptHandler::<T>::data_interrupts(true);
+        Self::cmd(sd_cmd::cmd6(set_function), true)?; // CMD6
+        let res = Self::complete_datapath_transfer().await;
+        // Host is allowed to use the new functions at least 8
+        // clocks after the end of the switch command
+        // transaction. We know the current clock period is < 80ns,
+        // so a total delay of 640ns is required here
+        for _ in 0..300 {
+            cortex_m::asm::nop();
+        }
+        match res {
+            Ok(_) => {
+                on_drop.defuse();
+                Self::stop_datapath();
+                drop(transfer);
+                // Function Selection of Function Group 1
+                let selection = (u32::from_be(status[4]) >> 24) & 0xF;
+                match selection {
+                    0 => Ok(Signalling::SDR12),
+                    1 => Ok(Signalling::SDR25),
+                    2 => Ok(Signalling::SDR50),
+                    3 => Ok(Signalling::SDR104),
+                    4 => Ok(Signalling::DDR50),
+                    _ => Err(Error::UnsupportedCardType),
+                }
+            }
+            Err(e) => Err(e),
+        }
    }
-    /// CMD17: Block Read
+    /// Reads the SCR register.
-    const fn read_single_block(addr: u32) -> Cmd {
+    ///
-        Cmd::new(17, addr, Response::Short)
+    /// SD only.
+    async fn get_scr(&mut self, card: &mut Card) -> Result<(), Error> {
+        // Read the 64-bit SCR register
+        Self::cmd(common_cmd::set_block_length(8), false)?; // CMD16
+        Self::cmd(common_cmd::app_cmd(card.rca), false)?;
+        let cmd_block = match self.cmd_block.as_deref_mut() {
+            Some(x) => x,
+            None => &mut CmdBlock::new(),
+        };
+        let scr = &mut cmd_block.0[..2];
+        // Arm `OnDrop` after the buffer, so it will be dropped first
+        let on_drop = OnDrop::new(|| Self::on_drop());
+        let transfer = Self::prepare_datapath_read(
+            &self.config,
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            scr,
+            8,
+            3,
+        );
+        InterruptHandler::<T>::data_interrupts(true);
+        Self::cmd(sd_cmd::send_scr(), true)?;
+        let res = Self::complete_datapath_transfer().await;
+        if res.is_ok() {
+            on_drop.defuse();
+            Self::stop_datapath();
+            drop(transfer);
+            unsafe {
+                let scr_bytes = &*(&scr as *const _ as *const [u8; 8]);
+                card.scr = SCR(u64::from_be_bytes(*scr_bytes));
+            }
+        }
+        res
    }
-    /// CMD18: Multiple Block Read
+    /// Reads the SD Status (ACMD13)
-    //const fn read_multiple_blocks(addr: u32) -> Cmd {
+    ///
-    //    Cmd::new(18, addr, Response::Short)
+    /// SD only.
-    //}
+    async fn read_sd_status(&mut self) -> Result<(), Error> {
+        let card = self.card.as_mut().ok_or(Error::NoCard)?.get_sd_card();
+        let rca = card.rca;
+        let cmd_block = match self.cmd_block.as_deref_mut() {
+            Some(x) => x,
+            None => &mut CmdBlock::new(),
+        };
+        Self::cmd(common_cmd::set_block_length(64), false)?; // CMD16
+        Self::cmd(common_cmd::app_cmd(rca), false)?; // APP
+        let status = cmd_block;
+        // Arm `OnDrop` after the buffer, so it will be dropped first
+        let on_drop = OnDrop::new(|| Self::on_drop());
-    /// CMD24: Block Write
+        let transfer = Self::prepare_datapath_read(
-    const fn write_single_block(addr: u32) -> Cmd {
+            &self.config,
-        Cmd::new(24, addr, Response::Short)
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            status.as_mut(),
+            64,
+            6,
+        );
+        InterruptHandler::<T>::data_interrupts(true);
+        Self::cmd(sd_cmd::sd_status(), true)?;
+        let res = Self::complete_datapath_transfer().await;
+        if res.is_ok() {
+            on_drop.defuse();
+            Self::stop_datapath();
+            drop(transfer);
+            for byte in status.iter_mut() {
+                *byte = u32::from_be(*byte);
+            }
+            card.status = status.0.into();
+        }
+        res
    }
-    const fn app_op_cmd(arg: u32) -> Cmd {
+    /// Initializes eMMC and sets the bus at the specified frequency.
-        Cmd::new(41, arg, Response::Short)
+    ///
+    /// eMMC only.
+    pub async fn init_emmc(&mut self, freq: Hertz) -> Result<(), Error> {
+        self.init_internal(freq, SdmmcPeripheral::Emmc(Emmc::default())).await
    }
-    const fn cmd51() -> Cmd {
+    /// Gets the EXT_CSD register.
-        Cmd::new(51, 0, Response::Short)
+    ///
+    /// eMMC only.
+    async fn read_ext_csd(&mut self) -> Result<(), Error> {
+        let card = self.card.as_mut().ok_or(Error::NoCard)?.get_emmc();
+        // Note: cmd_block can't be used because ExtCSD is too long to fit.
+        let mut data_block = DataBlock([0u8; 512]);
+        // NOTE(unsafe) DataBlock uses align 4
+        let buffer = unsafe { &mut *((&mut data_block.0) as *mut [u8; 512] as *mut [u32; 128]) };
+        Self::cmd(common_cmd::set_block_length(512), false).unwrap(); // CMD16
+        // Arm `OnDrop` after the buffer, so it will be dropped first
+        let on_drop = OnDrop::new(|| Self::on_drop());
+        let transfer = Self::prepare_datapath_read(
+            &self.config,
+            #[cfg(sdmmc_v1)]
+            &mut self.dma,
+            buffer,
+            512,
+            9,
+        );
+        InterruptHandler::<T>::data_interrupts(true);
+        Self::cmd(emmc_cmd::send_ext_csd(), true)?;
+        let res = Self::complete_datapath_transfer().await;
+        if res.is_ok() {
+            on_drop.defuse();
+            Self::stop_datapath();
+            drop(transfer);
+            card.ext_csd = unsafe { core::mem::transmute::<_, [u32; 128]>(data_block.0) }.into();
+        }
+        res
    }
+}
+impl<'d, T: Instance> Drop for Sdmmc<'d, T> {
+    fn drop(&mut self) {
+        T::Interrupt::disable();
+        Self::on_drop();
-    /// App Command. Indicates that next command will be a app command
+        critical_section::with(|_| {
-    const fn app_cmd(rca: u32) -> Cmd {
+            self.clk.set_as_disconnected();
-        Cmd::new(55, rca, Response::Short)
+            self.cmd.set_as_disconnected();
+            self.d0.set_as_disconnected();
+            if let Some(x) = &mut self.d1 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d2 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d3 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d4 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d5 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d6 {
+                x.set_as_disconnected();
+            }
+            if let Some(x) = &mut self.d7 {
+                x.set_as_disconnected();
+            }
+        });
    }
 }
@@ -1465,7 +1815,7 @@ trait SealedInstance {
 /// SDMMC instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
    /// Interrupt for this instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
@@ -1484,15 +1834,6 @@ pin_trait!(D7Pin, Instance);
 #[cfg(sdmmc_v1)]
 dma_trait!(SdmmcDma, Instance);
-/// DMA instance trait.
-///
-/// This is only implemented for `NoDma`, since SDMMCv2 has DMA built-in, instead of
-/// using ST's system-wide DMA peripheral.
-#[cfg(sdmmc_v2)]
-pub trait SdmmcDma<T: Instance> {}
-#[cfg(sdmmc_v2)]
-impl<T: Instance> SdmmcDma<T> for NoDma {}
 foreach_peripheral!(
    (sdmmc, $inst:ident) => {
        impl SealedInstance for peripherals::$inst {
@@ -1511,3 +1852,46 @@ foreach_peripheral!(
        }
    };
 );
+impl<'d, T: Instance> block_device_driver::BlockDevice<512> for Sdmmc<'d, T> {
+    type Error = Error;
+    type Align = aligned::A4;
+    async fn read(
+        &mut self,
+        block_address: u32,
+        buf: &mut [aligned::Aligned<Self::Align, [u8; 512]>],
+    ) -> Result<(), Self::Error> {
+        // TODO: I think block_address needs to be adjusted by the partition start offset
+        if buf.len() == 1 {
+            let block = unsafe { &mut *(&mut buf[0] as *mut _ as *mut crate::sdmmc::DataBlock) };
+            self.read_block(block_address, block).await?;
+        } else {
+            let blocks: &mut [DataBlock] =
+                unsafe { core::slice::from_raw_parts_mut(buf.as_mut_ptr() as *mut DataBlock, buf.len()) };
+            self.read_blocks(block_address, blocks).await?;
+        }
+        Ok(())
+    }
+    async fn write(
+        &mut self,
+        block_address: u32,
+        buf: &[aligned::Aligned<Self::Align, [u8; 512]>],
+    ) -> Result<(), Self::Error> {
+        // TODO: I think block_address needs to be adjusted by the partition start offset
+        if buf.len() == 1 {
+            let block = unsafe { &*(&buf[0] as *const _ as *const crate::sdmmc::DataBlock) };
+            self.write_block(block_address, block).await?;
+        } else {
+            let blocks: &[DataBlock] =
+                unsafe { core::slice::from_raw_parts(buf.as_ptr() as *const DataBlock, buf.len()) };
+            self.write_blocks(block_address, blocks).await?;
+        }
+        Ok(())
+    }
+    async fn size(&mut self) -> Result<u64, Self::Error> {
+        Ok(self.card()?.size())
+    }
+}
diff --git a/embassy-stm32/src/spdifrx/mod.rs b/embassy-stm32/src/spdifrx/mod.rs
new file mode 100644
index 000000000..9c42217f0
--- /dev/null
+++ b/embassy-stm32/src/spdifrx/mod.rs
@@ -0,0 +1,333 @@
+//! S/PDIF receiver
+#![macro_use]
+#![cfg_attr(gpdma, allow(unused))]
+use core::marker::PhantomData;
+use embassy_sync::waitqueue::AtomicWaker;
+use crate::dma::ringbuffer::Error as RingbufferError;
+pub use crate::dma::word;
+#[cfg(not(gpdma))]
+use crate::dma::ReadableRingBuffer;
+use crate::dma::{Channel, TransferOptions};
+use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
+use crate::interrupt::typelevel::Interrupt;
+use crate::pac::spdifrx::Spdifrx as Regs;
+use crate::rcc::{RccInfo, SealedRccPeripheral};
+use crate::{interrupt, peripherals, Peri};
+/// Possible S/PDIF preamble types.
+#[allow(dead_code)]
+#[repr(u8)]
+enum PreambleType {
+    Unused = 0x00,
+    /// The preamble changes to preamble “B” once every 192 frames to identify the start of the block structure used to
+    /// organize the channel status and user information.
+    B = 0x01,
+    /// The first sub-frame (left or “A” channel in stereophonic operation and primary channel in monophonic operation)
+    /// normally starts with preamble “M”
+    M = 0x02,
+    /// The second sub-frame (right or “B” channel in stereophonic operation and secondary channel in monophonic
+    /// operation) always starts with preamble “W”.
+    W = 0x03,
+}
+macro_rules! new_spdifrx_pin {
+    ($name:ident, $af_type:expr) => {{
+        let pin = $name;
+        let input_sel = pin.input_sel();
+        pin.set_as_af(pin.af_num(), $af_type);
+        (Some(pin.into()), input_sel)
+    }};
+}
+macro_rules! impl_spdifrx_pin {
+    ($inst:ident, $pin:ident, $af:expr, $sel:expr) => {
+        impl crate::spdifrx::InPin<peripherals::$inst> for crate::peripherals::$pin {
+            fn af_num(&self) -> u8 {
+                $af
+            }
+            fn input_sel(&self) -> u8 {
+                $sel
+            }
+        }
+    };
+}
+/// Ring-buffered SPDIFRX driver.
+///
+/// Data is read by DMAs and stored in a ring buffer.
+#[cfg(not(gpdma))]
+pub struct Spdifrx<'d, T: Instance> {
+    _peri: Peri<'d, T>,
+    spdifrx_in: Option<Peri<'d, AnyPin>>,
+    data_ring_buffer: ReadableRingBuffer<'d, u32>,
+}
+/// Gives the address of the data register.
+fn dr_address(r: Regs) -> *mut u32 {
+    #[cfg(spdifrx_v1)]
+    let address = r.dr().as_ptr() as _;
+    #[cfg(spdifrx_h7)]
+    let address = r.fmt0_dr().as_ptr() as _; // All fmtx_dr() implementations have the same address.
+    return address;
+}
+/// Gives the address of the channel status register.
+#[allow(unused)]
+fn csr_address(r: Regs) -> *mut u32 {
+    r.csr().as_ptr() as _
+}
+/// Select the channel for capturing control information.
+pub enum ControlChannelSelection {
+    /// Capture control info from channel A.
+    A,
+    /// Capture control info from channel B.
+    B,
+}
+/// Configuration options for the SPDIFRX driver.
+pub struct Config {
+    /// Select the channel for capturing control information.
+    pub control_channel_selection: ControlChannelSelection,
+}
+/// S/PDIF errors.
+#[derive(Debug)]
+pub enum Error {
+    /// DMA overrun error.
+    RingbufferError(RingbufferError),
+    /// Left/right channel synchronization error.
+    ChannelSyncError,
+}
+impl From<RingbufferError> for Error {
+    fn from(error: RingbufferError) -> Self {
+        Self::RingbufferError(error)
+    }
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            control_channel_selection: ControlChannelSelection::A,
+        }
+    }
+}
+#[cfg(not(gpdma))]
+impl<'d, T: Instance> Spdifrx<'d, T> {
+    fn dma_opts() -> TransferOptions {
+        TransferOptions {
+            half_transfer_ir: true,
+            // new_write() and new_read() always use circular mode
+            ..Default::default()
+        }
+    }
+    /// Create a new `Spdifrx` instance.
+    pub fn new(
+        peri: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::GlobalInterrupt, GlobalInterruptHandler<T>> + 'd,
+        config: Config,
+        spdifrx_in: Peri<'d, impl InPin<T>>,
+        data_dma: Peri<'d, impl Channel + Dma<T>>,
+        data_dma_buf: &'d mut [u32],
+    ) -> Self {
+        let (spdifrx_in, input_sel) = new_spdifrx_pin!(spdifrx_in, AfType::input(Pull::None));
+        Self::setup(config, input_sel);
+        let regs = T::info().regs;
+        let dr_request = data_dma.request();
+        let dr_ring_buffer =
+            unsafe { ReadableRingBuffer::new(data_dma, dr_request, dr_address(regs), data_dma_buf, Self::dma_opts()) };
+        Self {
+            _peri: peri,
+            spdifrx_in,
+            data_ring_buffer: dr_ring_buffer,
+        }
+    }
+    fn setup(config: Config, input_sel: u8) {
+        T::info().rcc.enable_and_reset();
+        T::GlobalInterrupt::unpend();
+        unsafe { T::GlobalInterrupt::enable() };
+        let regs = T::info().regs;
+        regs.imr().write(|imr| {
+            imr.set_ifeie(true); // Enables interrupts for TERR, SERR, FERR.
+            imr.set_syncdie(true); // Enables SYNCD interrupt.
+        });
+        regs.cr().write(|cr| {
+            cr.set_spdifen(0x00); // Disable SPDIF receiver synchronization.
+            cr.set_rxdmaen(true); // Use RX DMA for data. Enabled on `read`.
+            cr.set_cbdmaen(false); // Do not capture channel info.
+            cr.set_rxsteo(true); // Operate in stereo mode.
+            cr.set_drfmt(0x01); // Data is left-aligned (MSB).
+            // Disable all status fields in the data register.
+            // Status can be obtained directly with the status register DMA.
+            cr.set_pmsk(false); // Write parity bit to the data register. FIXME: Add parity check.
+            cr.set_vmsk(false); // Write validity to the data register.
+            cr.set_cumsk(true); // Do not write C and U bits to the data register.
+            cr.set_ptmsk(false); // Write preamble bits to the data register.
+            cr.set_chsel(match config.control_channel_selection {
+                ControlChannelSelection::A => false,
+                ControlChannelSelection::B => true,
+            }); // Select channel status source.
+            cr.set_nbtr(0x02); // 16 attempts are allowed.
+            cr.set_wfa(true); // Wait for activity before going to synchronization phase.
+            cr.set_insel(input_sel); // Input pin selection.
+            #[cfg(stm32h7)]
+            cr.set_cksen(true); // Generate a symbol clock.
+            #[cfg(stm32h7)]
+            cr.set_cksbkpen(true); // Generate a backup symbol clock.
+        });
+    }
+    /// Start the SPDIFRX driver.
+    pub fn start(&mut self) {
+        self.data_ring_buffer.start();
+        T::info().regs.cr().modify(|cr| {
+            cr.set_spdifen(0x03); // Enable S/PDIF receiver.
+        });
+    }
+    /// Read from the SPDIFRX data ring buffer.
+    ///
+    /// SPDIFRX is always receiving data in the background. This function pops already-received
+    /// data from the buffer.
+    ///
+    /// If there's less than `data.len()` data in the buffer, this waits until there is.
+    pub async fn read(&mut self, data: &mut [u32]) -> Result<(), Error> {
+        self.data_ring_buffer.read_exact(data).await?;
+        let first_preamble = (data[0] >> 4) & 0b11_u32;
+        if (first_preamble as u8) == (PreambleType::W as u8) {
+            trace!("S/PDIF left/right mismatch");
+            // Resynchronize until the first sample is for the left channel.
+            self.data_ring_buffer.clear();
+            return Err(Error::ChannelSyncError);
+        };
+        for sample in data.as_mut() {
+            if (*sample & (0x0002_u32)) != 0 {
+                // Discard invalid samples, setting them to mute level.
+                *sample = 0;
+            } else {
+                // Discard status information in the lowest byte.
+                *sample &= 0xFFFFFF00;
+            }
+        }
+        Ok(())
+    }
+}
+#[cfg(not(gpdma))]
+impl<'d, T: Instance> Drop for Spdifrx<'d, T> {
+    fn drop(&mut self) {
+        T::info().regs.cr().modify(|cr| cr.set_spdifen(0x00));
+        self.spdifrx_in.as_ref().map(|x| x.set_as_disconnected());
+    }
+}
+struct State {
+    #[allow(unused)]
+    waker: AtomicWaker,
+}
+impl State {
+    const fn new() -> Self {
+        Self {
+            waker: AtomicWaker::new(),
+        }
+    }
+}
+struct Info {
+    regs: crate::pac::spdifrx::Spdifrx,
+    rcc: RccInfo,
+}
+peri_trait!(
+    irqs: [GlobalInterrupt],
+);
+/// SPIDFRX pin trait
+pub trait InPin<T: Instance>: crate::gpio::Pin {
+    /// Get the GPIO AF number needed to use this pin.
+    fn af_num(&self) -> u8;
+    /// Get the SPIDFRX INSEL number needed to use this pin.
+    fn input_sel(&self) -> u8;
+}
+dma_trait!(Dma, Instance);
+/// Global interrupt handler.
+pub struct GlobalInterruptHandler<T: Instance> {
+    _phantom: PhantomData<T>,
+}
+impl<T: Instance> interrupt::typelevel::Handler<T::GlobalInterrupt> for GlobalInterruptHandler<T> {
+    unsafe fn on_interrupt() {
+        T::state().waker.wake();
+        let regs = T::info().regs;
+        let sr = regs.sr().read();
+        if sr.serr() || sr.terr() || sr.ferr() {
+            trace!("SPDIFRX error, resync");
+            // Clear errors by disabling SPDIFRX, then reenable.
+            regs.cr().modify(|cr| cr.set_spdifen(0x00));
+            regs.cr().modify(|cr| cr.set_spdifen(0x03));
+        } else if sr.syncd() {
+            // Synchronization was successful.
+            trace!("SPDIFRX sync success");
+        }
+        // Clear interrupt flags.
+        regs.ifcr().write(|ifcr| {
+            ifcr.set_perrcf(true); // Clears parity error flag.
+            ifcr.set_ovrcf(true); // Clears overrun error flag.
+            ifcr.set_sbdcf(true); // Clears synchronization block detected flag.
+            ifcr.set_syncdcf(true); // Clears SYNCD from SR (was read above).
+        });
+    }
+}
+foreach_peripheral!(
+    (spdifrx, $inst:ident) => {
+        #[allow(private_interfaces)]
+        impl SealedInstance for peripherals::$inst {
+            fn info() -> &'static Info {
+                static INFO: Info = Info{
+                    regs: crate::pac::$inst,
+                    rcc: crate::peripherals::$inst::RCC_INFO,
+                };
+                &INFO
+            }
+            fn state() -> &'static State {
+                static STATE: State = State::new();
+                &STATE
+            }
+        }
+        impl Instance for peripherals::$inst {
+            type GlobalInterrupt = crate::_generated::peripheral_interrupts::$inst::GLOBAL;
+        }
+    };
+);
diff --git a/embassy-stm32/src/spi/mod.rs b/embassy-stm32/src/spi/mod.rs
index 20718147a..9e2ba093a 100644
--- a/embassy-stm32/src/spi/mod.rs
+++ b/embassy-stm32/src/spi/mod.rs
@@ -6,7 +6,6 @@ use core::ptr;
 use embassy_embedded_hal::SetConfig;
 use embassy_futures::join::join;
-use embassy_hal_internal::PeripheralRef;
 pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
 use crate::dma::{word, ChannelAndRequest};
@@ -15,7 +14,7 @@ use crate::mode::{Async, Blocking, Mode as PeriMode};
 use crate::pac::spi::{regs, vals, Spi as Regs};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 /// SPI error.
 #[derive(Debug, PartialEq, Eq, Clone, Copy)]
@@ -31,6 +30,21 @@ pub enum Error {
    Overrun,
 }
+impl core::fmt::Display for Error {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let message = match self {
+            Self::Framing => "Invalid Framing",
+            Self::Crc => "Hardware CRC Check Failed",
+            Self::ModeFault => "Mode Fault",
+            Self::Overrun => "Buffer Overrun",
+        };
+        write!(f, "{}", message)
+    }
+}
+impl core::error::Error for Error {}
 /// SPI bit order
 #[derive(Copy, Clone)]
 pub enum BitOrder {
@@ -55,6 +69,9 @@ pub struct Config {
    /// There are some ICs that require a pull-up on the MISO pin for some applications.
    /// If you  are unsure, you probably don't need this.
    pub miso_pull: Pull,
+    /// signal rise/fall speed (slew rate) - defaults to `Medium`.
+    /// Increase for high SPI speeds. Change to `Low` to reduce ringing.
+    pub rise_fall_speed: Speed,
 }
 impl Default for Config {
@@ -64,6 +81,7 @@ impl Default for Config {
            bit_order: BitOrder::MsbFirst,
            frequency: Hertz(1_000_000),
            miso_pull: Pull::None,
+            rise_fall_speed: Speed::VeryHigh,
        }
    }
 }
@@ -71,15 +89,15 @@ impl Default for Config {
 impl Config {
    fn raw_phase(&self) -> vals::Cpha {
        match self.mode.phase {
-            Phase::CaptureOnSecondTransition => vals::Cpha::SECONDEDGE,
+            Phase::CaptureOnSecondTransition => vals::Cpha::SECOND_EDGE,
-            Phase::CaptureOnFirstTransition => vals::Cpha::FIRSTEDGE,
+            Phase::CaptureOnFirstTransition => vals::Cpha::FIRST_EDGE,
        }
    }
    fn raw_polarity(&self) -> vals::Cpol {
        match self.mode.polarity {
-            Polarity::IdleHigh => vals::Cpol::IDLEHIGH,
+            Polarity::IdleHigh => vals::Cpol::IDLE_HIGH,
-            Polarity::IdleLow => vals::Cpol::IDLELOW,
+            Polarity::IdleLow => vals::Cpol::IDLE_LOW,
        }
    }
@@ -92,14 +110,14 @@ impl Config {
    #[cfg(gpio_v1)]
    fn sck_af(&self) -> AfType {
-        AfType::output(OutputType::PushPull, Speed::VeryHigh)
+        AfType::output(OutputType::PushPull, self.rise_fall_speed)
    }
    #[cfg(gpio_v2)]
    fn sck_af(&self) -> AfType {
        AfType::output_pull(
            OutputType::PushPull,
-            Speed::VeryHigh,
+            self.rise_fall_speed,
            match self.mode.polarity {
                Polarity::IdleLow => Pull::Down,
                Polarity::IdleHigh => Pull::Up,
@@ -111,21 +129,22 @@ impl Config {
 pub struct Spi<'d, M: PeriMode> {
    pub(crate) info: &'static Info,
    kernel_clock: Hertz,
-    sck: Option<PeripheralRef<'d, AnyPin>>,
+    sck: Option<Peri<'d, AnyPin>>,
-    mosi: Option<PeripheralRef<'d, AnyPin>>,
+    mosi: Option<Peri<'d, AnyPin>>,
-    miso: Option<PeripheralRef<'d, AnyPin>>,
+    miso: Option<Peri<'d, AnyPin>>,
    tx_dma: Option<ChannelAndRequest<'d>>,
    rx_dma: Option<ChannelAndRequest<'d>>,
    _phantom: PhantomData<M>,
    current_word_size: word_impl::Config,
+    rise_fall_speed: Speed,
 }
 impl<'d, M: PeriMode> Spi<'d, M> {
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        sck: Option<PeripheralRef<'d, AnyPin>>,
+        sck: Option<Peri<'d, AnyPin>>,
-        mosi: Option<PeripheralRef<'d, AnyPin>>,
+        mosi: Option<Peri<'d, AnyPin>>,
-        miso: Option<PeripheralRef<'d, AnyPin>>,
+        miso: Option<Peri<'d, AnyPin>>,
        tx_dma: Option<ChannelAndRequest<'d>>,
        rx_dma: Option<ChannelAndRequest<'d>>,
        config: Config,
@@ -140,6 +159,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
            rx_dma,
            current_word_size: <u8 as SealedWord>::CONFIG,
            _phantom: PhantomData,
+            rise_fall_speed: config.rise_fall_speed,
        };
        this.enable_and_init(config);
        this
@@ -174,7 +194,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                // we're doing "fake rxonly", by actually writing one
                // byte to TXDR for each byte we want to receive. if we
                // set OUTPUTDISABLED here, this hangs.
-                w.set_rxonly(vals::Rxonly::FULLDUPLEX);
+                w.set_rxonly(vals::Rxonly::FULL_DUPLEX);
                w.set_dff(<u8 as SealedWord>::CONFIG)
            });
        }
@@ -211,18 +231,18 @@ impl<'d, M: PeriMode> Spi<'d, M> {
                w.set_lsbfirst(lsbfirst);
                w.set_ssm(true);
                w.set_master(vals::Master::MASTER);
-                w.set_comm(vals::Comm::FULLDUPLEX);
+                w.set_comm(vals::Comm::FULL_DUPLEX);
                w.set_ssom(vals::Ssom::ASSERTED);
                w.set_midi(0);
                w.set_mssi(0);
                w.set_afcntr(true);
-                w.set_ssiop(vals::Ssiop::ACTIVEHIGH);
+                w.set_ssiop(vals::Ssiop::ACTIVE_HIGH);
            });
            regs.cfg1().modify(|w| {
                w.set_crcen(false);
                w.set_mbr(br);
                w.set_dsize(<u8 as SealedWord>::CONFIG);
-                w.set_fthlv(vals::Fthlv::ONEFRAME);
+                w.set_fthlv(vals::Fthlv::ONE_FRAME);
            });
            regs.cr2().modify(|w| {
                w.set_tsize(0);
@@ -243,6 +263,17 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        let br = compute_baud_rate(self.kernel_clock, config.frequency);
+        #[cfg(gpio_v2)]
+        {
+            self.rise_fall_speed = config.rise_fall_speed;
+            if let Some(sck) = self.sck.as_ref() {
+                sck.set_speed(config.rise_fall_speed);
+            }
+            if let Some(mosi) = self.mosi.as_ref() {
+                mosi.set_speed(config.rise_fall_speed);
+            }
+        }
        #[cfg(any(spi_v1, spi_f1, spi_v2))]
        self.info.regs.cr1().modify(|w| {
            w.set_cpha(cpha);
@@ -253,6 +284,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        {
+            self.info.regs.cr1().modify(|w| {
+                w.set_spe(false);
+            });
            self.info.regs.cfg2().modify(|w| {
                w.set_cpha(cpha);
                w.set_cpol(cpol);
@@ -261,6 +296,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {
            self.info.regs.cfg1().modify(|w| {
                w.set_mbr(br);
            });
+            self.info.regs.cr1().modify(|w| {
+                w.set_spe(true);
+            });
        }
        Ok(())
    }
@@ -274,12 +313,12 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        let cfg1 = self.info.regs.cfg1().read();
-        let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
+        let polarity = if cfg.cpol() == vals::Cpol::IDLE_LOW {
            Polarity::IdleLow
        } else {
            Polarity::IdleHigh
        };
-        let phase = if cfg.cpha() == vals::Cpha::FIRSTEDGE {
+        let phase = if cfg.cpha() == vals::Cpha::FIRST_EDGE {
            Phase::CaptureOnFirstTransition
        } else {
            Phase::CaptureOnSecondTransition
@@ -308,54 +347,32 @@ impl<'d, M: PeriMode> Spi<'d, M> {
            bit_order,
            frequency,
            miso_pull,
+            rise_fall_speed: self.rise_fall_speed,
        }
    }
-    fn set_word_size(&mut self, word_size: word_impl::Config) {
+    pub(crate) fn set_word_size(&mut self, word_size: word_impl::Config) {
        if self.current_word_size == word_size {
            return;
        }
+        self.info.regs.cr1().modify(|w| {
+            w.set_spe(false);
+        });
        #[cfg(any(spi_v1, spi_f1))]
-        {
+        self.info.regs.cr1().modify(|reg| {
-            self.info.regs.cr1().modify(|reg| {
+            reg.set_dff(word_size);
-                reg.set_spe(false);
+        });
-                reg.set_dff(word_size)
-            });
-            self.info.regs.cr1().modify(|reg| {
-                reg.set_spe(true);
-            });
-        }
        #[cfg(spi_v2)]
-        {
+        self.info.regs.cr2().modify(|w| {
-            self.info.regs.cr1().modify(|w| {
+            w.set_frxth(word_size.1);
-                w.set_spe(false);
+            w.set_ds(word_size.0);
-            });
+        });
-            self.info.regs.cr2().modify(|w| {
-                w.set_frxth(word_size.1);
-                w.set_ds(word_size.0);
-            });
-            self.info.regs.cr1().modify(|w| {
-                w.set_spe(true);
-            });
-        }
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
-        {
+        self.info.regs.cfg1().modify(|w| {
-            self.info.regs.cr1().modify(|w| {
+            w.set_dsize(word_size);
-                w.set_csusp(true);
+        });
-            });
-            while self.info.regs.sr().read().eot() {}
-            self.info.regs.cr1().modify(|w| {
-                w.set_spe(false);
-            });
-            self.info.regs.cfg1().modify(|w| {
-                w.set_dsize(word_size);
-            });
-            self.info.regs.cr1().modify(|w| {
-                w.set_csusp(false);
-                w.set_spe(true);
-            });
-        }
        self.current_word_size = word_size;
    }
@@ -365,9 +382,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        self.info.regs.cr1().modify(|w| w.set_spe(false));
+        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| w.set_spe(true));
        flush_rx_fifo(self.info.regs);
-        self.set_word_size(W::CONFIG);
        for word in words.iter() {
            // this cannot use `transfer_word` because on SPIv2 and higher,
            // the SPI RX state machine hangs if no physical pin is connected to the SCK AF.
@@ -402,9 +419,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        self.info.regs.cr1().modify(|w| w.set_spe(false));
+        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| w.set_spe(true));
        flush_rx_fifo(self.info.regs);
-        self.set_word_size(W::CONFIG);
        for word in words.iter_mut() {
            *word = transfer_word(self.info.regs, W::default())?;
        }
@@ -418,9 +435,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        self.info.regs.cr1().modify(|w| w.set_spe(false));
+        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| w.set_spe(true));
        flush_rx_fifo(self.info.regs);
-        self.set_word_size(W::CONFIG);
        for word in words.iter_mut() {
            *word = transfer_word(self.info.regs, *word)?;
        }
@@ -437,9 +454,9 @@ impl<'d, M: PeriMode> Spi<'d, M> {
        // needed in v3+ to avoid overrun causing the SPI RX state machine to get stuck...?
        #[cfg(any(spi_v3, spi_v4, spi_v5))]
        self.info.regs.cr1().modify(|w| w.set_spe(false));
+        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| w.set_spe(true));
        flush_rx_fifo(self.info.regs);
-        self.set_word_size(W::CONFIG);
        let len = read.len().max(write.len());
        for i in 0..len {
            let wb = write.get(i).copied().unwrap_or_default();
@@ -455,16 +472,16 @@ impl<'d, M: PeriMode> Spi<'d, M> {
 impl<'d> Spi<'d, Blocking> {
    /// Create a new blocking SPI driver.
    pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        miso: Peri<'d, impl MisoPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            new_pin!(sck, config.sck_af()),
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            new_pin!(miso, AfType::input(config.miso_pull)),
            None,
            None,
@@ -474,9 +491,9 @@ impl<'d> Spi<'d, Blocking> {
    /// Create a new blocking SPI driver, in RX-only mode (only MISO pin, no MOSI).
    pub fn new_blocking_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        miso: Peri<'d, impl MisoPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -492,15 +509,15 @@ impl<'d> Spi<'d, Blocking> {
    /// Create a new blocking SPI driver, in TX-only mode (only MOSI pin, no MISO).
    pub fn new_blocking_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            new_pin!(sck, config.sck_af()),
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            None,
            None,
            None,
@@ -512,14 +529,14 @@ impl<'d> Spi<'d, Blocking> {
    ///
    /// This can be useful for bit-banging non-SPI protocols.
    pub fn new_blocking_txonly_nosck<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            None,
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            None,
            None,
            None,
@@ -531,18 +548,18 @@ impl<'d> Spi<'d, Blocking> {
 impl<'d> Spi<'d, Async> {
    /// Create a new SPI driver.
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        miso: Peri<'d, impl MisoPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            new_pin!(sck, config.sck_af()),
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            new_pin!(miso, AfType::input(config.miso_pull)),
            new_dma!(tx_dma),
            new_dma!(rx_dma),
@@ -552,11 +569,11 @@ impl<'d> Spi<'d, Async> {
    /// Create a new SPI driver, in RX-only mode (only MISO pin, no MOSI).
    pub fn new_rxonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
+        miso: Peri<'d, impl MisoPin<T>>,
-        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        #[cfg(any(spi_v1, spi_f1, spi_v2))] tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
@@ -575,16 +592,16 @@ impl<'d> Spi<'d, Async> {
    /// Create a new SPI driver, in TX-only mode (only MOSI pin, no MISO).
    pub fn new_txonly<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        sck: impl Peripheral<P = impl SckPin<T>> + 'd,
+        sck: Peri<'d, impl SckPin<T>>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            new_pin!(sck, config.sck_af()),
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            None,
            new_dma!(tx_dma),
            None,
@@ -596,15 +613,15 @@ impl<'d> Spi<'d, Async> {
    ///
    /// This can be useful for bit-banging non-SPI protocols.
    pub fn new_txonly_nosck<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
+        mosi: Peri<'d, impl MosiPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
        config: Config,
    ) -> Self {
        Self::new_inner(
            peri,
            None,
-            new_pin!(mosi, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(mosi, AfType::output(OutputType::PushPull, config.rise_fall_speed)),
            None,
            new_dma!(tx_dma),
            None,
@@ -615,9 +632,9 @@ impl<'d> Spi<'d, Async> {
    #[cfg(stm32wl)]
    /// Useful for on chip peripherals like SUBGHZ which are hardwired.
    pub fn new_subghz<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
    ) -> Self {
        // see RM0453 rev 1 section 7.2.13 page 291
        // The SUBGHZSPI_SCK frequency is obtained by PCLK3 divided by two.
@@ -634,7 +651,7 @@ impl<'d> Spi<'d, Async> {
    #[allow(dead_code)]
    pub(crate) fn new_internal<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        tx_dma: Option<ChannelAndRequest<'d>>,
        rx_dma: Option<ChannelAndRequest<'d>>,
        config: Config,
@@ -648,10 +665,10 @@ impl<'d> Spi<'d, Async> {
            return Ok(());
        }
-        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| {
            w.set_spe(false);
        });
+        self.set_word_size(W::CONFIG);
        let tx_dst = self.info.regs.tx_ptr();
        let tx_f = unsafe { self.tx_dma.as_mut().unwrap().write(data, tx_dst, Default::default()) };
@@ -685,6 +702,8 @@ impl<'d> Spi<'d, Async> {
            w.set_spe(false);
        });
+        self.set_word_size(W::CONFIG);
        let comm = regs.cfg2().modify(|w| {
            let prev = w.comm();
            w.set_comm(vals::Comm::RECEIVER);
@@ -696,8 +715,8 @@ impl<'d> Spi<'d, Async> {
            w.i2smod().then(|| {
                let prev = w.i2scfg();
                w.set_i2scfg(match prev {
-                    vals::I2scfg::SLAVERX | vals::I2scfg::SLAVEFULLDUPLEX => vals::I2scfg::SLAVERX,
+                    vals::I2scfg::SLAVE_RX | vals::I2scfg::SLAVE_FULL_DUPLEX => vals::I2scfg::SLAVE_RX,
-                    vals::I2scfg::MASTERRX | vals::I2scfg::MASTERFULLDUPLEX => vals::I2scfg::MASTERRX,
+                    vals::I2scfg::MASTER_RX | vals::I2scfg::MASTER_FULL_DUPLEX => vals::I2scfg::MASTER_RX,
                    _ => panic!("unsupported configuration"),
                });
                prev
@@ -707,7 +726,6 @@ impl<'d> Spi<'d, Async> {
        let rx_src = regs.rx_ptr();
        for mut chunk in data.chunks_mut(u16::max_value().into()) {
-            self.set_word_size(W::CONFIG);
            set_rxdmaen(regs, true);
            let tsize = chunk.len();
@@ -765,12 +783,12 @@ impl<'d> Spi<'d, Async> {
            return Ok(());
        }
-        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| {
            w.set_spe(false);
        });
+        self.set_word_size(W::CONFIG);
        // SPIv3 clears rxfifo on SPE=0
        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
        flush_rx_fifo(self.info.regs);
@@ -783,7 +801,7 @@ impl<'d> Spi<'d, Async> {
        let rx_f = unsafe { self.rx_dma.as_mut().unwrap().read(rx_src, data, Default::default()) };
        let tx_dst = self.info.regs.tx_ptr();
-        let clock_byte = 0x00u8;
+        let clock_byte = W::default();
        let tx_f = unsafe {
            self.tx_dma
                .as_mut()
@@ -813,11 +831,12 @@ impl<'d> Spi<'d, Async> {
            return Ok(());
        }
-        self.set_word_size(W::CONFIG);
        self.info.regs.cr1().modify(|w| {
            w.set_spe(false);
        });
+        self.set_word_size(W::CONFIG);
        // SPIv3 clears rxfifo on SPE=0
        #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
        flush_rx_fifo(self.info.regs);
@@ -827,7 +846,7 @@ impl<'d> Spi<'d, Async> {
        let rx_src = self.info.regs.rx_ptr();
        let rx_f = unsafe { self.rx_dma.as_mut().unwrap().read_raw(rx_src, read, Default::default()) };
-        let tx_dst = self.info.regs.tx_ptr();
+        let tx_dst: *mut W = self.info.regs.tx_ptr();
        let tx_f = unsafe {
            self.tx_dma
                .as_mut()
@@ -915,7 +934,7 @@ fn compute_frequency(kernel_clock: Hertz, br: Br) -> Hertz {
    kernel_clock / div
 }
-trait RegsExt {
+pub(crate) trait RegsExt {
    fn tx_ptr<W>(&self) -> *mut W;
    fn rx_ptr<W>(&self) -> *mut W;
 }
@@ -1003,7 +1022,7 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
    }
 }
-fn flush_rx_fifo(regs: Regs) {
+pub(crate) fn flush_rx_fifo(regs: Regs) {
    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
    while regs.sr().read().rxne() {
        #[cfg(not(spi_v2))]
@@ -1017,7 +1036,7 @@ fn flush_rx_fifo(regs: Regs) {
    }
 }
-fn set_txdmaen(regs: Regs, val: bool) {
+pub(crate) fn set_txdmaen(regs: Regs, val: bool) {
    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
    regs.cr2().modify(|reg| {
        reg.set_txdmaen(val);
@@ -1028,7 +1047,7 @@ fn set_txdmaen(regs: Regs, val: bool) {
    });
 }
-fn set_rxdmaen(regs: Regs, val: bool) {
+pub(crate) fn set_rxdmaen(regs: Regs, val: bool) {
    #[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
    regs.cr2().modify(|reg| {
        reg.set_rxdmaen(val);
@@ -1189,13 +1208,13 @@ impl<'d, W: Word> embedded_hal_async::spi::SpiBus<W> for Spi<'d, Async> {
    }
 }
-trait SealedWord {
+pub(crate) trait SealedWord {
    const CONFIG: word_impl::Config;
 }
 /// Word sizes usable for SPI.
 #[allow(private_bounds)]
-pub trait Word: word::Word + SealedWord {}
+pub trait Word: word::Word + SealedWord + Default {}
 macro_rules! impl_word {
    ($T:ty, $config:expr) => {
diff --git a/embassy-stm32/src/time.rs b/embassy-stm32/src/time.rs
index 802ff41ce..532877f70 100644
--- a/embassy-stm32/src/time.rs
+++ b/embassy-stm32/src/time.rs
@@ -1,12 +1,25 @@
 //! Time units
+use core::fmt::Display;
 use core::ops::{Div, Mul};
 /// Hertz
 #[derive(Eq, PartialEq, Ord, PartialOrd, Clone, Copy, Debug)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub struct Hertz(pub u32);
+impl Display for Hertz {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "{} Hz", self.0)
+    }
+}
+#[cfg(feature = "defmt")]
+impl defmt::Format for Hertz {
+    fn format(&self, f: defmt::Formatter) {
+        defmt::write!(f, "{=u32} Hz", self.0)
+    }
+}
 impl Hertz {
    /// Create a `Hertz` from the given hertz.
    pub const fn hz(hertz: u32) -> Self {
diff --git a/embassy-stm32/src/time_driver.rs b/embassy-stm32/src/time_driver.rs
index f8041bf1e..7db74bdf6 100644
--- a/embassy-stm32/src/time_driver.rs
+++ b/embassy-stm32/src/time_driver.rs
@@ -1,13 +1,13 @@
 #![allow(non_snake_case)]
-use core::cell::Cell;
+use core::cell::{Cell, RefCell};
-use core::sync::atomic::{compiler_fence, AtomicU32, AtomicU8, Ordering};
+use core::sync::atomic::{compiler_fence, AtomicU32, Ordering};
-use core::{mem, ptr};
 use critical_section::CriticalSection;
 use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
 use embassy_sync::blocking_mutex::Mutex;
-use embassy_time_driver::{AlarmHandle, Driver, TICK_HZ};
+use embassy_time_driver::{Driver, TICK_HZ};
+use embassy_time_queue_utils::Queue;
 use stm32_metapac::timer::{regs, TimGp16};
 use crate::interrupt::typelevel::Interrupt;
@@ -24,18 +24,6 @@ use crate::{interrupt, peripherals};
 // additional CC capabilities to provide timer alarms to embassy-time. embassy-time requires AT LEAST
 // one alarm to be allocatable, which means timers that only have CC1, such as TIM16/TIM17, are not
 // candidates for use as an embassy-time driver provider. (a.k.a 1CH and 1CH_CMP are not, others are good.)
-//
-// The values of ALARM_COUNT below are not the TOTAL CC registers available, but rather the number
-// available after reserving CC1 for regular time keeping. For example, TIM2 has four CC registers:
-// CC1, CC2, CC3, and CC4, so it can provide ALARM_COUNT = 3.
-cfg_if::cfg_if! {
-    if #[cfg(any(time_driver_tim9, time_driver_tim12, time_driver_tim15, time_driver_tim21, time_driver_tim22))] {
-        const ALARM_COUNT: usize = 1;
-    } else {
-        const ALARM_COUNT: usize = 3;
-    }
-}
 #[cfg(time_driver_tim1)]
 type T = peripherals::TIM1;
@@ -75,14 +63,6 @@ foreach_interrupt! {
            DRIVER.on_interrupt()
        }
    };
-    (TIM1, timer, $block:ident, CC, $irq:ident) => {
-        #[cfg(time_driver_tim1)]
-        #[cfg(feature = "rt")]
-        #[interrupt]
-        fn $irq() {
-            DRIVER.on_interrupt()
-        }
-    };
    (TIM2, timer, $block:ident, CC, $irq:ident) => {
        #[cfg(time_driver_tim2)]
        #[cfg(feature = "rt")]
@@ -123,14 +103,6 @@ foreach_interrupt! {
            DRIVER.on_interrupt()
        }
    };
-    (TIM8, timer, $block:ident, CC, $irq:ident) => {
-        #[cfg(time_driver_tim8)]
-        #[cfg(feature = "rt")]
-        #[interrupt]
-        fn $irq() {
-            DRIVER.on_interrupt()
-        }
-    };
    (TIM9, timer, $block:ident, CC, $irq:ident) => {
        #[cfg(time_driver_tim9)]
        #[cfg(feature = "rt")]
@@ -163,14 +135,6 @@ foreach_interrupt! {
            DRIVER.on_interrupt()
        }
    };
-    (TIM20, timer, $block:ident, CC, $irq:ident) => {
-        #[cfg(time_driver_tim20)]
-        #[cfg(feature = "rt")]
-        #[interrupt]
-        fn $irq() {
-            DRIVER.on_interrupt()
-        }
-    };
    (TIM21, timer, $block:ident, CC, $irq:ident) => {
        #[cfg(time_driver_tim21)]
        #[cfg(feature = "rt")]
@@ -232,11 +196,6 @@ fn calc_now(period: u32, counter: u16) -> u64 {
 struct AlarmState {
    timestamp: Cell<u64>,
-    // This is really a Option<(fn(*mut ()), *mut ())>
-    // but fn pointers aren't allowed in const yet
-    callback: Cell<*const ()>,
-    ctx: Cell<*mut ()>,
 }
 unsafe impl Send for AlarmState {}
@@ -245,8 +204,6 @@ impl AlarmState {
    const fn new() -> Self {
        Self {
            timestamp: Cell::new(u64::MAX),
-            callback: Cell::new(ptr::null()),
-            ctx: Cell::new(ptr::null_mut()),
        }
    }
 }
@@ -254,22 +211,18 @@ impl AlarmState {
 pub(crate) struct RtcDriver {
    /// Number of 2^15 periods elapsed since boot.
    period: AtomicU32,
-    alarm_count: AtomicU8,
+    alarm: Mutex<CriticalSectionRawMutex, AlarmState>,
-    /// Timestamp at which to fire alarm. u64::MAX if no alarm is scheduled.
-    alarms: Mutex<CriticalSectionRawMutex, [AlarmState; ALARM_COUNT]>,
    #[cfg(feature = "low-power")]
    rtc: Mutex<CriticalSectionRawMutex, Cell<Option<&'static Rtc>>>,
+    queue: Mutex<CriticalSectionRawMutex, RefCell<Queue>>,
 }
-#[allow(clippy::declare_interior_mutable_const)]
-const ALARM_STATE_NEW: AlarmState = AlarmState::new();
 embassy_time_driver::time_driver_impl!(static DRIVER: RtcDriver = RtcDriver {
    period: AtomicU32::new(0),
-    alarm_count: AtomicU8::new(0),
+    alarm: Mutex::const_new(CriticalSectionRawMutex::new(), AlarmState::new()),
-    alarms: Mutex::const_new(CriticalSectionRawMutex::new(), [ALARM_STATE_NEW; ALARM_COUNT]),
    #[cfg(feature = "low-power")]
    rtc: Mutex::const_new(CriticalSectionRawMutex::new(), Cell::new(None)),
+    queue: Mutex::new(RefCell::new(Queue::new()))
 });
 impl RtcDriver {
@@ -293,9 +246,9 @@ impl RtcDriver {
        r.arr().write(|w| w.set_arr(u16::MAX));
        // Set URS, generate update and clear URS
-        r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTERONLY));
+        r.cr1().modify(|w| w.set_urs(vals::Urs::COUNTER_ONLY));
        r.egr().write(|w| w.set_ug(true));
-        r.cr1().modify(|w| w.set_urs(vals::Urs::ANYEVENT));
+        r.cr1().modify(|w| w.set_urs(vals::Urs::ANY_EVENT));
        // Mid-way point
        r.ccr(0).write(|w| w.set_ccr(0x8000));
@@ -315,7 +268,6 @@ impl RtcDriver {
    fn on_interrupt(&self) {
        let r = regs_gp16();
-        // XXX: reduce the size of this critical section ?
        critical_section::with(|cs| {
            let sr = r.sr().read();
            let dier = r.dier().read();
@@ -335,10 +287,9 @@ impl RtcDriver {
                self.next_period();
            }
-            for n in 0..ALARM_COUNT {
+            let n = 0;
-                if sr.ccif(n + 1) && dier.ccie(n + 1) {
+            if sr.ccif(n + 1) && dier.ccie(n + 1) {
-                    self.trigger_alarm(n, cs);
+                self.trigger_alarm(cs);
-                }
            }
        })
    }
@@ -353,36 +304,23 @@ impl RtcDriver {
        critical_section::with(move |cs| {
            r.dier().modify(move |w| {
-                for n in 0..ALARM_COUNT {
+                let n = 0;
-                    let alarm = &self.alarms.borrow(cs)[n];
+                let alarm = self.alarm.borrow(cs);
-                    let at = alarm.timestamp.get();
+                let at = alarm.timestamp.get();
-                    if at < t + 0xc000 {
+                if at < t + 0xc000 {
-                        // just enable it. `set_alarm` has already set the correct CCR val.
+                    // just enable it. `set_alarm` has already set the correct CCR val.
-                        w.set_ccie(n + 1, true);
+                    w.set_ccie(n + 1, true);
-                    }
                }
            })
        })
    }
-    fn get_alarm<'a>(&'a self, cs: CriticalSection<'a>, alarm: AlarmHandle) -> &'a AlarmState {
+    fn trigger_alarm(&self, cs: CriticalSection) {
-        // safety: we're allowed to assume the AlarmState is created by us, and
+        let mut next = self.queue.borrow(cs).borrow_mut().next_expiration(self.now());
-        // we never create one that's out of bounds.
+        while !self.set_alarm(cs, next) {
-        unsafe { self.alarms.borrow(cs).get_unchecked(alarm.id() as usize) }
+            next = self.queue.borrow(cs).borrow_mut().next_expiration(self.now());
-    }
+        }
-    fn trigger_alarm(&self, n: usize, cs: CriticalSection) {
-        let alarm = &self.alarms.borrow(cs)[n];
-        alarm.timestamp.set(u64::MAX);
-        // Call after clearing alarm, so the callback can set another alarm.
-        // safety:
-        // - we can ignore the possibility of `f` being unset (null) because of the safety contract of `allocate_alarm`.
-        // - other than that we only store valid function pointers into alarm.callback
-        let f: fn(*mut ()) = unsafe { mem::transmute(alarm.callback.get()) };
-        f(alarm.ctx.get());
    }
    /*
@@ -394,14 +332,7 @@ impl RtcDriver {
    fn time_until_next_alarm(&self, cs: CriticalSection) -> embassy_time::Duration {
        let now = self.now() + 32;
-        embassy_time::Duration::from_ticks(
+        embassy_time::Duration::from_ticks(self.alarm.borrow(cs).timestamp.get().saturating_sub(now))
-            self.alarms
-                .borrow(cs)
-                .iter()
-                .map(|alarm: &AlarmState| alarm.timestamp.get().saturating_sub(now))
-                .min()
-                .unwrap_or(u64::MAX),
-        )
    }
    #[cfg(feature = "low-power")]
@@ -436,12 +367,12 @@ impl RtcDriver {
        self.period.store(period, Ordering::SeqCst);
        regs_gp16().cnt().write(|w| w.set_cnt(cnt as u16));
-        // Now, recompute all alarms
+        // Now, recompute alarm
-        for i in 0..ALARM_COUNT {
+        let alarm = self.alarm.borrow(cs);
-            let alarm_handle = unsafe { AlarmHandle::new(i as u8) };
-            let alarm = self.get_alarm(cs, alarm_handle);
-            self.set_alarm(alarm_handle, alarm.timestamp.get());
+        if !self.set_alarm(cs, alarm.timestamp.get()) {
+            // If the alarm timestamp has passed, we need to trigger it
+            self.trigger_alarm(cs);
        }
    }
@@ -513,82 +444,71 @@ impl RtcDriver {
            regs_gp16().cr1().modify(|w| w.set_cen(true));
        })
    }
-}
-impl Driver for RtcDriver {
+    fn set_alarm(&self, cs: CriticalSection, timestamp: u64) -> bool {
-    fn now(&self) -> u64 {
        let r = regs_gp16();
-        let period = self.period.load(Ordering::Relaxed);
+        let n = 0;
-        compiler_fence(Ordering::Acquire);
+        self.alarm.borrow(cs).timestamp.set(timestamp);
-        let counter = r.cnt().read().cnt();
-        calc_now(period, counter)
-    }
-    unsafe fn allocate_alarm(&self) -> Option<AlarmHandle> {
+        let t = self.now();
-        critical_section::with(|_| {
+        if timestamp <= t {
-            let id = self.alarm_count.load(Ordering::Relaxed);
+            // If alarm timestamp has passed the alarm will not fire.
-            if id < ALARM_COUNT as u8 {
+            // Disarm the alarm and return `false` to indicate that.
-                self.alarm_count.store(id + 1, Ordering::Relaxed);
+            r.dier().modify(|w| w.set_ccie(n + 1, false));
-                Some(AlarmHandle::new(id))
-            } else {
-                None
-            }
-        })
-    }
-    fn set_alarm_callback(&self, alarm: AlarmHandle, callback: fn(*mut ()), ctx: *mut ()) {
+            self.alarm.borrow(cs).timestamp.set(u64::MAX);
-        critical_section::with(|cs| {
-            let alarm = self.get_alarm(cs, alarm);
-            alarm.callback.set(callback as *const ());
+            return false;
-            alarm.ctx.set(ctx);
+        }
-        })
-    }
-    fn set_alarm(&self, alarm: AlarmHandle, timestamp: u64) -> bool {
+        // Write the CCR value regardless of whether we're going to enable it now or not.
-        critical_section::with(|cs| {
+        // This way, when we enable it later, the right value is already set.
-            let r = regs_gp16();
+        r.ccr(n + 1).write(|w| w.set_ccr(timestamp as u16));
-            let n = alarm.id() as usize;
+        // Enable it if it'll happen soon. Otherwise, `next_period` will enable it.
-            let alarm = self.get_alarm(cs, alarm);
+        let diff = timestamp - t;
-            alarm.timestamp.set(timestamp);
+        r.dier().modify(|w| w.set_ccie(n + 1, diff < 0xc000));
-            let t = self.now();
+        // Reevaluate if the alarm timestamp is still in the future
-            if timestamp <= t {
+        let t = self.now();
-                // If alarm timestamp has passed the alarm will not fire.
+        if timestamp <= t {
-                // Disarm the alarm and return `false` to indicate that.
+            // If alarm timestamp has passed since we set it, we have a race condition and
-                r.dier().modify(|w| w.set_ccie(n + 1, false));
+            // the alarm may or may not have fired.
+            // Disarm the alarm and return `false` to indicate that.
+            // It is the caller's responsibility to handle this ambiguity.
+            r.dier().modify(|w| w.set_ccie(n + 1, false));
-                alarm.timestamp.set(u64::MAX);
+            self.alarm.borrow(cs).timestamp.set(u64::MAX);
-                return false;
+            return false;
-            }
+        }
-            // Write the CCR value regardless of whether we're going to enable it now or not.
+        // We're confident the alarm will ring in the future.
-            // This way, when we enable it later, the right value is already set.
+        true
-            r.ccr(n + 1).write(|w| w.set_ccr(timestamp as u16));
+    }
+}
-            // Enable it if it'll happen soon. Otherwise, `next_period` will enable it.
+impl Driver for RtcDriver {
-            let diff = timestamp - t;
+    fn now(&self) -> u64 {
-            r.dier().modify(|w| w.set_ccie(n + 1, diff < 0xc000));
+        let r = regs_gp16();
-            // Reevaluate if the alarm timestamp is still in the future
+        let period = self.period.load(Ordering::Relaxed);
-            let t = self.now();
+        compiler_fence(Ordering::Acquire);
-            if timestamp <= t {
+        let counter = r.cnt().read().cnt();
-                // If alarm timestamp has passed since we set it, we have a race condition and
+        calc_now(period, counter)
-                // the alarm may or may not have fired.
+    }
-                // Disarm the alarm and return `false` to indicate that.
-                // It is the caller's responsibility to handle this ambiguity.
-                r.dier().modify(|w| w.set_ccie(n + 1, false));
-                alarm.timestamp.set(u64::MAX);
+    fn schedule_wake(&self, at: u64, waker: &core::task::Waker) {
+        critical_section::with(|cs| {
+            let mut queue = self.queue.borrow(cs).borrow_mut();
-                return false;
+            if queue.schedule_wake(at, waker) {
+                let mut next = queue.next_expiration(self.now());
+                while !self.set_alarm(cs, next) {
+                    next = queue.next_expiration(self.now());
+                }
            }
-            // We're confident the alarm will ring in the future.
-            true
        })
    }
 }
diff --git a/embassy-stm32/src/timer/complementary_pwm.rs b/embassy-stm32/src/timer/complementary_pwm.rs
index 46ccbf3df..8eec6c0c7 100644
--- a/embassy-stm32/src/timer/complementary_pwm.rs
+++ b/embassy-stm32/src/timer/complementary_pwm.rs
@@ -2,7 +2,6 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use stm32_metapac::timer::vals::Ckd;
 use super::low_level::{CountingMode, OutputPolarity, Timer};
@@ -14,13 +13,13 @@ use super::{
 use crate::gpio::{AnyPin, OutputType};
 use crate::time::Hertz;
 use crate::timer::low_level::OutputCompareMode;
-use crate::Peripheral;
+use crate::Peri;
 /// Complementary PWM pin wrapper.
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct ComplementaryPwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, C)>,
 }
@@ -28,8 +27,7 @@ macro_rules! complementary_channel_impl {
    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
        impl<'d, T: AdvancedInstance4Channel> ComplementaryPwmPin<'d, T, $channel> {
            #[doc = concat!("Create a new ", stringify!($channel), " complementary PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                into_ref!(pin);
                critical_section::with(|_| {
                    pin.set_low();
                    pin.set_as_af(
@@ -38,7 +36,7 @@ macro_rules! complementary_channel_impl {
                    );
                });
                ComplementaryPwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -60,7 +58,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
    /// Create a new complementary PWM driver.
    #[allow(clippy::too_many_arguments)]
    pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
        _ch1: Option<PwmPin<'d, T, Ch1>>,
        _ch1n: Option<ComplementaryPwmPin<'d, T, Ch1>>,
        _ch2: Option<PwmPin<'d, T, Ch2>>,
@@ -75,7 +73,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
        Self::new_inner(tim, freq, counting_mode)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
        let mut this = Self { inner: Timer::new(tim) };
        this.inner.set_counting_mode(counting_mode);
@@ -116,7 +114,7 @@ impl<'d, T: AdvancedInstance4Channel> ComplementaryPwm<'d, T> {
        } else {
            1u8
        };
-        self.inner.set_frequency(freq * multiplier);
+        self.inner.set_frequency_internal(freq * multiplier, 16);
    }
    /// Get max duty value.
@@ -242,11 +240,11 @@ fn compute_dead_time_value(value: u16) -> (Ckd, u8) {
        let (these_bits, result) = if target < 128 {
            (target as u8, target)
        } else if target < 255 {
-            (64 + (target / 2) as u8, (target - target % 2))
+            ((64 + (target / 2) as u8) | 128, (target - target % 2))
        } else if target < 508 {
-            (32 + (target / 8) as u8, (target - target % 8))
+            ((32 + (target / 8) as u8) | 192, (target - target % 8))
        } else if target < 1008 {
-            (32 + (target / 16) as u8, (target - target % 16))
+            ((32 + (target / 16) as u8) | 224, (target - target % 16))
        } else {
            (u8::MAX, 1008)
        };
@@ -302,7 +300,7 @@ mod tests {
            TestRun {
                value: 400,
                ckd: Ckd::DIV1,
-                bits: 32 + (400u16 / 8) as u8,
+                bits: 210,
            },
            TestRun {
                value: 600,
diff --git a/embassy-stm32/src/timer/input_capture.rs b/embassy-stm32/src/timer/input_capture.rs
index 341ac2c04..ec8b1ddf1 100644
--- a/embassy-stm32/src/timer/input_capture.rs
+++ b/embassy-stm32/src/timer/input_capture.rs
@@ -5,32 +5,22 @@ use core::marker::PhantomData;
 use core::pin::Pin;
 use core::task::{Context, Poll};
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use super::low_level::{CountingMode, FilterValue, InputCaptureMode, InputTISelection, Timer};
 use super::{
    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin,
    GeneralInstance4Channel,
 };
+pub use super::{Ch1, Ch2, Ch3, Ch4};
 use crate::gpio::{AfType, AnyPin, Pull};
 use crate::interrupt::typelevel::{Binding, Interrupt};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
-/// Channel 1 marker type.
-pub enum Ch1 {}
-/// Channel 2 marker type.
-pub enum Ch2 {}
-/// Channel 3 marker type.
-pub enum Ch3 {}
-/// Channel 4 marker type.
-pub enum Ch4 {}
 /// Capture pin wrapper.
 ///
 /// This wraps a pin to make it usable with capture.
 pub struct CapturePin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, C)>,
 }
@@ -38,11 +28,10 @@ macro_rules! channel_impl {
    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
        impl<'d, T: GeneralInstance4Channel> CapturePin<'d, T, $channel> {
            #[doc = concat!("Create a new ", stringify!($channel), " capture pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, pull: Pull) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
-                into_ref!(pin);
                pin.set_as_af(pin.af_num(), AfType::input(pull));
                CapturePin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -63,7 +52,7 @@ pub struct InputCapture<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
    /// Create a new input capture driver.
    pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
        _ch1: Option<CapturePin<'d, T, Ch1>>,
        _ch2: Option<CapturePin<'d, T, Ch2>>,
        _ch3: Option<CapturePin<'d, T, Ch3>>,
@@ -75,7 +64,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
        Self::new_inner(tim, freq, counting_mode)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
        let mut this = Self { inner: Timer::new(tim) };
        this.inner.set_counting_mode(counting_mode);
@@ -129,7 +118,7 @@ impl<'d, T: GeneralInstance4Channel> InputCapture<'d, T> {
        // Configuration steps from ST RM0390 (STM32F446) chapter 17.3.5
        // or ST RM0008 (STM32F103) chapter 15.3.5 Input capture mode
        self.inner.set_input_ti_selection(channel, tisel);
-        self.inner.set_input_capture_filter(channel, FilterValue::NOFILTER);
+        self.inner.set_input_capture_filter(channel, FilterValue::NO_FILTER);
        self.inner.set_input_capture_mode(channel, mode);
        self.inner.set_input_capture_prescaler(channel, 0);
        self.inner.enable_channel(channel, true);
diff --git a/embassy-stm32/src/timer/low_level.rs b/embassy-stm32/src/timer/low_level.rs
index e643722aa..dc8ceb725 100644
--- a/embassy-stm32/src/timer/low_level.rs
+++ b/embassy-stm32/src/timer/low_level.rs
@@ -6,7 +6,9 @@
 //!
 //! The available functionality depends on the timer type.
-use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
+use core::mem::ManuallyDrop;
+use embassy_hal_internal::Peri;
 // Re-export useful enums
 pub use stm32_metapac::timer::vals::{FilterValue, Sms as SlaveMode, Ts as TriggerSource};
@@ -93,11 +95,11 @@ impl CountingMode {
 impl From<CountingMode> for (vals::Cms, vals::Dir) {
    fn from(value: CountingMode) -> Self {
        match value {
-            CountingMode::EdgeAlignedUp => (vals::Cms::EDGEALIGNED, vals::Dir::UP),
+            CountingMode::EdgeAlignedUp => (vals::Cms::EDGE_ALIGNED, vals::Dir::UP),
-            CountingMode::EdgeAlignedDown => (vals::Cms::EDGEALIGNED, vals::Dir::DOWN),
+            CountingMode::EdgeAlignedDown => (vals::Cms::EDGE_ALIGNED, vals::Dir::DOWN),
-            CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTERALIGNED1, vals::Dir::UP),
+            CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTER_ALIGNED1, vals::Dir::UP),
-            CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTERALIGNED2, vals::Dir::UP),
+            CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTER_ALIGNED2, vals::Dir::UP),
-            CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTERALIGNED3, vals::Dir::UP),
+            CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTER_ALIGNED3, vals::Dir::UP),
        }
    }
 }
@@ -105,11 +107,11 @@ impl From<CountingMode> for (vals::Cms, vals::Dir) {
 impl From<(vals::Cms, vals::Dir)> for CountingMode {
    fn from(value: (vals::Cms, vals::Dir)) -> Self {
        match value {
-            (vals::Cms::EDGEALIGNED, vals::Dir::UP) => CountingMode::EdgeAlignedUp,
+            (vals::Cms::EDGE_ALIGNED, vals::Dir::UP) => CountingMode::EdgeAlignedUp,
-            (vals::Cms::EDGEALIGNED, vals::Dir::DOWN) => CountingMode::EdgeAlignedDown,
+            (vals::Cms::EDGE_ALIGNED, vals::Dir::DOWN) => CountingMode::EdgeAlignedDown,
-            (vals::Cms::CENTERALIGNED1, _) => CountingMode::CenterAlignedDownInterrupts,
+            (vals::Cms::CENTER_ALIGNED1, _) => CountingMode::CenterAlignedDownInterrupts,
-            (vals::Cms::CENTERALIGNED2, _) => CountingMode::CenterAlignedUpInterrupts,
+            (vals::Cms::CENTER_ALIGNED2, _) => CountingMode::CenterAlignedUpInterrupts,
-            (vals::Cms::CENTERALIGNED3, _) => CountingMode::CenterAlignedBothInterrupts,
+            (vals::Cms::CENTER_ALIGNED3, _) => CountingMode::CenterAlignedBothInterrupts,
        }
    }
 }
@@ -148,13 +150,13 @@ impl From<OutputCompareMode> for stm32_metapac::timer::vals::Ocm {
    fn from(mode: OutputCompareMode) -> Self {
        match mode {
            OutputCompareMode::Frozen => stm32_metapac::timer::vals::Ocm::FROZEN,
-            OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVEONMATCH,
+            OutputCompareMode::ActiveOnMatch => stm32_metapac::timer::vals::Ocm::ACTIVE_ON_MATCH,
-            OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVEONMATCH,
+            OutputCompareMode::InactiveOnMatch => stm32_metapac::timer::vals::Ocm::INACTIVE_ON_MATCH,
            OutputCompareMode::Toggle => stm32_metapac::timer::vals::Ocm::TOGGLE,
-            OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCEINACTIVE,
+            OutputCompareMode::ForceInactive => stm32_metapac::timer::vals::Ocm::FORCE_INACTIVE,
-            OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCEACTIVE,
+            OutputCompareMode::ForceActive => stm32_metapac::timer::vals::Ocm::FORCE_ACTIVE,
-            OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWMMODE1,
+            OutputCompareMode::PwmMode1 => stm32_metapac::timer::vals::Ocm::PWM_MODE1,
-            OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWMMODE2,
+            OutputCompareMode::PwmMode2 => stm32_metapac::timer::vals::Ocm::PWM_MODE2,
        }
    }
 }
@@ -179,7 +181,7 @@ impl From<OutputPolarity> for bool {
 /// Low-level timer driver.
 pub struct Timer<'d, T: CoreInstance> {
-    tim: PeripheralRef<'d, T>,
+    tim: Peri<'d, T>,
 }
 impl<'d, T: CoreInstance> Drop for Timer<'d, T> {
@@ -190,14 +192,17 @@ impl<'d, T: CoreInstance> Drop for Timer<'d, T> {
 impl<'d, T: CoreInstance> Timer<'d, T> {
    /// Create a new timer driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd) -> Self {
+    pub fn new(tim: Peri<'d, T>) -> Self {
-        into_ref!(tim);
        rcc::enable_and_reset::<T>();
        Self { tim }
    }
+    pub(crate) unsafe fn clone_unchecked(&self) -> ManuallyDrop<Self> {
+        let tim = unsafe { self.tim.clone_unchecked() };
+        ManuallyDrop::new(Self { tim })
+    }
    /// Get access to the virutal core 16bit timer registers.
    ///
    /// Note: This works even if the timer is more capable, because registers
@@ -228,6 +233,11 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
        self.regs_core().cnt().write(|r| r.set_cnt(0));
    }
+    /// get the capability of the timer
+    pub fn bits(&self) -> TimerBits {
+        T::BITS
+    }
    /// Set the frequency of how many times per second the timer counts up to the max value or down to 0.
    ///
    /// This means that in the default edge-aligned mode,
@@ -235,16 +245,28 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
    /// In center-aligned mode (which not all timers support), the wrap-around frequency is effectively halved
    /// because it needs to count up and down.
    pub fn set_frequency(&self, frequency: Hertz) {
+        match T::BITS {
+            TimerBits::Bits16 => {
+                self.set_frequency_internal(frequency, 16);
+            }
+            #[cfg(not(stm32l0))]
+            TimerBits::Bits32 => {
+                self.set_frequency_internal(frequency, 32);
+            }
+        }
+    }
+    pub(crate) fn set_frequency_internal(&self, frequency: Hertz, max_divide_by_bits: u8) {
        let f = frequency.0;
        assert!(f > 0);
        let timer_f = T::frequency().0;
+        let pclk_ticks_per_timer_period = (timer_f / f) as u64;
+        let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << max_divide_by_bits)).try_into());
+        let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1);
        match T::BITS {
            TimerBits::Bits16 => {
-                let pclk_ticks_per_timer_period = timer_f / f;
-                let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 16)).try_into());
-                let divide_by = pclk_ticks_per_timer_period / (u32::from(psc) + 1);
                // the timer counts `0..=arr`, we want it to count `0..divide_by`
                let arr = unwrap!(u16::try_from(divide_by - 1));
@@ -252,16 +274,12 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                regs.psc().write_value(psc);
                regs.arr().write(|r| r.set_arr(arr));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
            }
            #[cfg(not(stm32l0))]
            TimerBits::Bits32 => {
-                let pclk_ticks_per_timer_period = (timer_f / f) as u64;
-                let psc: u16 = unwrap!(((pclk_ticks_per_timer_period - 1) / (1 << 32)).try_into());
-                let divide_by = pclk_ticks_per_timer_period / (u64::from(psc) + 1);
                // the timer counts `0..=arr`, we want it to count `0..divide_by`
                let arr: u32 = unwrap!(u32::try_from(divide_by - 1));
@@ -269,9 +287,9 @@ impl<'d, T: CoreInstance> Timer<'d, T> {
                regs.psc().write_value(psc);
                regs.arr().write_value(arr);
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTERONLY));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
                regs.egr().write(|r| r.set_ug(true));
-                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANYEVENT));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
            }
        }
    }
@@ -405,6 +423,36 @@ impl<'d, T: GeneralInstance1Channel> Timer<'d, T> {
            TimerBits::Bits32 => self.regs_gp32_unchecked().arr().read(),
        }
    }
+    /// Set the max compare value.
+    ///
+    /// An update event is generated to load the new value. The update event is
+    /// generated such that it will not cause an interrupt or DMA request.
+    pub fn set_max_compare_value(&self, ticks: u32) {
+        match T::BITS {
+            TimerBits::Bits16 => {
+                let arr = unwrap!(u16::try_from(ticks));
+                let regs = self.regs_1ch();
+                regs.arr().write(|r| r.set_arr(arr));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+                regs.egr().write(|r| r.set_ug(true));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+            }
+            #[cfg(not(stm32l0))]
+            TimerBits::Bits32 => {
+                let arr = ticks;
+                let regs = self.regs_gp32_unchecked();
+                regs.arr().write_value(arr);
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::COUNTER_ONLY));
+                regs.egr().write(|r| r.set_ug(true));
+                regs.cr1().modify(|r| r.set_urs(vals::Urs::ANY_EVENT));
+            }
+        }
+    }
 }
 impl<'d, T: GeneralInstance2Channel> Timer<'d, T> {
diff --git a/embassy-stm32/src/timer/mod.rs b/embassy-stm32/src/timer/mod.rs
index 25782ee13..b29382fc8 100644
--- a/embassy-stm32/src/timer/mod.rs
+++ b/embassy-stm32/src/timer/mod.rs
@@ -2,12 +2,14 @@
 use core::marker::PhantomData;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(not(stm32l0))]
 pub mod complementary_pwm;
 pub mod input_capture;
 pub mod low_level;
+pub mod one_pulse;
 pub mod pwm_input;
 pub mod qei;
 pub mod simple_pwm;
@@ -40,6 +42,15 @@ impl Channel {
    }
 }
+/// Channel 1 marker type.
+pub enum Ch1 {}
+/// Channel 2 marker type.
+pub enum Ch2 {}
+/// Channel 3 marker type.
+pub enum Ch3 {}
+/// Channel 4 marker type.
+pub enum Ch4 {}
 /// Amount of bits of a timer.
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -58,15 +69,14 @@ struct State {
 impl State {
    const fn new() -> Self {
-        const NEW_AW: AtomicWaker = AtomicWaker::new();
        Self {
-            up_waker: NEW_AW,
+            up_waker: AtomicWaker::new(),
-            cc_waker: [NEW_AW; 4],
+            cc_waker: [const { AtomicWaker::new() }; 4],
        }
    }
 }
-trait SealedInstance: RccPeripheral {
+trait SealedInstance: RccPeripheral + PeripheralType {
    /// Async state for this timer
    fn state() -> &'static State;
 }
diff --git a/embassy-stm32/src/timer/one_pulse.rs b/embassy-stm32/src/timer/one_pulse.rs
new file mode 100644
index 000000000..933165ef9
--- /dev/null
+++ b/embassy-stm32/src/timer/one_pulse.rs
@@ -0,0 +1,383 @@
+//! One pulse mode driver.
+use core::future::Future;
+use core::marker::PhantomData;
+use core::mem::ManuallyDrop;
+use core::pin::Pin;
+use core::task::{Context, Poll};
+use super::low_level::{
+    CountingMode, FilterValue, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource,
+};
+use super::{
+    CaptureCompareInterruptHandler, Channel, Channel1Pin, Channel2Pin, ExternalTriggerPin, GeneralInstance4Channel,
+};
+pub use super::{Ch1, Ch2};
+use crate::gpio::{AfType, AnyPin, Pull};
+use crate::interrupt::typelevel::{Binding, Interrupt};
+use crate::pac::timer::vals::Etp;
+use crate::time::Hertz;
+use crate::Peri;
+/// External input marker type.
+pub enum Ext {}
+/// External trigger pin trigger polarity.
+#[derive(Clone, Copy)]
+pub enum ExternalTriggerPolarity {
+    /// Rising edge only.
+    Rising,
+    /// Falling edge only.
+    Falling,
+}
+impl From<ExternalTriggerPolarity> for Etp {
+    fn from(mode: ExternalTriggerPolarity) -> Self {
+        match mode {
+            ExternalTriggerPolarity::Rising => 0.into(),
+            ExternalTriggerPolarity::Falling => 1.into(),
+        }
+    }
+}
+/// Trigger pin wrapper.
+///
+/// This wraps a pin to make it usable as a timer trigger.
+pub struct TriggerPin<'d, T, C> {
+    _pin: Peri<'d, AnyPin>,
+    phantom: PhantomData<(T, C)>,
+}
+macro_rules! channel_impl {
+    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
+        impl<'d, T: GeneralInstance4Channel> TriggerPin<'d, T, $channel> {
+            #[doc = concat!("Create a new ", stringify!($channel), " trigger pin instance.")]
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, pull: Pull) -> Self {
+                pin.set_as_af(pin.af_num(), AfType::input(pull));
+                TriggerPin {
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
+        }
+    };
+}
+channel_impl!(new_ch1, Ch1, Channel1Pin);
+channel_impl!(new_ch2, Ch2, Channel2Pin);
+channel_impl!(new_ext, Ext, ExternalTriggerPin);
+/// One pulse driver.
+///
+/// Generates a pulse after a trigger and some configurable delay.
+pub struct OnePulse<'d, T: GeneralInstance4Channel> {
+    inner: Timer<'d, T>,
+}
+impl<'d, T: GeneralInstance4Channel> OnePulse<'d, T> {
+    /// Create a new one pulse driver.
+    ///
+    /// The pulse is triggered by a channel 1 input pin on both rising and
+    /// falling edges. Channel 1 will unusable as an output.
+    pub fn new_ch1_edge_detect(
+        tim: Peri<'d, T>,
+        _pin: TriggerPin<'d, T, Ch1>,
+        _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
+        freq: Hertz,
+        pulse_end: u32,
+        counting_mode: CountingMode,
+    ) -> Self {
+        let mut this = Self { inner: Timer::new(tim) };
+        this.inner.set_trigger_source(TriggerSource::TI1F_ED);
+        this.inner
+            .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
+        this.inner
+            .set_input_capture_filter(Channel::Ch1, FilterValue::NO_FILTER);
+        this.new_inner(freq, pulse_end, counting_mode);
+        this
+    }
+    /// Create a new one pulse driver.
+    ///
+    /// The pulse is triggered by a channel 1 input pin. Channel 1 will unusable
+    /// as an output.
+    pub fn new_ch1(
+        tim: Peri<'d, T>,
+        _pin: TriggerPin<'d, T, Ch1>,
+        _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
+        freq: Hertz,
+        pulse_end: u32,
+        counting_mode: CountingMode,
+        capture_mode: InputCaptureMode,
+    ) -> Self {
+        let mut this = Self { inner: Timer::new(tim) };
+        this.inner.set_trigger_source(TriggerSource::TI1FP1);
+        this.inner
+            .set_input_ti_selection(Channel::Ch1, InputTISelection::Normal);
+        this.inner
+            .set_input_capture_filter(Channel::Ch1, FilterValue::NO_FILTER);
+        this.inner.set_input_capture_mode(Channel::Ch1, capture_mode);
+        this.new_inner(freq, pulse_end, counting_mode);
+        this
+    }
+    /// Create a new one pulse driver.
+    ///
+    /// The pulse is triggered by a channel 2 input pin. Channel 2 will unusable
+    /// as an output.
+    pub fn new_ch2(
+        tim: Peri<'d, T>,
+        _pin: TriggerPin<'d, T, Ch1>,
+        _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
+        freq: Hertz,
+        pulse_end: u32,
+        counting_mode: CountingMode,
+        capture_mode: InputCaptureMode,
+    ) -> Self {
+        let mut this = Self { inner: Timer::new(tim) };
+        this.inner.set_trigger_source(TriggerSource::TI2FP2);
+        this.inner
+            .set_input_ti_selection(Channel::Ch2, InputTISelection::Normal);
+        this.inner
+            .set_input_capture_filter(Channel::Ch2, FilterValue::NO_FILTER);
+        this.inner.set_input_capture_mode(Channel::Ch2, capture_mode);
+        this.new_inner(freq, pulse_end, counting_mode);
+        this
+    }
+    /// Create a new one pulse driver.
+    ///
+    /// The pulse is triggered by a external trigger input pin.
+    pub fn new_ext(
+        tim: Peri<'d, T>,
+        _pin: TriggerPin<'d, T, Ext>,
+        _irq: impl Binding<T::CaptureCompareInterrupt, CaptureCompareInterruptHandler<T>> + 'd,
+        freq: Hertz,
+        pulse_end: u32,
+        counting_mode: CountingMode,
+        polarity: ExternalTriggerPolarity,
+    ) -> Self {
+        let mut this = Self { inner: Timer::new(tim) };
+        this.inner.regs_gp16().smcr().modify(|r| {
+            r.set_etp(polarity.into());
+            // No pre-scaling
+            r.set_etps(0.into());
+            // No filtering
+            r.set_etf(FilterValue::NO_FILTER);
+        });
+        this.inner.set_trigger_source(TriggerSource::ETRF);
+        this.new_inner(freq, pulse_end, counting_mode);
+        this
+    }
+    fn new_inner(&mut self, freq: Hertz, pulse_end: u32, counting_mode: CountingMode) {
+        self.inner.set_counting_mode(counting_mode);
+        self.inner.set_tick_freq(freq);
+        self.inner.set_max_compare_value(pulse_end);
+        self.inner.regs_core().cr1().modify(|r| r.set_opm(true));
+        // Required for advanced timers, see GeneralInstance4Channel for details
+        self.inner.enable_outputs();
+        self.inner.set_slave_mode(SlaveMode::TRIGGER_MODE);
+        T::CaptureCompareInterrupt::unpend();
+        unsafe { T::CaptureCompareInterrupt::enable() };
+    }
+    /// Get the end of the pulse in ticks from the trigger.
+    pub fn pulse_end(&self) -> u32 {
+        let max = self.inner.get_max_compare_value();
+        assert!(max < u32::MAX);
+        max + 1
+    }
+    /// Set the end of the pulse in ticks from the trigger.
+    pub fn set_pulse_end(&mut self, ticks: u32) {
+        self.inner.set_max_compare_value(ticks)
+    }
+    /// Reset the timer on each trigger
+    #[cfg(not(stm32l0))]
+    pub fn set_reset_on_trigger(&mut self, reset: bool) {
+        let slave_mode = if reset {
+            SlaveMode::COMBINED_RESET_TRIGGER
+        } else {
+            SlaveMode::TRIGGER_MODE
+        };
+        self.inner.set_slave_mode(slave_mode);
+    }
+    /// Get a single channel
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn channel(&mut self, channel: Channel) -> OnePulseChannel<'_, T> {
+        OnePulseChannel {
+            inner: unsafe { self.inner.clone_unchecked() },
+            channel,
+        }
+    }
+    /// Channel 1
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch1(&mut self) -> OnePulseChannel<'_, T> {
+        self.channel(Channel::Ch1)
+    }
+    /// Channel 2
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch2(&mut self) -> OnePulseChannel<'_, T> {
+        self.channel(Channel::Ch2)
+    }
+    /// Channel 3
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch3(&mut self) -> OnePulseChannel<'_, T> {
+        self.channel(Channel::Ch3)
+    }
+    /// Channel 4
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch4(&mut self) -> OnePulseChannel<'_, T> {
+        self.channel(Channel::Ch4)
+    }
+    /// Splits a [`OnePulse`] into four output channels.
+    // TODO: I hate the name "split"
+    pub fn split(self) -> OnePulseChannels<'static, T>
+    where
+        // must be static because the timer will never be dropped/disabled
+        'd: 'static,
+    {
+        // without this, the timer would be disabled at the end of this function
+        let timer = ManuallyDrop::new(self.inner);
+        let ch = |channel| OnePulseChannel {
+            inner: unsafe { timer.clone_unchecked() },
+            channel,
+        };
+        OnePulseChannels {
+            ch1: ch(Channel::Ch1),
+            ch2: ch(Channel::Ch2),
+            ch3: ch(Channel::Ch3),
+            ch4: ch(Channel::Ch4),
+        }
+    }
+}
+/// A group of four [`OnePulseChannel`]s, obtained from [`OnePulse::split`].
+pub struct OnePulseChannels<'d, T: GeneralInstance4Channel> {
+    /// Channel 1
+    pub ch1: OnePulseChannel<'d, T>,
+    /// Channel 2
+    pub ch2: OnePulseChannel<'d, T>,
+    /// Channel 3
+    pub ch3: OnePulseChannel<'d, T>,
+    /// Channel 4
+    pub ch4: OnePulseChannel<'d, T>,
+}
+/// A single channel of a one pulse-configured timer, obtained from
+/// [`OnePulse::split`],[`OnePulse::channel`], [`OnePulse::ch1`], etc.
+///
+/// It is not possible to change the pulse end tick because the end tick
+/// configuration is shared with all four channels.
+pub struct OnePulseChannel<'d, T: GeneralInstance4Channel> {
+    inner: ManuallyDrop<Timer<'d, T>>,
+    channel: Channel,
+}
+impl<'d, T: GeneralInstance4Channel> OnePulseChannel<'d, T> {
+    /// Get the end of the pulse in ticks from the trigger.
+    pub fn pulse_end(&self) -> u32 {
+        let max = self.inner.get_max_compare_value();
+        assert!(max < u32::MAX);
+        max + 1
+    }
+    /// Get the width of the pulse in ticks.
+    pub fn pulse_width(&mut self) -> u32 {
+        self.pulse_end().saturating_sub(self.pulse_delay())
+    }
+    /// Get the start of the pulse in ticks from the trigger.
+    pub fn pulse_delay(&mut self) -> u32 {
+        self.inner.get_compare_value(self.channel)
+    }
+    /// Set the start of the pulse in ticks from the trigger.
+    pub fn set_pulse_delay(&mut self, delay: u32) {
+        assert!(delay <= self.pulse_end());
+        self.inner.set_compare_value(self.channel, delay);
+    }
+    /// Set the pulse width in ticks.
+    pub fn set_pulse_width(&mut self, width: u32) {
+        assert!(width <= self.pulse_end());
+        self.set_pulse_delay(self.pulse_end() - width);
+    }
+    /// Waits until the trigger and following delay has passed.
+    pub async fn wait_for_pulse_start(&mut self) {
+        self.inner.enable_input_interrupt(self.channel, true);
+        OnePulseFuture::<T> {
+            channel: self.channel,
+            phantom: PhantomData,
+        }
+        .await
+    }
+}
+#[must_use = "futures do nothing unless you `.await` or poll them"]
+struct OnePulseFuture<T: GeneralInstance4Channel> {
+    channel: Channel,
+    phantom: PhantomData<T>,
+}
+impl<'d, T: GeneralInstance4Channel> Drop for OnePulseFuture<T> {
+    fn drop(&mut self) {
+        critical_section::with(|_| {
+            let regs = unsafe { crate::pac::timer::TimGp16::from_ptr(T::regs()) };
+            // disable interrupt enable
+            regs.dier().modify(|w| w.set_ccie(self.channel.index(), false));
+        });
+    }
+}
+impl<'d, T: GeneralInstance4Channel> Future for OnePulseFuture<T> {
+    type Output = ();
+    fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        T::state().cc_waker[self.channel.index()].register(cx.waker());
+        let regs = unsafe { crate::pac::timer::TimGp16::from_ptr(T::regs()) };
+        let dier = regs.dier().read();
+        if !dier.ccie(self.channel.index()) {
+            Poll::Ready(())
+        } else {
+            Poll::Pending
+        }
+    }
+}
diff --git a/embassy-stm32/src/timer/pwm_input.rs b/embassy-stm32/src/timer/pwm_input.rs
index e3eb6042a..98b798634 100644
--- a/embassy-stm32/src/timer/pwm_input.rs
+++ b/embassy-stm32/src/timer/pwm_input.rs
@@ -1,12 +1,10 @@
 //! PWM Input driver.
-use embassy_hal_internal::into_ref;
 use super::low_level::{CountingMode, InputCaptureMode, InputTISelection, SlaveMode, Timer, TriggerSource};
 use super::{Channel, Channel1Pin, Channel2Pin, GeneralInstance4Channel};
 use crate::gpio::{AfType, Pull};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 /// PWM Input driver.
 pub struct PwmInput<'d, T: GeneralInstance4Channel> {
@@ -16,34 +14,20 @@ pub struct PwmInput<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> PwmInput<'d, T> {
    /// Create a new PWM input driver.
-    pub fn new(
+    pub fn new(tim: Peri<'d, T>, pin: Peri<'d, impl Channel1Pin<T>>, pull: Pull, freq: Hertz) -> Self {
-        tim: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl Channel1Pin<T>> + 'd,
-        pull: Pull,
-        freq: Hertz,
-    ) -> Self {
-        into_ref!(pin);
        pin.set_as_af(pin.af_num(), AfType::input(pull));
        Self::new_inner(tim, freq, Channel::Ch1, Channel::Ch2)
    }
    /// Create a new PWM input driver.
-    pub fn new_alt(
+    pub fn new_alt(tim: Peri<'d, T>, pin: Peri<'d, impl Channel2Pin<T>>, pull: Pull, freq: Hertz) -> Self {
-        tim: impl Peripheral<P = T> + 'd,
-        pin: impl Peripheral<P = impl Channel2Pin<T>> + 'd,
-        pull: Pull,
-        freq: Hertz,
-    ) -> Self {
-        into_ref!(pin);
        pin.set_as_af(pin.af_num(), AfType::input(pull));
        Self::new_inner(tim, freq, Channel::Ch2, Channel::Ch1)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, ch1: Channel, ch2: Channel) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, ch1: Channel, ch2: Channel) -> Self {
        let mut inner = Timer::new(tim);
        inner.set_counting_mode(CountingMode::EdgeAlignedUp);
diff --git a/embassy-stm32/src/timer/qei.rs b/embassy-stm32/src/timer/qei.rs
index fc5835414..f3c81667c 100644
--- a/embassy-stm32/src/timer/qei.rs
+++ b/embassy-stm32/src/timer/qei.rs
@@ -2,13 +2,13 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use stm32_metapac::timer::vals;
 use super::low_level::Timer;
+pub use super::{Ch1, Ch2};
 use super::{Channel1Pin, Channel2Pin, GeneralInstance4Channel};
 use crate::gpio::{AfType, AnyPin, Pull};
-use crate::Peripheral;
+use crate::Peri;
 /// Counting direction
 pub enum Direction {
@@ -18,14 +18,9 @@ pub enum Direction {
    Downcounting,
 }
-/// Channel 1 marker type.
-pub enum Ch1 {}
-/// Channel 2 marker type.
-pub enum Ch2 {}
 /// Wrapper for using a pin with QEI.
 pub struct QeiPin<'d, T, Channel> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, Channel)>,
 }
@@ -33,14 +28,13 @@ macro_rules! channel_impl {
    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
        impl<'d, T: GeneralInstance4Channel> QeiPin<'d, T, $channel> {
            #[doc = concat!("Create a new ", stringify!($channel), " QEI pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>) -> Self {
-                into_ref!(pin);
                critical_section::with(|_| {
                    pin.set_low();
                    pin.set_as_af(pin.af_num(), AfType::input(Pull::None));
                });
                QeiPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -58,11 +52,11 @@ pub struct Qei<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> Qei<'d, T> {
    /// Create a new quadrature decoder driver.
-    pub fn new(tim: impl Peripheral<P = T> + 'd, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
+    pub fn new(tim: Peri<'d, T>, _ch1: QeiPin<'d, T, Ch1>, _ch2: QeiPin<'d, T, Ch2>) -> Self {
        Self::new_inner(tim)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd) -> Self {
+    fn new_inner(tim: Peri<'d, T>) -> Self {
        let inner = Timer::new(tim);
        let r = inner.regs_gp16();
diff --git a/embassy-stm32/src/timer/simple_pwm.rs b/embassy-stm32/src/timer/simple_pwm.rs
index b7771bd64..f7f433154 100644
--- a/embassy-stm32/src/timer/simple_pwm.rs
+++ b/embassy-stm32/src/timer/simple_pwm.rs
@@ -1,14 +1,15 @@
 //! Simple PWM driver.
 use core::marker::PhantomData;
+use core::mem::ManuallyDrop;
-use embassy_hal_internal::{into_ref, PeripheralRef};
 use super::low_level::{CountingMode, OutputCompareMode, OutputPolarity, Timer};
-use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel};
+use super::{Channel, Channel1Pin, Channel2Pin, Channel3Pin, Channel4Pin, GeneralInstance4Channel, TimerBits};
+#[cfg(gpio_v2)]
+use crate::gpio::Pull;
 use crate::gpio::{AfType, AnyPin, OutputType, Speed};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 /// Channel 1 marker type.
 pub enum Ch1 {}
@@ -23,22 +24,54 @@ pub enum Ch4 {}
 ///
 /// This wraps a pin to make it usable with PWM.
 pub struct PwmPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
+    _pin: Peri<'d, AnyPin>,
    phantom: PhantomData<(T, C)>,
 }
+/// PWM pin config
+///
+/// This configures the pwm pin settings
+#[derive(Debug, Copy, Clone)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct PwmPinConfig {
+    /// PWM Pin output type
+    pub output_type: OutputType,
+    /// PWM Pin speed
+    pub speed: Speed,
+    /// PWM Pin pull type
+    #[cfg(gpio_v2)]
+    pub pull: Pull,
+}
 macro_rules! channel_impl {
-    ($new_chx:ident, $channel:ident, $pin_trait:ident) => {
+    ($new_chx:ident, $new_chx_with_config:ident, $channel:ident, $pin_trait:ident) => {
        impl<'d, T: GeneralInstance4Channel> PwmPin<'d, T, $channel> {
            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance.")]
-            pub fn $new_chx(pin: impl Peripheral<P = impl $pin_trait<T>> + 'd, output_type: OutputType) -> Self {
+            pub fn $new_chx(pin: Peri<'d, impl $pin_trait<T>>, output_type: OutputType) -> Self {
-                into_ref!(pin);
                critical_section::with(|_| {
                    pin.set_low();
                    pin.set_as_af(pin.af_num(), AfType::output(output_type, Speed::VeryHigh));
                });
                PwmPin {
-                    _pin: pin.map_into(),
+                    _pin: pin.into(),
+                    phantom: PhantomData,
+                }
+            }
+            #[doc = concat!("Create a new ", stringify!($channel), " PWM pin instance with config.")]
+            pub fn $new_chx_with_config(pin: Peri<'d, impl $pin_trait<T>>, pin_config: PwmPinConfig) -> Self {
+                critical_section::with(|_| {
+                    pin.set_low();
+                    pin.set_as_af(
+                        pin.af_num(),
+                        #[cfg(gpio_v1)]
+                        AfType::output(pin_config.output_type, pin_config.speed),
+                        #[cfg(gpio_v2)]
+                        AfType::output_pull(pin_config.output_type, pin_config.speed, pin_config.pull),
+                    );
+                });
+                PwmPin {
+                    _pin: pin.into(),
                    phantom: PhantomData,
                }
            }
@@ -46,10 +79,115 @@ macro_rules! channel_impl {
    };
 }
-channel_impl!(new_ch1, Ch1, Channel1Pin);
+channel_impl!(new_ch1, new_ch1_with_config, Ch1, Channel1Pin);
-channel_impl!(new_ch2, Ch2, Channel2Pin);
+channel_impl!(new_ch2, new_ch2_with_config, Ch2, Channel2Pin);
-channel_impl!(new_ch3, Ch3, Channel3Pin);
+channel_impl!(new_ch3, new_ch3_with_config, Ch3, Channel3Pin);
-channel_impl!(new_ch4, Ch4, Channel4Pin);
+channel_impl!(new_ch4, new_ch4_with_config, Ch4, Channel4Pin);
+/// A single channel of a pwm, obtained from [`SimplePwm::split`],
+/// [`SimplePwm::channel`], [`SimplePwm::ch1`], etc.
+///
+/// It is not possible to change the pwm frequency because
+/// the frequency configuration is shared with all four channels.
+pub struct SimplePwmChannel<'d, T: GeneralInstance4Channel> {
+    timer: ManuallyDrop<Timer<'d, T>>,
+    channel: Channel,
+}
+// TODO: check for RMW races
+impl<'d, T: GeneralInstance4Channel> SimplePwmChannel<'d, T> {
+    /// Enable the given channel.
+    pub fn enable(&mut self) {
+        self.timer.enable_channel(self.channel, true);
+    }
+    /// Disable the given channel.
+    pub fn disable(&mut self) {
+        self.timer.enable_channel(self.channel, false);
+    }
+    /// Check whether given channel is enabled
+    pub fn is_enabled(&self) -> bool {
+        self.timer.get_channel_enable_state(self.channel)
+    }
+    /// Get max duty value.
+    ///
+    /// This value depends on the configured frequency and the timer's clock rate from RCC.
+    pub fn max_duty_cycle(&self) -> u16 {
+        let max = self.timer.get_max_compare_value();
+        assert!(max < u16::MAX as u32);
+        max as u16 + 1
+    }
+    /// Set the duty for a given channel.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`max_duty_cycle`](Self::max_duty_cycle) for 100% duty, both included.
+    pub fn set_duty_cycle(&mut self, duty: u16) {
+        assert!(duty <= (*self).max_duty_cycle());
+        self.timer.set_compare_value(self.channel, duty.into())
+    }
+    /// Set the duty cycle to 0%, or always inactive.
+    pub fn set_duty_cycle_fully_off(&mut self) {
+        self.set_duty_cycle(0);
+    }
+    /// Set the duty cycle to 100%, or always active.
+    pub fn set_duty_cycle_fully_on(&mut self) {
+        self.set_duty_cycle((*self).max_duty_cycle());
+    }
+    /// Set the duty cycle to `num / denom`.
+    ///
+    /// The caller is responsible for ensuring that `num` is less than or equal to `denom`,
+    /// and that `denom` is not zero.
+    pub fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) {
+        assert!(denom != 0);
+        assert!(num <= denom);
+        let duty = u32::from(num) * u32::from(self.max_duty_cycle()) / u32::from(denom);
+        // This is safe because we know that `num <= denom`, so `duty <= self.max_duty_cycle()` (u16)
+        #[allow(clippy::cast_possible_truncation)]
+        self.set_duty_cycle(duty as u16);
+    }
+    /// Set the duty cycle to `percent / 100`
+    ///
+    /// The caller is responsible for ensuring that `percent` is less than or equal to 100.
+    pub fn set_duty_cycle_percent(&mut self, percent: u8) {
+        self.set_duty_cycle_fraction(u16::from(percent), 100)
+    }
+    /// Get the duty for a given channel.
+    ///
+    /// The value ranges from 0 for 0% duty, to [`max_duty_cycle`](Self::max_duty_cycle) for 100% duty, both included.
+    pub fn current_duty_cycle(&self) -> u16 {
+        unwrap!(self.timer.get_compare_value(self.channel).try_into())
+    }
+    /// Set the output polarity for a given channel.
+    pub fn set_polarity(&mut self, polarity: OutputPolarity) {
+        self.timer.set_output_polarity(self.channel, polarity);
+    }
+    /// Set the output compare mode for a given channel.
+    pub fn set_output_compare_mode(&mut self, mode: OutputCompareMode) {
+        self.timer.set_output_compare_mode(self.channel, mode);
+    }
+}
+/// A group of four [`SimplePwmChannel`]s, obtained from [`SimplePwm::split`].
+pub struct SimplePwmChannels<'d, T: GeneralInstance4Channel> {
+    /// Channel 1
+    pub ch1: SimplePwmChannel<'d, T>,
+    /// Channel 2
+    pub ch2: SimplePwmChannel<'d, T>,
+    /// Channel 3
+    pub ch3: SimplePwmChannel<'d, T>,
+    /// Channel 4
+    pub ch4: SimplePwmChannel<'d, T>,
+}
 /// Simple PWM driver.
 pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
@@ -59,7 +197,7 @@ pub struct SimplePwm<'d, T: GeneralInstance4Channel> {
 impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
    /// Create a new simple PWM driver.
    pub fn new(
-        tim: impl Peripheral<P = T> + 'd,
+        tim: Peri<'d, T>,
        _ch1: Option<PwmPin<'d, T, Ch1>>,
        _ch2: Option<PwmPin<'d, T, Ch2>>,
        _ch3: Option<PwmPin<'d, T, Ch3>>,
@@ -70,7 +208,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
        Self::new_inner(tim, freq, counting_mode)
    }
-    fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
+    fn new_inner(tim: Peri<'d, T>, freq: Hertz, counting_mode: CountingMode) -> Self {
        let mut this = Self { inner: Timer::new(tim) };
        this.inner.set_counting_mode(counting_mode);
@@ -89,19 +227,76 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
        this
    }
-    /// Enable the given channel.
+    /// Get a single channel
-    pub fn enable(&mut self, channel: Channel) {
+    ///
-        self.inner.enable_channel(channel, true);
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn channel(&mut self, channel: Channel) -> SimplePwmChannel<'_, T> {
+        SimplePwmChannel {
+            timer: unsafe { self.inner.clone_unchecked() },
+            channel,
+        }
    }
-    /// Disable the given channel.
+    /// Channel 1
-    pub fn disable(&mut self, channel: Channel) {
+    ///
-        self.inner.enable_channel(channel, false);
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch1(&mut self) -> SimplePwmChannel<'_, T> {
+        self.channel(Channel::Ch1)
    }
-    /// Check whether given channel is enabled
+    /// Channel 2
-    pub fn is_enabled(&self, channel: Channel) -> bool {
+    ///
-        self.inner.get_channel_enable_state(channel)
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch2(&mut self) -> SimplePwmChannel<'_, T> {
+        self.channel(Channel::Ch2)
+    }
+    /// Channel 3
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch3(&mut self) -> SimplePwmChannel<'_, T> {
+        self.channel(Channel::Ch3)
+    }
+    /// Channel 4
+    ///
+    /// This is just a convenience wrapper around [`Self::channel`].
+    ///
+    /// If you need to use multiple channels, use [`Self::split`].
+    pub fn ch4(&mut self) -> SimplePwmChannel<'_, T> {
+        self.channel(Channel::Ch4)
+    }
+    /// Splits a [`SimplePwm`] into four pwm channels.
+    ///
+    /// This returns all four channels, including channels that
+    /// aren't configured with a [`PwmPin`].
+    // TODO: I hate the name "split"
+    pub fn split(self) -> SimplePwmChannels<'static, T>
+    where
+        // must be static because the timer will never be dropped/disabled
+        'd: 'static,
+    {
+        // without this, the timer would be disabled at the end of this function
+        let timer = ManuallyDrop::new(self.inner);
+        let ch = |channel| SimplePwmChannel {
+            timer: unsafe { timer.clone_unchecked() },
+            channel,
+        };
+        SimplePwmChannels {
+            ch1: ch(Channel::Ch1),
+            ch2: ch(Channel::Ch2),
+            ch3: ch(Channel::Ch3),
+            ch4: ch(Channel::Ch4),
+        }
    }
    /// Set PWM frequency.
@@ -109,63 +304,34 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
    /// Note: when you call this, the max duty value changes, so you will have to
    /// call `set_duty` on all channels with the duty calculated based on the new max duty.
    pub fn set_frequency(&mut self, freq: Hertz) {
+        // TODO: prevent ARR = u16::MAX?
        let multiplier = if self.inner.get_counting_mode().is_center_aligned() {
            2u8
        } else {
            1u8
        };
-        self.inner.set_frequency(freq * multiplier);
+        self.inner.set_frequency_internal(freq * multiplier, 16);
    }
    /// Get max duty value.
    ///
    /// This value depends on the configured frequency and the timer's clock rate from RCC.
-    pub fn get_max_duty(&self) -> u32 {
+    pub fn max_duty_cycle(&self) -> u16 {
-        self.inner.get_max_compare_value() + 1
+        let max = self.inner.get_max_compare_value();
-    }
+        assert!(max < u16::MAX as u32);
+        max as u16 + 1
-    /// Set the duty for a given channel.
-    ///
-    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
-    pub fn set_duty(&mut self, channel: Channel, duty: u32) {
-        assert!(duty <= self.get_max_duty());
-        self.inner.set_compare_value(channel, duty)
-    }
-    /// Get the duty for a given channel.
-    ///
-    /// The value ranges from 0 for 0% duty, to [`get_max_duty`](Self::get_max_duty) for 100% duty, both included.
-    pub fn get_duty(&self, channel: Channel) -> u32 {
-        self.inner.get_compare_value(channel)
-    }
-    /// Set the output polarity for a given channel.
-    pub fn set_polarity(&mut self, channel: Channel, polarity: OutputPolarity) {
-        self.inner.set_output_polarity(channel, polarity);
-    }
-    /// Set the output compare mode for a given channel.
-    pub fn set_output_compare_mode(&mut self, channel: Channel, mode: OutputCompareMode) {
-        self.inner.set_output_compare_mode(channel, mode);
    }
    /// Generate a sequence of PWM waveform
    ///
-    /// Note:  
+    /// Note:
    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
-    pub async fn waveform_up(
+    pub async fn waveform_up(&mut self, dma: Peri<'_, impl super::UpDma<T>>, channel: Channel, duty: &[u16]) {
-        &mut self,
-        dma: impl Peripheral<P = impl super::UpDma<T>>,
-        channel: Channel,
-        duty: &[u16],
-    ) {
-        into_ref!(dma);
        #[allow(clippy::let_unit_value)] // eg. stm32f334
        let req = dma.request();
-        let original_duty_state = self.get_duty(channel);
+        let original_duty_state = self.channel(channel).current_duty_cycle();
-        let original_enable_state = self.is_enabled(channel);
+        let original_enable_state = self.channel(channel).is_enabled();
        let original_update_dma_state = self.inner.get_update_dma_state();
        if !original_update_dma_state {
@@ -173,7 +339,7 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
        }
        if !original_enable_state {
-            self.enable(channel);
+            self.channel(channel).enable();
        }
        unsafe {
@@ -190,10 +356,10 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
            };
            Transfer::new_write(
-                &mut dma,
+                dma,
                req,
                duty,
-                self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut _,
+                self.inner.regs_1ch().ccr(channel.index()).as_ptr() as *mut u16,
                dma_transfer_option,
            )
            .await
@@ -201,10 +367,10 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
        // restore output compare state
        if !original_enable_state {
-            self.disable(channel);
+            self.channel(channel).disable();
        }
-        self.set_duty(channel, original_duty_state);
+        self.channel(channel).set_duty_cycle(original_duty_state);
        // Since DMA is closed before timer update event trigger DMA is turn off,
        // this can almost always trigger a DMA FIFO error.
@@ -215,33 +381,111 @@ impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
            self.inner.enable_update_dma(false);
        }
    }
+    /// Generate a multichannel sequence of PWM waveforms using DMA triggered by timer update events.
+    ///
+    /// This method utilizes the timer's DMA burst transfer capability to update multiple CCRx registers
+    /// in sequence on each update event (UEV). The data is written via the DMAR register using the
+    /// DMA base address (DBA) and burst length (DBL) configured in the DCR register.
+    ///
+    /// The `duty` buffer must be structured as a flattened 2D array in row-major order, where each row
+    /// represents a single update event and each column corresponds to a specific timer channel (starting
+    /// from `starting_channel` up to and including `ending_channel`).
+    ///
+    /// For example, if using channels 1 through 4, a buffer of 4 update steps might look like:
+    ///
+    /// let dma_buf: [u16; 16] = [
+    ///     ch1_duty_1, ch2_duty_1, ch3_duty_1, ch4_duty_1, // update 1
+    ///     ch1_duty_2, ch2_duty_2, ch3_duty_2, ch4_duty_2, // update 2
+    ///     ch1_duty_3, ch2_duty_3, ch3_duty_3, ch4_duty_3, // update 3
+    ///     ch1_duty_4, ch2_duty_4, ch3_duty_4, ch4_duty_4, // update 4
+    /// ];
+    ///
+    /// Each group of N values (where N = number of channels) is transferred on one update event,
+    /// updating the duty cycles of all selected channels simultaneously.
+    ///
+    /// Note:
+    /// you will need to provide corresponding TIMx_UP DMA channel to use this method.
+    pub async fn waveform_up_multi_channel(
+        &mut self,
+        dma: Peri<'_, impl super::UpDma<T>>,
+        starting_channel: Channel,
+        ending_channel: Channel,
+        duty: &[u16],
+    ) {
+        let cr1_addr = self.inner.regs_gp16().cr1().as_ptr() as u32;
+        let start_ch_index = starting_channel.index();
+        let end_ch_index = ending_channel.index();
+        assert!(start_ch_index <= end_ch_index);
+        let ccrx_addr = self.inner.regs_gp16().ccr(start_ch_index).as_ptr() as u32;
+        self.inner
+            .regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dba(((ccrx_addr - cr1_addr) / 4) as u8));
+        self.inner
+            .regs_gp16()
+            .dcr()
+            .modify(|w| w.set_dbl((end_ch_index - start_ch_index) as u8));
+        #[allow(clippy::let_unit_value)] // eg. stm32f334
+        let req = dma.request();
+        let original_update_dma_state = self.inner.get_update_dma_state();
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(true);
+        }
+        unsafe {
+            #[cfg(not(any(bdma, gpdma)))]
+            use crate::dma::{Burst, FifoThreshold};
+            use crate::dma::{Transfer, TransferOptions};
+            let dma_transfer_option = TransferOptions {
+                #[cfg(not(any(bdma, gpdma)))]
+                fifo_threshold: Some(FifoThreshold::Full),
+                #[cfg(not(any(bdma, gpdma)))]
+                mburst: Burst::Incr4,
+                ..Default::default()
+            };
+            Transfer::new_write(
+                dma,
+                req,
+                duty,
+                self.inner.regs_gp16().dmar().as_ptr() as *mut u16,
+                dma_transfer_option,
+            )
+            .await
+        };
+        if !original_update_dma_state {
+            self.inner.enable_update_dma(false);
+        }
+    }
 }
 macro_rules! impl_waveform_chx {
    ($fn_name:ident, $dma_ch:ident, $cc_ch:ident) => {
        impl<'d, T: GeneralInstance4Channel> SimplePwm<'d, T> {
            /// Generate a sequence of PWM waveform
-            ///
+            pub async fn $fn_name(&mut self, dma: Peri<'_, impl super::$dma_ch<T>>, duty: &[u16]) {
-            /// Note:
-            /// you will need to provide corresponding TIMx_CHy DMA channel to use this method.
-            pub async fn $fn_name(&mut self, dma: impl Peripheral<P = impl super::$dma_ch<T>>, duty: &[u16]) {
                use crate::pac::timer::vals::Ccds;
-                into_ref!(dma);
                #[allow(clippy::let_unit_value)] // eg. stm32f334
                let req = dma.request();
                let cc_channel = Channel::$cc_ch;
-                let original_duty_state = self.get_duty(cc_channel);
+                let original_duty_state = self.channel(cc_channel).current_duty_cycle();
-                let original_enable_state = self.is_enabled(cc_channel);
+                let original_enable_state = self.channel(cc_channel).is_enabled();
-                let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ONUPDATE;
+                let original_cc_dma_on_update = self.inner.get_cc_dma_selection() == Ccds::ON_UPDATE;
                let original_cc_dma_enabled = self.inner.get_cc_dma_enable_state(cc_channel);
                // redirect CC DMA request onto Update Event
                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ONUPDATE)
+                    self.inner.set_cc_dma_selection(Ccds::ON_UPDATE)
                }
                if !original_cc_dma_enabled {
@@ -249,7 +493,7 @@ macro_rules! impl_waveform_chx {
                }
                if !original_enable_state {
-                    self.enable(cc_channel);
+                    self.channel(cc_channel).enable();
                }
                unsafe {
@@ -265,22 +509,41 @@ macro_rules! impl_waveform_chx {
                        ..Default::default()
                    };
-                    Transfer::new_write(
+                    match self.inner.bits() {
-                        &mut dma,
+                        TimerBits::Bits16 => {
-                        req,
+                            Transfer::new_write(
-                        duty,
+                                dma,
-                        self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut _,
+                                req,
-                        dma_transfer_option,
+                                duty,
-                    )
+                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u16,
-                    .await
+                                dma_transfer_option,
+                            )
+                            .await
+                        }
+                        #[cfg(not(any(stm32l0)))]
+                        TimerBits::Bits32 => {
+                            #[cfg(not(any(bdma, gpdma)))]
+                            panic!("unsupported timer bits");
+                            #[cfg(any(bdma, gpdma))]
+                            Transfer::new_write(
+                                dma,
+                                req,
+                                duty,
+                                self.inner.regs_gp16().ccr(cc_channel.index()).as_ptr() as *mut u32,
+                                dma_transfer_option,
+                            )
+                            .await
+                        }
+                    };
                };
                // restore output compare state
                if !original_enable_state {
-                    self.disable(cc_channel);
+                    self.channel(cc_channel).disable();
                }
-                self.set_duty(cc_channel, original_duty_state);
+                self.channel(cc_channel).set_duty_cycle(original_duty_state);
                // Since DMA is closed before timer Capture Compare Event trigger DMA is turn off,
                // this can almost always trigger a DMA FIFO error.
@@ -292,7 +555,7 @@ macro_rules! impl_waveform_chx {
                }
                if !original_cc_dma_on_update {
-                    self.inner.set_cc_dma_selection(Ccds::ONCOMPARE)
+                    self.inner.set_cc_dma_selection(Ccds::ON_COMPARE)
                }
            }
        }
@@ -304,6 +567,41 @@ impl_waveform_chx!(waveform_ch2, Ch2Dma, Ch2);
 impl_waveform_chx!(waveform_ch3, Ch3Dma, Ch3);
 impl_waveform_chx!(waveform_ch4, Ch4Dma, Ch4);
+impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::ErrorType for SimplePwmChannel<'d, T> {
+    type Error = core::convert::Infallible;
+}
+impl<'d, T: GeneralInstance4Channel> embedded_hal_1::pwm::SetDutyCycle for SimplePwmChannel<'d, T> {
+    fn max_duty_cycle(&self) -> u16 {
+        self.max_duty_cycle()
+    }
+    fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
+        self.set_duty_cycle(duty);
+        Ok(())
+    }
+    fn set_duty_cycle_fully_off(&mut self) -> Result<(), Self::Error> {
+        self.set_duty_cycle_fully_off();
+        Ok(())
+    }
+    fn set_duty_cycle_fully_on(&mut self) -> Result<(), Self::Error> {
+        self.set_duty_cycle_fully_on();
+        Ok(())
+    }
+    fn set_duty_cycle_fraction(&mut self, num: u16, denom: u16) -> Result<(), Self::Error> {
+        self.set_duty_cycle_fraction(num, denom);
+        Ok(())
+    }
+    fn set_duty_cycle_percent(&mut self, percent: u8) -> Result<(), Self::Error> {
+        self.set_duty_cycle_percent(percent);
+        Ok(())
+    }
+}
 impl<'d, T: GeneralInstance4Channel> embedded_hal_02::Pwm for SimplePwm<'d, T> {
    type Channel = Channel;
    type Time = Hertz;
@@ -330,7 +628,7 @@ impl<'d, T: GeneralInstance4Channel> embedded_hal_02::Pwm for SimplePwm<'d, T> {
    }
    fn set_duty(&mut self, channel: Self::Channel, duty: Self::Duty) {
-        assert!(duty <= self.get_max_duty());
+        assert!(duty <= self.max_duty_cycle() as u32);
        self.inner.set_compare_value(channel, duty)
    }
diff --git a/embassy-stm32/src/tsc/acquisition_banks.rs b/embassy-stm32/src/tsc/acquisition_banks.rs
new file mode 100644
index 000000000..6791ef6c1
--- /dev/null
+++ b/embassy-stm32/src/tsc/acquisition_banks.rs
@@ -0,0 +1,209 @@
+use super::io_pin::*;
+#[cfg(any(tsc_v2, tsc_v3))]
+use super::pin_groups::G7;
+#[cfg(tsc_v3)]
+use super::pin_groups::G8;
+use super::pin_groups::{pin_roles, G1, G2, G3, G4, G5, G6};
+use super::types::{Group, GroupStatus};
+use super::TSC_NUM_GROUPS;
+/// Represents a collection of TSC (Touch Sensing Controller) pins for an acquisition bank.
+///
+/// This struct holds optional `tsc::IOPin` values for each TSC group, allowing for flexible
+/// configuration of TSC acquisition banks. Each field corresponds to a specific TSC group
+/// and can be set to `Some(tsc::IOPin)` if that group is to be included in the acquisition,
+/// or `None` if it should be excluded.
+#[allow(missing_docs)]
+#[derive(Default)]
+pub struct AcquisitionBankPins {
+    pub g1_pin: Option<IOPinWithRole<G1, pin_roles::Channel>>,
+    pub g2_pin: Option<IOPinWithRole<G2, pin_roles::Channel>>,
+    pub g3_pin: Option<IOPinWithRole<G3, pin_roles::Channel>>,
+    pub g4_pin: Option<IOPinWithRole<G4, pin_roles::Channel>>,
+    pub g5_pin: Option<IOPinWithRole<G5, pin_roles::Channel>>,
+    pub g6_pin: Option<IOPinWithRole<G6, pin_roles::Channel>>,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    pub g7_pin: Option<IOPinWithRole<G7, pin_roles::Channel>>,
+    #[cfg(tsc_v3)]
+    pub g8_pin: Option<IOPinWithRole<G8, pin_roles::Channel>>,
+}
+impl AcquisitionBankPins {
+    /// Returns an iterator over the pins in this acquisition bank.
+    ///
+    /// This method allows for easy traversal of all configured pins in the bank.
+    pub fn iter(&self) -> AcquisitionBankPinsIterator {
+        AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
+    }
+}
+/// Iterator for TSC acquisition banks.
+///
+/// This iterator allows traversing through the pins of a `AcquisitionBankPins` struct,
+/// yielding each configured pin in order of the TSC groups.
+pub struct AcquisitionBankIterator<'a> {
+    pins: &'a AcquisitionBankPins,
+    current_group: u8,
+}
+impl<'a> AcquisitionBankIterator<'a> {
+    fn new(pins: &'a AcquisitionBankPins) -> Self {
+        Self { pins, current_group: 0 }
+    }
+    fn next_pin(&mut self) -> Option<IOPin> {
+        while self.current_group < TSC_NUM_GROUPS as u8 {
+            let pin = match self.current_group {
+                0 => self.pins.g1_pin.map(IOPinWithRole::get_pin),
+                1 => self.pins.g2_pin.map(IOPinWithRole::get_pin),
+                2 => self.pins.g3_pin.map(IOPinWithRole::get_pin),
+                3 => self.pins.g4_pin.map(IOPinWithRole::get_pin),
+                4 => self.pins.g5_pin.map(IOPinWithRole::get_pin),
+                5 => self.pins.g6_pin.map(IOPinWithRole::get_pin),
+                #[cfg(any(tsc_v2, tsc_v3))]
+                6 => self.pins.g7_pin.map(IOPinWithRole::get_pin),
+                #[cfg(tsc_v3)]
+                7 => self.pins.g8_pin.map(IOPinWithRole::get_pin),
+                _ => None,
+            };
+            self.current_group += 1;
+            if pin.is_some() {
+                return pin;
+            }
+        }
+        None
+    }
+}
+/// Iterator for TSC acquisition bank pins.
+///
+/// This iterator yields `tsc::IOPin` values for each configured pin in the acquisition bank.
+pub struct AcquisitionBankPinsIterator<'a>(AcquisitionBankIterator<'a>);
+impl<'a> Iterator for AcquisitionBankPinsIterator<'a> {
+    type Item = IOPin;
+    fn next(&mut self) -> Option<Self::Item> {
+        self.0.next_pin()
+    }
+}
+impl AcquisitionBankPins {
+    /// Returns an iterator over the available pins in the bank
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+        AcquisitionBankPinsIterator(AcquisitionBankIterator::new(self))
+    }
+}
+/// Represents a collection of TSC pins to be acquired simultaneously.
+///
+/// This struct contains a set of pins to be used in a TSC acquisition with a pre-computed and
+/// verified mask for efficiently setting up the TSC peripheral before performing an acquisition.
+/// It ensures that only one channel pin per TSC group is included, adhering to hardware limitations.
+pub struct AcquisitionBank {
+    pub(super) pins: AcquisitionBankPins,
+    pub(super) mask: u32,
+}
+impl AcquisitionBank {
+    /// Returns an iterator over the available pins in the bank.
+    pub fn pins_iterator(&self) -> AcquisitionBankPinsIterator {
+        self.pins.pins_iterator()
+    }
+    /// Returns the mask for this bank.
+    pub fn mask(&self) -> u32 {
+        self.mask
+    }
+    /// Retrieves the TSC I/O pin for a given group in this acquisition bank.
+    ///
+    /// # Arguments
+    /// * `group` - The TSC group to retrieve the pin for.
+    ///
+    /// # Returns
+    /// An `Option<tsc::IOPin>` containing the pin if it exists for the given group, or `None` if not.
+    pub fn get_pin(&self, group: Group) -> Option<IOPin> {
+        match group {
+            Group::One => self.pins.g1_pin.map(|p| p.pin),
+            Group::Two => self.pins.g2_pin.map(|p| p.pin),
+            Group::Three => self.pins.g3_pin.map(|p| p.pin),
+            Group::Four => self.pins.g4_pin.map(|p| p.pin),
+            Group::Five => self.pins.g5_pin.map(|p| p.pin),
+            Group::Six => self.pins.g6_pin.map(|p| p.pin),
+            #[cfg(any(tsc_v2, tsc_v3))]
+            Group::Seven => self.pins.g7_pin.map(|p| p.pin),
+            #[cfg(tsc_v3)]
+            Group::Eight => self.pins.g8_pin.map(|p| p.pin),
+        }
+    }
+}
+/// Represents the status of all TSC groups in an acquisition bank
+#[derive(Default)]
+pub struct AcquisitionBankStatus {
+    pub(super) groups: [Option<GroupStatus>; TSC_NUM_GROUPS],
+}
+impl AcquisitionBankStatus {
+    /// Check if all groups in the bank are complete
+    pub fn all_complete(&self) -> bool {
+        self.groups
+            .iter()
+            .all(|&status| status.map_or(true, |s| s == GroupStatus::Complete))
+    }
+    /// Check if any group in the bank is ongoing
+    pub fn any_ongoing(&self) -> bool {
+        self.groups.iter().any(|&status| status == Some(GroupStatus::Ongoing))
+    }
+    /// Get the status of a specific group, if the group is present in the bank
+    pub fn get_group_status(&self, group: Group) -> Option<GroupStatus> {
+        let index: usize = group.into();
+        self.groups[index]
+    }
+    /// Iterator for groups present in the bank
+    pub fn iter(&self) -> impl Iterator<Item = (Group, GroupStatus)> + '_ {
+        self.groups.iter().enumerate().filter_map(|(group_num, status)| {
+            status.and_then(|s| Group::try_from(group_num).ok().map(|group| (group, s)))
+        })
+    }
+}
+/// Represents the result of a Touch Sensing Controller (TSC) acquisition for a specific pin.
+///
+/// This struct contains a reference to the `tsc::IOPin` from which a value was read,
+/// along with the actual sensor reading for that pin. It provides a convenient way
+/// to associate TSC readings with their corresponding pins after an acquisition.
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(Clone, Copy, Debug)]
+pub struct ChannelReading {
+    /// The sensor reading value obtained from the TSC acquisition.
+    /// Lower values typically indicate a detected touch, while higher values indicate no touch.
+    pub sensor_value: u16,
+    /// The `tsc::IOPin` associated with this reading.
+    /// This allows for easy identification of which pin the reading corresponds to.
+    pub tsc_pin: IOPin,
+}
+/// Represents the readings from all TSC groups
+#[derive(Default)]
+pub struct AcquisitionBankReadings {
+    pub(super) groups: [Option<ChannelReading>; TSC_NUM_GROUPS],
+}
+impl AcquisitionBankReadings {
+    /// Get the reading for a specific group, if the group is present in the bank
+    pub fn get_group_reading(&self, group: Group) -> Option<ChannelReading> {
+        let index: usize = group.into();
+        self.groups[index]
+    }
+    /// Iterator for readings for groups present in the bank
+    pub fn iter(&self) -> impl Iterator<Item = ChannelReading> + '_ {
+        self.groups.iter().filter_map(|&x| x)
+    }
+}
diff --git a/embassy-stm32/src/tsc/config.rs b/embassy-stm32/src/tsc/config.rs
new file mode 100644
index 000000000..efa1f9a0d
--- /dev/null
+++ b/embassy-stm32/src/tsc/config.rs
@@ -0,0 +1,175 @@
+/// Charge transfer pulse cycles
+#[allow(missing_docs)]
+#[derive(Copy, Clone, PartialEq)]
+pub enum ChargeTransferPulseCycle {
+    _1,
+    _2,
+    _3,
+    _4,
+    _5,
+    _6,
+    _7,
+    _8,
+    _9,
+    _10,
+    _11,
+    _12,
+    _13,
+    _14,
+    _15,
+    _16,
+}
+impl Into<u8> for ChargeTransferPulseCycle {
+    fn into(self) -> u8 {
+        match self {
+            ChargeTransferPulseCycle::_1 => 0,
+            ChargeTransferPulseCycle::_2 => 1,
+            ChargeTransferPulseCycle::_3 => 2,
+            ChargeTransferPulseCycle::_4 => 3,
+            ChargeTransferPulseCycle::_5 => 4,
+            ChargeTransferPulseCycle::_6 => 5,
+            ChargeTransferPulseCycle::_7 => 6,
+            ChargeTransferPulseCycle::_8 => 7,
+            ChargeTransferPulseCycle::_9 => 8,
+            ChargeTransferPulseCycle::_10 => 9,
+            ChargeTransferPulseCycle::_11 => 10,
+            ChargeTransferPulseCycle::_12 => 11,
+            ChargeTransferPulseCycle::_13 => 12,
+            ChargeTransferPulseCycle::_14 => 13,
+            ChargeTransferPulseCycle::_15 => 14,
+            ChargeTransferPulseCycle::_16 => 15,
+        }
+    }
+}
+/// Max count
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum MaxCount {
+    _255,
+    _511,
+    _1023,
+    _2047,
+    _4095,
+    _8191,
+    _16383,
+}
+impl Into<u8> for MaxCount {
+    fn into(self) -> u8 {
+        match self {
+            MaxCount::_255 => 0,
+            MaxCount::_511 => 1,
+            MaxCount::_1023 => 2,
+            MaxCount::_2047 => 3,
+            MaxCount::_4095 => 4,
+            MaxCount::_8191 => 5,
+            MaxCount::_16383 => 6,
+        }
+    }
+}
+/// Prescaler divider
+#[allow(missing_docs)]
+#[derive(Copy, Clone, PartialEq)]
+pub enum PGPrescalerDivider {
+    _1,
+    _2,
+    _4,
+    _8,
+    _16,
+    _32,
+    _64,
+    _128,
+}
+impl Into<u8> for PGPrescalerDivider {
+    fn into(self) -> u8 {
+        match self {
+            PGPrescalerDivider::_1 => 0,
+            PGPrescalerDivider::_2 => 1,
+            PGPrescalerDivider::_4 => 2,
+            PGPrescalerDivider::_8 => 3,
+            PGPrescalerDivider::_16 => 4,
+            PGPrescalerDivider::_32 => 5,
+            PGPrescalerDivider::_64 => 6,
+            PGPrescalerDivider::_128 => 7,
+        }
+    }
+}
+/// Error type for SSDeviation
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub enum SSDeviationError {
+    /// The provided value is too low (0)
+    ValueTooLow,
+    /// The provided value is too high (greater than 128)
+    ValueTooHigh,
+}
+/// Spread Spectrum Deviation
+#[derive(Copy, Clone)]
+pub struct SSDeviation(u8);
+impl SSDeviation {
+    /// Create new deviation value, acceptable inputs are 1-128
+    pub fn new(val: u8) -> Result<Self, SSDeviationError> {
+        if val == 0 {
+            return Err(SSDeviationError::ValueTooLow);
+        } else if val > 128 {
+            return Err(SSDeviationError::ValueTooHigh);
+        }
+        Ok(Self(val - 1))
+    }
+}
+impl Into<u8> for SSDeviation {
+    fn into(self) -> u8 {
+        self.0
+    }
+}
+/// Peripheral configuration
+#[derive(Clone, Copy)]
+pub struct Config {
+    /// Duration of high state of the charge transfer pulse
+    pub ct_pulse_high_length: ChargeTransferPulseCycle,
+    /// Duration of the low state of the charge transfer pulse
+    pub ct_pulse_low_length: ChargeTransferPulseCycle,
+    /// Enable/disable of spread spectrum feature
+    pub spread_spectrum: bool,
+    /// Adds variable number of periods of the SS clk to pulse high state
+    pub spread_spectrum_deviation: SSDeviation,
+    /// Selects AHB clock divider used to generate SS clk
+    pub spread_spectrum_prescaler: bool,
+    /// Selects AHB clock divider used to generate pulse generator clk
+    pub pulse_generator_prescaler: PGPrescalerDivider,
+    /// Maximum number of charge transfer pulses that can be generated before error
+    pub max_count_value: MaxCount,
+    /// Defines config of all IOs when no ongoing acquisition
+    pub io_default_mode: bool,
+    /// Polarity of sync input pin
+    pub synchro_pin_polarity: bool,
+    /// Acquisition starts when start bit is set or with sync pin input
+    pub acquisition_mode: bool,
+    /// Enable max count interrupt
+    pub max_count_interrupt: bool,
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            ct_pulse_high_length: ChargeTransferPulseCycle::_1,
+            ct_pulse_low_length: ChargeTransferPulseCycle::_1,
+            spread_spectrum: false,
+            spread_spectrum_deviation: SSDeviation::new(1).unwrap(),
+            spread_spectrum_prescaler: false,
+            pulse_generator_prescaler: PGPrescalerDivider::_1,
+            max_count_value: MaxCount::_255,
+            io_default_mode: false,
+            synchro_pin_polarity: false,
+            acquisition_mode: false,
+            max_count_interrupt: false,
+        }
+    }
+}
diff --git a/embassy-stm32/src/tsc/enums.rs b/embassy-stm32/src/tsc/enums.rs
deleted file mode 100644
index 0d34a43ec..000000000
--- a/embassy-stm32/src/tsc/enums.rs
+++ /dev/null
@@ -1,238 +0,0 @@
-use core::ops::BitOr;
-/// Pin defines
-#[allow(missing_docs)]
-pub enum TscIOPin {
-    Group1Io1,
-    Group1Io2,
-    Group1Io3,
-    Group1Io4,
-    Group2Io1,
-    Group2Io2,
-    Group2Io3,
-    Group2Io4,
-    Group3Io1,
-    Group3Io2,
-    Group3Io3,
-    Group3Io4,
-    Group4Io1,
-    Group4Io2,
-    Group4Io3,
-    Group4Io4,
-    Group5Io1,
-    Group5Io2,
-    Group5Io3,
-    Group5Io4,
-    Group6Io1,
-    Group6Io2,
-    Group6Io3,
-    Group6Io4,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    Group7Io1,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    Group7Io2,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    Group7Io3,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    Group7Io4,
-    #[cfg(tsc_v3)]
-    Group8Io1,
-    #[cfg(tsc_v3)]
-    Group8Io2,
-    #[cfg(tsc_v3)]
-    Group8Io3,
-    #[cfg(tsc_v3)]
-    Group8Io4,
-}
-impl BitOr<TscIOPin> for u32 {
-    type Output = u32;
-    fn bitor(self, rhs: TscIOPin) -> Self::Output {
-        let rhs: u32 = rhs.into();
-        self | rhs
-    }
-}
-impl BitOr<u32> for TscIOPin {
-    type Output = u32;
-    fn bitor(self, rhs: u32) -> Self::Output {
-        let val: u32 = self.into();
-        val | rhs
-    }
-}
-impl BitOr for TscIOPin {
-    type Output = u32;
-    fn bitor(self, rhs: Self) -> Self::Output {
-        let val: u32 = self.into();
-        let rhs: u32 = rhs.into();
-        val | rhs
-    }
-}
-impl Into<u32> for TscIOPin {
-    fn into(self) -> u32 {
-        match self {
-            TscIOPin::Group1Io1 => 0x00000001,
-            TscIOPin::Group1Io2 => 0x00000002,
-            TscIOPin::Group1Io3 => 0x00000004,
-            TscIOPin::Group1Io4 => 0x00000008,
-            TscIOPin::Group2Io1 => 0x00000010,
-            TscIOPin::Group2Io2 => 0x00000020,
-            TscIOPin::Group2Io3 => 0x00000040,
-            TscIOPin::Group2Io4 => 0x00000080,
-            TscIOPin::Group3Io1 => 0x00000100,
-            TscIOPin::Group3Io2 => 0x00000200,
-            TscIOPin::Group3Io3 => 0x00000400,
-            TscIOPin::Group3Io4 => 0x00000800,
-            TscIOPin::Group4Io1 => 0x00001000,
-            TscIOPin::Group4Io2 => 0x00002000,
-            TscIOPin::Group4Io3 => 0x00004000,
-            TscIOPin::Group4Io4 => 0x00008000,
-            TscIOPin::Group5Io1 => 0x00010000,
-            TscIOPin::Group5Io2 => 0x00020000,
-            TscIOPin::Group5Io3 => 0x00040000,
-            TscIOPin::Group5Io4 => 0x00080000,
-            TscIOPin::Group6Io1 => 0x00100000,
-            TscIOPin::Group6Io2 => 0x00200000,
-            TscIOPin::Group6Io3 => 0x00400000,
-            TscIOPin::Group6Io4 => 0x00800000,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            TscIOPin::Group7Io1 => 0x01000000,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            TscIOPin::Group7Io2 => 0x02000000,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            TscIOPin::Group7Io3 => 0x04000000,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            TscIOPin::Group7Io4 => 0x08000000,
-            #[cfg(tsc_v3)]
-            TscIOPin::Group8Io1 => 0x10000000,
-            #[cfg(tsc_v3)]
-            TscIOPin::Group8Io2 => 0x20000000,
-            #[cfg(tsc_v3)]
-            TscIOPin::Group8Io3 => 0x40000000,
-            #[cfg(tsc_v3)]
-            TscIOPin::Group8Io4 => 0x80000000,
-        }
-    }
-}
-/// Spread Spectrum Deviation
-#[derive(Copy, Clone)]
-pub struct SSDeviation(u8);
-impl SSDeviation {
-    /// Create new deviation value, acceptable inputs are 1-128
-    pub fn new(val: u8) -> Result<Self, ()> {
-        if val == 0 || val > 128 {
-            return Err(());
-        }
-        Ok(Self(val - 1))
-    }
-}
-impl Into<u8> for SSDeviation {
-    fn into(self) -> u8 {
-        self.0
-    }
-}
-/// Charge transfer pulse cycles
-#[allow(missing_docs)]
-#[derive(Copy, Clone, PartialEq)]
-pub enum ChargeTransferPulseCycle {
-    _1,
-    _2,
-    _3,
-    _4,
-    _5,
-    _6,
-    _7,
-    _8,
-    _9,
-    _10,
-    _11,
-    _12,
-    _13,
-    _14,
-    _15,
-    _16,
-}
-impl Into<u8> for ChargeTransferPulseCycle {
-    fn into(self) -> u8 {
-        match self {
-            ChargeTransferPulseCycle::_1 => 0,
-            ChargeTransferPulseCycle::_2 => 1,
-            ChargeTransferPulseCycle::_3 => 2,
-            ChargeTransferPulseCycle::_4 => 3,
-            ChargeTransferPulseCycle::_5 => 4,
-            ChargeTransferPulseCycle::_6 => 5,
-            ChargeTransferPulseCycle::_7 => 6,
-            ChargeTransferPulseCycle::_8 => 7,
-            ChargeTransferPulseCycle::_9 => 8,
-            ChargeTransferPulseCycle::_10 => 9,
-            ChargeTransferPulseCycle::_11 => 10,
-            ChargeTransferPulseCycle::_12 => 11,
-            ChargeTransferPulseCycle::_13 => 12,
-            ChargeTransferPulseCycle::_14 => 13,
-            ChargeTransferPulseCycle::_15 => 14,
-            ChargeTransferPulseCycle::_16 => 15,
-        }
-    }
-}
-/// Prescaler divider
-#[allow(missing_docs)]
-#[derive(Copy, Clone, PartialEq)]
-pub enum PGPrescalerDivider {
-    _1,
-    _2,
-    _4,
-    _8,
-    _16,
-    _32,
-    _64,
-    _128,
-}
-impl Into<u8> for PGPrescalerDivider {
-    fn into(self) -> u8 {
-        match self {
-            PGPrescalerDivider::_1 => 0,
-            PGPrescalerDivider::_2 => 1,
-            PGPrescalerDivider::_4 => 2,
-            PGPrescalerDivider::_8 => 3,
-            PGPrescalerDivider::_16 => 4,
-            PGPrescalerDivider::_32 => 5,
-            PGPrescalerDivider::_64 => 6,
-            PGPrescalerDivider::_128 => 7,
-        }
-    }
-}
-/// Max count
-#[allow(missing_docs)]
-#[derive(Copy, Clone)]
-pub enum MaxCount {
-    _255,
-    _511,
-    _1023,
-    _2047,
-    _4095,
-    _8191,
-    _16383,
-}
-impl Into<u8> for MaxCount {
-    fn into(self) -> u8 {
-        match self {
-            MaxCount::_255 => 0,
-            MaxCount::_511 => 1,
-            MaxCount::_1023 => 2,
-            MaxCount::_2047 => 3,
-            MaxCount::_4095 => 4,
-            MaxCount::_8191 => 5,
-            MaxCount::_16383 => 6,
-        }
-    }
-}
diff --git a/embassy-stm32/src/tsc/errors.rs b/embassy-stm32/src/tsc/errors.rs
new file mode 100644
index 000000000..21f6441ba
--- /dev/null
+++ b/embassy-stm32/src/tsc/errors.rs
@@ -0,0 +1,21 @@
+/// Represents errors that can occur when configuring or validating TSC pin groups.
+#[derive(Debug)]
+pub enum GroupError {
+    /// Error when a group has no sampling capacitor
+    NoSamplingCapacitor,
+    /// Error when a group has neither channel IOs nor a shield IO
+    NoChannelOrShield,
+    /// Error when a group has both channel IOs and a shield IO
+    MixedChannelAndShield,
+    /// Error when there is more than one shield IO across all groups
+    MultipleShields,
+}
+/// Error returned when attempting to set an invalid channel pin as active in the TSC.
+#[derive(Debug)]
+pub enum AcquisitionBankError {
+    /// Indicates that one or more of the provided pins is not a valid channel pin.
+    InvalidChannelPin,
+    /// Indicates that multiple channels from the same group were provided.
+    MultipleChannelsPerGroup,
+}
diff --git a/embassy-stm32/src/tsc/io_pin.rs b/embassy-stm32/src/tsc/io_pin.rs
new file mode 100644
index 000000000..ad2010ed7
--- /dev/null
+++ b/embassy-stm32/src/tsc/io_pin.rs
@@ -0,0 +1,200 @@
+use core::marker::PhantomData;
+use core::ops::{BitAnd, BitOr, BitOrAssign};
+use super::pin_roles;
+use super::types::Group;
+/// Pin defines
+#[allow(missing_docs)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(PartialEq, Clone, Copy, Debug)]
+pub enum IOPin {
+    Group1Io1,
+    Group1Io2,
+    Group1Io3,
+    Group1Io4,
+    Group2Io1,
+    Group2Io2,
+    Group2Io3,
+    Group2Io4,
+    Group3Io1,
+    Group3Io2,
+    Group3Io3,
+    Group3Io4,
+    Group4Io1,
+    Group4Io2,
+    Group4Io3,
+    Group4Io4,
+    Group5Io1,
+    Group5Io2,
+    Group5Io3,
+    Group5Io4,
+    Group6Io1,
+    Group6Io2,
+    Group6Io3,
+    Group6Io4,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    Group7Io1,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    Group7Io2,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    Group7Io3,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    Group7Io4,
+    #[cfg(tsc_v3)]
+    Group8Io1,
+    #[cfg(tsc_v3)]
+    Group8Io2,
+    #[cfg(tsc_v3)]
+    Group8Io3,
+    #[cfg(tsc_v3)]
+    Group8Io4,
+}
+/// Represents a TSC I/O pin with associated group and role information.
+///
+/// This type combines an `tsc::IOPin` with phantom type parameters to statically
+/// encode the pin's group and role. This allows for type-safe operations
+/// on TSC pins within their specific contexts.
+///
+/// - `Group`: A type parameter representing the TSC group (e.g., `G1`, `G2`).
+/// - `Role`: A type parameter representing the pin's role (e.g., `Channel`, `Sample`).
+#[derive(Clone, Copy, Debug)]
+pub struct IOPinWithRole<Group, Role: pin_roles::Role> {
+    /// The underlying TSC I/O pin.
+    pub pin: IOPin,
+    pub(super) phantom: PhantomData<(Group, Role)>,
+}
+impl<G, R: pin_roles::Role> IOPinWithRole<G, R> {
+    pub(super) fn get_pin(wrapped_pin: IOPinWithRole<G, R>) -> IOPin {
+        wrapped_pin.pin
+    }
+}
+impl IOPin {
+    /// Maps this IOPin to the Group it belongs to.
+    ///
+    /// This method provides a convenient way to determine which Group
+    /// a specific TSC I/O pin is associated with.
+    pub const fn group(&self) -> Group {
+        match self {
+            IOPin::Group1Io1 | IOPin::Group1Io2 | IOPin::Group1Io3 | IOPin::Group1Io4 => Group::One,
+            IOPin::Group2Io1 | IOPin::Group2Io2 | IOPin::Group2Io3 | IOPin::Group2Io4 => Group::Two,
+            IOPin::Group3Io1 | IOPin::Group3Io2 | IOPin::Group3Io3 | IOPin::Group3Io4 => Group::Three,
+            IOPin::Group4Io1 | IOPin::Group4Io2 | IOPin::Group4Io3 | IOPin::Group4Io4 => Group::Four,
+            IOPin::Group5Io1 | IOPin::Group5Io2 | IOPin::Group5Io3 | IOPin::Group5Io4 => Group::Five,
+            IOPin::Group6Io1 | IOPin::Group6Io2 | IOPin::Group6Io3 | IOPin::Group6Io4 => Group::Six,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            IOPin::Group7Io1 | IOPin::Group7Io2 | IOPin::Group7Io3 | IOPin::Group7Io4 => Group::Seven,
+            #[cfg(tsc_v3)]
+            IOPin::Group8Io1 | IOPin::Group8Io2 | IOPin::Group8Io3 | IOPin::Group8Io4 => Group::Eight,
+        }
+    }
+    /// Returns the `Group` associated with the given `IOPin`.
+    pub fn get_group(pin: IOPin) -> Group {
+        pin.group()
+    }
+}
+impl BitOr<IOPin> for u32 {
+    type Output = u32;
+    fn bitor(self, rhs: IOPin) -> Self::Output {
+        let rhs: u32 = rhs.into();
+        self | rhs
+    }
+}
+impl BitOr<u32> for IOPin {
+    type Output = u32;
+    fn bitor(self, rhs: u32) -> Self::Output {
+        let val: u32 = self.into();
+        val | rhs
+    }
+}
+impl BitOr for IOPin {
+    type Output = u32;
+    fn bitor(self, rhs: Self) -> Self::Output {
+        let val: u32 = self.into();
+        let rhs: u32 = rhs.into();
+        val | rhs
+    }
+}
+impl BitOrAssign<IOPin> for u32 {
+    fn bitor_assign(&mut self, rhs: IOPin) {
+        let rhs: u32 = rhs.into();
+        *self |= rhs;
+    }
+}
+impl BitAnd<IOPin> for u32 {
+    type Output = u32;
+    fn bitand(self, rhs: IOPin) -> Self::Output {
+        let rhs: u32 = rhs.into();
+        self & rhs
+    }
+}
+impl BitAnd<u32> for IOPin {
+    type Output = u32;
+    fn bitand(self, rhs: u32) -> Self::Output {
+        let val: u32 = self.into();
+        val & rhs
+    }
+}
+impl IOPin {
+    const fn to_u32(self) -> u32 {
+        match self {
+            IOPin::Group1Io1 => 0x00000001,
+            IOPin::Group1Io2 => 0x00000002,
+            IOPin::Group1Io3 => 0x00000004,
+            IOPin::Group1Io4 => 0x00000008,
+            IOPin::Group2Io1 => 0x00000010,
+            IOPin::Group2Io2 => 0x00000020,
+            IOPin::Group2Io3 => 0x00000040,
+            IOPin::Group2Io4 => 0x00000080,
+            IOPin::Group3Io1 => 0x00000100,
+            IOPin::Group3Io2 => 0x00000200,
+            IOPin::Group3Io3 => 0x00000400,
+            IOPin::Group3Io4 => 0x00000800,
+            IOPin::Group4Io1 => 0x00001000,
+            IOPin::Group4Io2 => 0x00002000,
+            IOPin::Group4Io3 => 0x00004000,
+            IOPin::Group4Io4 => 0x00008000,
+            IOPin::Group5Io1 => 0x00010000,
+            IOPin::Group5Io2 => 0x00020000,
+            IOPin::Group5Io3 => 0x00040000,
+            IOPin::Group5Io4 => 0x00080000,
+            IOPin::Group6Io1 => 0x00100000,
+            IOPin::Group6Io2 => 0x00200000,
+            IOPin::Group6Io3 => 0x00400000,
+            IOPin::Group6Io4 => 0x00800000,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            IOPin::Group7Io1 => 0x01000000,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            IOPin::Group7Io2 => 0x02000000,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            IOPin::Group7Io3 => 0x04000000,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            IOPin::Group7Io4 => 0x08000000,
+            #[cfg(tsc_v3)]
+            IOPin::Group8Io1 => 0x10000000,
+            #[cfg(tsc_v3)]
+            IOPin::Group8Io2 => 0x20000000,
+            #[cfg(tsc_v3)]
+            IOPin::Group8Io3 => 0x40000000,
+            #[cfg(tsc_v3)]
+            IOPin::Group8Io4 => 0x80000000,
+        }
+    }
+}
+impl Into<u32> for IOPin {
+    fn into(self) -> u32 {
+        self.to_u32()
+    }
+}
diff --git a/embassy-stm32/src/tsc/mod.rs b/embassy-stm32/src/tsc/mod.rs
index 17240e6bc..9359d83e9 100644
--- a/embassy-stm32/src/tsc/mod.rs
+++ b/embassy-stm32/src/tsc/mod.rs
@@ -1,90 +1,120 @@
 //! TSC Peripheral Interface
 //!
+//! This module provides an interface for the Touch Sensing Controller (TSC) peripheral.
+//! It supports both blocking and async modes of operation, as well as different TSC versions (v1, v2, v3).
 //!
-//! # Example (stm32)
+//! # Key Concepts
-//! ``` rust, ignore
 //!
-//! let mut device_config = embassy_stm32::Config::default();
+//! - **Pin Groups**: TSC pins are organized into groups, each containing up to four IOs.
-//! {
+//! - **Pin Roles**: Each pin in a group can have a role: Channel, Sample, or Shield.
-//!     device_config.rcc.mux = ClockSrc::MSI(Msirange::RANGE_4MHZ);
+//! - **Acquisition Banks**: Used for efficient, repeated TSC acquisitions on specific sets of pins.
-//! }
+//!
+//! # Example (stm32)
 //!
+//! ```rust
+//! let device_config = embassy_stm32::Config::default();
 //! let context = embassy_stm32::init(device_config);
 //!
 //! let config = tsc::Config {
-//!     ct_pulse_high_length: ChargeTransferPulseCycle::_2,
+//!     ct_pulse_high_length: ChargeTransferPulseCycle::_4,
-//!     ct_pulse_low_length: ChargeTransferPulseCycle::_2,
+//!     ct_pulse_low_length: ChargeTransferPulseCycle::_4,
 //!     spread_spectrum: false,
 //!     spread_spectrum_deviation: SSDeviation::new(2).unwrap(),
 //!     spread_spectrum_prescaler: false,
-//!     pulse_generator_prescaler: PGPrescalerDivider::_4,
+//!     pulse_generator_prescaler: PGPrescalerDivider::_16,
-//!     max_count_value: MaxCount::_8191,
+//!     max_count_value: MaxCount::_255,
 //!     io_default_mode: false,
 //!     synchro_pin_polarity: false,
 //!     acquisition_mode: false,
 //!     max_count_interrupt: false,
-//!     channel_ios: TscIOPin::Group2Io2 | TscIOPin::Group7Io3,
-//!     shield_ios: TscIOPin::Group1Io3.into(),
-//!     sampling_ios: TscIOPin::Group1Io2 | TscIOPin::Group2Io1 | TscIOPin::Group7Io2,
 //! };
 //!
-//! let mut g1: PinGroup<embassy_stm32::peripherals::TSC, G1> = PinGroup::new();
+//! let mut g2: PinGroupWithRoles<embassy_stm32::peripherals::TSC, G2> = PinGroupWithRoles::new();
-//! g1.set_io2(context.PB13, PinType::Sample);
+//! g2.set_io1::<tsc_pin_roles::Sample>(context.PB4);
-//! g1.set_io3(context.PB14, PinType::Shield);
+//! let sensor_pin = g2.set_io2::<tsc_pin_roles::Channel>(context.PB5);
-//!
-//! let mut g2: PinGroup<embassy_stm32::peripherals::TSC, G2> = PinGroup::new();
-//! g2.set_io1(context.PB4, PinType::Sample);
-//! g2.set_io2(context.PB5, PinType::Channel);
 //!
-//! let mut g7: PinGroup<embassy_stm32::peripherals::TSC, G7> = PinGroup::new();
+//! let pin_groups = PinGroups {
-//! g7.set_io2(context.PE3, PinType::Sample);
+//!     g2: Some(g2.pin_group),
-//! g7.set_io3(context.PE4, PinType::Channel);
+//!     ..Default::default()
+//! };
 //!
 //! let mut touch_controller = tsc::Tsc::new_blocking(
 //!     context.TSC,
-//!     Some(g1),
+//!     pin_groups,
-//!     Some(g2),
-//!     None,
-//!     None,
-//!     None,
-//!     None,
-//!     Some(g7),
-//!     None,
 //!     config,
-//! );
+//! ).unwrap();
 //!
-//! touch_controller.discharge_io(true);
+//! let discharge_delay = 5; // ms
-//! Timer::after_millis(1).await;
 //!
-//! touch_controller.start();
+//! loop {
+//!     touch_controller.set_active_channels_mask(sensor_pin.pin.into());
+//!     touch_controller.start();
+//!     touch_controller.poll_for_acquisition();
+//!     touch_controller.discharge_io(true);
+//!     Timer::after_millis(discharge_delay).await;
 //!
+//!     match touch_controller.group_get_status(sensor_pin.pin.group()) {
+//!         GroupStatus::Complete => {
+//!             let group_val = touch_controller.group_get_value(sensor_pin.pin.group());
+//!             // Process the touch value
+//!             // ...
+//!         }
+//!         GroupStatus::Ongoing => {
+//!             // Handle ongoing acquisition
+//!             // ...
+//!         }
+//!     }
+//! }
 //! ```
+//!
+//! # Async Usage
+//!
+//! For async operation, use `Tsc::new_async` and `pend_for_acquisition` instead of polling.
 #![macro_use]
-/// Enums defined for peripheral parameters
+/// Configuration structures and enums for the TSC peripheral.
-pub mod enums;
+pub mod config;
+/// Definitions and implementations for TSC pin groups.
+pub mod pin_groups;
+/// Definitions and implementations for individual TSC I/O pins.
+pub mod io_pin;
+/// Structures and implementations for TSC acquisition banks.
+pub mod acquisition_banks;
+/// Core implementation of the TSC (Touch Sensing Controller) driver.
+pub mod tsc;
+/// Type definitions used throughout the TSC module.
+pub mod types;
+/// Error types and definitions for the TSC module.
+pub mod errors;
-use core::future::poll_fn;
 use core::marker::PhantomData;
-use core::task::Poll;
-use embassy_hal_internal::{into_ref, PeripheralRef};
+pub use acquisition_banks::*;
+pub use config::*;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
-pub use enums::*;
+pub use errors::*;
+pub use io_pin::*;
+pub use pin_groups::*;
+pub use tsc::*;
+pub use types::*;
-use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::rcc::RccPeripheral;
-use crate::interrupt::typelevel::Interrupt;
+use crate::{interrupt, peripherals};
-use crate::mode::{Async, Blocking, Mode as PeriMode};
-use crate::rcc::{self, RccPeripheral};
-use crate::{interrupt, peripherals, Peripheral};
 #[cfg(tsc_v1)]
-const TSC_NUM_GROUPS: u32 = 6;
+const TSC_NUM_GROUPS: usize = 6;
 #[cfg(tsc_v2)]
-const TSC_NUM_GROUPS: u32 = 7;
+const TSC_NUM_GROUPS: usize = 7;
 #[cfg(tsc_v3)]
-const TSC_NUM_GROUPS: u32 = 8;
+const TSC_NUM_GROUPS: usize = 8;
 /// Error type defined for TSC
 #[derive(Debug, Clone, Copy)]
@@ -106,859 +136,6 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
    }
 }
-/// Pin type definition to control IO parameters
-pub enum PinType {
-    /// Sensing channel pin connected to an electrode
-    Channel,
-    /// Sampling capacitor pin, one required for every pin group
-    Sample,
-    /// Shield pin connected to capacitive sensing shield
-    Shield,
-}
-/// Peripheral state
-#[derive(PartialEq, Clone, Copy)]
-pub enum State {
-    /// Peripheral is being setup or reconfigured
-    Reset,
-    /// Ready to start acquisition
-    Ready,
-    /// In process of sensor acquisition
-    Busy,
-    /// Error occured during acquisition
-    Error,
-}
-/// Individual group status checked after acquisition reported as complete
-/// For groups with multiple channel pins, may take longer because acquisitions
-/// are done sequentially. Check this status before pulling count for each
-/// sampled channel
-#[derive(PartialEq)]
-pub enum GroupStatus {
-    /// Acquisition for channel still in progress
-    Ongoing,
-    /// Acquisition either not started or complete
-    Complete,
-}
-/// Group identifier used to interrogate status
-#[allow(missing_docs)]
-pub enum Group {
-    One,
-    Two,
-    Three,
-    Four,
-    Five,
-    Six,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    Seven,
-    #[cfg(tsc_v3)]
-    Eight,
-}
-impl Into<usize> for Group {
-    fn into(self) -> usize {
-        match self {
-            Group::One => 0,
-            Group::Two => 1,
-            Group::Three => 2,
-            Group::Four => 3,
-            Group::Five => 4,
-            Group::Six => 5,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            Group::Seven => 6,
-            #[cfg(tsc_v3)]
-            Group::Eight => 7,
-        }
-    }
-}
-/// Peripheral configuration
-#[derive(Clone, Copy)]
-pub struct Config {
-    /// Duration of high state of the charge transfer pulse
-    pub ct_pulse_high_length: ChargeTransferPulseCycle,
-    /// Duration of the low state of the charge transfer pulse
-    pub ct_pulse_low_length: ChargeTransferPulseCycle,
-    /// Enable/disable of spread spectrum feature
-    pub spread_spectrum: bool,
-    /// Adds variable number of periods of the SS clk to pulse high state
-    pub spread_spectrum_deviation: SSDeviation,
-    /// Selects AHB clock divider used to generate SS clk
-    pub spread_spectrum_prescaler: bool,
-    /// Selects AHB clock divider used to generate pulse generator clk
-    pub pulse_generator_prescaler: PGPrescalerDivider,
-    /// Maximum number of charge transfer pulses that can be generated before error
-    pub max_count_value: MaxCount,
-    /// Defines config of all IOs when no ongoing acquisition
-    pub io_default_mode: bool,
-    /// Polarity of sync input pin
-    pub synchro_pin_polarity: bool,
-    /// Acquisition starts when start bit is set or with sync pin input
-    pub acquisition_mode: bool,
-    /// Enable max count interrupt
-    pub max_count_interrupt: bool,
-    /// Channel IO mask
-    pub channel_ios: u32,
-    /// Shield IO mask
-    pub shield_ios: u32,
-    /// Sampling IO mask
-    pub sampling_ios: u32,
-}
-impl Default for Config {
-    fn default() -> Self {
-        Self {
-            ct_pulse_high_length: ChargeTransferPulseCycle::_1,
-            ct_pulse_low_length: ChargeTransferPulseCycle::_1,
-            spread_spectrum: false,
-            spread_spectrum_deviation: SSDeviation::new(1).unwrap(),
-            spread_spectrum_prescaler: false,
-            pulse_generator_prescaler: PGPrescalerDivider::_1,
-            max_count_value: MaxCount::_255,
-            io_default_mode: false,
-            synchro_pin_polarity: false,
-            acquisition_mode: false,
-            max_count_interrupt: false,
-            channel_ios: 0,
-            shield_ios: 0,
-            sampling_ios: 0,
-        }
-    }
-}
-/// Pin struct that maintains usage
-#[allow(missing_docs)]
-pub struct TscPin<'d, T, C> {
-    _pin: PeripheralRef<'d, AnyPin>,
-    role: PinType,
-    phantom: PhantomData<(T, C)>,
-}
-enum GroupError {
-    NoSample,
-    ChannelShield,
-}
-/// Pin group definition
-/// Pins are organized into groups of four IOs, all groups with a
-/// sampling channel must also have a sampling capacitor channel.
-#[allow(missing_docs)]
-#[derive(Default)]
-pub struct PinGroup<'d, T, C> {
-    d1: Option<TscPin<'d, T, C>>,
-    d2: Option<TscPin<'d, T, C>>,
-    d3: Option<TscPin<'d, T, C>>,
-    d4: Option<TscPin<'d, T, C>>,
-}
-impl<'d, T: Instance, C> PinGroup<'d, T, C> {
-    /// Create new sensing group
-    pub fn new() -> Self {
-        Self {
-            d1: None,
-            d2: None,
-            d3: None,
-            d4: None,
-        }
-    }
-    fn contains_shield(&self) -> bool {
-        let mut shield_count = 0;
-        if let Some(pin) = &self.d1 {
-            if let PinType::Shield = pin.role {
-                shield_count += 1;
-            }
-        }
-        if let Some(pin) = &self.d2 {
-            if let PinType::Shield = pin.role {
-                shield_count += 1;
-            }
-        }
-        if let Some(pin) = &self.d3 {
-            if let PinType::Shield = pin.role {
-                shield_count += 1;
-            }
-        }
-        if let Some(pin) = &self.d4 {
-            if let PinType::Shield = pin.role {
-                shield_count += 1;
-            }
-        }
-        shield_count == 1
-    }
-    fn check_group(&self) -> Result<(), GroupError> {
-        let mut channel_count = 0;
-        let mut shield_count = 0;
-        let mut sample_count = 0;
-        if let Some(pin) = &self.d1 {
-            match pin.role {
-                PinType::Channel => {
-                    channel_count += 1;
-                }
-                PinType::Shield => {
-                    shield_count += 1;
-                }
-                PinType::Sample => {
-                    sample_count += 1;
-                }
-            }
-        }
-        if let Some(pin) = &self.d2 {
-            match pin.role {
-                PinType::Channel => {
-                    channel_count += 1;
-                }
-                PinType::Shield => {
-                    shield_count += 1;
-                }
-                PinType::Sample => {
-                    sample_count += 1;
-                }
-            }
-        }
-        if let Some(pin) = &self.d3 {
-            match pin.role {
-                PinType::Channel => {
-                    channel_count += 1;
-                }
-                PinType::Shield => {
-                    shield_count += 1;
-                }
-                PinType::Sample => {
-                    sample_count += 1;
-                }
-            }
-        }
-        if let Some(pin) = &self.d4 {
-            match pin.role {
-                PinType::Channel => {
-                    channel_count += 1;
-                }
-                PinType::Shield => {
-                    shield_count += 1;
-                }
-                PinType::Sample => {
-                    sample_count += 1;
-                }
-            }
-        }
-        // Every group requires one sampling capacitor
-        if sample_count != 1 {
-            return Err(GroupError::NoSample);
-        }
-        // Each group must have at least one shield or channel IO
-        if shield_count == 0 && channel_count == 0 {
-            return Err(GroupError::ChannelShield);
-        }
-        // Any group can either contain channel ios or a shield IO
-        if shield_count != 0 && channel_count != 0 {
-            return Err(GroupError::ChannelShield);
-        }
-        // No more than one shield IO is allow per group and amongst all groups
-        if shield_count > 1 {
-            return Err(GroupError::ChannelShield);
-        }
-        Ok(())
-    }
-}
-macro_rules! group_impl {
-    ($group:ident, $trait1:ident, $trait2:ident, $trait3:ident, $trait4:ident) => {
-        impl<'d, T: Instance> PinGroup<'d, T, $group> {
-            #[doc = concat!("Create a new pin1 for ", stringify!($group), " TSC group instance.")]
-            pub fn set_io1(&mut self, pin: impl Peripheral<P = impl $trait1<T>> + 'd, role: PinType) {
-                into_ref!(pin);
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(
-                            match role {
-                                PinType::Channel => OutputType::PushPull,
-                                PinType::Sample => OutputType::OpenDrain,
-                                PinType::Shield => OutputType::PushPull,
-                            },
-                            Speed::VeryHigh,
-                        ),
-                    );
-                    self.d1 = Some(TscPin {
-                        _pin: pin.map_into(),
-                        role: role,
-                        phantom: PhantomData,
-                    })
-                })
-            }
-            #[doc = concat!("Create a new pin2 for ", stringify!($group), " TSC group instance.")]
-            pub fn set_io2(&mut self, pin: impl Peripheral<P = impl $trait2<T>> + 'd, role: PinType) {
-                into_ref!(pin);
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(
-                            match role {
-                                PinType::Channel => OutputType::PushPull,
-                                PinType::Sample => OutputType::OpenDrain,
-                                PinType::Shield => OutputType::PushPull,
-                            },
-                            Speed::VeryHigh,
-                        ),
-                    );
-                    self.d2 = Some(TscPin {
-                        _pin: pin.map_into(),
-                        role: role,
-                        phantom: PhantomData,
-                    })
-                })
-            }
-            #[doc = concat!("Create a new pin3 for ", stringify!($group), " TSC group instance.")]
-            pub fn set_io3(&mut self, pin: impl Peripheral<P = impl $trait3<T>> + 'd, role: PinType) {
-                into_ref!(pin);
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(
-                            match role {
-                                PinType::Channel => OutputType::PushPull,
-                                PinType::Sample => OutputType::OpenDrain,
-                                PinType::Shield => OutputType::PushPull,
-                            },
-                            Speed::VeryHigh,
-                        ),
-                    );
-                    self.d3 = Some(TscPin {
-                        _pin: pin.map_into(),
-                        role: role,
-                        phantom: PhantomData,
-                    })
-                })
-            }
-            #[doc = concat!("Create a new pin4 for ", stringify!($group), " TSC group instance.")]
-            pub fn set_io4(&mut self, pin: impl Peripheral<P = impl $trait4<T>> + 'd, role: PinType) {
-                into_ref!(pin);
-                critical_section::with(|_| {
-                    pin.set_low();
-                    pin.set_as_af(
-                        pin.af_num(),
-                        AfType::output(
-                            match role {
-                                PinType::Channel => OutputType::PushPull,
-                                PinType::Sample => OutputType::OpenDrain,
-                                PinType::Shield => OutputType::PushPull,
-                            },
-                            Speed::VeryHigh,
-                        ),
-                    );
-                    self.d4 = Some(TscPin {
-                        _pin: pin.map_into(),
-                        role: role,
-                        phantom: PhantomData,
-                    })
-                })
-            }
-        }
-    };
-}
-group_impl!(G1, G1IO1Pin, G1IO2Pin, G1IO3Pin, G1IO4Pin);
-group_impl!(G2, G2IO1Pin, G2IO2Pin, G2IO3Pin, G2IO4Pin);
-group_impl!(G3, G3IO1Pin, G3IO2Pin, G3IO3Pin, G3IO4Pin);
-group_impl!(G4, G4IO1Pin, G4IO2Pin, G4IO3Pin, G4IO4Pin);
-group_impl!(G5, G5IO1Pin, G5IO2Pin, G5IO3Pin, G5IO4Pin);
-group_impl!(G6, G6IO1Pin, G6IO2Pin, G6IO3Pin, G6IO4Pin);
-group_impl!(G7, G7IO1Pin, G7IO2Pin, G7IO3Pin, G7IO4Pin);
-group_impl!(G8, G8IO1Pin, G8IO2Pin, G8IO3Pin, G8IO4Pin);
-/// Group 1 marker type.
-pub enum G1 {}
-/// Group 2 marker type.
-pub enum G2 {}
-/// Group 3 marker type.
-pub enum G3 {}
-/// Group 4 marker type.
-pub enum G4 {}
-/// Group 5 marker type.
-pub enum G5 {}
-/// Group 6 marker type.
-pub enum G6 {}
-/// Group 7 marker type.
-pub enum G7 {}
-/// Group 8 marker type.
-pub enum G8 {}
-/// TSC driver
-pub struct Tsc<'d, T: Instance, K: PeriMode> {
-    _peri: PeripheralRef<'d, T>,
-    _g1: Option<PinGroup<'d, T, G1>>,
-    _g2: Option<PinGroup<'d, T, G2>>,
-    _g3: Option<PinGroup<'d, T, G3>>,
-    _g4: Option<PinGroup<'d, T, G4>>,
-    _g5: Option<PinGroup<'d, T, G5>>,
-    _g6: Option<PinGroup<'d, T, G6>>,
-    #[cfg(any(tsc_v2, tsc_v3))]
-    _g7: Option<PinGroup<'d, T, G7>>,
-    #[cfg(tsc_v3)]
-    _g8: Option<PinGroup<'d, T, G8>>,
-    state: State,
-    config: Config,
-    _kind: PhantomData<K>,
-}
-impl<'d, T: Instance> Tsc<'d, T, Async> {
-    /// Create a Tsc instance that can be awaited for completion
-    pub fn new_async(
-        peri: impl Peripheral<P = T> + 'd,
-        g1: Option<PinGroup<'d, T, G1>>,
-        g2: Option<PinGroup<'d, T, G2>>,
-        g3: Option<PinGroup<'d, T, G3>>,
-        g4: Option<PinGroup<'d, T, G4>>,
-        g5: Option<PinGroup<'d, T, G5>>,
-        g6: Option<PinGroup<'d, T, G6>>,
-        #[cfg(any(tsc_v2, tsc_v3))] g7: Option<PinGroup<'d, T, G7>>,
-        #[cfg(tsc_v3)] g8: Option<PinGroup<'d, T, G8>>,
-        config: Config,
-        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-    ) -> Self {
-        // Need to check valid pin configuration input
-        let g1 = g1.filter(|b| b.check_group().is_ok());
-        let g2 = g2.filter(|b| b.check_group().is_ok());
-        let g3 = g3.filter(|b| b.check_group().is_ok());
-        let g4 = g4.filter(|b| b.check_group().is_ok());
-        let g5 = g5.filter(|b| b.check_group().is_ok());
-        let g6 = g6.filter(|b| b.check_group().is_ok());
-        #[cfg(any(tsc_v2, tsc_v3))]
-        let g7 = g7.filter(|b| b.check_group().is_ok());
-        #[cfg(tsc_v3)]
-        let g8 = g8.filter(|b| b.check_group().is_ok());
-        match Self::check_shields(
-            &g1,
-            &g2,
-            &g3,
-            &g4,
-            &g5,
-            &g6,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            &g7,
-            #[cfg(tsc_v3)]
-            &g8,
-        ) {
-            Ok(()) => Self::new_inner(
-                peri,
-                g1,
-                g2,
-                g3,
-                g4,
-                g5,
-                g6,
-                #[cfg(any(tsc_v2, tsc_v3))]
-                g7,
-                #[cfg(tsc_v3)]
-                g8,
-                config,
-            ),
-            Err(_) => Self::new_inner(
-                peri,
-                None,
-                None,
-                None,
-                None,
-                None,
-                None,
-                #[cfg(any(tsc_v2, tsc_v3))]
-                None,
-                #[cfg(tsc_v3)]
-                None,
-                config,
-            ),
-        }
-    }
-    /// Asyncronously wait for the end of an acquisition
-    pub async fn pend_for_acquisition(&mut self) {
-        poll_fn(|cx| match self.get_state() {
-            State::Busy => {
-                T::waker().register(cx.waker());
-                T::regs().ier().write(|w| w.set_eoaie(true));
-                if self.get_state() != State::Busy {
-                    T::regs().ier().write(|w| w.set_eoaie(false));
-                    return Poll::Ready(());
-                }
-                Poll::Pending
-            }
-            _ => {
-                T::regs().ier().write(|w| w.set_eoaie(false));
-                Poll::Ready(())
-            }
-        })
-        .await;
-    }
-}
-impl<'d, T: Instance> Tsc<'d, T, Blocking> {
-    /// Create a Tsc instance that must be polled for completion
-    pub fn new_blocking(
-        peri: impl Peripheral<P = T> + 'd,
-        g1: Option<PinGroup<'d, T, G1>>,
-        g2: Option<PinGroup<'d, T, G2>>,
-        g3: Option<PinGroup<'d, T, G3>>,
-        g4: Option<PinGroup<'d, T, G4>>,
-        g5: Option<PinGroup<'d, T, G5>>,
-        g6: Option<PinGroup<'d, T, G6>>,
-        #[cfg(any(tsc_v2, tsc_v3))] g7: Option<PinGroup<'d, T, G7>>,
-        #[cfg(tsc_v3)] g8: Option<PinGroup<'d, T, G8>>,
-        config: Config,
-    ) -> Self {
-        // Need to check valid pin configuration input
-        let g1 = g1.filter(|b| b.check_group().is_ok());
-        let g2 = g2.filter(|b| b.check_group().is_ok());
-        let g3 = g3.filter(|b| b.check_group().is_ok());
-        let g4 = g4.filter(|b| b.check_group().is_ok());
-        let g5 = g5.filter(|b| b.check_group().is_ok());
-        let g6 = g6.filter(|b| b.check_group().is_ok());
-        #[cfg(any(tsc_v2, tsc_v3))]
-        let g7 = g7.filter(|b| b.check_group().is_ok());
-        #[cfg(tsc_v3)]
-        let g8 = g8.filter(|b| b.check_group().is_ok());
-        match Self::check_shields(
-            &g1,
-            &g2,
-            &g3,
-            &g4,
-            &g5,
-            &g6,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            &g7,
-            #[cfg(tsc_v3)]
-            &g8,
-        ) {
-            Ok(()) => Self::new_inner(
-                peri,
-                g1,
-                g2,
-                g3,
-                g4,
-                g5,
-                g6,
-                #[cfg(any(tsc_v2, tsc_v3))]
-                g7,
-                #[cfg(tsc_v3)]
-                g8,
-                config,
-            ),
-            Err(_) => Self::new_inner(
-                peri,
-                None,
-                None,
-                None,
-                None,
-                None,
-                None,
-                #[cfg(any(tsc_v2, tsc_v3))]
-                None,
-                #[cfg(tsc_v3)]
-                None,
-                config,
-            ),
-        }
-    }
-    /// Wait for end of acquisition
-    pub fn poll_for_acquisition(&mut self) {
-        while self.get_state() == State::Busy {}
-    }
-}
-impl<'d, T: Instance, K: PeriMode> Tsc<'d, T, K> {
-    /// Create new TSC driver
-    fn check_shields(
-        g1: &Option<PinGroup<'d, T, G1>>,
-        g2: &Option<PinGroup<'d, T, G2>>,
-        g3: &Option<PinGroup<'d, T, G3>>,
-        g4: &Option<PinGroup<'d, T, G4>>,
-        g5: &Option<PinGroup<'d, T, G5>>,
-        g6: &Option<PinGroup<'d, T, G6>>,
-        #[cfg(any(tsc_v2, tsc_v3))] g7: &Option<PinGroup<'d, T, G7>>,
-        #[cfg(tsc_v3)] g8: &Option<PinGroup<'d, T, G8>>,
-    ) -> Result<(), GroupError> {
-        let mut shield_count = 0;
-        if let Some(pin_group) = g1 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if let Some(pin_group) = g2 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if let Some(pin_group) = g3 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if let Some(pin_group) = g4 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if let Some(pin_group) = g5 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if let Some(pin_group) = g6 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        #[cfg(any(tsc_v2, tsc_v3))]
-        if let Some(pin_group) = g7 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        #[cfg(tsc_v3)]
-        if let Some(pin_group) = g8 {
-            if pin_group.contains_shield() {
-                shield_count += 1;
-            }
-        };
-        if shield_count > 1 {
-            return Err(GroupError::ChannelShield);
-        }
-        Ok(())
-    }
-    fn extract_groups(io_mask: u32) -> u32 {
-        let mut groups: u32 = 0;
-        for idx in 0..TSC_NUM_GROUPS {
-            if io_mask & (0x0F << idx * 4) != 0 {
-                groups |= 1 << idx
-            }
-        }
-        groups
-    }
-    fn new_inner(
-        peri: impl Peripheral<P = T> + 'd,
-        g1: Option<PinGroup<'d, T, G1>>,
-        g2: Option<PinGroup<'d, T, G2>>,
-        g3: Option<PinGroup<'d, T, G3>>,
-        g4: Option<PinGroup<'d, T, G4>>,
-        g5: Option<PinGroup<'d, T, G5>>,
-        g6: Option<PinGroup<'d, T, G6>>,
-        #[cfg(any(tsc_v2, tsc_v3))] g7: Option<PinGroup<'d, T, G7>>,
-        #[cfg(tsc_v3)] g8: Option<PinGroup<'d, T, G8>>,
-        config: Config,
-    ) -> Self {
-        into_ref!(peri);
-        rcc::enable_and_reset::<T>();
-        T::regs().cr().modify(|w| {
-            w.set_tsce(true);
-            w.set_ctph(config.ct_pulse_high_length.into());
-            w.set_ctpl(config.ct_pulse_low_length.into());
-            w.set_sse(config.spread_spectrum);
-            // Prevent invalid configuration for pulse generator prescaler
-            if config.ct_pulse_low_length == ChargeTransferPulseCycle::_1
-                && (config.pulse_generator_prescaler == PGPrescalerDivider::_1
-                    || config.pulse_generator_prescaler == PGPrescalerDivider::_2)
-            {
-                w.set_pgpsc(PGPrescalerDivider::_4.into());
-            } else if config.ct_pulse_low_length == ChargeTransferPulseCycle::_2
-                && config.pulse_generator_prescaler == PGPrescalerDivider::_1
-            {
-                w.set_pgpsc(PGPrescalerDivider::_2.into());
-            } else {
-                w.set_pgpsc(config.pulse_generator_prescaler.into());
-            }
-            w.set_ssd(config.spread_spectrum_deviation.into());
-            w.set_sspsc(config.spread_spectrum_prescaler);
-            w.set_mcv(config.max_count_value.into());
-            w.set_syncpol(config.synchro_pin_polarity);
-            w.set_am(config.acquisition_mode);
-        });
-        // Set IO configuration
-        // Disable Schmitt trigger hysteresis on all used TSC IOs
-        T::regs()
-            .iohcr()
-            .write(|w| w.0 = !(config.channel_ios | config.shield_ios | config.sampling_ios));
-        // Set channel and shield IOs
-        T::regs()
-            .ioccr()
-            .write(|w| w.0 = config.channel_ios | config.shield_ios);
-        // Set sampling IOs
-        T::regs().ioscr().write(|w| w.0 = config.sampling_ios);
-        // Set the groups to be acquired
-        T::regs()
-            .iogcsr()
-            .write(|w| w.0 = Self::extract_groups(config.channel_ios));
-        // Disable interrupts
-        T::regs().ier().modify(|w| {
-            w.set_eoaie(false);
-            w.set_mceie(false);
-        });
-        // Clear flags
-        T::regs().icr().modify(|w| {
-            w.set_eoaic(true);
-            w.set_mceic(true);
-        });
-        unsafe {
-            T::Interrupt::enable();
-        }
-        Self {
-            _peri: peri,
-            _g1: g1,
-            _g2: g2,
-            _g3: g3,
-            _g4: g4,
-            _g5: g5,
-            _g6: g6,
-            #[cfg(any(tsc_v2, tsc_v3))]
-            _g7: g7,
-            #[cfg(tsc_v3)]
-            _g8: g8,
-            state: State::Ready,
-            config,
-            _kind: PhantomData,
-        }
-    }
-    /// Start charge transfer acquisition
-    pub fn start(&mut self) {
-        self.state = State::Busy;
-        // Disable interrupts
-        T::regs().ier().modify(|w| {
-            w.set_eoaie(false);
-            w.set_mceie(false);
-        });
-        // Clear flags
-        T::regs().icr().modify(|w| {
-            w.set_eoaic(true);
-            w.set_mceic(true);
-        });
-        // Set the touch sensing IOs not acquired to the default mode
-        T::regs().cr().modify(|w| {
-            w.set_iodef(self.config.io_default_mode);
-        });
-        // Start the acquisition
-        T::regs().cr().modify(|w| {
-            w.set_start(true);
-        });
-    }
-    /// Stop charge transfer acquisition
-    pub fn stop(&mut self) {
-        T::regs().cr().modify(|w| {
-            w.set_start(false);
-        });
-        // Set the touch sensing IOs in low power mode
-        T::regs().cr().modify(|w| {
-            w.set_iodef(false);
-        });
-        // Clear flags
-        T::regs().icr().modify(|w| {
-            w.set_eoaic(true);
-            w.set_mceic(true);
-        });
-        self.state = State::Ready;
-    }
-    /// Get current state of acquisition
-    pub fn get_state(&mut self) -> State {
-        if self.state == State::Busy {
-            if T::regs().isr().read().eoaf() {
-                if T::regs().isr().read().mcef() {
-                    self.state = State::Error
-                } else {
-                    self.state = State::Ready
-                }
-            }
-        }
-        self.state
-    }
-    /// Get the individual group status to check acquisition complete
-    pub fn group_get_status(&mut self, index: Group) -> GroupStatus {
-        // Status bits are set by hardware when the acquisition on the corresponding
-        // enabled analog IO group is complete, cleared when new acquisition is started
-        let status = match index {
-            Group::One => T::regs().iogcsr().read().g1s(),
-            Group::Two => T::regs().iogcsr().read().g2s(),
-            Group::Three => T::regs().iogcsr().read().g3s(),
-            Group::Four => T::regs().iogcsr().read().g4s(),
-            Group::Five => T::regs().iogcsr().read().g5s(),
-            Group::Six => T::regs().iogcsr().read().g6s(),
-            #[cfg(any(tsc_v2, tsc_v3))]
-            Group::Seven => T::regs().iogcsr().read().g7s(),
-            #[cfg(tsc_v3)]
-            Group::Eight => T::regs().iogcsr().read().g8s(),
-        };
-        match status {
-            true => GroupStatus::Complete,
-            false => GroupStatus::Ongoing,
-        }
-    }
-    /// Get the count for the acquisiton, valid once group status is set
-    pub fn group_get_value(&mut self, index: Group) -> u16 {
-        T::regs().iogcr(index.into()).read().cnt()
-    }
-    /// Discharge the IOs for subsequent acquisition
-    pub fn discharge_io(&mut self, status: bool) {
-        // Set the touch sensing IOs in low power mode
-        T::regs().cr().modify(|w| {
-            w.set_iodef(!status);
-        });
-    }
-}
-impl<'d, T: Instance, K: PeriMode> Drop for Tsc<'d, T, K> {
-    fn drop(&mut self) {
-        rcc::disable::<T>();
-    }
-}
 pub(crate) trait SealedInstance {
    fn regs() -> crate::pac::tsc::Tsc;
    fn waker() -> &'static AtomicWaker;
@@ -966,7 +143,7 @@ pub(crate) trait SealedInstance {
 /// TSC instance trait
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + RccPeripheral {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {
    /// Interrupt for this TSC instance
    type Interrupt: interrupt::typelevel::Interrupt;
 }
@@ -988,36 +165,3 @@ foreach_interrupt!(
        }
    };
 );
-pin_trait!(G1IO1Pin, Instance);
-pin_trait!(G1IO2Pin, Instance);
-pin_trait!(G1IO3Pin, Instance);
-pin_trait!(G1IO4Pin, Instance);
-pin_trait!(G2IO1Pin, Instance);
-pin_trait!(G2IO2Pin, Instance);
-pin_trait!(G2IO3Pin, Instance);
-pin_trait!(G2IO4Pin, Instance);
-pin_trait!(G3IO1Pin, Instance);
-pin_trait!(G3IO2Pin, Instance);
-pin_trait!(G3IO3Pin, Instance);
-pin_trait!(G3IO4Pin, Instance);
-pin_trait!(G4IO1Pin, Instance);
-pin_trait!(G4IO2Pin, Instance);
-pin_trait!(G4IO3Pin, Instance);
-pin_trait!(G4IO4Pin, Instance);
-pin_trait!(G5IO1Pin, Instance);
-pin_trait!(G5IO2Pin, Instance);
-pin_trait!(G5IO3Pin, Instance);
-pin_trait!(G5IO4Pin, Instance);
-pin_trait!(G6IO1Pin, Instance);
-pin_trait!(G6IO2Pin, Instance);
-pin_trait!(G6IO3Pin, Instance);
-pin_trait!(G6IO4Pin, Instance);
-pin_trait!(G7IO1Pin, Instance);
-pin_trait!(G7IO2Pin, Instance);
-pin_trait!(G7IO3Pin, Instance);
-pin_trait!(G7IO4Pin, Instance);
-pin_trait!(G8IO1Pin, Instance);
-pin_trait!(G8IO2Pin, Instance);
-pin_trait!(G8IO3Pin, Instance);
-pin_trait!(G8IO4Pin, Instance);
diff --git a/embassy-stm32/src/tsc/pin_groups.rs b/embassy-stm32/src/tsc/pin_groups.rs
new file mode 100644
index 000000000..6f914a94e
--- /dev/null
+++ b/embassy-stm32/src/tsc/pin_groups.rs
@@ -0,0 +1,663 @@
+use core::marker::PhantomData;
+use core::ops::BitOr;
+use super::errors::GroupError;
+use super::io_pin::*;
+use super::Instance;
+use crate::gpio::{AfType, AnyPin, OutputType, Speed};
+use crate::Peri;
+/// Pin type definition to control IO parameters
+#[derive(PartialEq, Clone, Copy)]
+pub enum PinType {
+    /// Sensing channel pin connected to an electrode
+    Channel,
+    /// Sampling capacitor pin, one required for every pin group
+    Sample,
+    /// Shield pin connected to capacitive sensing shield
+    Shield,
+}
+/// Pin struct that maintains usage
+#[allow(missing_docs)]
+pub struct Pin<'d, T, Group> {
+    _pin: Peri<'d, AnyPin>,
+    role: PinType,
+    tsc_io_pin: IOPin,
+    phantom: PhantomData<(T, Group)>,
+}
+impl<'d, T, Group> Pin<'d, T, Group> {
+    /// Returns the role of this TSC pin.
+    ///
+    /// The role indicates whether this pin is configured as a channel,
+    /// sampling capacitor, or shield in the TSC group.
+    ///
+    /// # Returns
+    /// The `PinType` representing the role of this pin.
+    pub fn role(&self) -> PinType {
+        self.role
+    }
+    /// Returns the TSC IO pin associated with this pin.
+    ///
+    /// This method provides access to the specific TSC IO pin configuration,
+    /// which includes information about the pin's group and position within that group.
+    ///
+    /// # Returns
+    /// The `IOPin` representing this pin's TSC-specific configuration.
+    pub fn tsc_io_pin(&self) -> IOPin {
+        self.tsc_io_pin
+    }
+}
+/// Represents a group of TSC (Touch Sensing Controller) pins.
+///
+/// In the TSC peripheral, pins are organized into groups of four IOs. Each group
+/// must have exactly one sampling capacitor pin and can have multiple channel pins
+/// or a single shield pin. This structure encapsulates these pin configurations
+/// for a single TSC group.
+///
+/// # Pin Roles
+/// - Sampling Capacitor: One required per group, used for charge transfer.
+/// - Channel: Sensing pins connected to electrodes for touch detection.
+/// - Shield: Optional, used for active shielding to improve sensitivity.
+///
+/// # Constraints
+/// - Each group must have exactly one sampling capacitor pin.
+/// - A group can have either channel pins or a shield pin, but not both.
+/// - No more than one shield pin is allowed across all groups.
+#[allow(missing_docs)]
+pub struct PinGroup<'d, T, Group> {
+    pin1: Option<Pin<'d, T, Group>>,
+    pin2: Option<Pin<'d, T, Group>>,
+    pin3: Option<Pin<'d, T, Group>>,
+    pin4: Option<Pin<'d, T, Group>>,
+}
+impl<'d, T, G> Default for PinGroup<'d, T, G> {
+    fn default() -> Self {
+        Self {
+            pin1: None,
+            pin2: None,
+            pin3: None,
+            pin4: None,
+        }
+    }
+}
+/// Defines roles and traits for TSC (Touch Sensing Controller) pins.
+///
+/// This module contains marker types and traits that represent different roles
+/// a TSC pin can have, such as channel, sample, or shield.
+pub mod pin_roles {
+    use super::{OutputType, PinType};
+    /// Marker type for a TSC channel pin.
+    #[derive(PartialEq, Clone, Copy, Debug)]
+    pub struct Channel;
+    /// Marker type for a TSC sampling pin.
+    #[derive(PartialEq, Clone, Copy, Debug)]
+    pub struct Sample;
+    /// Marker type for a TSC shield pin.
+    #[derive(PartialEq, Clone, Copy, Debug)]
+    pub struct Shield;
+    /// Trait for TSC pin roles.
+    ///
+    /// This trait defines the behavior and properties of different TSC pin roles.
+    /// It is implemented by the marker types `Channel`, `Sample`, and `Shield`.
+    pub trait Role {
+        /// Returns the `PinType` associated with this role.
+        fn pin_type() -> PinType;
+        /// Returns the `OutputType` associated with this role.
+        fn output_type() -> OutputType;
+    }
+    impl Role for Channel {
+        fn pin_type() -> PinType {
+            PinType::Channel
+        }
+        fn output_type() -> OutputType {
+            OutputType::PushPull
+        }
+    }
+    impl Role for Sample {
+        fn pin_type() -> PinType {
+            PinType::Sample
+        }
+        fn output_type() -> OutputType {
+            OutputType::OpenDrain
+        }
+    }
+    impl Role for Shield {
+        fn pin_type() -> PinType {
+            PinType::Shield
+        }
+        fn output_type() -> OutputType {
+            OutputType::PushPull
+        }
+    }
+}
+/// Represents a group of TSC pins with their associated roles.
+///
+/// This struct allows for type-safe configuration of TSC pin groups,
+/// ensuring that pins are assigned appropriate roles within their group.
+/// This type is essentially just a wrapper type around a `PinGroup` value.
+///
+/// # Type Parameters
+/// - `'d`: Lifetime of the pin group.
+/// - `T`: The TSC instance type.
+/// - `G`: The group identifier.
+/// - `R1`, `R2`, `R3`, `R4`: Role types for each pin in the group, defaulting to `Channel`.
+pub struct PinGroupWithRoles<
+    'd,
+    T: Instance,
+    G,
+    R1 = pin_roles::Channel,
+    R2 = pin_roles::Channel,
+    R3 = pin_roles::Channel,
+    R4 = pin_roles::Channel,
+> {
+    /// The underlying pin group without role information.
+    pub pin_group: PinGroup<'d, T, G>,
+    _phantom: PhantomData<(R1, R2, R3, R4)>,
+}
+impl<'d, T: Instance, G, R1, R2, R3, R4> Default for PinGroupWithRoles<'d, T, G, R1, R2, R3, R4> {
+    fn default() -> Self {
+        Self {
+            pin_group: PinGroup::default(),
+            _phantom: PhantomData,
+        }
+    }
+}
+impl<'d, T: Instance, G> PinGroup<'d, T, G> {
+    fn contains_exactly_one_shield_pin(&self) -> bool {
+        let shield_count = self.shield_pins().count();
+        shield_count == 1
+    }
+    fn check_group(&self) -> Result<(), GroupError> {
+        let mut channel_count = 0;
+        let mut shield_count = 0;
+        let mut sample_count = 0;
+        for pin in self.pins().into_iter().flatten() {
+            match pin.role {
+                PinType::Channel => {
+                    channel_count += 1;
+                }
+                PinType::Shield => {
+                    shield_count += 1;
+                }
+                PinType::Sample => {
+                    sample_count += 1;
+                }
+            }
+        }
+        // Every group requires exactly one sampling capacitor
+        if sample_count != 1 {
+            return Err(GroupError::NoSamplingCapacitor);
+        }
+        // Each group must have at least one shield or channel IO
+        if shield_count == 0 && channel_count == 0 {
+            return Err(GroupError::NoChannelOrShield);
+        }
+        // Any group can either contain channel ios or a shield IO.
+        // (An active shield requires its own sampling capacitor)
+        if shield_count != 0 && channel_count != 0 {
+            return Err(GroupError::MixedChannelAndShield);
+        }
+        // No more than one shield IO is allow per group and amongst all groups
+        if shield_count > 1 {
+            return Err(GroupError::MultipleShields);
+        }
+        Ok(())
+    }
+    /// Returns a reference to the first pin in the group, if configured.
+    pub fn pin1(&self) -> Option<&Pin<'d, T, G>> {
+        self.pin1.as_ref()
+    }
+    /// Returns a reference to the second pin in the group, if configured.
+    pub fn pin2(&self) -> Option<&Pin<'d, T, G>> {
+        self.pin2.as_ref()
+    }
+    /// Returns a reference to the third pin in the group, if configured.
+    pub fn pin3(&self) -> Option<&Pin<'d, T, G>> {
+        self.pin3.as_ref()
+    }
+    /// Returns a reference to the fourth pin in the group, if configured.
+    pub fn pin4(&self) -> Option<&Pin<'d, T, G>> {
+        self.pin4.as_ref()
+    }
+    fn sample_pins(&self) -> impl Iterator<Item = IOPin> + '_ {
+        self.pins_filtered(PinType::Sample)
+    }
+    fn shield_pins(&self) -> impl Iterator<Item = IOPin> + '_ {
+        self.pins_filtered(PinType::Shield)
+    }
+    fn channel_pins(&self) -> impl Iterator<Item = IOPin> + '_ {
+        self.pins_filtered(PinType::Channel)
+    }
+    fn pins_filtered(&self, pin_type: PinType) -> impl Iterator<Item = IOPin> + '_ {
+        self.pins().into_iter().filter_map(move |pin| {
+            pin.as_ref()
+                .and_then(|p| if p.role == pin_type { Some(p.tsc_io_pin) } else { None })
+        })
+    }
+    fn make_channel_ios_mask(&self) -> u32 {
+        self.channel_pins().fold(0, u32::bitor)
+    }
+    fn make_shield_ios_mask(&self) -> u32 {
+        self.shield_pins().fold(0, u32::bitor)
+    }
+    fn make_sample_ios_mask(&self) -> u32 {
+        self.sample_pins().fold(0, u32::bitor)
+    }
+    fn pins(&self) -> [&Option<Pin<'d, T, G>>; 4] {
+        [&self.pin1, &self.pin2, &self.pin3, &self.pin4]
+    }
+    fn pins_mut(&mut self) -> [&mut Option<Pin<'d, T, G>>; 4] {
+        [&mut self.pin1, &mut self.pin2, &mut self.pin3, &mut self.pin4]
+    }
+}
+#[cfg(any(tsc_v2, tsc_v3))]
+macro_rules! TSC_V2_V3_GUARD {
+    ($e:expr) => {{
+        #[cfg(any(tsc_v2, tsc_v3))]
+        {
+            $e
+        }
+        #[cfg(not(any(tsc_v2, tsc_v3)))]
+        {
+            compile_error!("Group 7 is not supported in this TSC version")
+        }
+    }};
+}
+#[cfg(tsc_v3)]
+macro_rules! TSC_V3_GUARD {
+    ($e:expr) => {{
+        #[cfg(tsc_v3)]
+        {
+            $e
+        }
+        #[cfg(not(tsc_v3))]
+        {
+            compile_error!("Group 8 is not supported in this TSC version")
+        }
+    }};
+}
+macro_rules! trait_to_io_pin {
+    (G1IO1Pin) => {
+        IOPin::Group1Io1
+    };
+    (G1IO2Pin) => {
+        IOPin::Group1Io2
+    };
+    (G1IO3Pin) => {
+        IOPin::Group1Io3
+    };
+    (G1IO4Pin) => {
+        IOPin::Group1Io4
+    };
+    (G2IO1Pin) => {
+        IOPin::Group2Io1
+    };
+    (G2IO2Pin) => {
+        IOPin::Group2Io2
+    };
+    (G2IO3Pin) => {
+        IOPin::Group2Io3
+    };
+    (G2IO4Pin) => {
+        IOPin::Group2Io4
+    };
+    (G3IO1Pin) => {
+        IOPin::Group3Io1
+    };
+    (G3IO2Pin) => {
+        IOPin::Group3Io2
+    };
+    (G3IO3Pin) => {
+        IOPin::Group3Io3
+    };
+    (G3IO4Pin) => {
+        IOPin::Group3Io4
+    };
+    (G4IO1Pin) => {
+        IOPin::Group4Io1
+    };
+    (G4IO2Pin) => {
+        IOPin::Group4Io2
+    };
+    (G4IO3Pin) => {
+        IOPin::Group4Io3
+    };
+    (G4IO4Pin) => {
+        IOPin::Group4Io4
+    };
+    (G5IO1Pin) => {
+        IOPin::Group5Io1
+    };
+    (G5IO2Pin) => {
+        IOPin::Group5Io2
+    };
+    (G5IO3Pin) => {
+        IOPin::Group5Io3
+    };
+    (G5IO4Pin) => {
+        IOPin::Group5Io4
+    };
+    (G6IO1Pin) => {
+        IOPin::Group6Io1
+    };
+    (G6IO2Pin) => {
+        IOPin::Group6Io2
+    };
+    (G6IO3Pin) => {
+        IOPin::Group6Io3
+    };
+    (G6IO4Pin) => {
+        IOPin::Group6Io4
+    };
+    (G7IO1Pin) => {
+        TSC_V2_V3_GUARD!(IOPin::Group7Io1)
+    };
+    (G7IO2Pin) => {
+        TSC_V2_V3_GUARD!(IOPin::Group7Io2)
+    };
+    (G7IO3Pin) => {
+        TSC_V2_V3_GUARD!(IOPin::Group7Io3)
+    };
+    (G7IO4Pin) => {
+        TSC_V2_V3_GUARD!(IOPin::Group7Io4)
+    };
+    (G8IO1Pin) => {
+        TSC_V3_GUARD!(IOPin::Group8Io1)
+    };
+    (G8IO2Pin) => {
+        TSC_V3_GUARD!(IOPin::Group8Io2)
+    };
+    (G8IO3Pin) => {
+        TSC_V3_GUARD!(IOPin::Group8Io3)
+    };
+    (G8IO4Pin) => {
+        TSC_V3_GUARD!(IOPin::Group8Io4)
+    };
+}
+macro_rules! impl_set_io {
+    ($method:ident, $group:ident, $trait:ident, $index:expr) => {
+        #[doc = concat!("Create a new pin1 for ", stringify!($group), " TSC group instance.")]
+        pub fn $method<Role: pin_roles::Role>(&mut self, pin: Peri<'d, impl $trait<T>>) -> IOPinWithRole<$group, Role> {
+            critical_section::with(|_| {
+                pin.set_low();
+                pin.set_as_af(pin.af_num(), AfType::output(Role::output_type(), Speed::VeryHigh));
+                let tsc_io_pin = trait_to_io_pin!($trait);
+                let new_pin = Pin {
+                    _pin: pin.into(),
+                    role: Role::pin_type(),
+                    tsc_io_pin,
+                    phantom: PhantomData,
+                };
+                *self.pin_group.pins_mut()[$index] = Some(new_pin);
+                IOPinWithRole {
+                    pin: tsc_io_pin,
+                    phantom: PhantomData,
+                }
+            })
+        }
+    };
+}
+macro_rules! group_impl {
+    ($group:ident, $trait1:ident, $trait2:ident, $trait3:ident, $trait4:ident) => {
+        impl<'d, T: Instance, R1: pin_roles::Role, R2: pin_roles::Role, R3: pin_roles::Role, R4: pin_roles::Role>
+            PinGroupWithRoles<'d, T, $group, R1, R2, R3, R4>
+        {
+            impl_set_io!(set_io1, $group, $trait1, 0);
+            impl_set_io!(set_io2, $group, $trait2, 1);
+            impl_set_io!(set_io3, $group, $trait3, 2);
+            impl_set_io!(set_io4, $group, $trait4, 3);
+        }
+    };
+}
+group_impl!(G1, G1IO1Pin, G1IO2Pin, G1IO3Pin, G1IO4Pin);
+group_impl!(G2, G2IO1Pin, G2IO2Pin, G2IO3Pin, G2IO4Pin);
+group_impl!(G3, G3IO1Pin, G3IO2Pin, G3IO3Pin, G3IO4Pin);
+group_impl!(G4, G4IO1Pin, G4IO2Pin, G4IO3Pin, G4IO4Pin);
+group_impl!(G5, G5IO1Pin, G5IO2Pin, G5IO3Pin, G5IO4Pin);
+group_impl!(G6, G6IO1Pin, G6IO2Pin, G6IO3Pin, G6IO4Pin);
+#[cfg(any(tsc_v2, tsc_v3))]
+group_impl!(G7, G7IO1Pin, G7IO2Pin, G7IO3Pin, G7IO4Pin);
+#[cfg(tsc_v3)]
+group_impl!(G8, G8IO1Pin, G8IO2Pin, G8IO3Pin, G8IO4Pin);
+/// Group 1 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G1 {}
+/// Group 2 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G2 {}
+/// Group 3 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G3 {}
+/// Group 4 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G4 {}
+/// Group 5 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G5 {}
+/// Group 6 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G6 {}
+/// Group 7 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G7 {}
+/// Group 8 marker type.
+#[derive(Clone, Copy, Debug)]
+pub enum G8 {}
+/// Represents the collection of pin groups for the Touch Sensing Controller (TSC).
+///
+/// Each field corresponds to a specific group of TSC pins:
+#[allow(missing_docs)]
+pub struct PinGroups<'d, T: Instance> {
+    pub g1: Option<PinGroup<'d, T, G1>>,
+    pub g2: Option<PinGroup<'d, T, G2>>,
+    pub g3: Option<PinGroup<'d, T, G3>>,
+    pub g4: Option<PinGroup<'d, T, G4>>,
+    pub g5: Option<PinGroup<'d, T, G5>>,
+    pub g6: Option<PinGroup<'d, T, G6>>,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    pub g7: Option<PinGroup<'d, T, G7>>,
+    #[cfg(tsc_v3)]
+    pub g8: Option<PinGroup<'d, T, G8>>,
+}
+impl<'d, T: Instance> PinGroups<'d, T> {
+    pub(super) fn check(&self) -> Result<(), GroupError> {
+        let mut shield_count = 0;
+        // Helper function to check a single group
+        fn check_group<C, T: Instance>(
+            group: &Option<PinGroup<'_, T, C>>,
+            shield_count: &mut u32,
+        ) -> Result<(), GroupError> {
+            if let Some(group) = group {
+                group.check_group()?;
+                if group.contains_exactly_one_shield_pin() {
+                    *shield_count += 1;
+                    if *shield_count > 1 {
+                        return Err(GroupError::MultipleShields);
+                    }
+                }
+            }
+            Ok(())
+        }
+        // Check each group
+        check_group(&self.g1, &mut shield_count)?;
+        check_group(&self.g2, &mut shield_count)?;
+        check_group(&self.g3, &mut shield_count)?;
+        check_group(&self.g4, &mut shield_count)?;
+        check_group(&self.g5, &mut shield_count)?;
+        check_group(&self.g6, &mut shield_count)?;
+        #[cfg(any(tsc_v2, tsc_v3))]
+        check_group(&self.g7, &mut shield_count)?;
+        #[cfg(tsc_v3)]
+        check_group(&self.g8, &mut shield_count)?;
+        Ok(())
+    }
+    pub(super) fn make_channel_ios_mask(&self) -> u32 {
+        #[allow(unused_mut)]
+        let mut mask = self.g1.as_ref().map_or(0, |g| g.make_channel_ios_mask())
+            | self.g2.as_ref().map_or(0, |g| g.make_channel_ios_mask())
+            | self.g3.as_ref().map_or(0, |g| g.make_channel_ios_mask())
+            | self.g4.as_ref().map_or(0, |g| g.make_channel_ios_mask())
+            | self.g5.as_ref().map_or(0, |g| g.make_channel_ios_mask())
+            | self.g6.as_ref().map_or(0, |g| g.make_channel_ios_mask());
+        #[cfg(any(tsc_v2, tsc_v3))]
+        {
+            mask |= self.g7.as_ref().map_or(0, |g| g.make_channel_ios_mask());
+        }
+        #[cfg(tsc_v3)]
+        {
+            mask |= self.g8.as_ref().map_or(0, |g| g.make_channel_ios_mask());
+        }
+        mask
+    }
+    pub(super) fn make_shield_ios_mask(&self) -> u32 {
+        #[allow(unused_mut)]
+        let mut mask = self.g1.as_ref().map_or(0, |g| g.make_shield_ios_mask())
+            | self.g2.as_ref().map_or(0, |g| g.make_shield_ios_mask())
+            | self.g3.as_ref().map_or(0, |g| g.make_shield_ios_mask())
+            | self.g4.as_ref().map_or(0, |g| g.make_shield_ios_mask())
+            | self.g5.as_ref().map_or(0, |g| g.make_shield_ios_mask())
+            | self.g6.as_ref().map_or(0, |g| g.make_shield_ios_mask());
+        #[cfg(any(tsc_v2, tsc_v3))]
+        {
+            mask |= self.g7.as_ref().map_or(0, |g| g.make_shield_ios_mask());
+        }
+        #[cfg(tsc_v3)]
+        {
+            mask |= self.g8.as_ref().map_or(0, |g| g.make_shield_ios_mask());
+        }
+        mask
+    }
+    pub(super) fn make_sample_ios_mask(&self) -> u32 {
+        #[allow(unused_mut)]
+        let mut mask = self.g1.as_ref().map_or(0, |g| g.make_sample_ios_mask())
+            | self.g2.as_ref().map_or(0, |g| g.make_sample_ios_mask())
+            | self.g3.as_ref().map_or(0, |g| g.make_sample_ios_mask())
+            | self.g4.as_ref().map_or(0, |g| g.make_sample_ios_mask())
+            | self.g5.as_ref().map_or(0, |g| g.make_sample_ios_mask())
+            | self.g6.as_ref().map_or(0, |g| g.make_sample_ios_mask());
+        #[cfg(any(tsc_v2, tsc_v3))]
+        {
+            mask |= self.g7.as_ref().map_or(0, |g| g.make_sample_ios_mask());
+        }
+        #[cfg(tsc_v3)]
+        {
+            mask |= self.g8.as_ref().map_or(0, |g| g.make_sample_ios_mask());
+        }
+        mask
+    }
+}
+impl<'d, T: Instance> Default for PinGroups<'d, T> {
+    fn default() -> Self {
+        Self {
+            g1: None,
+            g2: None,
+            g3: None,
+            g4: None,
+            g5: None,
+            g6: None,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            g7: None,
+            #[cfg(tsc_v3)]
+            g8: None,
+        }
+    }
+}
+pin_trait!(G1IO1Pin, Instance);
+pin_trait!(G1IO2Pin, Instance);
+pin_trait!(G1IO3Pin, Instance);
+pin_trait!(G1IO4Pin, Instance);
+pin_trait!(G2IO1Pin, Instance);
+pin_trait!(G2IO2Pin, Instance);
+pin_trait!(G2IO3Pin, Instance);
+pin_trait!(G2IO4Pin, Instance);
+pin_trait!(G3IO1Pin, Instance);
+pin_trait!(G3IO2Pin, Instance);
+pin_trait!(G3IO3Pin, Instance);
+pin_trait!(G3IO4Pin, Instance);
+pin_trait!(G4IO1Pin, Instance);
+pin_trait!(G4IO2Pin, Instance);
+pin_trait!(G4IO3Pin, Instance);
+pin_trait!(G4IO4Pin, Instance);
+pin_trait!(G5IO1Pin, Instance);
+pin_trait!(G5IO2Pin, Instance);
+pin_trait!(G5IO3Pin, Instance);
+pin_trait!(G5IO4Pin, Instance);
+pin_trait!(G6IO1Pin, Instance);
+pin_trait!(G6IO2Pin, Instance);
+pin_trait!(G6IO3Pin, Instance);
+pin_trait!(G6IO4Pin, Instance);
+pin_trait!(G7IO1Pin, Instance);
+pin_trait!(G7IO2Pin, Instance);
+pin_trait!(G7IO3Pin, Instance);
+pin_trait!(G7IO4Pin, Instance);
+pin_trait!(G8IO1Pin, Instance);
+pin_trait!(G8IO2Pin, Instance);
+pin_trait!(G8IO3Pin, Instance);
+pin_trait!(G8IO4Pin, Instance);
diff --git a/embassy-stm32/src/tsc/tsc.rs b/embassy-stm32/src/tsc/tsc.rs
new file mode 100644
index 000000000..e92479c26
--- /dev/null
+++ b/embassy-stm32/src/tsc/tsc.rs
@@ -0,0 +1,446 @@
+use core::future::poll_fn;
+use core::marker::PhantomData;
+use core::ops::BitOr;
+use core::task::Poll;
+use embassy_hal_internal::Peri;
+use super::acquisition_banks::*;
+use super::config::*;
+use super::errors::*;
+use super::io_pin::*;
+use super::pin_groups::*;
+use super::types::*;
+use super::{Instance, InterruptHandler, TSC_NUM_GROUPS};
+use crate::interrupt::typelevel::Interrupt;
+use crate::mode::{Async, Blocking, Mode as PeriMode};
+use crate::{interrupt, rcc};
+/// Internal structure holding masks for different types of TSC IOs.
+///
+/// These masks are used during the initial configuration of the TSC peripheral
+/// and for validating pin types during operations like creating acquisition banks.
+struct IOMasks {
+    /// Mask representing all configured channel IOs
+    channel_ios: u32,
+    /// Mask representing all configured shield IOs
+    shield_ios: u32,
+    /// Mask representing all configured sampling IOs
+    sampling_ios: u32,
+}
+/// TSC driver
+pub struct Tsc<'d, T: Instance, K: PeriMode> {
+    _peri: Peri<'d, T>,
+    _pin_groups: PinGroups<'d, T>,
+    state: State,
+    config: Config,
+    masks: IOMasks,
+    _kind: PhantomData<K>,
+}
+impl<'d, T: Instance, K: PeriMode> Tsc<'d, T, K> {
+    // Helper method to check if a pin is a channel pin
+    fn is_channel_pin(&self, pin: IOPin) -> bool {
+        (self.masks.channel_ios & pin) != 0
+    }
+    /// Get the status of all groups involved in a AcquisitionBank
+    pub fn get_acquisition_bank_status(&self, bank: &AcquisitionBank) -> AcquisitionBankStatus {
+        let mut bank_status = AcquisitionBankStatus::default();
+        for pin in bank.pins_iterator() {
+            let group = pin.group();
+            let group_status = self.group_get_status(group);
+            let index: usize = group.into();
+            bank_status.groups[index] = Some(group_status);
+        }
+        bank_status
+    }
+    /// Get the values for all channels involved in a AcquisitionBank
+    pub fn get_acquisition_bank_values(&self, bank: &AcquisitionBank) -> AcquisitionBankReadings {
+        let mut bank_readings = AcquisitionBankReadings::default();
+        for pin in bank.pins_iterator() {
+            let group = pin.group();
+            let value = self.group_get_value(group);
+            let reading = ChannelReading {
+                sensor_value: value,
+                tsc_pin: pin,
+            };
+            let index: usize = group.into();
+            bank_readings.groups[index] = Some(reading);
+        }
+        bank_readings
+    }
+    /// Creates a new TSC acquisition bank from the provided pin configuration.
+    ///
+    /// This method creates a `AcquisitionBank` that can be used for efficient,
+    /// repeated TSC acquisitions. It automatically generates the appropriate mask
+    /// for the provided pins.
+    ///
+    /// # Note on TSC Hardware Limitation
+    ///
+    /// The TSC hardware can only read one channel pin from each TSC group per acquisition.
+    ///
+    /// # Arguments
+    /// * `acquisition_bank_pins` - The pin configuration for the acquisition bank.
+    ///
+    /// # Returns
+    /// A new `AcquisitionBank` instance.
+    ///
+    /// # Example
+    ///
+    /// ```
+    /// let tsc = // ... initialize TSC
+    /// let tsc_sensor1: tsc::IOPinWithRole<G1, tsc_pin_roles::Channel> = ...;
+    /// let tsc_sensor2: tsc::IOPinWithRole<G2, tsc_pin_roles::Channel> = ...;
+    ///
+    /// let bank = tsc.create_acquisition_bank(AcquisitionBankPins {
+    ///     g1_pin: Some(tsc_sensor1),
+    ///     g2_pin: Some(tsc_sensor2),
+    ///     ..Default::default()
+    /// });
+    ///
+    /// // Use the bank for acquisitions
+    /// tsc.set_active_channels_bank(&bank);
+    /// tsc.start();
+    /// // ... perform acquisition ...
+    /// ```
+    pub fn create_acquisition_bank(&self, acquisition_bank_pins: AcquisitionBankPins) -> AcquisitionBank {
+        let bank_mask = acquisition_bank_pins.iter().fold(0u32, BitOr::bitor);
+        AcquisitionBank {
+            pins: acquisition_bank_pins,
+            mask: bank_mask,
+        }
+    }
+    fn make_channels_mask<Itt>(&self, channels: Itt) -> Result<u32, AcquisitionBankError>
+    where
+        Itt: IntoIterator<Item = IOPin>,
+    {
+        let mut group_mask = 0u32;
+        let mut channel_mask = 0u32;
+        for channel in channels {
+            if !self.is_channel_pin(channel) {
+                return Err(AcquisitionBankError::InvalidChannelPin);
+            }
+            let group = channel.group();
+            let group_bit: u32 = 1 << Into::<usize>::into(group);
+            if group_mask & group_bit != 0 {
+                return Err(AcquisitionBankError::MultipleChannelsPerGroup);
+            }
+            group_mask |= group_bit;
+            channel_mask |= channel;
+        }
+        Ok(channel_mask)
+    }
+    /// Sets the active channels for the next TSC acquisition.
+    ///
+    /// This is a low-level method that directly sets the channel mask. For most use cases,
+    /// consider using `set_active_channels_bank` with a `AcquisitionBank` instead, which
+    /// provides a higher-level interface and additional safety checks.
+    ///
+    /// This method configures which sensor channels will be read during the next
+    /// touch sensing acquisition cycle. It should be called before starting a new
+    /// acquisition with the start() method.
+    ///
+    /// # Arguments
+    /// * `mask` - A 32-bit mask where each bit represents a channel. Set bits indicate
+    ///            active channels.
+    ///
+    /// # Note
+    /// Only one pin from each TSC group can be read for each acquisition. This method
+    /// does not perform checks to ensure this limitation is met. Incorrect masks may
+    /// lead to unexpected behavior.
+    ///
+    /// # Safety
+    /// This method doesn't perform extensive checks on the provided mask. Ensure that
+    /// the mask is valid and adheres to hardware limitations to avoid undefined behavior.
+    pub fn set_active_channels_mask(&mut self, mask: u32) {
+        T::regs().ioccr().write(|w| w.0 = mask | self.masks.shield_ios);
+    }
+    /// Convenience method for setting active channels directly from a slice of tsc::IOPin.
+    /// This method performs safety checks but is less efficient for repeated use.
+    pub fn set_active_channels(&mut self, channels: &[IOPin]) -> Result<(), AcquisitionBankError> {
+        let mask = self.make_channels_mask(channels.iter().cloned())?;
+        self.set_active_channels_mask(mask);
+        Ok(())
+    }
+    /// Sets the active channels for the next TSC acquisition using a pre-configured acquisition bank.
+    ///
+    /// This method efficiently configures the TSC peripheral to read the channels specified
+    /// in the provided `AcquisitionBank`. It's the recommended way to set up
+    /// channel configurations for acquisition, especially when using the same set of channels repeatedly.
+    ///
+    /// # Arguments
+    ///
+    /// * `bank` - A reference to a `AcquisitionBank` containing the pre-configured
+    ///            TSC channel mask.
+    ///
+    /// # Example
+    ///
+    /// ```
+    /// let tsc_sensor1: tsc::IOPinWithRole<G1, Channel> = ...;
+    /// let tsc_sensor2: tsc::IOPinWithRole<G5, Channel> = ...;
+    /// let mut touch_controller: Tsc<'_, TSC, Async> = ...;
+    /// let bank = touch_controller.create_acquisition_bank(AcquisitionBankPins {
+    ///     g1_pin: Some(tsc_sensor1),
+    ///     g2_pin: Some(tsc_sensor2),
+    ///     ..Default::default()
+    /// });
+    ///
+    /// touch_controller.set_active_channels_bank(&bank);
+    /// touch_controller.start();
+    /// // ... perform acquisition ...
+    /// ```
+    ///
+    /// This method should be called before starting a new acquisition with the `start()` method.
+    pub fn set_active_channels_bank(&mut self, bank: &AcquisitionBank) {
+        self.set_active_channels_mask(bank.mask)
+    }
+    fn extract_groups(io_mask: u32) -> u32 {
+        let mut groups: u32 = 0;
+        for idx in 0..TSC_NUM_GROUPS {
+            if io_mask & (0x0F << (idx * 4)) != 0 {
+                groups |= 1 << idx
+            }
+        }
+        groups
+    }
+    fn new_inner(peri: Peri<'d, T>, pin_groups: PinGroups<'d, T>, config: Config) -> Result<Self, GroupError> {
+        pin_groups.check()?;
+        let masks = IOMasks {
+            channel_ios: pin_groups.make_channel_ios_mask(),
+            shield_ios: pin_groups.make_shield_ios_mask(),
+            sampling_ios: pin_groups.make_sample_ios_mask(),
+        };
+        rcc::enable_and_reset::<T>();
+        T::regs().cr().modify(|w| {
+            w.set_tsce(true);
+            w.set_ctph(config.ct_pulse_high_length.into());
+            w.set_ctpl(config.ct_pulse_low_length.into());
+            w.set_sse(config.spread_spectrum);
+            // Prevent invalid configuration for pulse generator prescaler
+            if config.ct_pulse_low_length == ChargeTransferPulseCycle::_1
+                && (config.pulse_generator_prescaler == PGPrescalerDivider::_1
+                    || config.pulse_generator_prescaler == PGPrescalerDivider::_2)
+            {
+                w.set_pgpsc(PGPrescalerDivider::_4.into());
+            } else if config.ct_pulse_low_length == ChargeTransferPulseCycle::_2
+                && config.pulse_generator_prescaler == PGPrescalerDivider::_1
+            {
+                w.set_pgpsc(PGPrescalerDivider::_2.into());
+            } else {
+                w.set_pgpsc(config.pulse_generator_prescaler.into());
+            }
+            w.set_ssd(config.spread_spectrum_deviation.into());
+            w.set_sspsc(config.spread_spectrum_prescaler);
+            w.set_mcv(config.max_count_value.into());
+            w.set_syncpol(config.synchro_pin_polarity);
+            w.set_am(config.acquisition_mode);
+        });
+        // Set IO configuration
+        // Disable Schmitt trigger hysteresis on all used TSC IOs
+        T::regs()
+            .iohcr()
+            .write(|w| w.0 = !(masks.channel_ios | masks.shield_ios | masks.sampling_ios));
+        // Set channel and shield IOs
+        T::regs().ioccr().write(|w| w.0 = masks.channel_ios | masks.shield_ios);
+        // Set sampling IOs
+        T::regs().ioscr().write(|w| w.0 = masks.sampling_ios);
+        // Set the groups to be acquired
+        // Lower bits of `iogcsr` are for enabling groups, while the higher bits are for reading
+        // status of acquisiton for a group, see method `Tsc::group_get_status`.
+        T::regs()
+            .iogcsr()
+            .write(|w| w.0 = Self::extract_groups(masks.channel_ios));
+        // Disable interrupts
+        T::regs().ier().modify(|w| {
+            w.set_eoaie(false);
+            w.set_mceie(false);
+        });
+        // Clear flags
+        T::regs().icr().modify(|w| {
+            w.set_eoaic(true);
+            w.set_mceic(true);
+        });
+        unsafe {
+            T::Interrupt::enable();
+        }
+        Ok(Self {
+            _peri: peri,
+            _pin_groups: pin_groups,
+            state: State::Ready,
+            config,
+            masks,
+            _kind: PhantomData,
+        })
+    }
+    /// Start charge transfer acquisition
+    pub fn start(&mut self) {
+        self.state = State::Busy;
+        // Disable interrupts
+        T::regs().ier().modify(|w| {
+            w.set_eoaie(false);
+            w.set_mceie(false);
+        });
+        // Clear flags
+        T::regs().icr().modify(|w| {
+            w.set_eoaic(true);
+            w.set_mceic(true);
+        });
+        // Set the touch sensing IOs not acquired to the default mode
+        T::regs().cr().modify(|w| {
+            w.set_iodef(self.config.io_default_mode);
+        });
+        // Start the acquisition
+        T::regs().cr().modify(|w| {
+            w.set_start(true);
+        });
+    }
+    /// Stop charge transfer acquisition
+    pub fn stop(&mut self) {
+        T::regs().cr().modify(|w| {
+            w.set_start(false);
+        });
+        // Set the touch sensing IOs in low power mode
+        T::regs().cr().modify(|w| {
+            w.set_iodef(false);
+        });
+        // Clear flags
+        T::regs().icr().modify(|w| {
+            w.set_eoaic(true);
+            w.set_mceic(true);
+        });
+        self.state = State::Ready;
+    }
+    /// Get current state of acquisition
+    pub fn get_state(&mut self) -> State {
+        if self.state == State::Busy && T::regs().isr().read().eoaf() {
+            if T::regs().isr().read().mcef() {
+                self.state = State::Error
+            } else {
+                self.state = State::Ready
+            }
+        }
+        self.state
+    }
+    /// Get the individual group status to check acquisition complete
+    pub fn group_get_status(&self, index: Group) -> GroupStatus {
+        // Status bits are set by hardware when the acquisition on the corresponding
+        // enabled analog IO group is complete, cleared when new acquisition is started
+        let status = match index {
+            Group::One => T::regs().iogcsr().read().g1s(),
+            Group::Two => T::regs().iogcsr().read().g2s(),
+            Group::Three => T::regs().iogcsr().read().g3s(),
+            Group::Four => T::regs().iogcsr().read().g4s(),
+            Group::Five => T::regs().iogcsr().read().g5s(),
+            Group::Six => T::regs().iogcsr().read().g6s(),
+            #[cfg(any(tsc_v2, tsc_v3))]
+            Group::Seven => T::regs().iogcsr().read().g7s(),
+            #[cfg(tsc_v3)]
+            Group::Eight => T::regs().iogcsr().read().g8s(),
+        };
+        match status {
+            true => GroupStatus::Complete,
+            false => GroupStatus::Ongoing,
+        }
+    }
+    /// Get the count for the acquisiton, valid once group status is set
+    pub fn group_get_value(&self, index: Group) -> u16 {
+        T::regs().iogcr(index.into()).read().cnt()
+    }
+    /// Discharge the IOs for subsequent acquisition
+    pub fn discharge_io(&mut self, status: bool) {
+        // Set the touch sensing IOs in low power mode
+        T::regs().cr().modify(|w| {
+            w.set_iodef(!status);
+        });
+    }
+}
+impl<'d, T: Instance, K: PeriMode> Drop for Tsc<'d, T, K> {
+    fn drop(&mut self) {
+        rcc::disable::<T>();
+    }
+}
+impl<'d, T: Instance> Tsc<'d, T, Async> {
+    /// Create a Tsc instance that can be awaited for completion
+    pub fn new_async(
+        peri: Peri<'d, T>,
+        pin_groups: PinGroups<'d, T>,
+        config: Config,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+    ) -> Result<Self, GroupError> {
+        Self::new_inner(peri, pin_groups, config)
+    }
+    /// Asyncronously wait for the end of an acquisition
+    pub async fn pend_for_acquisition(&mut self) {
+        poll_fn(|cx| match self.get_state() {
+            State::Busy => {
+                T::waker().register(cx.waker());
+                T::regs().ier().write(|w| w.set_eoaie(true));
+                if self.get_state() != State::Busy {
+                    T::regs().ier().write(|w| w.set_eoaie(false));
+                    return Poll::Ready(());
+                }
+                Poll::Pending
+            }
+            _ => {
+                T::regs().ier().write(|w| w.set_eoaie(false));
+                Poll::Ready(())
+            }
+        })
+        .await;
+    }
+}
+impl<'d, T: Instance> Tsc<'d, T, Blocking> {
+    /// Create a Tsc instance that must be polled for completion
+    pub fn new_blocking(peri: Peri<'d, T>, pin_groups: PinGroups<'d, T>, config: Config) -> Result<Self, GroupError> {
+        Self::new_inner(peri, pin_groups, config)
+    }
+    /// Wait for end of acquisition
+    pub fn poll_for_acquisition(&mut self) {
+        while self.get_state() == State::Busy {}
+    }
+}
diff --git a/embassy-stm32/src/tsc/types.rs b/embassy-stm32/src/tsc/types.rs
new file mode 100644
index 000000000..0e8fa7f28
--- /dev/null
+++ b/embassy-stm32/src/tsc/types.rs
@@ -0,0 +1,93 @@
+/// Peripheral state
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(PartialEq, Clone, Copy)]
+pub enum State {
+    /// Peripheral is being setup or reconfigured
+    Reset,
+    /// Ready to start acquisition
+    Ready,
+    /// In process of sensor acquisition
+    Busy,
+    /// Error occured during acquisition
+    Error,
+}
+/// Individual group status checked after acquisition reported as complete
+/// For groups with multiple channel pins, may take longer because acquisitions
+/// are done sequentially. Check this status before pulling count for each
+/// sampled channel
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[derive(PartialEq, Clone, Copy)]
+pub enum GroupStatus {
+    /// Acquisition for channel still in progress
+    Ongoing,
+    /// Acquisition either not started or complete
+    Complete,
+}
+/// Group identifier used to interrogate status
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+#[allow(missing_docs)]
+#[derive(PartialEq, Clone, Copy)]
+pub enum Group {
+    One,
+    Two,
+    Three,
+    Four,
+    Five,
+    Six,
+    #[cfg(any(tsc_v2, tsc_v3))]
+    Seven,
+    #[cfg(tsc_v3)]
+    Eight,
+}
+impl Into<usize> for Group {
+    fn into(self) -> usize {
+        match self {
+            Group::One => 0,
+            Group::Two => 1,
+            Group::Three => 2,
+            Group::Four => 3,
+            Group::Five => 4,
+            Group::Six => 5,
+            #[cfg(any(tsc_v2, tsc_v3))]
+            Group::Seven => 6,
+            #[cfg(tsc_v3)]
+            Group::Eight => 7,
+        }
+    }
+}
+/// Error returned when attempting to create a Group from an invalid numeric value.
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
+pub struct InvalidGroupError {
+    invalid_value: usize,
+}
+impl InvalidGroupError {
+    #[allow(missing_docs)]
+    pub fn new(value: usize) -> Self {
+        Self { invalid_value: value }
+    }
+}
+impl TryFrom<usize> for Group {
+    type Error = InvalidGroupError;
+    fn try_from(value: usize) -> Result<Self, Self::Error> {
+        match value {
+            0 => Ok(Group::One),
+            1 => Ok(Group::Two),
+            2 => Ok(Group::Three),
+            3 => Ok(Group::Four),
+            4 => Ok(Group::Five),
+            5 => Ok(Group::Six),
+            #[cfg(any(tsc_v2, tsc_v3))]
+            6 => Ok(Group::Two),
+            #[cfg(tsc_v3)]
+            7 => Ok(Group::Two),
+            n => Err(InvalidGroupError::new(n)),
+        }
+    }
+}
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index 40aea75cb..87693f148 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -20,15 +20,15 @@ use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use crate::dma::{ChannelAndRequest, TransferOptions};
-use crate::interrupt;
 use crate::interrupt::typelevel::Interrupt;
 use crate::pac::ucpd::vals::{Anamode, Ccenable, PscUsbpdclk, Txmode};
-pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, TypecVstateCc as CcVState};
+pub use crate::pac::ucpd::vals::{Phyccsel as CcSel, Rxordset, TypecVstateCc as CcVState};
 use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, Peri};
 pub(crate) fn init(
    _cs: critical_section::CriticalSection,
@@ -86,6 +86,34 @@ pub enum CcPull {
    Source3_0A,
 }
+/// UCPD configuration
+#[non_exhaustive]
+#[derive(Copy, Clone, Debug)]
+pub struct Config {
+    /// Receive SOP packets
+    pub sop: bool,
+    /// Receive SOP' packets
+    pub sop_prime: bool,
+    /// Receive SOP'' packets
+    pub sop_double_prime: bool,
+    /// Receive SOP'_Debug packets
+    pub sop_prime_debug: bool,
+    /// Receive SOP''_Debug packets
+    pub sop_double_prime_debug: bool,
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            sop: true,
+            sop_prime: false,
+            sop_double_prime: false,
+            sop_prime_debug: false,
+            sop_double_prime_debug: false,
+        }
+    }
+}
 /// UCPD driver.
 pub struct Ucpd<'d, T: Instance> {
    cc_phy: CcPhy<'d, T>,
@@ -94,12 +122,12 @@ pub struct Ucpd<'d, T: Instance> {
 impl<'d, T: Instance> Ucpd<'d, T> {
    /// Creates a new UCPD driver instance.
    pub fn new(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        cc1: impl Peripheral<P = impl Cc1Pin<T>> + 'd,
+        cc1: Peri<'d, impl Cc1Pin<T>>,
-        cc2: impl Peripheral<P = impl Cc2Pin<T>> + 'd,
+        cc2: Peri<'d, impl Cc2Pin<T>>,
+        config: Config,
    ) -> Self {
-        into_ref!(cc1, cc2);
        cc1.set_as_analog();
        cc2.set_as_analog();
@@ -108,6 +136,13 @@ impl<'d, T: Instance> Ucpd<'d, T> {
        unsafe { T::Interrupt::enable() };
        let r = T::REGS;
+        #[cfg(stm32h5)]
+        r.cfgr2().write(|w| {
+            // Only takes effect, when UCPDEN=0.
+            w.set_rxafilten(true);
+        });
        r.cfgr1().write(|w| {
            // "The receiver is designed to work in the clock frequency range from 6 to 18 MHz.
            // However, the optimum performance is ensured in the range from 6 to 12 MHz"
@@ -129,9 +164,15 @@ impl<'d, T: Instance> Ucpd<'d, T> {
            // 1.75us * 17 = ~30us
            w.set_ifrgap(17 - 1);
-            // TODO: Currently only hard reset and SOP messages can be received.
            // UNDOCUMENTED: This register can only be written while UCPDEN=0 (found by testing).
-            w.set_rxordseten(0b1001);
+            let rxordset = (config.sop as u16) << 0
+                | (config.sop_prime as u16) << 1
+                | (config.sop_double_prime as u16) << 2
+                // Hard reset
+                | 0x1 << 3
+                | (config.sop_prime_debug as u16) << 4
+                | (config.sop_double_prime_debug as u16) << 5;
+            w.set_rxordseten(rxordset);
            // Enable DMA
            w.set_txdmaen(true);
@@ -140,6 +181,18 @@ impl<'d, T: Instance> Ucpd<'d, T> {
            w.set_ucpden(true);
        });
+        // Software trim according to RM0481, p. 2650/2668
+        #[cfg(stm32h5)]
+        {
+            let trim_rd_cc1 = unsafe { *(0x4002_242C as *const u32) & 0xF };
+            let trim_rd_cc2 = unsafe { ((*(0x4002_242C as *const u32)) >> 8) & 0xF };
+            r.cfgr3().write(|w| {
+                w.set_trim_cc1_rd(trim_rd_cc1 as u8);
+                w.set_trim_cc2_rd(trim_rd_cc2 as u8);
+            });
+        }
        Self {
            cc_phy: CcPhy { _lifetime: PhantomData },
        }
@@ -154,8 +207,8 @@ impl<'d, T: Instance> Ucpd<'d, T> {
    /// and a Power Delivery (PD) PHY with receiver and transmitter.
    pub fn split_pd_phy(
        self,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
        cc_sel: CcSel,
    ) -> (CcPhy<'d, T>, PdPhy<'d, T>) {
        let r = T::REGS;
@@ -175,7 +228,6 @@ impl<'d, T: Instance> Ucpd<'d, T> {
        // Both parts must be dropped before the peripheral can be disabled.
        T::state().drop_not_ready.store(true, Ordering::Relaxed);
-        into_ref!(rx_dma, tx_dma);
        let rx_dma_req = rx_dma.request();
        let tx_dma_req = tx_dma.request();
        (
@@ -183,11 +235,11 @@ impl<'d, T: Instance> Ucpd<'d, T> {
            PdPhy {
                _lifetime: PhantomData,
                rx_dma: ChannelAndRequest {
-                    channel: rx_dma.map_into(),
+                    channel: rx_dma.into(),
                    request: rx_dma_req,
                },
                tx_dma: ChannelAndRequest {
-                    channel: tx_dma.map_into(),
+                    channel: tx_dma.into(),
                    request: tx_dma_req,
                },
            },
@@ -212,7 +264,7 @@ impl<'d, T: Instance> Drop for CcPhy<'d, T> {
        // Check if the PdPhy part was dropped already.
        let drop_not_ready = &T::state().drop_not_ready;
        if drop_not_ready.load(Ordering::Relaxed) {
-            drop_not_ready.store(true, Ordering::Relaxed);
+            drop_not_ready.store(false, Ordering::Relaxed);
        } else {
            r.cfgr1().write(|w| w.set_ucpden(false));
            rcc::disable::<T>();
@@ -243,6 +295,25 @@ impl<'d, T: Instance> CcPhy<'d, T> {
            });
        });
+        // Software trim according to RM0481, p. 2650/2668
+        #[cfg(stm32h5)]
+        T::REGS.cfgr3().modify(|w| match cc_pull {
+            CcPull::Source1_5A => {
+                let trim_1a5_cc1 = unsafe { *(0x08FF_F844 as *const u32) & 0xF };
+                let trim_1a5_cc2 = unsafe { ((*(0x08FF_F844 as *const u32)) >> 16) & 0xF };
+                w.set_trim_cc1_rp(trim_1a5_cc1 as u8);
+                w.set_trim_cc2_rp(trim_1a5_cc2 as u8);
+            }
+            _ => {
+                let trim_3a0_cc1 = unsafe { (*(0x4002_242C as *const u32) >> 4) & 0xF };
+                let trim_3a0_cc2 = unsafe { ((*(0x4002_242C as *const u32)) >> 12) & 0xF };
+                w.set_trim_cc1_rp(trim_3a0_cc1 as u8);
+                w.set_trim_cc2_rp(trim_3a0_cc2 as u8);
+            }
+        });
        // Disable dead-battery pull-down resistors which are enabled by default on boot.
        critical_section::with(|cs| {
            init(
@@ -288,6 +359,22 @@ impl<'d, T: Instance> CcPhy<'d, T> {
    }
 }
+/// Receive SOP.
+#[derive(Debug, Clone, Copy)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Sop {
+    /// SOP
+    Sop,
+    /// SOP'
+    SopPrime,
+    /// SOP''
+    SopDoublePrime,
+    /// SOP'_Debug
+    SopPrimeDebug,
+    /// SOP''_Debug
+    SopDoublePrimeDebug,
+}
 /// Receive Error.
 #[derive(Debug, Clone, Copy)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -322,13 +409,14 @@ pub struct PdPhy<'d, T: Instance> {
 impl<'d, T: Instance> Drop for PdPhy<'d, T> {
    fn drop(&mut self) {
-        T::REGS.cr().modify(|w| w.set_phyrxen(false));
+        let r = T::REGS;
-        // Check if the Type-C part was dropped already.
+        r.cr().modify(|w| w.set_phyrxen(false));
+        // Check if the CcPhy part was dropped already.
        let drop_not_ready = &T::state().drop_not_ready;
        if drop_not_ready.load(Ordering::Relaxed) {
-            drop_not_ready.store(true, Ordering::Relaxed);
+            drop_not_ready.store(false, Ordering::Relaxed);
        } else {
-            T::REGS.cfgr1().write(|w| w.set_ucpden(false));
+            r.cfgr1().write(|w| w.set_ucpden(false));
            rcc::disable::<T>();
            T::Interrupt::disable();
        }
@@ -340,9 +428,16 @@ impl<'d, T: Instance> PdPhy<'d, T> {
    ///
    /// Returns the number of received bytes or an error.
    pub async fn receive(&mut self, buf: &mut [u8]) -> Result<usize, RxError> {
+        self.receive_with_sop(buf).await.map(|(_sop, size)| size)
+    }
+    /// Receives SOP and a PD message into the provided buffer.
+    ///
+    /// Returns the start of packet type and number of received bytes or an error.
+    pub async fn receive_with_sop(&mut self, buf: &mut [u8]) -> Result<(Sop, usize), RxError> {
        let r = T::REGS;
-        let dma = unsafe {
+        let mut dma = unsafe {
            self.rx_dma
                .read(r.rxdr().as_ptr() as *mut u8, buf, TransferOptions::default())
        };
@@ -357,14 +452,24 @@ impl<'d, T: Instance> PdPhy<'d, T> {
            });
        });
+        let mut rxpaysz = 0;
+        // Stop DMA reception immediately after receiving a packet, to prevent storing multiple packets in the same buffer.
        poll_fn(|cx| {
            let sr = r.sr().read();
            if sr.rxhrstdet() {
+                dma.request_stop();
                // Clean and re-enable hard reset receive interrupt.
                r.icr().write(|w| w.set_rxhrstdetcf(true));
                r.imr().modify(|w| w.set_rxhrstdetie(true));
                Poll::Ready(Err(RxError::HardReset))
            } else if sr.rxmsgend() {
+                dma.request_stop();
+                // Should be read immediately on interrupt.
+                rxpaysz = r.rx_payszr().read().rxpaysz().into();
                let ret = if sr.rxovr() {
                    Err(RxError::Overrun)
                } else if sr.rxerr() {
@@ -388,7 +493,18 @@ impl<'d, T: Instance> PdPhy<'d, T> {
            }
        }
-        Ok(r.rx_payszr().read().rxpaysz().into())
+        let sop = match r.rx_ordsetr().read().rxordset() {
+            Rxordset::SOP => Sop::Sop,
+            Rxordset::SOP_PRIME => Sop::SopPrime,
+            Rxordset::SOP_DOUBLE_PRIME => Sop::SopDoublePrime,
+            Rxordset::SOP_PRIME_DEBUG => Sop::SopPrimeDebug,
+            Rxordset::SOP_DOUBLE_PRIME_DEBUG => Sop::SopDoublePrimeDebug,
+            Rxordset::CABLE_RESET => return Err(RxError::HardReset),
+            // Extension headers are not supported
+            _ => unreachable!(),
+        };
+        Ok((sop, rxpaysz))
    }
    fn enable_rx_interrupt(enable: bool) {
@@ -571,7 +687,7 @@ trait SealedInstance {
 /// UCPD instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {
    /// Interrupt for this instance.
    type Interrupt: crate::interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/usart/buffered.rs b/embassy-stm32/src/usart/buffered.rs
index 06cc0e41d..73ab46404 100644
--- a/embassy-stm32/src/usart/buffered.rs
+++ b/embassy-stm32/src/usart/buffered.rs
@@ -6,16 +6,17 @@ use core::task::Poll;
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
-use embassy_hal_internal::{Peripheral, PeripheralRef};
+use embassy_hal_internal::Peri;
 use embassy_sync::waitqueue::AtomicWaker;
 #[cfg(not(any(usart_v1, usart_v2)))]
 use super::DePin;
 use super::{
-    clear_interrupt_flags, configure, rdr, reconfigure, sr, tdr, Config, ConfigError, CtsPin, Error, Info, Instance,
+    clear_interrupt_flags, configure, half_duplex_set_rx_tx_before_write, rdr, reconfigure, send_break, set_baudrate,
-    Regs, RtsPin, RxPin, TxPin,
+    sr, tdr, Config, ConfigError, CtsPin, Duplex, Error, HalfDuplexReadback, Info, Instance, Regs, RtsPin, RxPin,
+    TxPin,
 };
-use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
+use crate::gpio::{AfType, AnyPin, Pull, SealedPin as _};
 use crate::interrupt::{self, InterruptExt};
 use crate::time::Hertz;
@@ -108,6 +109,8 @@ unsafe fn on_interrupt(r: Regs, state: &'static State) {
                });
            }
+            half_duplex_set_rx_tx_before_write(&r, state.half_duplex_readback.load(Ordering::Relaxed));
            tdr(r).write_volatile(buf[0].into());
            tx_reader.pop_done(1);
        } else {
@@ -126,6 +129,7 @@ pub(super) struct State {
    tx_buf: RingBuffer,
    tx_done: AtomicBool,
    tx_rx_refcount: AtomicU8,
+    half_duplex_readback: AtomicBool,
 }
 impl State {
@@ -137,6 +141,7 @@ impl State {
            tx_waker: AtomicWaker::new(),
            tx_done: AtomicBool::new(true),
            tx_rx_refcount: AtomicU8::new(0),
+            half_duplex_readback: AtomicBool::new(false),
        }
    }
 }
@@ -154,9 +159,10 @@ pub struct BufferedUartTx<'d> {
    info: &'static Info,
    state: &'static State,
    kernel_clock: Hertz,
-    tx: Option<PeripheralRef<'d, AnyPin>>,
+    tx: Option<Peri<'d, AnyPin>>,
-    cts: Option<PeripheralRef<'d, AnyPin>>,
+    cts: Option<Peri<'d, AnyPin>>,
-    de: Option<PeripheralRef<'d, AnyPin>>,
+    de: Option<Peri<'d, AnyPin>>,
+    is_borrowed: bool,
 }
 /// Rx-only buffered UART
@@ -166,8 +172,9 @@ pub struct BufferedUartRx<'d> {
    info: &'static Info,
    state: &'static State,
    kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
+    is_borrowed: bool,
 }
 impl<'d> SetConfig for BufferedUart<'d> {
@@ -200,18 +207,18 @@ impl<'d> SetConfig for BufferedUartTx<'d> {
 impl<'d> BufferedUart<'d> {
    /// Create a new bidirectional buffered UART driver
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
        tx_buffer: &'d mut [u8],
        rx_buffer: &'d mut [u8],
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
+            new_pin!(rx, config.rx_af()),
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
            None,
            None,
            None,
@@ -223,23 +230,71 @@ impl<'d> BufferedUart<'d> {
    /// Create a new bidirectional buffered UART driver with request-to-send and clear-to-send pins
    pub fn new_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        cts: Peri<'d, impl CtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            peri,
+            new_pin!(rx, config.rx_af()),
+            new_pin!(tx, config.tx_af()),
+            new_pin!(rts, config.rts_config.af_type()),
+            new_pin!(cts, AfType::input(config.cts_pull)),
+            None,
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+    /// Create a new bidirectional buffered UART driver with only the RTS pin as the DE pin
+    pub fn new_with_rts_as_de<T: Instance>(
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
        tx_buffer: &'d mut [u8],
        rx_buffer: &'d mut [u8],
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
+            new_pin!(rx, config.rx_af()),
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
-            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
-            new_pin!(cts, AfType::input(Pull::None)),
            None,
+            None,
+            new_pin!(rts, AfType::input(Pull::None)), // RTS mapped used as DE
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+    /// Create a new bidirectional buffered UART driver with only the request-to-send pin
+    pub fn new_with_rts<T: Instance>(
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        rts: Peri<'d, impl RtsPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Result<Self, ConfigError> {
+        Self::new_inner(
+            peri,
+            new_pin!(rx, config.rx_af()),
+            new_pin!(tx, config.tx_af()),
+            new_pin!(rts, AfType::input(Pull::None)),
+            None, // no CTS
+            None, // no DE
            tx_buffer,
            rx_buffer,
            config,
@@ -249,22 +304,98 @@ impl<'d> BufferedUart<'d> {
    /// Create a new bidirectional buffered UART driver with a driver-enable pin
    #[cfg(not(any(usart_v1, usart_v2)))]
    pub fn new_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        tx: Peri<'d, impl TxPin<T>>,
+        de: Peri<'d, impl DePin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
        tx_buffer: &'d mut [u8],
        rx_buffer: &'d mut [u8],
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
+            new_pin!(rx, config.rx_af()),
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
+            None,
+            None,
+            new_pin!(de, config.de_config.af_type()),
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+    /// Create a single-wire half-duplex Uart transceiver on a single Tx pin.
+    ///
+    /// See [`new_half_duplex_on_rx`][`Self::new_half_duplex_on_rx`] if you would prefer to use an Rx pin
+    /// (when it is available for your chip). There is no functional difference between these methods, as both
+    /// allow bidirectional communication.
+    ///
+    /// The TX pin is always released when no data is transmitted. Thus, it acts as a standard
+    /// I/O in idle or in reception. It means that the I/O must be configured so that TX is
+    /// configured as alternate function open-drain with an external pull-up
+    /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
+    /// on the line must be managed by software (for instance by using a centralized arbiter).
+    #[doc(alias("HDSEL"))]
+    pub fn new_half_duplex<T: Instance>(
+        peri: Peri<'d, T>,
+        tx: Peri<'d, impl TxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        mut config: Config,
+        readback: HalfDuplexReadback,
+    ) -> Result<Self, ConfigError> {
+        #[cfg(not(any(usart_v1, usart_v2)))]
+        {
+            config.swap_rx_tx = false;
+        }
+        config.duplex = Duplex::Half(readback);
+        Self::new_inner(
+            peri,
+            None,
+            new_pin!(tx, config.tx_af()),
+            None,
+            None,
+            None,
+            tx_buffer,
+            rx_buffer,
+            config,
+        )
+    }
+    /// Create a single-wire half-duplex Uart transceiver on a single Rx pin.
+    ///
+    /// See [`new_half_duplex`][`Self::new_half_duplex`] if you would prefer to use an Tx pin.
+    /// There is no functional difference between these methods, as both allow bidirectional communication.
+    ///
+    /// The pin is always released when no data is transmitted. Thus, it acts as a standard
+    /// I/O in idle or in reception.
+    /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
+    /// on the line must be managed by software (for instance by using a centralized arbiter).
+    #[cfg(not(any(usart_v1, usart_v2)))]
+    #[doc(alias("HDSEL"))]
+    pub fn new_half_duplex_on_rx<T: Instance>(
+        peri: Peri<'d, T>,
+        rx: Peri<'d, impl RxPin<T>>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        tx_buffer: &'d mut [u8],
+        rx_buffer: &'d mut [u8],
+        mut config: Config,
+        readback: HalfDuplexReadback,
+    ) -> Result<Self, ConfigError> {
+        config.swap_rx_tx = true;
+        config.duplex = Duplex::Half(readback);
+        Self::new_inner(
+            peri,
+            new_pin!(rx, config.rx_af()),
+            None,
+            None,
            None,
            None,
-            new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)),
            tx_buffer,
            rx_buffer,
            config,
@@ -272,12 +403,12 @@ impl<'d> BufferedUart<'d> {
    }
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
+        rx: Option<Peri<'d, AnyPin>>,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
-        de: Option<PeripheralRef<'d, AnyPin>>,
+        de: Option<Peri<'d, AnyPin>>,
        tx_buffer: &'d mut [u8],
        rx_buffer: &'d mut [u8],
        config: Config,
@@ -286,6 +417,11 @@ impl<'d> BufferedUart<'d> {
        let state = T::buffered_state();
        let kernel_clock = T::frequency();
+        state.half_duplex_readback.store(
+            config.duplex == Duplex::Half(HalfDuplexReadback::Readback),
+            Ordering::Relaxed,
+        );
        let mut this = Self {
            rx: BufferedUartRx {
                info,
@@ -293,6 +429,7 @@ impl<'d> BufferedUart<'d> {
                kernel_clock,
                rx,
                rts,
+                is_borrowed: false,
            },
            tx: BufferedUartTx {
                info,
@@ -301,6 +438,7 @@ impl<'d> BufferedUart<'d> {
                tx,
                cts,
                de,
+                is_borrowed: false,
            },
        };
        this.enable_and_configure(tx_buffer, rx_buffer, &config)?;
@@ -319,8 +457,10 @@ impl<'d> BufferedUart<'d> {
        info.rcc.enable_and_reset();
+        assert!(!tx_buffer.is_empty());
        let len = tx_buffer.len();
        unsafe { state.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
+        assert!(!rx_buffer.is_empty());
        let len = rx_buffer.len();
        unsafe { state.rx_buf.init(rx_buffer.as_mut_ptr(), len) };
@@ -329,12 +469,20 @@ impl<'d> BufferedUart<'d> {
            w.set_ctse(self.tx.cts.is_some());
            #[cfg(not(any(usart_v1, usart_v2)))]
            w.set_dem(self.tx.de.is_some());
+            w.set_hdsel(config.duplex.is_half());
        });
        configure(info, self.rx.kernel_clock, &config, true, true)?;
        info.regs.cr1().modify(|w| {
            w.set_rxneie(true);
            w.set_idleie(true);
+            if config.duplex.is_half() {
+                // The te and re bits will be set by write, read and flush methods.
+                // Receiver should be enabled by default for Half-Duplex.
+                w.set_te(false);
+                w.set_re(true);
+            }
        });
        info.interrupt.unpend();
@@ -348,6 +496,31 @@ impl<'d> BufferedUart<'d> {
        (self.tx, self.rx)
    }
+    /// Split the Uart into a transmitter and receiver,
+    /// which is particularly useful when having two tasks correlating to
+    /// transmitting and receiving.
+    pub fn split_ref(&mut self) -> (BufferedUartTx<'_>, BufferedUartRx<'_>) {
+        (
+            BufferedUartTx {
+                info: self.tx.info,
+                state: self.tx.state,
+                kernel_clock: self.tx.kernel_clock,
+                tx: self.tx.tx.as_mut().map(Peri::reborrow),
+                cts: self.tx.cts.as_mut().map(Peri::reborrow),
+                de: self.tx.de.as_mut().map(Peri::reborrow),
+                is_borrowed: true,
+            },
+            BufferedUartRx {
+                info: self.rx.info,
+                state: self.rx.state,
+                kernel_clock: self.rx.kernel_clock,
+                rx: self.rx.rx.as_mut().map(Peri::reborrow),
+                rts: self.rx.rts.as_mut().map(Peri::reborrow),
+                is_borrowed: true,
+            },
+        )
+    }
    /// Reconfigure the driver
    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
        reconfigure(self.rx.info, self.rx.kernel_clock, config)?;
@@ -359,6 +532,18 @@ impl<'d> BufferedUart<'d> {
        Ok(())
    }
+    /// Send break character
+    pub fn send_break(&self) {
+        self.tx.send_break()
+    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        self.tx.set_baudrate(baudrate)?;
+        self.rx.set_baudrate(baudrate)?;
+        Ok(())
+    }
 }
 impl<'d> BufferedUartRx<'d> {
@@ -453,6 +638,11 @@ impl<'d> BufferedUartRx<'d> {
        Ok(())
    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        set_baudrate(self.info, self.kernel_clock, baudrate)
+    }
 }
 impl<'d> BufferedUartTx<'d> {
@@ -538,44 +728,58 @@ impl<'d> BufferedUartTx<'d> {
        Ok(())
    }
+    /// Send break character
+    pub fn send_break(&self) {
+        send_break(&self.info.regs);
+    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        set_baudrate(self.info, self.kernel_clock, baudrate)
+    }
 }
 impl<'d> Drop for BufferedUartRx<'d> {
    fn drop(&mut self) {
-        let state = self.state;
+        if !self.is_borrowed {
-        unsafe {
+            let state = self.state;
-            state.rx_buf.deinit();
+            unsafe {
+                state.rx_buf.deinit();
-            // TX is inactive if the the buffer is not available.
+                // TX is inactive if the buffer is not available.
-            // We can now unregister the interrupt handler
+                // We can now unregister the interrupt handler
-            if state.tx_buf.len() == 0 {
+                if state.tx_buf.len() == 0 {
-                self.info.interrupt.disable();
+                    self.info.interrupt.disable();
+                }
            }
-        }
-        self.rx.as_ref().map(|x| x.set_as_disconnected());
+            self.rx.as_ref().map(|x| x.set_as_disconnected());
-        self.rts.as_ref().map(|x| x.set_as_disconnected());
+            self.rts.as_ref().map(|x| x.set_as_disconnected());
-        drop_tx_rx(self.info, state);
+            drop_tx_rx(self.info, state);
+        }
    }
 }
 impl<'d> Drop for BufferedUartTx<'d> {
    fn drop(&mut self) {
-        let state = self.state;
+        if !self.is_borrowed {
-        unsafe {
+            let state = self.state;
-            state.tx_buf.deinit();
+            unsafe {
+                state.tx_buf.deinit();
-            // RX is inactive if the the buffer is not available.
+                // RX is inactive if the buffer is not available.
-            // We can now unregister the interrupt handler
+                // We can now unregister the interrupt handler
-            if state.rx_buf.len() == 0 {
+                if state.rx_buf.len() == 0 {
-                self.info.interrupt.disable();
+                    self.info.interrupt.disable();
+                }
            }
-        }
-        self.tx.as_ref().map(|x| x.set_as_disconnected());
+            self.tx.as_ref().map(|x| x.set_as_disconnected());
-        self.cts.as_ref().map(|x| x.set_as_disconnected());
+            self.cts.as_ref().map(|x| x.set_as_disconnected());
-        self.de.as_ref().map(|x| x.set_as_disconnected());
+            self.de.as_ref().map(|x| x.set_as_disconnected());
-        drop_tx_rx(self.info, state);
+            drop_tx_rx(self.info, state);
+        }
    }
 }
@@ -704,26 +908,17 @@ impl<'d> embedded_hal_02::serial::Read<u8> for BufferedUartRx<'d> {
    type Error = Error;
    fn read(&mut self) -> Result<u8, nb::Error<Self::Error>> {
-        let r = self.info.regs;
+        let state = self.state;
-        unsafe {
+        let mut rx_reader = unsafe { state.rx_buf.reader() };
-            let sr = sr(r).read();
-            if sr.pe() {
+        let do_pend = state.rx_buf.is_full();
-                rdr(r).read_volatile();
+        if let Some(data) = rx_reader.pop_one() {
-                Err(nb::Error::Other(Error::Parity))
+            if do_pend {
-            } else if sr.fe() {
+                self.info.interrupt.pend();
-                rdr(r).read_volatile();
-                Err(nb::Error::Other(Error::Framing))
-            } else if sr.ne() {
-                rdr(r).read_volatile();
-                Err(nb::Error::Other(Error::Noise))
-            } else if sr.ore() {
-                rdr(r).read_volatile();
-                Err(nb::Error::Other(Error::Overrun))
-            } else if sr.rxne() {
-                Ok(rdr(r).read_volatile())
-            } else {
-                Err(nb::Error::WouldBlock)
            }
+            Ok(data)
+        } else {
+            Err(nb::Error::WouldBlock)
        }
    }
 }
diff --git a/embassy-stm32/src/usart/mod.rs b/embassy-stm32/src/usart/mod.rs
index 7ed3793a1..b3f8bc00c 100644
--- a/embassy-stm32/src/usart/mod.rs
+++ b/embassy-stm32/src/usart/mod.rs
@@ -9,7 +9,7 @@ use core::task::Poll;
 use embassy_embedded_hal::SetConfig;
 use embassy_hal_internal::drop::OnDrop;
-use embassy_hal_internal::PeripheralRef;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use futures_util::future::{select, Either};
@@ -18,11 +18,6 @@ use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
 use crate::interrupt::typelevel::Interrupt as _;
 use crate::interrupt::{self, Interrupt, InterruptExt};
 use crate::mode::{Async, Blocking, Mode};
-#[allow(unused_imports)]
-#[cfg(not(any(usart_v1, usart_v2)))]
-use crate::pac::usart::regs::Isr as Sr;
-#[cfg(any(usart_v1, usart_v2))]
-use crate::pac::usart::regs::Sr;
 #[cfg(not(any(usart_v1, usart_v2)))]
 use crate::pac::usart::Lpuart as Regs;
 #[cfg(any(usart_v1, usart_v2))]
@@ -30,7 +25,7 @@ use crate::pac::usart::Usart as Regs;
 use crate::pac::usart::{regs, vals};
 use crate::rcc::{RccInfo, SealedRccPeripheral};
 use crate::time::Hertz;
-use crate::Peripheral;
+use crate::Peri;
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -69,6 +64,12 @@ unsafe fn on_interrupt(r: Regs, s: &'static State) {
            // disable idle line detection
            w.set_idleie(false);
        });
+    } else if cr1.tcie() && sr.tc() {
+        // Transmission complete detected
+        r.cr1().modify(|w| {
+            // disable Transmission complete interrupt
+            w.set_tcie(false);
+        });
    } else if cr1.rxneie() {
        // We cannot check the RXNE flag as it is auto-cleared by the DMA controller
@@ -79,12 +80,15 @@ unsafe fn on_interrupt(r: Regs, s: &'static State) {
    compiler_fence(Ordering::SeqCst);
    s.rx_waker.wake();
+    s.tx_waker.wake();
 }
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 /// Number of data bits
 pub enum DataBits {
+    /// 7 Data Bits
+    DataBits7,
    /// 8 Data Bits
    DataBits8,
    /// 9 Data Bits
@@ -117,6 +121,57 @@ pub enum StopBits {
    STOP1P5,
 }
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Enables or disables receiver so written data are read back in half-duplex mode
+pub enum HalfDuplexReadback {
+    /// Disables receiver so written data are not read back
+    NoReadback,
+    /// Enables receiver so written data are read back
+    Readback,
+}
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Half duplex IO mode
+pub enum OutputConfig {
+    /// Push pull allows for faster baudrates, no internal pullup
+    PushPull,
+    /// Open drain output (external pull up needed)
+    OpenDrain,
+    #[cfg(not(gpio_v1))]
+    /// Open drain output with internal pull up resistor
+    OpenDrainPullUp,
+}
+impl OutputConfig {
+    const fn af_type(self) -> AfType {
+        match self {
+            OutputConfig::PushPull => AfType::output(OutputType::PushPull, Speed::Medium),
+            OutputConfig::OpenDrain => AfType::output(OutputType::OpenDrain, Speed::Medium),
+            #[cfg(not(gpio_v1))]
+            OutputConfig::OpenDrainPullUp => AfType::output_pull(OutputType::OpenDrain, Speed::Medium, Pull::Up),
+        }
+    }
+}
+#[derive(Clone, Copy, PartialEq, Eq, Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+/// Duplex mode
+pub enum Duplex {
+    /// Full duplex
+    Full,
+    /// Half duplex with possibility to read back written data
+    Half(HalfDuplexReadback),
+}
+impl Duplex {
+    /// Returns true if half-duplex
+    fn is_half(&self) -> bool {
+        matches!(self, Duplex::Half(_))
+    }
+}
 #[non_exhaustive]
 #[derive(Clone, Copy, PartialEq, Eq, Debug)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
@@ -128,6 +183,8 @@ pub enum ConfigError {
    BaudrateTooHigh,
    /// Rx or Tx not enabled
    RxOrTxNotEnabled,
+    /// Data bits and parity combination not supported
+    DataParityNotSupported,
 }
 #[non_exhaustive]
@@ -167,25 +224,40 @@ pub struct Config {
    #[cfg(any(usart_v3, usart_v4))]
    pub invert_rx: bool,
+    /// Set the pull configuration for the RX pin.
+    pub rx_pull: Pull,
+    /// Set the pull configuration for the CTS pin.
+    pub cts_pull: Pull,
+    /// Set the pin configuration for the TX pin.
+    pub tx_config: OutputConfig,
+    /// Set the pin configuration for the RTS pin.
+    pub rts_config: OutputConfig,
+    /// Set the pin configuration for the DE pin.
+    pub de_config: OutputConfig,
    // private: set by new_half_duplex, not by the user.
-    half_duplex: bool,
+    duplex: Duplex,
 }
 impl Config {
    fn tx_af(&self) -> AfType {
        #[cfg(any(usart_v3, usart_v4))]
        if self.swap_rx_tx {
-            return AfType::input(Pull::None);
+            return AfType::input(self.rx_pull);
        };
-        AfType::output(OutputType::PushPull, Speed::Medium)
+        self.tx_config.af_type()
    }
    fn rx_af(&self) -> AfType {
        #[cfg(any(usart_v3, usart_v4))]
        if self.swap_rx_tx {
-            return AfType::output(OutputType::PushPull, Speed::Medium);
+            return self.tx_config.af_type();
        };
-        AfType::input(Pull::None)
+        AfType::input(self.rx_pull)
    }
 }
@@ -206,7 +278,12 @@ impl Default for Config {
            invert_tx: false,
            #[cfg(any(usart_v3, usart_v4))]
            invert_rx: false,
-            half_duplex: false,
+            rx_pull: Pull::None,
+            cts_pull: Pull::None,
+            tx_config: OutputConfig::PushPull,
+            rts_config: OutputConfig::PushPull,
+            de_config: OutputConfig::PushPull,
+            duplex: Duplex::Full,
        }
    }
 }
@@ -228,6 +305,22 @@ pub enum Error {
    BufferTooLong,
 }
+impl core::fmt::Display for Error {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        let message = match self {
+            Self::Framing => "Framing Error",
+            Self::Noise => "Noise Error",
+            Self::Overrun => "RX Buffer Overrun",
+            Self::Parity => "Parity Check Error",
+            Self::BufferTooLong => "Buffer too large for DMA",
+        };
+        write!(f, "{}", message)
+    }
+}
+impl core::error::Error for Error {}
 enum ReadCompletionEvent {
    // DMA Read transfer completed first
    DmaCompleted,
@@ -266,10 +359,11 @@ pub struct UartTx<'d, M: Mode> {
    info: &'static Info,
    state: &'static State,
    kernel_clock: Hertz,
-    tx: Option<PeripheralRef<'d, AnyPin>>,
+    tx: Option<Peri<'d, AnyPin>>,
-    cts: Option<PeripheralRef<'d, AnyPin>>,
+    cts: Option<Peri<'d, AnyPin>>,
-    de: Option<PeripheralRef<'d, AnyPin>>,
+    de: Option<Peri<'d, AnyPin>>,
    tx_dma: Option<ChannelAndRequest<'d>>,
+    duplex: Duplex,
    _phantom: PhantomData<M>,
 }
@@ -315,12 +409,12 @@ pub struct UartRx<'d, M: Mode> {
    info: &'static Info,
    state: &'static State,
    kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
    rx_dma: Option<ChannelAndRequest<'d>>,
    detect_previous_overrun: bool,
    #[cfg(any(usart_v1, usart_v2))]
-    buffered_sr: stm32_metapac::usart::regs::Sr,
+    buffered_sr: regs::Sr,
    _phantom: PhantomData<M>,
 }
@@ -336,32 +430,26 @@ impl<'d, M: Mode> SetConfig for UartRx<'d, M> {
 impl<'d> UartTx<'d, Async> {
    /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
-        Self::new_inner(
+        Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, new_dma!(tx_dma), config)
-            peri,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
-            None,
-            new_dma!(tx_dma),
-            config,
-        )
    }
    /// Create a new tx-only UART with a clear-to-send pin
    pub fn new_with_cts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        cts: Peri<'d, impl CtsPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
-            new_pin!(cts, AfType::input(Pull::None)),
+            new_pin!(cts, AfType::input(config.cts_pull)),
            new_dma!(tx_dma),
            config,
        )
@@ -371,13 +459,7 @@ impl<'d> UartTx<'d, Async> {
    pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
        let r = self.info.regs;
-        // Enable Transmitter and disable Receiver for Half-Duplex mode
+        half_duplex_set_rx_tx_before_write(&r, self.duplex == Duplex::Half(HalfDuplexReadback::Readback));
-        let mut cr1 = r.cr1().read();
-        if r.cr3().read().hdsel() && !cr1.te() {
-            cr1.set_te(true);
-            cr1.set_re(false);
-            r.cr1().write_value(cr1);
-        }
        let ch = self.tx_dma.as_mut().unwrap();
        r.cr3().modify(|reg| {
@@ -392,7 +474,7 @@ impl<'d> UartTx<'d, Async> {
    /// Wait until transmission complete
    pub async fn flush(&mut self) -> Result<(), Error> {
-        self.blocking_flush()
+        flush(&self.info, &self.state).await
    }
 }
@@ -401,30 +483,24 @@ impl<'d> UartTx<'d, Blocking> {
    ///
    /// Useful if you only want Uart Tx. It saves 1 pin and consumes a little less power.
    pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
-        Self::new_inner(
+        Self::new_inner(peri, new_pin!(tx, config.tx_af()), None, None, config)
-            peri,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
-            None,
-            None,
-            config,
-        )
    }
    /// Create a new blocking tx-only UART with a clear-to-send pin
    pub fn new_blocking_with_cts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        cts: Peri<'d, impl CtsPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
-            new_pin!(cts, AfType::input(Pull::None)),
+            new_pin!(cts, AfType::input(config.cts_pull)),
            None,
            config,
        )
@@ -433,9 +509,9 @@ impl<'d> UartTx<'d, Blocking> {
 impl<'d, M: Mode> UartTx<'d, M> {
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
        tx_dma: Option<ChannelAndRequest<'d>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
@@ -447,6 +523,7 @@ impl<'d, M: Mode> UartTx<'d, M> {
            cts,
            de: None,
            tx_dma,
+            duplex: config.duplex,
            _phantom: PhantomData,
        };
        this.enable_and_configure(&config)?;
@@ -477,13 +554,7 @@ impl<'d, M: Mode> UartTx<'d, M> {
    pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
        let r = self.info.regs;
-        // Enable Transmitter and disable Receiver for Half-Duplex mode
+        half_duplex_set_rx_tx_before_write(&r, self.duplex == Duplex::Half(HalfDuplexReadback::Readback));
-        let mut cr1 = r.cr1().read();
-        if r.cr3().read().hdsel() && !cr1.te() {
-            cr1.set_te(true);
-            cr1.set_re(false);
-            r.cr1().write_value(cr1);
-        }
        for &b in buffer {
            while !sr(r).read().txe() {}
@@ -496,53 +567,110 @@ impl<'d, M: Mode> UartTx<'d, M> {
    pub fn blocking_flush(&mut self) -> Result<(), Error> {
        blocking_flush(self.info)
    }
+    /// Send break character
+    pub fn send_break(&self) {
+        send_break(&self.info.regs);
+    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        set_baudrate(self.info, self.kernel_clock, baudrate)
+    }
 }
-fn blocking_flush(info: &Info) -> Result<(), Error> {
+/// Wait until transmission complete
+async fn flush(info: &Info, state: &State) -> Result<(), Error> {
    let r = info.regs;
-    while !sr(r).read().tc() {}
+    if r.cr1().read().te() && !sr(r).read().tc() {
+        r.cr1().modify(|w| {
+            // enable Transmission Complete interrupt
+            w.set_tcie(true);
+        });
+        compiler_fence(Ordering::SeqCst);
+        // future which completes when Transmission complete is detected
+        let abort = poll_fn(move |cx| {
+            state.tx_waker.register(cx.waker());
-    // Enable Receiver after transmission complete for Half-Duplex mode
+            let sr = sr(r).read();
-    if r.cr3().read().hdsel() {
+            if sr.tc() {
-        r.cr1().modify(|reg| reg.set_re(true));
+                // Transmission complete detected
+                return Poll::Ready(());
+            }
+            Poll::Pending
+        });
+        abort.await;
    }
    Ok(())
 }
+fn blocking_flush(info: &Info) -> Result<(), Error> {
+    let r = info.regs;
+    if r.cr1().read().te() {
+        while !sr(r).read().tc() {}
+    }
+    Ok(())
+}
+/// Send break character
+pub fn send_break(regs: &Regs) {
+    // Busy wait until previous break has been sent
+    #[cfg(any(usart_v1, usart_v2))]
+    while regs.cr1().read().sbk() {}
+    #[cfg(any(usart_v3, usart_v4))]
+    while regs.isr().read().sbkf() {}
+    // Send break right after completing the current character transmission
+    #[cfg(any(usart_v1, usart_v2))]
+    regs.cr1().modify(|w| w.set_sbk(true));
+    #[cfg(any(usart_v3, usart_v4))]
+    regs.rqr().write(|w| w.set_sbkrq(true));
+}
+/// Enable Transmitter and disable Receiver for Half-Duplex mode
+/// In case of readback, keep Receiver enabled
+fn half_duplex_set_rx_tx_before_write(r: &Regs, enable_readback: bool) {
+    let mut cr1 = r.cr1().read();
+    if r.cr3().read().hdsel() && !cr1.te() {
+        cr1.set_te(true);
+        cr1.set_re(enable_readback);
+        r.cr1().write_value(cr1);
+    }
+}
 impl<'d> UartRx<'d, Async> {
    /// Create a new rx-only UART with no hardware flow control.
    ///
    /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
-        Self::new_inner(
+        Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, new_dma!(rx_dma), config)
-            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
-            None,
-            new_dma!(rx_dma),
-            config,
-        )
    }
    /// Create a new rx-only UART with a request-to-send pin
    pub fn new_with_rts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rts: Peri<'d, impl RtsPin<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
+            new_pin!(rx, config.rx_af()),
-            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rts, config.rts_config.af_type()),
            new_dma!(rx_dma),
            config,
        )
@@ -570,12 +698,17 @@ impl<'d> UartRx<'d, Async> {
        // Call flush for Half-Duplex mode if some bytes were written and flush was not called.
        // It prevents reading of bytes which have just been written.
        if r.cr3().read().hdsel() && r.cr1().read().te() {
-            blocking_flush(self.info)?;
+            flush(&self.info, &self.state).await?;
+            // Disable Transmitter and enable Receiver after flush
+            r.cr1().modify(|reg| {
+                reg.set_re(true);
+                reg.set_te(false);
+            });
        }
        // make sure USART state is restored to neutral state when this future is dropped
        let on_drop = OnDrop::new(move || {
-            // defmt::trace!("Clear all USART interrupts and DMA Read Request");
            // clear all interrupts and DMA Rx Request
            r.cr1().modify(|w| {
                // disable RXNE interrupt
@@ -767,24 +900,24 @@ impl<'d> UartRx<'d, Blocking> {
    ///
    /// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
    pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
-        Self::new_inner(peri, new_pin!(rx, AfType::input(Pull::None)), None, None, config)
+        Self::new_inner(peri, new_pin!(rx, config.rx_af()), None, None, config)
    }
    /// Create a new rx-only UART with a request-to-send pin
    pub fn new_blocking_with_rts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rts: Peri<'d, impl RtsPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
-            new_pin!(rx, AfType::input(Pull::None)),
+            new_pin!(rx, config.rx_af()),
-            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rts, config.rts_config.af_type()),
            None,
            config,
        )
@@ -793,9 +926,9 @@ impl<'d> UartRx<'d, Blocking> {
 impl<'d, M: Mode> UartRx<'d, M> {
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
+        rx: Option<Peri<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
        rx_dma: Option<ChannelAndRequest<'d>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
@@ -809,7 +942,7 @@ impl<'d, M: Mode> UartRx<'d, M> {
            rx_dma,
            detect_previous_overrun: config.detect_previous_overrun,
            #[cfg(any(usart_v1, usart_v2))]
-            buffered_sr: stm32_metapac::usart::regs::Sr(0),
+            buffered_sr: regs::Sr(0),
        };
        this.enable_and_configure(&config)?;
        Ok(this)
@@ -909,6 +1042,12 @@ impl<'d, M: Mode> UartRx<'d, M> {
        // It prevents reading of bytes which have just been written.
        if r.cr3().read().hdsel() && r.cr1().read().te() {
            blocking_flush(self.info)?;
+            // Disable Transmitter and enable Receiver after flush
+            r.cr1().modify(|reg| {
+                reg.set_re(true);
+                reg.set_te(false);
+            });
        }
        for b in buffer {
@@ -917,6 +1056,11 @@ impl<'d, M: Mode> UartRx<'d, M> {
        }
        Ok(())
    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        set_baudrate(self.info, self.kernel_clock, baudrate)
+    }
 }
 impl<'d, M: Mode> Drop for UartTx<'d, M> {
@@ -952,12 +1096,12 @@ fn drop_tx_rx(info: &Info, state: &State) {
 impl<'d> Uart<'d, Async> {
    /// Create a new bidirectional UART
    pub fn new<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
@@ -975,22 +1119,22 @@ impl<'d> Uart<'d, Async> {
    /// Create a new bidirectional UART with request-to-send and clear-to-send pins
    pub fn new_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rts: Peri<'d, impl RtsPin<T>>,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        cts: Peri<'d, impl CtsPin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
            new_pin!(rx, config.rx_af()),
            new_pin!(tx, config.tx_af()),
-            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rts, config.rts_config.af_type()),
-            new_pin!(cts, AfType::input(Pull::None)),
+            new_pin!(cts, AfType::input(config.cts_pull)),
            None,
            new_dma!(tx_dma),
            new_dma!(rx_dma),
@@ -1001,13 +1145,13 @@ impl<'d> Uart<'d, Async> {
    #[cfg(not(any(usart_v1, usart_v2)))]
    /// Create a new bidirectional UART with a driver-enable pin
    pub fn new_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
+        de: Peri<'d, impl DePin<T>>,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
@@ -1016,7 +1160,7 @@ impl<'d> Uart<'d, Async> {
            new_pin!(tx, config.tx_af()),
            None,
            None,
-            new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(de, config.de_config.af_type()),
            new_dma!(tx_dma),
            new_dma!(rx_dma),
            config,
@@ -1029,29 +1173,31 @@ impl<'d> Uart<'d, Async> {
    /// (when it is available for your chip). There is no functional difference between these methods, as both
    /// allow bidirectional communication.
    ///
-    /// The pin is always released when no data is transmitted. Thus, it acts as a standard
+    /// The TX pin is always released when no data is transmitted. Thus, it acts as a standard
-    /// I/O in idle or in reception.
+    /// I/O in idle or in reception. It means that the I/O must be configured so that TX is
+    /// configured as alternate function open-drain with an external pull-up
    /// Apart from this, the communication protocol is similar to normal USART mode. Any conflict
    /// on the line must be managed by software (for instance by using a centralized arbiter).
    #[doc(alias("HDSEL"))]
    pub fn new_half_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        mut config: Config,
+        readback: HalfDuplexReadback,
    ) -> Result<Self, ConfigError> {
        #[cfg(not(any(usart_v1, usart_v2)))]
        {
            config.swap_rx_tx = false;
        }
-        config.half_duplex = true;
+        config.duplex = Duplex::Half(readback);
        Self::new_inner(
            peri,
            None,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
            None,
            None,
            None,
@@ -1073,21 +1219,22 @@ impl<'d> Uart<'d, Async> {
    #[cfg(not(any(usart_v1, usart_v2)))]
    #[doc(alias("HDSEL"))]
    pub fn new_half_duplex_on_rx<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
+        tx_dma: Peri<'d, impl TxDma<T>>,
-        rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
+        rx_dma: Peri<'d, impl RxDma<T>>,
        mut config: Config,
+        readback: HalfDuplexReadback,
    ) -> Result<Self, ConfigError> {
        config.swap_rx_tx = true;
-        config.half_duplex = true;
+        config.duplex = Duplex::Half(readback);
        Self::new_inner(
            peri,
            None,
            None,
-            new_pin!(rx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rx, config.rx_af()),
            None,
            None,
            new_dma!(tx_dma),
@@ -1101,6 +1248,11 @@ impl<'d> Uart<'d, Async> {
        self.tx.write(buffer).await
    }
+    /// Wait until transmission complete
+    pub async fn flush(&mut self) -> Result<(), Error> {
+        self.tx.flush().await
+    }
    /// Perform an asynchronous read into `buffer`
    pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
        self.rx.read(buffer).await
@@ -1115,9 +1267,9 @@ impl<'d> Uart<'d, Async> {
 impl<'d> Uart<'d, Blocking> {
    /// Create a new blocking bidirectional UART.
    pub fn new_blocking<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
@@ -1135,19 +1287,19 @@ impl<'d> Uart<'d, Blocking> {
    /// Create a new bidirectional UART with request-to-send and clear-to-send pins
    pub fn new_blocking_with_rtscts<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
+        rts: Peri<'d, impl RtsPin<T>>,
-        cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
+        cts: Peri<'d, impl CtsPin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
            peri,
            new_pin!(rx, config.rx_af()),
            new_pin!(tx, config.tx_af()),
-            new_pin!(rts, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rts, config.rts_config.af_type()),
-            new_pin!(cts, AfType::input(Pull::None)),
+            new_pin!(cts, AfType::input(config.cts_pull)),
            None,
            None,
            None,
@@ -1158,10 +1310,10 @@ impl<'d> Uart<'d, Blocking> {
    #[cfg(not(any(usart_v1, usart_v2)))]
    /// Create a new bidirectional UART with a driver-enable pin
    pub fn new_blocking_with_de<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
-        de: impl Peripheral<P = impl DePin<T>> + 'd,
+        de: Peri<'d, impl DePin<T>>,
        config: Config,
    ) -> Result<Self, ConfigError> {
        Self::new_inner(
@@ -1170,7 +1322,7 @@ impl<'d> Uart<'d, Blocking> {
            new_pin!(tx, config.tx_af()),
            None,
            None,
-            new_pin!(de, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(de, config.de_config.af_type()),
            None,
            None,
            config,
@@ -1189,20 +1341,21 @@ impl<'d> Uart<'d, Blocking> {
    /// on the line must be managed by software (for instance by using a centralized arbiter).
    #[doc(alias("HDSEL"))]
    pub fn new_blocking_half_duplex<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        tx: impl Peripheral<P = impl TxPin<T>> + 'd,
+        tx: Peri<'d, impl TxPin<T>>,
        mut config: Config,
+        readback: HalfDuplexReadback,
    ) -> Result<Self, ConfigError> {
        #[cfg(not(any(usart_v1, usart_v2)))]
        {
            config.swap_rx_tx = false;
        }
-        config.half_duplex = true;
+        config.duplex = Duplex::Half(readback);
        Self::new_inner(
            peri,
            None,
-            new_pin!(tx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(tx, config.tx_af()),
            None,
            None,
            None,
@@ -1224,18 +1377,19 @@ impl<'d> Uart<'d, Blocking> {
    #[cfg(not(any(usart_v1, usart_v2)))]
    #[doc(alias("HDSEL"))]
    pub fn new_blocking_half_duplex_on_rx<T: Instance>(
-        peri: impl Peripheral<P = T> + 'd,
+        peri: Peri<'d, T>,
-        rx: impl Peripheral<P = impl RxPin<T>> + 'd,
+        rx: Peri<'d, impl RxPin<T>>,
        mut config: Config,
+        readback: HalfDuplexReadback,
    ) -> Result<Self, ConfigError> {
        config.swap_rx_tx = true;
-        config.half_duplex = true;
+        config.duplex = Duplex::Half(readback);
        Self::new_inner(
            peri,
            None,
            None,
-            new_pin!(rx, AfType::output(OutputType::PushPull, Speed::Medium)),
+            new_pin!(rx, config.rx_af()),
            None,
            None,
            None,
@@ -1247,12 +1401,12 @@ impl<'d> Uart<'d, Blocking> {
 impl<'d, M: Mode> Uart<'d, M> {
    fn new_inner<T: Instance>(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
-        rx: Option<PeripheralRef<'d, AnyPin>>,
+        rx: Option<Peri<'d, AnyPin>>,
-        tx: Option<PeripheralRef<'d, AnyPin>>,
+        tx: Option<Peri<'d, AnyPin>>,
-        rts: Option<PeripheralRef<'d, AnyPin>>,
+        rts: Option<Peri<'d, AnyPin>>,
-        cts: Option<PeripheralRef<'d, AnyPin>>,
+        cts: Option<Peri<'d, AnyPin>>,
-        de: Option<PeripheralRef<'d, AnyPin>>,
+        de: Option<Peri<'d, AnyPin>>,
        tx_dma: Option<ChannelAndRequest<'d>>,
        rx_dma: Option<ChannelAndRequest<'d>>,
        config: Config,
@@ -1271,6 +1425,7 @@ impl<'d, M: Mode> Uart<'d, M> {
                cts,
                de,
                tx_dma,
+                duplex: config.duplex,
            },
            rx: UartRx {
                _phantom: PhantomData,
@@ -1282,7 +1437,7 @@ impl<'d, M: Mode> Uart<'d, M> {
                rx_dma,
                detect_previous_overrun: config.detect_previous_overrun,
                #[cfg(any(usart_v1, usart_v2))]
-                buffered_sr: stm32_metapac::usart::regs::Sr(0),
+                buffered_sr: regs::Sr(0),
            },
        };
        this.enable_and_configure(&config)?;
@@ -1336,6 +1491,25 @@ impl<'d, M: Mode> Uart<'d, M> {
    pub fn split(self) -> (UartTx<'d, M>, UartRx<'d, M>) {
        (self.tx, self.rx)
    }
+    /// Split the Uart into a transmitter and receiver by mutable reference,
+    /// which is particularly useful when having two tasks correlating to
+    /// transmitting and receiving.
+    pub fn split_ref(&mut self) -> (&mut UartTx<'d, M>, &mut UartRx<'d, M>) {
+        (&mut self.tx, &mut self.rx)
+    }
+    /// Send break character
+    pub fn send_break(&self) {
+        self.tx.send_break();
+    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        self.tx.set_baudrate(baudrate)?;
+        self.rx.set_baudrate(baudrate)?;
+        Ok(())
+    }
 }
 fn reconfigure(info: &Info, kernel_clock: Hertz, config: &Config) -> Result<(), ConfigError> {
@@ -1351,20 +1525,33 @@ fn reconfigure(info: &Info, kernel_clock: Hertz, config: &Config) -> Result<(),
    Ok(())
 }
-fn configure(
+fn calculate_brr(baud: u32, pclk: u32, presc: u32, mul: u32) -> u32 {
-    info: &Info,
+    // The calculation to be done to get the BRR is `mul * pclk / presc / baud`
-    kernel_clock: Hertz,
+    // To do this in 32-bit only we can't multiply `mul` and `pclk`
-    config: &Config,
+    let clock = pclk / presc;
-    enable_rx: bool,
-    enable_tx: bool,
-) -> Result<(), ConfigError> {
-    let r = info.regs;
-    let kind = info.kind;
-    if !enable_rx && !enable_tx {
+    // The mul is applied as the last operation to prevent overflow
-        return Err(ConfigError::RxOrTxNotEnabled);
+    let brr = clock / baud * mul;
-    }
+    // The BRR calculation will be a bit off because of integer rounding.
+    // Because we multiplied our inaccuracy with mul, our rounding now needs to be in proportion to mul.
+    let rounding = ((clock % baud) * mul + (baud / 2)) / baud;
+    brr + rounding
+}
+fn set_baudrate(info: &Info, kernel_clock: Hertz, baudrate: u32) -> Result<(), ConfigError> {
+    info.interrupt.disable();
+    set_usart_baudrate(info, kernel_clock, baudrate)?;
+    info.interrupt.unpend();
+    unsafe { info.interrupt.enable() };
+    Ok(())
+}
+fn find_and_set_brr(r: Regs, kind: Kind, kernel_clock: Hertz, baudrate: u32) -> Result<bool, ConfigError> {
    #[cfg(not(usart_v4))]
    static DIVS: [(u16, ()); 1] = [(1, ())];
@@ -1396,31 +1583,14 @@ fn configure(
        }
    };
-    fn calculate_brr(baud: u32, pclk: u32, presc: u32, mul: u32) -> u32 {
+    let mut found_brr = None;
-        // The calculation to be done to get the BRR is `mul * pclk / presc / baud`
-        // To do this in 32-bit only we can't multiply `mul` and `pclk`
-        let clock = pclk / presc;
-        // The mul is applied as the last operation to prevent overflow
-        let brr = clock / baud * mul;
-        // The BRR calculation will be a bit off because of integer rounding.
-        // Because we multiplied our inaccuracy with mul, our rounding now needs to be in proportion to mul.
-        let rounding = ((clock % baud) * mul + (baud / 2)) / baud;
-        brr + rounding
-    }
-    // UART must be disabled during configuration.
-    r.cr1().modify(|w| {
-        w.set_ue(false);
-    });
    #[cfg(not(usart_v1))]
    let mut over8 = false;
-    let mut found_brr = None;
+    #[cfg(usart_v1)]
+    let over8 = false;
    for &(presc, _presc_val) in &DIVS {
-        let brr = calculate_brr(config.baudrate, kernel_clock.0, presc as u32, mul);
+        let brr = calculate_brr(baudrate, kernel_clock.0, presc as u32, mul);
        trace!(
            "USART: presc={}, div=0x{:08x} (mantissa = {}, fraction = {})",
            presc,
@@ -1451,18 +1621,70 @@ fn configure(
        }
    }
-    let brr = found_brr.ok_or(ConfigError::BaudrateTooLow)?;
+    match found_brr {
+        Some(brr) => {
+            #[cfg(not(usart_v1))]
+            let oversampling = if over8 { "8 bit" } else { "16 bit" };
+            #[cfg(usart_v1)]
+            let oversampling = "default";
+            trace!(
+                "Using {} oversampling, desired baudrate: {}, actual baudrate: {}",
+                oversampling,
+                baudrate,
+                kernel_clock.0 / brr * mul
+            );
+            Ok(over8)
+        }
+        None => Err(ConfigError::BaudrateTooLow),
+    }
+}
+fn set_usart_baudrate(info: &Info, kernel_clock: Hertz, baudrate: u32) -> Result<(), ConfigError> {
+    let r = info.regs;
+    r.cr1().modify(|w| {
+        // disable uart
+        w.set_ue(false);
+    });
+    #[cfg(not(usart_v1))]
+    let over8 = find_and_set_brr(r, info.kind, kernel_clock, baudrate)?;
+    #[cfg(usart_v1)]
+    let _over8 = find_and_set_brr(r, info.kind, kernel_clock, baudrate)?;
+    r.cr1().modify(|w| {
+        // enable uart
+        w.set_ue(true);
+        #[cfg(not(usart_v1))]
+        w.set_over8(vals::Over8::from_bits(over8 as _));
+    });
+    Ok(())
+}
+fn configure(
+    info: &Info,
+    kernel_clock: Hertz,
+    config: &Config,
+    enable_rx: bool,
+    enable_tx: bool,
+) -> Result<(), ConfigError> {
+    let r = info.regs;
+    let kind = info.kind;
+    if !enable_rx && !enable_tx {
+        return Err(ConfigError::RxOrTxNotEnabled);
+    }
+    // UART must be disabled during configuration.
+    r.cr1().modify(|w| {
+        w.set_ue(false);
+    });
    #[cfg(not(usart_v1))]
-    let oversampling = if over8 { "8 bit" } else { "16 bit" };
+    let over8 = find_and_set_brr(r, kind, kernel_clock, config.baudrate)?;
    #[cfg(usart_v1)]
-    let oversampling = "default";
+    let _over8 = find_and_set_brr(r, kind, kernel_clock, config.baudrate)?;
-    trace!(
-        "Using {} oversampling, desired baudrate: {}, actual baudrate: {}",
-        oversampling,
-        config.baudrate,
-        kernel_clock.0 / brr * mul
-    );
    r.cr2().write(|w| {
        w.set_stop(match config.stop_bits {
@@ -1483,14 +1705,14 @@ fn configure(
    r.cr3().modify(|w| {
        #[cfg(not(usart_v1))]
        w.set_onebit(config.assume_noise_free);
-        w.set_hdsel(config.half_duplex);
+        w.set_hdsel(config.duplex.is_half());
    });
    r.cr1().write(|w| {
        // enable uart
        w.set_ue(true);
-        if config.half_duplex {
+        if config.duplex.is_half() {
            // The te and re bits will be set by write, read and flush methods.
            // Receiver should be enabled by default for Half-Duplex.
            w.set_te(false);
@@ -1502,31 +1724,66 @@ fn configure(
            w.set_re(enable_rx);
        }
-        // configure word size
+        // configure word size and parity, since the parity bit is inserted into the MSB position,
-        // if using odd or even parity it must be configured to 9bits
+        // it increases the effective word size
-        w.set_m0(if config.parity != Parity::ParityNone {
+        match (config.parity, config.data_bits) {
-            trace!("USART: m0: vals::M0::BIT9");
+            (Parity::ParityNone, DataBits::DataBits8) => {
-            vals::M0::BIT9
+                trace!("USART: m0: 8 data bits, no parity");
-        } else {
+                w.set_m0(vals::M0::BIT8);
-            trace!("USART: m0: vals::M0::BIT8");
+                #[cfg(any(usart_v3, usart_v4))]
-            vals::M0::BIT8
+                w.set_m1(vals::M1::M0);
-        });
+                w.set_pce(false);
-        // configure parity
-        w.set_pce(config.parity != Parity::ParityNone);
-        w.set_ps(match config.parity {
-            Parity::ParityOdd => {
-                trace!("USART: set_ps: vals::Ps::ODD");
-                vals::Ps::ODD
            }
-            Parity::ParityEven => {
+            (Parity::ParityNone, DataBits::DataBits9) => {
-                trace!("USART: set_ps: vals::Ps::EVEN");
+                trace!("USART: m0: 9 data bits, no parity");
-                vals::Ps::EVEN
+                w.set_m0(vals::M0::BIT9);
+                #[cfg(any(usart_v3, usart_v4))]
+                w.set_m1(vals::M1::M0);
+                w.set_pce(false);
+            }
+            #[cfg(any(usart_v3, usart_v4))]
+            (Parity::ParityNone, DataBits::DataBits7) => {
+                trace!("USART: m0: 7 data bits, no parity");
+                w.set_m0(vals::M0::BIT8);
+                w.set_m1(vals::M1::BIT7);
+                w.set_pce(false);
+            }
+            (Parity::ParityEven, DataBits::DataBits8) => {
+                trace!("USART: m0: 8 data bits, even parity");
+                w.set_m0(vals::M0::BIT9);
+                #[cfg(any(usart_v3, usart_v4))]
+                w.set_m1(vals::M1::M0);
+                w.set_pce(true);
+                w.set_ps(vals::Ps::EVEN);
+            }
+            (Parity::ParityEven, DataBits::DataBits7) => {
+                trace!("USART: m0: 7 data bits, even parity");
+                w.set_m0(vals::M0::BIT8);
+                #[cfg(any(usart_v3, usart_v4))]
+                w.set_m1(vals::M1::M0);
+                w.set_pce(true);
+                w.set_ps(vals::Ps::EVEN);
+            }
+            (Parity::ParityOdd, DataBits::DataBits8) => {
+                trace!("USART: m0: 8 data bits, odd parity");
+                w.set_m0(vals::M0::BIT9);
+                #[cfg(any(usart_v3, usart_v4))]
+                w.set_m1(vals::M1::M0);
+                w.set_pce(true);
+                w.set_ps(vals::Ps::ODD);
+            }
+            (Parity::ParityOdd, DataBits::DataBits7) => {
+                trace!("USART: m0: 7 data bits, odd parity");
+                w.set_m0(vals::M0::BIT8);
+                #[cfg(any(usart_v3, usart_v4))]
+                w.set_m1(vals::M1::M0);
+                w.set_pce(true);
+                w.set_ps(vals::Ps::ODD);
            }
            _ => {
-                trace!("USART: set_ps: vals::Ps::EVEN");
+                return Err(ConfigError::DataParityNotSupported);
-                vals::Ps::EVEN
            }
-        });
+        }
        #[cfg(not(usart_v1))]
        w.set_over8(vals::Over8::from_bits(over8 as _));
        #[cfg(usart_v4)]
@@ -1534,7 +1791,9 @@ fn configure(
            trace!("USART: set_fifoen: true (usart_v4)");
            w.set_fifoen(true);
        }
-    });
+        Ok(())
+    })?;
    Ok(())
 }
@@ -1672,7 +1931,7 @@ impl embedded_io_async::Write for Uart<'_, Async> {
    }
    async fn flush(&mut self) -> Result<(), Self::Error> {
-        self.blocking_flush()
+        self.flush().await
    }
 }
@@ -1683,7 +1942,7 @@ impl embedded_io_async::Write for UartTx<'_, Async> {
    }
    async fn flush(&mut self) -> Result<(), Self::Error> {
-        self.blocking_flush()
+        self.flush().await
    }
 }
@@ -1749,6 +2008,7 @@ enum Kind {
 struct State {
    rx_waker: AtomicWaker,
+    tx_waker: AtomicWaker,
    tx_rx_refcount: AtomicU8,
 }
@@ -1756,6 +2016,7 @@ impl State {
    const fn new() -> Self {
        Self {
            rx_waker: AtomicWaker::new(),
+            tx_waker: AtomicWaker::new(),
            tx_rx_refcount: AtomicU8::new(0),
        }
    }
@@ -1777,7 +2038,7 @@ pub(crate) trait SealedInstance: crate::rcc::RccPeripheral {
 /// USART peripheral instance trait.
 #[allow(private_bounds)]
-pub trait Instance: Peripheral<P = Self> + SealedInstance + 'static + Send {
+pub trait Instance: SealedInstance + PeripheralType + 'static + Send {
    /// Interrupt for this peripheral.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
diff --git a/embassy-stm32/src/usart/ringbuffered.rs b/embassy-stm32/src/usart/ringbuffered.rs
index 8cf75933a..1d4a44896 100644
--- a/embassy-stm32/src/usart/ringbuffered.rs
+++ b/embassy-stm32/src/usart/ringbuffered.rs
@@ -4,25 +4,85 @@ use core::sync::atomic::{compiler_fence, Ordering};
 use core::task::Poll;
 use embassy_embedded_hal::SetConfig;
-use embassy_hal_internal::PeripheralRef;
+use embedded_io_async::ReadReady;
 use futures_util::future::{select, Either};
-use super::{clear_interrupt_flags, rdr, reconfigure, sr, Config, ConfigError, Error, Info, State, UartRx};
+use super::{rdr, reconfigure, set_baudrate, sr, Config, ConfigError, Error, Info, State, UartRx};
 use crate::dma::ReadableRingBuffer;
 use crate::gpio::{AnyPin, SealedPin as _};
 use crate::mode::Async;
 use crate::time::Hertz;
-use crate::usart::{Regs, Sr};
+use crate::usart::Regs;
+use crate::Peri;
 /// Rx-only Ring-buffered UART Driver
 ///
 /// Created with [UartRx::into_ring_buffered]
+///
+/// ### Notes on 'waiting for bytes'
+///
+/// The `read(buf)` (but not `read()`) and `read_exact(buf)` functions
+/// may need to wait for bytes to arrive, if the ring buffer does not
+/// contain enough bytes to fill the buffer passed by the caller of
+/// the function, or is empty.
+///
+/// Waiting for bytes operates in one of two modes, depending on
+/// the behavior of the sender and the size of the buffer passed
+/// to the function:
+///
+/// - If the sender sends intermittently, the 'idle line'
+/// condition will be detected when the sender stops, and any
+/// bytes in the ring buffer will be returned. If there are no
+/// bytes in the buffer, the check will be repeated each time the
+/// 'idle line' condition is detected, so if the sender sends just
+/// a single byte, it will be returned once the 'idle line'
+/// condition is detected.
+///
+/// - If the sender sends continuously, the call will wait until
+/// the DMA controller indicates that it has written to either the
+/// middle byte or last byte of the ring buffer ('half transfer'
+/// or 'transfer complete', respectively). This does not indicate
+/// the buffer is half-full or full, though, because the DMA
+/// controller does not detect those conditions; it sends an
+/// interrupt when those specific buffer addresses have been
+/// written.
+///
+/// In both cases this will result in variable latency due to the
+/// buffering effect. For example, if the baudrate is 2400 bps, and
+/// the configuration is 8 data bits, no parity bit, and one stop bit,
+/// then a byte will be received every ~4.16ms. If the ring buffer is
+/// 32 bytes, then a 'wait for bytes' delay may have to wait for 16
+/// bytes in the worst case, resulting in a delay (latency) of
+/// ~62.46ms for the first byte in the ring buffer. If the sender
+/// sends only 6 bytes and then stops, but the buffer was empty when
+/// the read function was called, then those bytes may not be returned
+/// until ~24.96ms after the first byte was received (time for 5
+/// additional bytes plus the 'idle frame' which triggers the 'idle
+/// line' condition).
+///
+/// Applications subject to this latency must be careful if they
+/// also apply timeouts during reception, as it may appear (to
+/// them) that the sender has stopped sending when it did not. In
+/// the example above, a 50ms timeout (12 bytes at 2400bps) might
+/// seem to be reasonable to detect that the sender has stopped
+/// sending, but would be falsely triggered in the worst-case
+/// buffer delay scenario.
+///
+/// Note: This latency is caused by the limited capabilities of the
+/// STM32 DMA controller; since it cannot generate an interrupt when
+/// it stores a byte into an empty ring buffer, or in any other
+/// configurable conditions, it is not possible to take notice of the
+/// contents of the ring buffer more quickly without introducing
+/// polling. As a result the latency can be reduced by calling the
+/// read functions repeatedly with smaller buffers to receive the
+/// available bytes, as each call to a read function will explicitly
+/// check the ring buffer for available bytes.
 pub struct RingBufferedUartRx<'d> {
    info: &'static Info,
    state: &'static State,
    kernel_clock: Hertz,
-    rx: Option<PeripheralRef<'d, AnyPin>>,
+    rx: Option<Peri<'d, AnyPin>>,
-    rts: Option<PeripheralRef<'d, AnyPin>>,
+    rts: Option<Peri<'d, AnyPin>>,
    ring_buf: ReadableRingBuffer<'d, u8>,
 }
@@ -71,33 +131,18 @@ impl<'d> UartRx<'d, Async> {
 }
 impl<'d> RingBufferedUartRx<'d> {
-    /// Clear the ring buffer and start receiving in the background
-    pub fn start(&mut self) -> Result<(), Error> {
-        // Clear the ring buffer so that it is ready to receive data
-        self.ring_buf.clear();
-        self.setup_uart();
-        Ok(())
-    }
-    fn stop(&mut self, err: Error) -> Result<usize, Error> {
-        self.teardown_uart();
-        Err(err)
-    }
    /// Reconfigure the driver
    pub fn set_config(&mut self, config: &Config) -> Result<(), ConfigError> {
        reconfigure(self.info, self.kernel_clock, config)
    }
-    /// Start uart background receive
+    /// Configure and start the DMA backed UART receiver
-    fn setup_uart(&mut self) {
+    ///
-        // fence before starting DMA.
+    /// Note: This is also done automatically by the read functions if
+    /// required.
+    pub fn start_uart(&mut self) {
+        // Clear the buffer so that it is ready to receive data
        compiler_fence(Ordering::SeqCst);
-        // start the dma controller
        self.ring_buf.start();
        let r = self.info.regs;
@@ -118,9 +163,9 @@ impl<'d> RingBufferedUartRx<'d> {
        });
    }
-    /// Stop uart background receive
+    /// Stop DMA backed UART receiver
-    fn teardown_uart(&mut self) {
+    fn stop_uart(&mut self) {
-        self.ring_buf.request_stop();
+        self.ring_buf.request_pause();
        let r = self.info.regs;
        // clear all interrupts and DMA Rx Request
@@ -142,23 +187,40 @@ impl<'d> RingBufferedUartRx<'d> {
        compiler_fence(Ordering::SeqCst);
    }
-    /// Read bytes that are readily available in the ring buffer.
+    /// (Re-)start DMA and Uart if it is not running (has not been started yet or has failed), and
-    /// If no bytes are currently available in the buffer the call waits until the some
+    /// check for errors in status register. Error flags are checked/cleared first.
-    /// bytes are available (at least one byte and at most half the buffer size)
+    fn start_dma_or_check_errors(&mut self) -> Result<(), Error> {
-    ///
-    /// Background receive is started if `start()` has not been previously called.
-    ///
-    /// Receive in the background is terminated if an error is returned.
-    /// It must then manually be started again by calling `start()` or by re-calling `read()`.
-    pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
        let r = self.info.regs;
-        // Start background receive if it was not already started
+        check_idle_and_errors(r)?;
        if !r.cr3().read().dmar() {
-            self.start()?;
+            self.start_uart();
        }
+        Ok(())
+    }
+    /// Read bytes that are available in the ring buffer, or wait for
+    /// bytes to become available and return them.
+    ///
+    /// Background reception is started if necessary (if `start_uart()` had
+    /// not previously been called, or if an error was detected which
+    /// caused background reception to be stopped).
+    ///
+    /// Background reception is terminated when an error is returned.
+    /// It must be started again by calling `start_uart()` or by
+    /// calling a read function again.
+    pub async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Error> {
+        self.start_dma_or_check_errors()?;
-        check_for_errors(clear_idle_flag(r))?;
+        // In half-duplex mode, we need to disable the Transmitter and enable the Receiver
+        // since they can't operate simultaneously on the shared line
+        let r = self.info.regs;
+        if r.cr3().read().hdsel() && r.cr1().read().te() {
+            r.cr1().modify(|reg| {
+                reg.set_re(true);
+                reg.set_te(false);
+            });
+        }
        loop {
            match self.ring_buf.read(buf) {
@@ -167,14 +229,16 @@ impl<'d> RingBufferedUartRx<'d> {
                    return Ok(len);
                }
                Err(_) => {
-                    return self.stop(Error::Overrun);
+                    self.stop_uart();
+                    return Err(Error::Overrun);
                }
            }
            match self.wait_for_data_or_idle().await {
                Ok(_) => {}
                Err(err) => {
-                    return self.stop(err);
+                    self.stop_uart();
+                    return Err(err);
                }
            }
        }
@@ -184,20 +248,6 @@ impl<'d> RingBufferedUartRx<'d> {
    async fn wait_for_data_or_idle(&mut self) -> Result<(), Error> {
        compiler_fence(Ordering::SeqCst);
-        let mut dma_init = false;
-        // Future which completes when there is dma is half full or full
-        let dma = poll_fn(|cx| {
-            self.ring_buf.set_waker(cx.waker());
-            let status = match dma_init {
-                false => Poll::Pending,
-                true => Poll::Ready(()),
-            };
-            dma_init = true;
-            status
-        });
        // Future which completes when idle line is detected
        let s = self.state;
        let uart = poll_fn(|cx| {
@@ -205,13 +255,7 @@ impl<'d> RingBufferedUartRx<'d> {
            compiler_fence(Ordering::SeqCst);
-            // Critical section is needed so that IDLE isn't set after
+            if check_idle_and_errors(self.info.regs)? {
-            // our read but before we clear it.
-            let sr = critical_section::with(|_| clear_idle_flag(self.info.regs));
-            check_for_errors(sr)?;
-            if sr.idle() {
                // Idle line is detected
                Poll::Ready(Ok(()))
            } else {
@@ -219,58 +263,131 @@ impl<'d> RingBufferedUartRx<'d> {
            }
        });
-        match select(dma, uart).await {
+        let mut dma_init = false;
-            Either::Left(((), _)) => Ok(()),
+        // Future which completes when the DMA controller indicates it
-            Either::Right((result, _)) => result,
+        // has written to the ring buffer's middle byte, or last byte
+        let dma = poll_fn(|cx| {
+            self.ring_buf.set_waker(cx.waker());
+            let status = match dma_init {
+                false => Poll::Pending,
+                true => Poll::Ready(()),
+            };
+            dma_init = true;
+            status
+        });
+        match select(uart, dma).await {
+            Either::Left((result, _)) => result,
+            Either::Right(((), _)) => Ok(()),
        }
    }
+    /// Set baudrate
+    pub fn set_baudrate(&self, baudrate: u32) -> Result<(), ConfigError> {
+        set_baudrate(self.info, self.kernel_clock, baudrate)
+    }
 }
 impl Drop for RingBufferedUartRx<'_> {
    fn drop(&mut self) {
-        self.teardown_uart();
+        self.stop_uart();
        self.rx.as_ref().map(|x| x.set_as_disconnected());
        self.rts.as_ref().map(|x| x.set_as_disconnected());
        super::drop_tx_rx(self.info, self.state);
    }
 }
-/// Return an error result if the Sr register has errors
+/// Check and clear idle and error interrupts, return true if idle, Err(e) on error
-fn check_for_errors(s: Sr) -> Result<(), Error> {
+///
-    if s.pe() {
+/// All flags are read and cleared in a single step, respectively. When more than one flag is set
+/// at the same time, all flags will be cleared but only one flag will be reported. So the other
+/// flag(s) will gone missing unnoticed. The error flags are checked first, the idle flag last.
+///
+/// For usart_v1 and usart_v2, all status flags must be handled together anyway because all flags
+/// are cleared by a single read to the RDR register.
+fn check_idle_and_errors(r: Regs) -> Result<bool, Error> {
+    // Critical section is required so that the flags aren't set after read and before clear
+    let sr = critical_section::with(|_| {
+        // SAFETY: read only and we only use Rx related flags
+        let sr = sr(r).read();
+        #[cfg(any(usart_v3, usart_v4))]
+        r.icr().write(|w| {
+            w.set_idle(true);
+            w.set_pe(true);
+            w.set_fe(true);
+            w.set_ne(true);
+            w.set_ore(true);
+        });
+        #[cfg(not(any(usart_v3, usart_v4)))]
+        unsafe {
+            // This read also clears the error and idle interrupt flags on v1 (TODO and v2?)
+            rdr(r).read_volatile()
+        };
+        sr
+    });
+    if sr.pe() {
        Err(Error::Parity)
-    } else if s.fe() {
+    } else if sr.fe() {
        Err(Error::Framing)
-    } else if s.ne() {
+    } else if sr.ne() {
        Err(Error::Noise)
-    } else if s.ore() {
+    } else if sr.ore() {
        Err(Error::Overrun)
    } else {
-        Ok(())
+        r.cr1().modify(|w| w.set_idleie(true));
+        Ok(sr.idle())
    }
 }
-/// Clear IDLE and return the Sr register
+impl embedded_io_async::ErrorType for RingBufferedUartRx<'_> {
-fn clear_idle_flag(r: Regs) -> Sr {
+    type Error = Error;
-    // SAFETY: read only and we only use Rx related flags
+}
-    let sr = sr(r).read();
-    // This read also clears the error and idle interrupt flags on v1.
+impl embedded_io_async::Read for RingBufferedUartRx<'_> {
-    unsafe { rdr(r).read_volatile() };
+    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
-    clear_interrupt_flags(r, sr);
+        self.read(buf).await
+    }
+}
-    r.cr1().modify(|w| w.set_idleie(true));
+impl embedded_hal_nb::serial::Read for RingBufferedUartRx<'_> {
+    fn read(&mut self) -> nb::Result<u8, Self::Error> {
+        self.start_dma_or_check_errors()?;
-    sr
+        let mut buf = [0u8; 1];
+        match self.ring_buf.read(&mut buf) {
+            Ok((0, _)) => Err(nb::Error::WouldBlock),
+            Ok((len, _)) => {
+                assert!(len == 1);
+                Ok(buf[0])
+            }
+            Err(_) => {
+                self.stop_uart();
+                Err(nb::Error::Other(Error::Overrun))
+            }
+        }
+    }
 }
-impl embedded_io_async::ErrorType for RingBufferedUartRx<'_> {
+impl embedded_hal_nb::serial::ErrorType for RingBufferedUartRx<'_> {
    type Error = Error;
 }
-impl embedded_io_async::Read for RingBufferedUartRx<'_> {
+impl ReadReady for RingBufferedUartRx<'_> {
-    async fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
+    fn read_ready(&mut self) -> Result<bool, Self::Error> {
-        self.read(buf).await
+        let len = self.ring_buf.len().map_err(|e| match e {
+            crate::dma::ringbuffer::Error::Overrun => Self::Error::Overrun,
+            crate::dma::ringbuffer::Error::DmaUnsynced => {
+                error!(
+                    "Ringbuffer error: DmaUNsynced, driver implementation is 
+                    probably bugged please open an issue"
+                );
+                // we report this as overrun since its recoverable in the same way
+                Self::Error::Overrun
+            }
+        })?;
+        Ok(len > 0)
    }
 }
diff --git a/embassy-stm32/src/usb/mod.rs b/embassy-stm32/src/usb/mod.rs
index ce9fe0a9b..ae5963420 100644
--- a/embassy-stm32/src/usb/mod.rs
+++ b/embassy-stm32/src/usb/mod.rs
@@ -13,9 +13,19 @@ fn common_init<T: Instance>() {
    // Check the USB clock is enabled and running at exactly 48 MHz.
    // frequency() will panic if not enabled
    let freq = T::frequency();
+    // On the H7RS, the USBPHYC embeds a PLL accepting one of the input frequencies listed below and providing 48MHz to OTG_FS and 60MHz to OTG_HS internally
+    #[cfg(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs)))]
+    if ![16_000_000, 19_200_000, 20_000_000, 24_000_000, 26_000_000, 32_000_000].contains(&freq.0) {
+        panic!(
+            "USB clock should be one of 16, 19.2, 20, 24, 26, 32Mhz but is {} Hz. Please double-check your RCC settings.",
+            freq.0
+        )
+    }
    // Check frequency is within the 0.25% tolerance allowed by the spec.
    // Clock might not be exact 48Mhz due to rounding errors in PLL calculation, or if the user
    // has tight clock restrictions due to something else (like audio).
+    #[cfg(not(any(stm32h7rs, all(stm32u5, peri_usb_otg_hs))))]
    if freq.0.abs_diff(48_000_000) > 120_000 {
        panic!(
            "USB clock should be 48Mhz but is {} Hz. Please double-check your RCC settings.",
@@ -48,6 +58,26 @@ fn common_init<T: Instance>() {
        while !crate::pac::PWR.cr3().read().usb33rdy() {}
    }
+    #[cfg(stm32h7rs)]
+    {
+        // If true, VDD33USB is generated by internal regulator from VDD50USB
+        // If false, VDD33USB and VDD50USB must be suplied directly with 3.3V (default on nucleo)
+        // TODO: unhardcode
+        let internal_regulator = false;
+        // Enable USB power
+        critical_section::with(|_| {
+            crate::pac::PWR.csr2().modify(|w| {
+                w.set_usbregen(internal_regulator);
+                w.set_usb33den(true);
+                w.set_usbhsregen(true);
+            })
+        });
+        // Wait for USB power to stabilize
+        while !crate::pac::PWR.csr2().read().usb33rdy() {}
+    }
    #[cfg(stm32u5)]
    {
        // Enable USB power
@@ -60,6 +90,16 @@ fn common_init<T: Instance>() {
        // Wait for USB power to stabilize
        while !crate::pac::PWR.svmsr().read().vddusbrdy() {}
+        // Now set up transceiver power if it's a OTG-HS
+        #[cfg(peri_usb_otg_hs)]
+        {
+            crate::pac::PWR.vosr().modify(|w| {
+                w.set_usbpwren(true);
+                w.set_usbboosten(true);
+            });
+            while !crate::pac::PWR.vosr().read().usbboostrdy() {}
+        }
    }
    T::Interrupt::unpend();
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 8ee8dcc36..590d1a427 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -1,6 +1,6 @@
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use embassy_usb_driver::{EndpointAddress, EndpointAllocError, EndpointType, Event, Unsupported};
 use embassy_usb_synopsys_otg::otg_v1::vals::Dspd;
 use embassy_usb_synopsys_otg::otg_v1::Otg;
@@ -11,9 +11,9 @@ use embassy_usb_synopsys_otg::{
 };
 use crate::gpio::{AfType, OutputType, Speed};
-use crate::interrupt;
 use crate::interrupt::typelevel::Interrupt;
 use crate::rcc::{self, RccPeripheral};
+use crate::{interrupt, Peri};
 const MAX_EP_COUNT: usize = 9;
@@ -24,20 +24,15 @@ pub struct InterruptHandler<T: Instance> {
 impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
    unsafe fn on_interrupt() {
-        trace!("irq");
        let r = T::regs();
        let state = T::state();
+        on_interrupt_impl(r, state, T::ENDPOINT_COUNT);
-        let setup_late_cnak = quirk_setup_late_cnak(r);
-        on_interrupt_impl(r, state, T::ENDPOINT_COUNT, setup_late_cnak);
    }
 }
 macro_rules! config_ulpi_pins {
    ($($pin:ident),*) => {
-        into_ref!($($pin),*);
+                critical_section::with(|_| {
-        critical_section::with(|_| {
            $(
                $pin.set_as_af($pin.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
            )*
@@ -66,15 +61,13 @@ impl<'d, T: Instance> Driver<'d, T> {
    /// Must be large enough to fit all OUT endpoint max packet sizes.
    /// Endpoint allocation will fail if it is too small.
    pub fn new_fs(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dp: impl Peripheral<P = impl DpPin<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
-        dm: impl Peripheral<P = impl DmPin<T>> + 'd,
+        dm: Peri<'d, impl DmPin<T>>,
        ep_out_buffer: &'d mut [u8],
        config: Config,
    ) -> Self {
-        into_ref!(dp, dm);
        dp.set_as_af(dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
        dm.set_as_af(dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
@@ -87,7 +80,90 @@ impl<'d, T: Instance> Driver<'d, T> {
            extra_rx_fifo_words: RX_FIFO_EXTRA_SIZE_WORDS,
            endpoint_count: T::ENDPOINT_COUNT,
            phy_type: PhyType::InternalFullSpeed,
-            quirk_setup_late_cnak: quirk_setup_late_cnak(regs),
+            calculate_trdt_fn: calculate_trdt::<T>,
+        };
+        Self {
+            inner: OtgDriver::new(ep_out_buffer, instance, config),
+            phantom: PhantomData,
+        }
+    }
+    /// Initializes USB OTG peripheral with internal High-Speed PHY.
+    ///
+    /// # Arguments
+    ///
+    /// * `ep_out_buffer` - An internal buffer used to temporarily store received packets.
+    /// Must be large enough to fit all OUT endpoint max packet sizes.
+    /// Endpoint allocation will fail if it is too small.
+    pub fn new_hs(
+        _peri: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        _dp: Peri<'d, impl DpPin<T>>,
+        _dm: Peri<'d, impl DmPin<T>>,
+        ep_out_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Self {
+        // For STM32U5 High speed pins need to be left in analog mode
+        #[cfg(not(all(stm32u5, peri_usb_otg_hs)))]
+        {
+            _dp.set_as_af(_dp.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+            _dm.set_as_af(_dm.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        }
+        let instance = OtgInstance {
+            regs: T::regs(),
+            state: T::state(),
+            fifo_depth_words: T::FIFO_DEPTH_WORDS,
+            extra_rx_fifo_words: RX_FIFO_EXTRA_SIZE_WORDS,
+            endpoint_count: T::ENDPOINT_COUNT,
+            phy_type: PhyType::InternalHighSpeed,
+            calculate_trdt_fn: calculate_trdt::<T>,
+        };
+        Self {
+            inner: OtgDriver::new(ep_out_buffer, instance, config),
+            phantom: PhantomData,
+        }
+    }
+    /// Initializes USB OTG peripheral with external Full-speed PHY (usually, a High-speed PHY in Full-speed mode).
+    ///
+    /// # Arguments
+    ///
+    /// * `ep_out_buffer` - An internal buffer used to temporarily store received packets.
+    /// Must be large enough to fit all OUT endpoint max packet sizes.
+    /// Endpoint allocation will fail if it is too small.
+    pub fn new_fs_ulpi(
+        _peri: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        ulpi_clk: Peri<'d, impl UlpiClkPin<T>>,
+        ulpi_dir: Peri<'d, impl UlpiDirPin<T>>,
+        ulpi_nxt: Peri<'d, impl UlpiNxtPin<T>>,
+        ulpi_stp: Peri<'d, impl UlpiStpPin<T>>,
+        ulpi_d0: Peri<'d, impl UlpiD0Pin<T>>,
+        ulpi_d1: Peri<'d, impl UlpiD1Pin<T>>,
+        ulpi_d2: Peri<'d, impl UlpiD2Pin<T>>,
+        ulpi_d3: Peri<'d, impl UlpiD3Pin<T>>,
+        ulpi_d4: Peri<'d, impl UlpiD4Pin<T>>,
+        ulpi_d5: Peri<'d, impl UlpiD5Pin<T>>,
+        ulpi_d6: Peri<'d, impl UlpiD6Pin<T>>,
+        ulpi_d7: Peri<'d, impl UlpiD7Pin<T>>,
+        ep_out_buffer: &'d mut [u8],
+        config: Config,
+    ) -> Self {
+        config_ulpi_pins!(
+            ulpi_clk, ulpi_dir, ulpi_nxt, ulpi_stp, ulpi_d0, ulpi_d1, ulpi_d2, ulpi_d3, ulpi_d4, ulpi_d5, ulpi_d6,
+            ulpi_d7
+        );
+        let instance = OtgInstance {
+            regs: T::regs(),
+            state: T::state(),
+            fifo_depth_words: T::FIFO_DEPTH_WORDS,
+            extra_rx_fifo_words: RX_FIFO_EXTRA_SIZE_WORDS,
+            endpoint_count: T::ENDPOINT_COUNT,
+            phy_type: PhyType::ExternalFullSpeed,
            calculate_trdt_fn: calculate_trdt::<T>,
        };
@@ -105,20 +181,20 @@ impl<'d, T: Instance> Driver<'d, T> {
    /// Must be large enough to fit all OUT endpoint max packet sizes.
    /// Endpoint allocation will fail if it is too small.
    pub fn new_hs_ulpi(
-        _peri: impl Peripheral<P = T> + 'd,
+        _peri: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
+        ulpi_clk: Peri<'d, impl UlpiClkPin<T>>,
-        ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
+        ulpi_dir: Peri<'d, impl UlpiDirPin<T>>,
-        ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,
+        ulpi_nxt: Peri<'d, impl UlpiNxtPin<T>>,
-        ulpi_stp: impl Peripheral<P = impl UlpiStpPin<T>> + 'd,
+        ulpi_stp: Peri<'d, impl UlpiStpPin<T>>,
-        ulpi_d0: impl Peripheral<P = impl UlpiD0Pin<T>> + 'd,
+        ulpi_d0: Peri<'d, impl UlpiD0Pin<T>>,
-        ulpi_d1: impl Peripheral<P = impl UlpiD1Pin<T>> + 'd,
+        ulpi_d1: Peri<'d, impl UlpiD1Pin<T>>,
-        ulpi_d2: impl Peripheral<P = impl UlpiD2Pin<T>> + 'd,
+        ulpi_d2: Peri<'d, impl UlpiD2Pin<T>>,
-        ulpi_d3: impl Peripheral<P = impl UlpiD3Pin<T>> + 'd,
+        ulpi_d3: Peri<'d, impl UlpiD3Pin<T>>,
-        ulpi_d4: impl Peripheral<P = impl UlpiD4Pin<T>> + 'd,
+        ulpi_d4: Peri<'d, impl UlpiD4Pin<T>>,
-        ulpi_d5: impl Peripheral<P = impl UlpiD5Pin<T>> + 'd,
+        ulpi_d5: Peri<'d, impl UlpiD5Pin<T>>,
-        ulpi_d6: impl Peripheral<P = impl UlpiD6Pin<T>> + 'd,
+        ulpi_d6: Peri<'d, impl UlpiD6Pin<T>>,
-        ulpi_d7: impl Peripheral<P = impl UlpiD7Pin<T>> + 'd,
+        ulpi_d7: Peri<'d, impl UlpiD7Pin<T>>,
        ep_out_buffer: &'d mut [u8],
        config: Config,
    ) -> Self {
@@ -129,8 +205,6 @@ impl<'d, T: Instance> Driver<'d, T> {
            ulpi_d7
        );
-        let regs = T::regs();
        let instance = OtgInstance {
            regs: T::regs(),
            state: T::state(),
@@ -138,7 +212,6 @@ impl<'d, T: Instance> Driver<'d, T> {
            extra_rx_fifo_words: RX_FIFO_EXTRA_SIZE_WORDS,
            endpoint_count: T::ENDPOINT_COUNT,
            phy_type: PhyType::ExternalHighSpeed,
-            quirk_setup_late_cnak: quirk_setup_late_cnak(regs),
            calculate_trdt_fn: calculate_trdt::<T>,
        };
@@ -223,6 +296,33 @@ impl<'d, T: Instance> Bus<'d, T> {
            }
        });
+        #[cfg(stm32h7rs)]
+        critical_section::with(|_| {
+            let rcc = crate::pac::RCC;
+            rcc.ahb1enr().modify(|w| {
+                w.set_usbphycen(true);
+                w.set_usb_otg_hsen(true);
+            });
+            rcc.ahb1lpenr().modify(|w| {
+                w.set_usbphyclpen(true);
+                w.set_usb_otg_hslpen(true);
+            });
+        });
+        #[cfg(all(stm32u5, peri_usb_otg_hs))]
+        {
+            crate::pac::SYSCFG.otghsphycr().modify(|w| {
+                w.set_en(true);
+            });
+            critical_section::with(|_| {
+                crate::pac::RCC.ahb2enr1().modify(|w| {
+                    w.set_usb_otg_hsen(true);
+                    w.set_usb_otg_hs_phyen(true);
+                });
+            });
+        }
        let r = T::regs();
        let core_id = r.cid().read().0;
        trace!("Core id {:08x}", core_id);
@@ -235,8 +335,9 @@ impl<'d, T: Instance> Bus<'d, T> {
        // Configuring Vbus sense and SOF output
        match core_id {
-            0x0000_1200 | 0x0000_1100 => self.inner.config_v1(),
+            0x0000_1200 | 0x0000_1100 | 0x0000_1000 => self.inner.config_v1(),
            0x0000_2000 | 0x0000_2100 | 0x0000_2300 | 0x0000_3000 | 0x0000_3100 => self.inner.config_v2v3(),
+            0x0000_5000 => self.inner.config_v5(),
            _ => unimplemented!("Unknown USB core id {:X}", core_id),
        }
    }
@@ -306,7 +407,7 @@ trait SealedInstance {
 /// USB instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
    /// Interrupt for this USB instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
@@ -448,11 +549,11 @@ foreach_interrupt!(
 );
 fn calculate_trdt<T: Instance>(speed: Dspd) -> u8 {
-    let ahb_freq = T::frequency().0;
+    let ahb_freq = T::bus_frequency().0;
    match speed {
        Dspd::HIGH_SPEED => {
            // From RM0431 (F72xx), RM0090 (F429), RM0390 (F446)
-            if ahb_freq >= 30_000_000 {
+            if ahb_freq >= 30_000_000 || cfg!(stm32h7rs) {
                0x9
            } else {
                panic!("AHB frequency is too low")
@@ -477,7 +578,3 @@ fn calculate_trdt<T: Instance>(speed: Dspd) -> u8 {
        _ => unimplemented!(),
    }
 }
-fn quirk_setup_late_cnak(r: Otg) -> bool {
-    r.cid().read().0 & 0xf000 == 0x1000
-}
diff --git a/embassy-stm32/src/usb/usb.rs b/embassy-stm32/src/usb/usb.rs
index 9384c8688..3e8e74a1f 100644
--- a/embassy-stm32/src/usb/usb.rs
+++ b/embassy-stm32/src/usb/usb.rs
@@ -5,7 +5,7 @@ use core::marker::PhantomData;
 use core::sync::atomic::{AtomicBool, Ordering};
 use core::task::Poll;
-use embassy_hal_internal::into_ref;
+use embassy_hal_internal::PeripheralType;
 use embassy_sync::waitqueue::AtomicWaker;
 use embassy_usb_driver as driver;
 use embassy_usb_driver::{
@@ -16,7 +16,7 @@ use crate::pac::usb::regs;
 use crate::pac::usb::vals::{EpType, Stat};
 use crate::pac::USBRAM;
 use crate::rcc::RccPeripheral;
-use crate::{interrupt, Peripheral};
+use crate::{interrupt, Peri};
 /// Interrupt handler.
 pub struct InterruptHandler<T: Instance> {
@@ -80,8 +80,10 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
        if istr.ctr() {
            let index = istr.ep_id() as usize;
            let mut epr = regs.epr(index).read();
            if epr.ctr_rx() {
+                RX_COMPLETE[index].store(true, Ordering::Relaxed);
                if index == 0 && epr.setup() {
                    EP0_SETUP.store(true, Ordering::Relaxed);
                }
@@ -89,6 +91,7 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
                EP_OUT_WAKERS[index].wake();
            }
            if epr.ctr_tx() {
+                TX_PENDING[index].store(false, Ordering::Relaxed);
                //trace!("EP {} TX", index);
                EP_IN_WAKERS[index].wake();
            }
@@ -117,11 +120,13 @@ const USBRAM_ALIGN: usize = 2;
 #[cfg(any(usbram_32_2048, usbram_32_1024))]
 const USBRAM_ALIGN: usize = 4;
-const NEW_AW: AtomicWaker = AtomicWaker::new();
+static BUS_WAKER: AtomicWaker = AtomicWaker::new();
-static BUS_WAKER: AtomicWaker = NEW_AW;
 static EP0_SETUP: AtomicBool = AtomicBool::new(false);
-static EP_IN_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
-static EP_OUT_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
+static TX_PENDING: [AtomicBool; EP_COUNT] = [const { AtomicBool::new(false) }; EP_COUNT];
+static RX_COMPLETE: [AtomicBool; EP_COUNT] = [const { AtomicBool::new(false) }; EP_COUNT];
+static EP_IN_WAKERS: [AtomicWaker; EP_COUNT] = [const { AtomicWaker::new() }; EP_COUNT];
+static EP_OUT_WAKERS: [AtomicWaker; EP_COUNT] = [const { AtomicWaker::new() }; EP_COUNT];
 static IRQ_RESET: AtomicBool = AtomicBool::new(false);
 static IRQ_SUSPEND: AtomicBool = AtomicBool::new(false);
 static IRQ_RESUME: AtomicBool = AtomicBool::new(false);
@@ -163,20 +168,37 @@ fn calc_out_len(len: u16) -> (u16, u16) {
 mod btable {
    use super::*;
-    pub(super) fn write_in<T: Instance>(index: usize, addr: u16) {
+    pub(super) fn write_in_tx<T: Instance>(index: usize, addr: u16) {
        USBRAM.mem(index * 4 + 0).write_value(addr);
    }
-    pub(super) fn write_in_len<T: Instance>(index: usize, _addr: u16, len: u16) {
+    pub(super) fn write_in_rx<T: Instance>(index: usize, addr: u16) {
+        USBRAM.mem(index * 4 + 2).write_value(addr);
+    }
+    pub(super) fn write_in_len_rx<T: Instance>(index: usize, _addr: u16, len: u16) {
+        USBRAM.mem(index * 4 + 3).write_value(len);
+    }
+    pub(super) fn write_in_len_tx<T: Instance>(index: usize, _addr: u16, len: u16) {
        USBRAM.mem(index * 4 + 1).write_value(len);
    }
-    pub(super) fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
+    pub(super) fn write_out_rx<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
        USBRAM.mem(index * 4 + 2).write_value(addr);
        USBRAM.mem(index * 4 + 3).write_value(max_len_bits);
    }
-    pub(super) fn read_out_len<T: Instance>(index: usize) -> u16 {
+    pub(super) fn write_out_tx<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
+        USBRAM.mem(index * 4 + 0).write_value(addr);
+        USBRAM.mem(index * 4 + 1).write_value(max_len_bits);
+    }
+    pub(super) fn read_out_len_tx<T: Instance>(index: usize) -> u16 {
+        USBRAM.mem(index * 4 + 1).read()
+    }
+    pub(super) fn read_out_len_rx<T: Instance>(index: usize) -> u16 {
        USBRAM.mem(index * 4 + 3).read()
    }
 }
@@ -184,19 +206,35 @@ mod btable {
 mod btable {
    use super::*;
-    pub(super) fn write_in<T: Instance>(_index: usize, _addr: u16) {}
+    pub(super) fn write_in_len_tx<T: Instance>(index: usize, addr: u16, len: u16) {
+        assert_eq!(addr & 0b11, 0);
-    pub(super) fn write_in_len<T: Instance>(index: usize, addr: u16, len: u16) {
        USBRAM.mem(index * 2).write_value((addr as u32) | ((len as u32) << 16));
    }
-    pub(super) fn write_out<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
+    pub(super) fn write_in_len_rx<T: Instance>(index: usize, addr: u16, len: u16) {
+        assert_eq!(addr & 0b11, 0);
+        USBRAM
+            .mem(index * 2 + 1)
+            .write_value((addr as u32) | ((len as u32) << 16));
+    }
+    pub(super) fn write_out_tx<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
+        USBRAM
+            .mem(index * 2)
+            .write_value((addr as u32) | ((max_len_bits as u32) << 16));
+    }
+    pub(super) fn write_out_rx<T: Instance>(index: usize, addr: u16, max_len_bits: u16) {
        USBRAM
            .mem(index * 2 + 1)
            .write_value((addr as u32) | ((max_len_bits as u32) << 16));
    }
-    pub(super) fn read_out_len<T: Instance>(index: usize) -> u16 {
+    pub(super) fn read_out_len_tx<T: Instance>(index: usize) -> u16 {
+        (USBRAM.mem(index * 2).read() >> 16) as u16
+    }
+    pub(super) fn read_out_len_rx<T: Instance>(index: usize) -> u16 {
        (USBRAM.mem(index * 2 + 1).read() >> 16) as u16
    }
 }
@@ -249,15 +287,30 @@ pub struct Driver<'d, T: Instance> {
 }
 impl<'d, T: Instance> Driver<'d, T> {
+    /// Create a new USB driver with start-of-frame (SOF) output.
+    #[cfg(not(stm32l1))]
+    pub fn new_with_sof(
+        _usb: Peri<'d, T>,
+        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
+        dm: Peri<'d, impl DmPin<T>>,
+        sof: Peri<'d, impl SofPin<T>>,
+    ) -> Self {
+        {
+            use crate::gpio::{AfType, OutputType, Speed};
+            sof.set_as_af(sof.af_num(), AfType::output(OutputType::PushPull, Speed::VeryHigh));
+        }
+        Self::new(_usb, _irq, dp, dm)
+    }
    /// Create a new USB driver.
    pub fn new(
-        _usb: impl Peripheral<P = T> + 'd,
+        _usb: Peri<'d, T>,
        _irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
-        dp: impl Peripheral<P = impl DpPin<T>> + 'd,
+        dp: Peri<'d, impl DpPin<T>>,
-        dm: impl Peripheral<P = impl DmPin<T>> + 'd,
+        dm: Peri<'d, impl DmPin<T>>,
    ) -> Self {
-        into_ref!(dp, dm);
        super::common_init::<T>();
        let regs = T::regs();
@@ -267,10 +320,8 @@ impl<'d, T: Instance> Driver<'d, T> {
            w.set_fres(true);
        });
-        #[cfg(feature = "time")]
+        // wait t_STARTUP = 1us
-        embassy_time::block_for(embassy_time::Duration::from_millis(100));
+        cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 1_000_000);
-        #[cfg(not(feature = "time"))]
-        cortex_m::asm::delay(unsafe { crate::rcc::get_freqs() }.sys.to_hertz().unwrap().0 / 10);
        #[cfg(not(usb_v4))]
        regs.btable().write(|w| w.set_btable(0));
@@ -327,6 +378,14 @@ impl<'d, T: Instance> Driver<'d, T> {
                return false; // reserved for control pipe
            }
            let used = ep.used_out || ep.used_in;
+            if used && (ep.ep_type == EndpointType::Isochronous) {
+                // Isochronous endpoints are always double-buffered.
+                // Their corresponding endpoint/channel registers are forced to be unidirectional.
+                // Do not reuse this index.
+                // FIXME: Bulk endpoints can be double buffered, but are not in the current implementation.
+                return false;
+            }
            let used_dir = match D::dir() {
                Direction::Out => ep.used_out,
                Direction::In => ep.used_in,
@@ -350,7 +409,11 @@ impl<'d, T: Instance> Driver<'d, T> {
                let addr = self.alloc_ep_mem(len);
                trace!("  len_bits = {:04x}", len_bits);
-                btable::write_out::<T>(index, addr, len_bits);
+                btable::write_out_rx::<T>(index, addr, len_bits);
+                if ep_type == EndpointType::Isochronous {
+                    btable::write_out_tx::<T>(index, addr, len_bits);
+                }
                EndpointBuffer {
                    addr,
@@ -365,8 +428,24 @@ impl<'d, T: Instance> Driver<'d, T> {
                let len = align_len_up(max_packet_size);
                let addr = self.alloc_ep_mem(len);
-                // ep_in_len is written when actually TXing packets.
+                #[cfg(not(any(usbram_32_2048, usbram_32_1024)))]
-                btable::write_in::<T>(index, addr);
+                {
+                    // ep_in_len is written when actually transmitting packets.
+                    btable::write_in_tx::<T>(index, addr);
+                    if ep_type == EndpointType::Isochronous {
+                        btable::write_in_rx::<T>(index, addr);
+                    }
+                }
+                #[cfg(any(usbram_32_2048, usbram_32_1024))]
+                {
+                    btable::write_in_len_tx::<T>(index, addr, 0);
+                    if ep_type == EndpointType::Isochronous {
+                        btable::write_in_len_rx::<T>(index, addr, 0);
+                    }
+                }
                EndpointBuffer {
                    addr,
@@ -587,24 +666,27 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
    }
    fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
-        trace!("set_enabled {:x} {}", ep_addr, enabled);
+        trace!("set_enabled {:?} {}", ep_addr, enabled);
        // This can race, so do a retry loop.
-        let reg = T::regs().epr(ep_addr.index() as _);
+        let epr = T::regs().epr(ep_addr.index() as _);
-        trace!("EPR before: {:04x}", reg.read().0);
+        trace!("EPR before: {:04x}", epr.read().0);
        match ep_addr.direction() {
            Direction::In => {
                loop {
                    let want_stat = match enabled {
                        false => Stat::DISABLED,
-                        true => Stat::NAK,
+                        true => match epr.read().ep_type() {
+                            EpType::ISO => Stat::VALID,
+                            _ => Stat::NAK,
+                        },
                    };
-                    let r = reg.read();
+                    let r = epr.read();
                    if r.stat_tx() == want_stat {
                        break;
                    }
                    let mut w = invariant(r);
                    w.set_stat_tx(Stat::from_bits(r.stat_tx().to_bits() ^ want_stat.to_bits()));
-                    reg.write_value(w);
+                    epr.write_value(w);
                }
                EP_IN_WAKERS[ep_addr.index()].wake();
            }
@@ -614,18 +696,18 @@ impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
                        false => Stat::DISABLED,
                        true => Stat::VALID,
                    };
-                    let r = reg.read();
+                    let r = epr.read();
                    if r.stat_rx() == want_stat {
                        break;
                    }
                    let mut w = invariant(r);
                    w.set_stat_rx(Stat::from_bits(r.stat_rx().to_bits() ^ want_stat.to_bits()));
-                    reg.write_value(w);
+                    epr.write_value(w);
                }
                EP_OUT_WAKERS[ep_addr.index()].wake();
            }
        }
-        trace!("EPR after: {:04x}", reg.read().0);
+        trace!("EPR after: {:04x}", epr.read().0);
    }
    async fn enable(&mut self) {}
@@ -656,6 +738,19 @@ impl Dir for Out {
    }
 }
+/// Selects the packet buffer.
+///
+/// For double-buffered endpoints, both the `Rx` and `Tx` buffer from a channel are used for the same
+/// direction of transfer. This is opposed to single-buffered endpoints, where one channel can serve
+/// two directions at the same time.
+#[derive(Clone, Copy, Debug)]
+enum PacketBuffer {
+    /// The RX buffer - must be used for single-buffered OUT endpoints
+    Rx,
+    /// The TX buffer - must be used for single-buffered IN endpoints
+    Tx,
+}
 /// USB endpoint.
 pub struct Endpoint<'d, T: Instance, D> {
    _phantom: PhantomData<(&'d mut T, D)>,
@@ -664,15 +759,46 @@ pub struct Endpoint<'d, T: Instance, D> {
 }
 impl<'d, T: Instance, D> Endpoint<'d, T, D> {
-    fn write_data(&mut self, buf: &[u8]) {
+    /// Write to a double-buffered endpoint.
+    ///
+    /// For double-buffered endpoints, the data buffers overlap, but we still need to write to the right counter field.
+    /// The DTOG_TX bit indicates the buffer that is currently in use by the USB peripheral, that is, the buffer in
+    /// which the next transmit packet will be stored, so we need to write the counter of the OTHER buffer, which is
+    /// where the last transmitted packet was stored.
+    fn write_data_double_buffered(&mut self, buf: &[u8], packet_buffer: PacketBuffer) {
        let index = self.info.addr.index();
        self.buf.write(buf);
-        btable::write_in_len::<T>(index, self.buf.addr, buf.len() as _);
+        match packet_buffer {
+            PacketBuffer::Rx => btable::write_in_len_rx::<T>(index, self.buf.addr, buf.len() as _),
+            PacketBuffer::Tx => btable::write_in_len_tx::<T>(index, self.buf.addr, buf.len() as _),
+        }
    }
-    fn read_data(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
+    /// Write to a single-buffered endpoint.
+    fn write_data(&mut self, buf: &[u8]) {
+        self.write_data_double_buffered(buf, PacketBuffer::Tx);
+    }
+    /// Read from a double-buffered endpoint.
+    ///
+    /// For double-buffered endpoints, the data buffers overlap, but we still need to read from the right counter field.
+    /// The DTOG_RX bit indicates the buffer that is currently in use by the USB peripheral, that is, the buffer in
+    /// which the next received packet will be stored, so we need to read the counter of the OTHER buffer, which is
+    /// where the last received packet was stored.
+    fn read_data_double_buffered(
+        &mut self,
+        buf: &mut [u8],
+        packet_buffer: PacketBuffer,
+    ) -> Result<usize, EndpointError> {
        let index = self.info.addr.index();
-        let rx_len = btable::read_out_len::<T>(index) as usize & 0x3FF;
+        let rx_len = match packet_buffer {
+            PacketBuffer::Rx => btable::read_out_len_rx::<T>(index),
+            PacketBuffer::Tx => btable::read_out_len_tx::<T>(index),
+        } as usize
+            & 0x3FF;
        trace!("READ DONE, rx_len = {}", rx_len);
        if rx_len > buf.len() {
            return Err(EndpointError::BufferOverflow);
@@ -680,6 +806,11 @@ impl<'d, T: Instance, D> Endpoint<'d, T, D> {
        self.buf.read(&mut buf[..rx_len]);
        Ok(rx_len)
    }
+    /// Read from a single-buffered endpoint.
+    fn read_data(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
+        self.read_data_double_buffered(buf, PacketBuffer::Rx)
+    }
 }
 impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, In> {
@@ -734,29 +865,65 @@ impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
            EP_OUT_WAKERS[index].register(cx.waker());
            let regs = T::regs();
            let stat = regs.epr(index).read().stat_rx();
-            if matches!(stat, Stat::NAK | Stat::DISABLED) {
+            if self.info.ep_type == EndpointType::Isochronous {
-                Poll::Ready(stat)
+                // The isochronous endpoint does not change its `STAT_RX` field to `NAK` when receiving a packet.
+                // Therefore, this instead waits until the `CTR` interrupt was triggered.
+                if matches!(stat, Stat::DISABLED) || RX_COMPLETE[index].load(Ordering::Relaxed) {
+                    assert!(matches!(stat, Stat::VALID | Stat::DISABLED));
+                    Poll::Ready(stat)
+                } else {
+                    Poll::Pending
+                }
            } else {
-                Poll::Pending
+                if matches!(stat, Stat::NAK | Stat::DISABLED) {
+                    Poll::Ready(stat)
+                } else {
+                    Poll::Pending
+                }
            }
        })
        .await;
+        // Errata for STM32H5, 2.20.1:
+        // During OUT transfers, the correct transfer interrupt (CTR) is triggered a little before the last USB SRAM accesses
+        // have completed. If the software responds quickly to the interrupt, the full buffer contents may not be correct.
+        //
+        // Workaround:
+        // Software should ensure that a small delay is included before accessing the SRAM contents. This delay should be
+        // 800 ns in Full Speed mode and 6.4 μs in Low Speed mode.
+        #[cfg(stm32h5)]
+        embassy_time::block_for(embassy_time::Duration::from_nanos(800));
+        RX_COMPLETE[index].store(false, Ordering::Relaxed);
        if stat == Stat::DISABLED {
            return Err(EndpointError::Disabled);
        }
-        let rx_len = self.read_data(buf)?;
        let regs = T::regs();
-        regs.epr(index).write(|w| {
-            w.set_ep_type(convert_type(self.info.ep_type));
+        let rx_len = if self.info.ep_type == EndpointType::Isochronous {
-            w.set_ea(self.info.addr.index() as _);
+            // Find the buffer, which is currently in use. Read from the OTHER buffer.
-            w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
+            let packet_buffer = if regs.epr(index).read().dtog_rx() {
-            w.set_stat_tx(Stat::from_bits(0));
+                PacketBuffer::Tx
-            w.set_ctr_rx(true); // don't clear
+            } else {
-            w.set_ctr_tx(true); // don't clear
+                PacketBuffer::Rx
-        });
+            };
+            self.read_data_double_buffered(buf, packet_buffer)?
+        } else {
+            let len = self.read_data(buf)?;
+            regs.epr(index).write(|w| {
+                w.set_ep_type(convert_type(self.info.ep_type));
+                w.set_ea(self.info.addr.index() as _);
+                w.set_stat_rx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
+                w.set_stat_tx(Stat::from_bits(0));
+                w.set_ctr_rx(true); // don't clear
+                w.set_ctr_tx(true); // don't clear
+            });
+            len
+        };
        trace!("READ OK, rx_len = {}", rx_len);
        Ok(rx_len)
@@ -768,18 +935,41 @@ impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
        if buf.len() > self.info.max_packet_size as usize {
            return Err(EndpointError::BufferOverflow);
        }
+        trace!("WRITE WAITING, buf.len() = {}", buf.len());
+        let regs = T::regs();
        let index = self.info.addr.index();
-        trace!("WRITE WAITING");
+        if self.info.ep_type == EndpointType::Isochronous {
+            // Find the buffer, which is currently in use. Write to the OTHER buffer.
+            let packet_buffer = if regs.epr(index).read().dtog_tx() {
+                PacketBuffer::Rx
+            } else {
+                PacketBuffer::Tx
+            };
+            self.write_data_double_buffered(buf, packet_buffer);
+        }
        let stat = poll_fn(|cx| {
            EP_IN_WAKERS[index].register(cx.waker());
            let regs = T::regs();
            let stat = regs.epr(index).read().stat_tx();
-            if matches!(stat, Stat::NAK | Stat::DISABLED) {
+            if self.info.ep_type == EndpointType::Isochronous {
-                Poll::Ready(stat)
+                // The isochronous endpoint does not change its `STAT_TX` field to `NAK` after sending a packet.
+                // Therefore, this instead waits until the `CTR` interrupt was triggered.
+                if matches!(stat, Stat::DISABLED) || !TX_PENDING[index].load(Ordering::Relaxed) {
+                    assert!(matches!(stat, Stat::VALID | Stat::DISABLED));
+                    Poll::Ready(stat)
+                } else {
+                    Poll::Pending
+                }
            } else {
-                Poll::Pending
+                if matches!(stat, Stat::NAK | Stat::DISABLED) {
+                    Poll::Ready(stat)
+                } else {
+                    Poll::Pending
+                }
            }
        })
        .await;
@@ -788,18 +978,19 @@ impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
            return Err(EndpointError::Disabled);
        }
-        self.write_data(buf);
+        if self.info.ep_type != EndpointType::Isochronous {
+            self.write_data(buf);
-        let regs = T::regs();
-        regs.epr(index).write(|w| {
-            w.set_ep_type(convert_type(self.info.ep_type));
-            w.set_ea(self.info.addr.index() as _);
-            w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
-            w.set_stat_rx(Stat::from_bits(0));
-            w.set_ctr_rx(true); // don't clear
-            w.set_ctr_tx(true); // don't clear
-        });
+            regs.epr(index).write(|w| {
+                w.set_ep_type(convert_type(self.info.ep_type));
+                w.set_ea(self.info.addr.index() as _);
+                w.set_stat_tx(Stat::from_bits(Stat::NAK.to_bits() ^ Stat::VALID.to_bits()));
+                w.set_stat_rx(Stat::from_bits(0));
+                w.set_ctr_rx(true); // don't clear
+                w.set_ctr_tx(true); // don't clear
+            });
+        }
+        TX_PENDING[index].store(true, Ordering::Relaxed);
        trace!("WRITE OK");
        Ok(())
@@ -1044,7 +1235,7 @@ trait SealedInstance {
 /// USB instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance + RccPeripheral + 'static {
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + 'static {
    /// Interrupt for this USB instance.
    type Interrupt: interrupt::typelevel::Interrupt;
 }
@@ -1052,6 +1243,7 @@ pub trait Instance: SealedInstance + RccPeripheral + 'static {
 // Internal PHY pins
 pin_trait!(DpPin, Instance);
 pin_trait!(DmPin, Instance);
+pin_trait!(SofPin, Instance);
 foreach_interrupt!(
    ($inst:ident, usb, $block:ident, LP, $irq:ident) => {
diff --git a/embassy-stm32/src/wdg/mod.rs b/embassy-stm32/src/wdg/mod.rs
index ab21c4b6b..fb5c3d930 100644
--- a/embassy-stm32/src/wdg/mod.rs
+++ b/embassy-stm32/src/wdg/mod.rs
@@ -1,10 +1,11 @@
 //! Watchdog Timer (IWDG, WWDG)
 use core::marker::PhantomData;
-use embassy_hal_internal::{into_ref, Peripheral};
+use embassy_hal_internal::PeripheralType;
 use stm32_metapac::iwdg::vals::{Key, Pr};
 use crate::rcc::LSI_FREQ;
+use crate::Peri;
 /// Independent watchdog (IWDG) driver.
 pub struct IndependentWatchdog<'d, T: Instance> {
@@ -29,9 +30,7 @@ impl<'d, T: Instance> IndependentWatchdog<'d, T> {
    ///
    /// [Self] has to be started with [Self::unleash()].
    /// Once timer expires, MCU will be reset. To prevent this, timer must be reloaded by repeatedly calling [Self::pet()] within timeout interval.
-    pub fn new(_instance: impl Peripheral<P = T> + 'd, timeout_us: u32) -> Self {
+    pub fn new(_instance: Peri<'d, T>, timeout_us: u32) -> Self {
-        into_ref!(_instance);
        // Find lowest prescaler value, which makes watchdog period longer or equal to timeout.
        // This iterates from 4 (2^2) to 256 (2^8).
        let psc_power = unwrap!((2..=8).find(|psc_power| {
@@ -86,7 +85,7 @@ trait SealedInstance {
 /// IWDG instance trait.
 #[allow(private_bounds)]
-pub trait Instance: SealedInstance {}
+pub trait Instance: SealedInstance + PeripheralType {}
 foreach_peripheral!(
    (iwdg, $inst:ident) => {
diff --git a/embassy-stm32/src/xspi/enums.rs b/embassy-stm32/src/xspi/enums.rs
new file mode 100644
index 000000000..c96641180
--- /dev/null
+++ b/embassy-stm32/src/xspi/enums.rs
@@ -0,0 +1,364 @@
+//! Enums used in Xspi configuration.
+#[derive(Copy, Clone)]
+pub(crate) enum XspiMode {
+    IndirectWrite,
+    IndirectRead,
+    #[expect(dead_code)]
+    AutoPolling,
+    #[expect(dead_code)]
+    MemoryMapped,
+}
+impl Into<u8> for XspiMode {
+    fn into(self) -> u8 {
+        match self {
+            XspiMode::IndirectWrite => 0b00,
+            XspiMode::IndirectRead => 0b01,
+            XspiMode::AutoPolling => 0b10,
+            XspiMode::MemoryMapped => 0b11,
+        }
+    }
+}
+/// Xspi lane width
+#[derive(Copy, Clone)]
+pub enum XspiWidth {
+    /// None
+    NONE,
+    /// Single lane
+    SING,
+    /// Dual lanes
+    DUAL,
+    /// Quad lanes
+    QUAD,
+    /// Eight lanes
+    OCTO,
+}
+impl Into<u8> for XspiWidth {
+    fn into(self) -> u8 {
+        match self {
+            XspiWidth::NONE => 0b00,
+            XspiWidth::SING => 0b01,
+            XspiWidth::DUAL => 0b10,
+            XspiWidth::QUAD => 0b11,
+            XspiWidth::OCTO => 0b100,
+        }
+    }
+}
+/// Wrap Size
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum WrapSize {
+    None,
+    _16Bytes,
+    _32Bytes,
+    _64Bytes,
+    _128Bytes,
+}
+impl Into<u8> for WrapSize {
+    fn into(self) -> u8 {
+        match self {
+            WrapSize::None => 0x00,
+            WrapSize::_16Bytes => 0x02,
+            WrapSize::_32Bytes => 0x03,
+            WrapSize::_64Bytes => 0x04,
+            WrapSize::_128Bytes => 0x05,
+        }
+    }
+}
+/// Memory Type
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum MemoryType {
+    Micron,
+    Macronix,
+    Standard,
+    MacronixRam,
+    HyperBusMemory,
+    HyperBusRegister,
+}
+impl Into<u8> for MemoryType {
+    fn into(self) -> u8 {
+        match self {
+            MemoryType::Micron => 0x00,
+            MemoryType::Macronix => 0x01,
+            MemoryType::Standard => 0x02,
+            MemoryType::MacronixRam => 0x03,
+            MemoryType::HyperBusMemory => 0x04,
+            MemoryType::HyperBusRegister => 0x04,
+        }
+    }
+}
+/// Xspi memory size.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum MemorySize {
+    _1KiB,
+    _2KiB,
+    _4KiB,
+    _8KiB,
+    _16KiB,
+    _32KiB,
+    _64KiB,
+    _128KiB,
+    _256KiB,
+    _512KiB,
+    _1MiB,
+    _2MiB,
+    _4MiB,
+    _8MiB,
+    _16MiB,
+    _32MiB,
+    _64MiB,
+    _128MiB,
+    _256MiB,
+    _512MiB,
+    _1GiB,
+    _2GiB,
+    _4GiB,
+    Other(u8),
+}
+impl Into<u8> for MemorySize {
+    fn into(self) -> u8 {
+        match self {
+            MemorySize::_1KiB => 9,
+            MemorySize::_2KiB => 10,
+            MemorySize::_4KiB => 11,
+            MemorySize::_8KiB => 12,
+            MemorySize::_16KiB => 13,
+            MemorySize::_32KiB => 14,
+            MemorySize::_64KiB => 15,
+            MemorySize::_128KiB => 16,
+            MemorySize::_256KiB => 17,
+            MemorySize::_512KiB => 18,
+            MemorySize::_1MiB => 19,
+            MemorySize::_2MiB => 20,
+            MemorySize::_4MiB => 21,
+            MemorySize::_8MiB => 22,
+            MemorySize::_16MiB => 23,
+            MemorySize::_32MiB => 24,
+            MemorySize::_64MiB => 25,
+            MemorySize::_128MiB => 26,
+            MemorySize::_256MiB => 27,
+            MemorySize::_512MiB => 28,
+            MemorySize::_1GiB => 29,
+            MemorySize::_2GiB => 30,
+            MemorySize::_4GiB => 31,
+            MemorySize::Other(val) => val,
+        }
+    }
+}
+/// Xspi Address size
+#[derive(Copy, Clone)]
+pub enum AddressSize {
+    /// 8-bit address
+    _8bit,
+    /// 16-bit address
+    _16bit,
+    /// 24-bit address
+    _24bit,
+    /// 32-bit address
+    _32bit,
+}
+impl Into<u8> for AddressSize {
+    fn into(self) -> u8 {
+        match self {
+            AddressSize::_8bit => 0b00,
+            AddressSize::_16bit => 0b01,
+            AddressSize::_24bit => 0b10,
+            AddressSize::_32bit => 0b11,
+        }
+    }
+}
+/// Time the Chip Select line stays high.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum ChipSelectHighTime {
+    _1Cycle,
+    _2Cycle,
+    _3Cycle,
+    _4Cycle,
+    _5Cycle,
+    _6Cycle,
+    _7Cycle,
+    _8Cycle,
+}
+impl Into<u8> for ChipSelectHighTime {
+    fn into(self) -> u8 {
+        match self {
+            ChipSelectHighTime::_1Cycle => 0,
+            ChipSelectHighTime::_2Cycle => 1,
+            ChipSelectHighTime::_3Cycle => 2,
+            ChipSelectHighTime::_4Cycle => 3,
+            ChipSelectHighTime::_5Cycle => 4,
+            ChipSelectHighTime::_6Cycle => 5,
+            ChipSelectHighTime::_7Cycle => 6,
+            ChipSelectHighTime::_8Cycle => 7,
+        }
+    }
+}
+/// FIFO threshold.
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum FIFOThresholdLevel {
+    _1Bytes,
+    _2Bytes,
+    _3Bytes,
+    _4Bytes,
+    _5Bytes,
+    _6Bytes,
+    _7Bytes,
+    _8Bytes,
+    _9Bytes,
+    _10Bytes,
+    _11Bytes,
+    _12Bytes,
+    _13Bytes,
+    _14Bytes,
+    _15Bytes,
+    _16Bytes,
+    _17Bytes,
+    _18Bytes,
+    _19Bytes,
+    _20Bytes,
+    _21Bytes,
+    _22Bytes,
+    _23Bytes,
+    _24Bytes,
+    _25Bytes,
+    _26Bytes,
+    _27Bytes,
+    _28Bytes,
+    _29Bytes,
+    _30Bytes,
+    _31Bytes,
+    _32Bytes,
+}
+impl Into<u8> for FIFOThresholdLevel {
+    fn into(self) -> u8 {
+        match self {
+            FIFOThresholdLevel::_1Bytes => 0,
+            FIFOThresholdLevel::_2Bytes => 1,
+            FIFOThresholdLevel::_3Bytes => 2,
+            FIFOThresholdLevel::_4Bytes => 3,
+            FIFOThresholdLevel::_5Bytes => 4,
+            FIFOThresholdLevel::_6Bytes => 5,
+            FIFOThresholdLevel::_7Bytes => 6,
+            FIFOThresholdLevel::_8Bytes => 7,
+            FIFOThresholdLevel::_9Bytes => 8,
+            FIFOThresholdLevel::_10Bytes => 9,
+            FIFOThresholdLevel::_11Bytes => 10,
+            FIFOThresholdLevel::_12Bytes => 11,
+            FIFOThresholdLevel::_13Bytes => 12,
+            FIFOThresholdLevel::_14Bytes => 13,
+            FIFOThresholdLevel::_15Bytes => 14,
+            FIFOThresholdLevel::_16Bytes => 15,
+            FIFOThresholdLevel::_17Bytes => 16,
+            FIFOThresholdLevel::_18Bytes => 17,
+            FIFOThresholdLevel::_19Bytes => 18,
+            FIFOThresholdLevel::_20Bytes => 19,
+            FIFOThresholdLevel::_21Bytes => 20,
+            FIFOThresholdLevel::_22Bytes => 21,
+            FIFOThresholdLevel::_23Bytes => 22,
+            FIFOThresholdLevel::_24Bytes => 23,
+            FIFOThresholdLevel::_25Bytes => 24,
+            FIFOThresholdLevel::_26Bytes => 25,
+            FIFOThresholdLevel::_27Bytes => 26,
+            FIFOThresholdLevel::_28Bytes => 27,
+            FIFOThresholdLevel::_29Bytes => 28,
+            FIFOThresholdLevel::_30Bytes => 29,
+            FIFOThresholdLevel::_31Bytes => 30,
+            FIFOThresholdLevel::_32Bytes => 31,
+        }
+    }
+}
+/// Dummy cycle count
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum DummyCycles {
+    _0,
+    _1,
+    _2,
+    _3,
+    _4,
+    _5,
+    _6,
+    _7,
+    _8,
+    _9,
+    _10,
+    _11,
+    _12,
+    _13,
+    _14,
+    _15,
+    _16,
+    _17,
+    _18,
+    _19,
+    _20,
+    _21,
+    _22,
+    _23,
+    _24,
+    _25,
+    _26,
+    _27,
+    _28,
+    _29,
+    _30,
+    _31,
+}
+impl Into<u8> for DummyCycles {
+    fn into(self) -> u8 {
+        match self {
+            DummyCycles::_0 => 0,
+            DummyCycles::_1 => 1,
+            DummyCycles::_2 => 2,
+            DummyCycles::_3 => 3,
+            DummyCycles::_4 => 4,
+            DummyCycles::_5 => 5,
+            DummyCycles::_6 => 6,
+            DummyCycles::_7 => 7,
+            DummyCycles::_8 => 8,
+            DummyCycles::_9 => 9,
+            DummyCycles::_10 => 10,
+            DummyCycles::_11 => 11,
+            DummyCycles::_12 => 12,
+            DummyCycles::_13 => 13,
+            DummyCycles::_14 => 14,
+            DummyCycles::_15 => 15,
+            DummyCycles::_16 => 16,
+            DummyCycles::_17 => 17,
+            DummyCycles::_18 => 18,
+            DummyCycles::_19 => 19,
+            DummyCycles::_20 => 20,
+            DummyCycles::_21 => 21,
+            DummyCycles::_22 => 22,
+            DummyCycles::_23 => 23,
+            DummyCycles::_24 => 24,
+            DummyCycles::_25 => 25,
+            DummyCycles::_26 => 26,
+            DummyCycles::_27 => 27,
+            DummyCycles::_28 => 28,
+            DummyCycles::_29 => 29,
+            DummyCycles::_30 => 30,
+            DummyCycles::_31 => 31,
+        }
+    }
+}
diff --git a/embassy-stm32/src/xspi/mod.rs b/embassy-stm32/src/xspi/mod.rs
new file mode 100644
index 000000000..44c10b961
--- /dev/null
+++ b/embassy-stm32/src/xspi/mod.rs
@@ -0,0 +1,1425 @@
+//! XSPI Serial Peripheral Interface
+//!
+#![macro_use]
+pub mod enums;
+use core::marker::PhantomData;
+use embassy_embedded_hal::{GetConfig, SetConfig};
+use embassy_hal_internal::PeripheralType;
+pub use enums::*;
+use crate::dma::{word, ChannelAndRequest};
+use crate::gpio::{AfType, AnyPin, OutputType, Pull, SealedPin as _, Speed};
+use crate::mode::{Async, Blocking, Mode as PeriMode};
+use crate::pac::xspi::vals::*;
+use crate::pac::xspi::Xspi as Regs;
+#[cfg(xspim_v1)]
+use crate::pac::xspim::Xspim;
+use crate::rcc::{self, RccPeripheral};
+use crate::{peripherals, Peri};
+/// XPSI driver config.
+#[derive(Clone, Copy)]
+pub struct Config {
+    /// Fifo threshold used by the peripheral to generate the interrupt indicating data
+    /// or space is available in the FIFO
+    pub fifo_threshold: FIFOThresholdLevel,
+    /// Indicates the type of external device connected
+    pub memory_type: MemoryType, // Need to add an additional enum to provide this public interface
+    /// Defines the size of the external device connected to the XSPI corresponding
+    /// to the number of address bits required to access the device
+    pub device_size: MemorySize,
+    /// Sets the minimum number of clock cycles that the chip select signal must be held high
+    /// between commands
+    pub chip_select_high_time: ChipSelectHighTime,
+    /// Enables the free running clock
+    pub free_running_clock: bool,
+    /// Sets the clock level when the device is not selected
+    pub clock_mode: bool,
+    /// Indicates the wrap size corresponding to the external device configuration
+    pub wrap_size: WrapSize,
+    /// Specified the prescaler factor used for generating the external clock based
+    /// on the AHB clock. 0 = Fkernel, 1 = Fkernel/2, 2 = Fkernel/3 etc.
+    pub clock_prescaler: u8,
+    /// Allows the delay of 1/2 cycle the data sampling to account for external
+    /// signal delays
+    pub sample_shifting: bool,
+    /// Allows hold to 1/4 cycle the data
+    pub delay_hold_quarter_cycle: bool,
+    /// Enables the transaction boundary feature and defines the boundary to release
+    /// the chip select
+    pub chip_select_boundary: u8,
+    /// Enables communication regulation feature. Chip select is released when the other
+    /// XSpi requests access to the bus
+    pub max_transfer: u8,
+    /// Enables the refresh feature, chip select is released every refresh + 1 clock cycles
+    pub refresh: u32,
+}
+impl Default for Config {
+    fn default() -> Self {
+        Self {
+            fifo_threshold: FIFOThresholdLevel::_16Bytes, // 32 bytes FIFO, half capacity
+            memory_type: MemoryType::Micron,
+            device_size: MemorySize::Other(0),
+            chip_select_high_time: ChipSelectHighTime::_5Cycle,
+            free_running_clock: false,
+            clock_mode: false,
+            wrap_size: WrapSize::None,
+            clock_prescaler: 0,
+            sample_shifting: false,
+            delay_hold_quarter_cycle: false,
+            chip_select_boundary: 0, // Acceptable range 0 to 31
+            max_transfer: 0,
+            refresh: 0,
+        }
+    }
+}
+/// XSPI transfer configuration.
+pub struct TransferConfig {
+    /// Instruction width (IMODE)
+    pub iwidth: XspiWidth,
+    /// Instruction Id
+    pub instruction: Option<u32>,
+    /// Number of Instruction Bytes
+    pub isize: AddressSize,
+    /// Instruction Double Transfer rate enable
+    pub idtr: bool,
+    /// Address width (ADMODE)
+    pub adwidth: XspiWidth,
+    /// Device memory address
+    pub address: Option<u32>,
+    /// Number of Address Bytes
+    pub adsize: AddressSize,
+    /// Address Double Transfer rate enable
+    pub addtr: bool,
+    /// Alternate bytes width (ABMODE)
+    pub abwidth: XspiWidth,
+    /// Alternate Bytes
+    pub alternate_bytes: Option<u32>,
+    /// Number of Alternate Bytes
+    pub absize: AddressSize,
+    /// Alternate Bytes Double Transfer rate enable
+    pub abdtr: bool,
+    /// Data width (DMODE)
+    pub dwidth: XspiWidth,
+    /// Data buffer
+    pub ddtr: bool,
+    /// Number of dummy cycles (DCYC)
+    pub dummy: DummyCycles,
+}
+impl Default for TransferConfig {
+    fn default() -> Self {
+        Self {
+            iwidth: XspiWidth::NONE,
+            instruction: None,
+            isize: AddressSize::_8bit,
+            idtr: false,
+            adwidth: XspiWidth::NONE,
+            address: None,
+            adsize: AddressSize::_8bit,
+            addtr: false,
+            abwidth: XspiWidth::NONE,
+            alternate_bytes: None,
+            absize: AddressSize::_8bit,
+            abdtr: false,
+            dwidth: XspiWidth::NONE,
+            ddtr: false,
+            dummy: DummyCycles::_0,
+        }
+    }
+}
+/// Error used for Xspi implementation
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum XspiError {
+    /// Peripheral configuration is invalid
+    InvalidConfiguration,
+    /// Operation configuration is invalid
+    InvalidCommand,
+    /// Size zero buffer passed to instruction
+    EmptyBuffer,
+}
+/// XSPI driver.
+pub struct Xspi<'d, T: Instance, M: PeriMode> {
+    _peri: Peri<'d, T>,
+    clk: Option<Peri<'d, AnyPin>>,
+    d0: Option<Peri<'d, AnyPin>>,
+    d1: Option<Peri<'d, AnyPin>>,
+    d2: Option<Peri<'d, AnyPin>>,
+    d3: Option<Peri<'d, AnyPin>>,
+    d4: Option<Peri<'d, AnyPin>>,
+    d5: Option<Peri<'d, AnyPin>>,
+    d6: Option<Peri<'d, AnyPin>>,
+    d7: Option<Peri<'d, AnyPin>>,
+    d8: Option<Peri<'d, AnyPin>>,
+    d9: Option<Peri<'d, AnyPin>>,
+    d10: Option<Peri<'d, AnyPin>>,
+    d11: Option<Peri<'d, AnyPin>>,
+    d12: Option<Peri<'d, AnyPin>>,
+    d13: Option<Peri<'d, AnyPin>>,
+    d14: Option<Peri<'d, AnyPin>>,
+    d15: Option<Peri<'d, AnyPin>>,
+    ncs: Option<Peri<'d, AnyPin>>,
+    // TODO: allow switching between multiple chips
+    ncs_alt: Option<Peri<'d, AnyPin>>,
+    // false if ncs == NCS1, true if ncs == NCS2
+    // (ncs_alt will be the opposite to ncs).
+    _cssel_swap: bool,
+    dqs0: Option<Peri<'d, AnyPin>>,
+    dqs1: Option<Peri<'d, AnyPin>>,
+    dma: Option<ChannelAndRequest<'d>>,
+    _phantom: PhantomData<M>,
+    config: Config,
+    width: XspiWidth,
+}
+impl<'d, T: Instance, M: PeriMode> Xspi<'d, T, M> {
+    /// Enter memory mode.
+    /// The Input `read_config` is used to configure the read operation in memory mode
+    pub fn enable_memory_mapped_mode(
+        &mut self,
+        read_config: TransferConfig,
+        write_config: TransferConfig,
+    ) -> Result<(), XspiError> {
+        // Use configure command to set read config
+        self.configure_command(&read_config, None)?;
+        let reg = T::REGS;
+        while reg.sr().read().busy() {}
+        reg.ccr().modify(|r| {
+            r.set_dqse(false);
+        });
+        // Set wrting configurations, there are separate registers for write configurations in memory mapped mode
+        reg.wccr().modify(|w| {
+            w.set_imode(WccrImode::from_bits(write_config.iwidth.into()));
+            w.set_idtr(write_config.idtr);
+            w.set_isize(WccrIsize::from_bits(write_config.isize.into()));
+            w.set_admode(WccrAdmode::from_bits(write_config.adwidth.into()));
+            w.set_addtr(write_config.addtr);
+            w.set_adsize(WccrAdsize::from_bits(write_config.adsize.into()));
+            w.set_dmode(WccrDmode::from_bits(write_config.dwidth.into()));
+            w.set_ddtr(write_config.ddtr);
+            w.set_abmode(WccrAbmode::from_bits(write_config.abwidth.into()));
+            w.set_dqse(true);
+        });
+        reg.wtcr().modify(|w| w.set_dcyc(write_config.dummy.into()));
+        // Enable memory mapped mode
+        reg.cr().modify(|r| {
+            r.set_fmode(Fmode::B_0X3);
+            r.set_tcen(false);
+        });
+        Ok(())
+    }
+    /// Quit from memory mapped mode
+    pub fn disable_memory_mapped_mode(&mut self) {
+        let reg = T::REGS;
+        reg.cr().modify(|r| {
+            r.set_fmode(Fmode::B_0X0);
+            r.set_abort(true);
+            r.set_dmaen(false);
+            r.set_en(false);
+        });
+        // Clear transfer complete flag
+        reg.fcr().write(|w| w.set_ctcf(true));
+        // Re-enable ospi
+        reg.cr().modify(|r| {
+            r.set_en(true);
+        });
+    }
+    fn new_inner(
+        peri: Peri<'d, T>,
+        d0: Option<Peri<'d, AnyPin>>,
+        d1: Option<Peri<'d, AnyPin>>,
+        d2: Option<Peri<'d, AnyPin>>,
+        d3: Option<Peri<'d, AnyPin>>,
+        d4: Option<Peri<'d, AnyPin>>,
+        d5: Option<Peri<'d, AnyPin>>,
+        d6: Option<Peri<'d, AnyPin>>,
+        d7: Option<Peri<'d, AnyPin>>,
+        d8: Option<Peri<'d, AnyPin>>,
+        d9: Option<Peri<'d, AnyPin>>,
+        d10: Option<Peri<'d, AnyPin>>,
+        d11: Option<Peri<'d, AnyPin>>,
+        d12: Option<Peri<'d, AnyPin>>,
+        d13: Option<Peri<'d, AnyPin>>,
+        d14: Option<Peri<'d, AnyPin>>,
+        d15: Option<Peri<'d, AnyPin>>,
+        clk: Option<Peri<'d, AnyPin>>,
+        ncs_cssel: u8,
+        ncs: Option<Peri<'d, AnyPin>>,
+        ncs_alt: Option<Peri<'d, AnyPin>>,
+        dqs0: Option<Peri<'d, AnyPin>>,
+        dqs1: Option<Peri<'d, AnyPin>>,
+        dma: Option<ChannelAndRequest<'d>>,
+        config: Config,
+        width: XspiWidth,
+        dual_quad: bool,
+    ) -> Self {
+        // Enable the interface
+        match T::SPI_IDX {
+            1 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim1(true)),
+            2 => crate::pac::PWR.csr2().modify(|r| r.set_en_xspim2(true)),
+            _ => unreachable!(),
+        };
+        #[cfg(xspim_v1)]
+        {
+            // RCC for xspim should be enabled before writing register
+            crate::pac::RCC.ahb5enr().modify(|w| w.set_iomngren(true));
+            // Disable XSPI peripheral first
+            T::REGS.cr().modify(|w| {
+                w.set_en(false);
+            });
+            // XSPI IO Manager has been enabled before
+            T::SPIM_REGS.cr().modify(|w| {
+                w.set_muxen(false);
+                w.set_req2ack_time(0xff);
+            });
+        }
+        // System configuration
+        rcc::enable_and_reset::<T>();
+        while T::REGS.sr().read().busy() {}
+        // Device configuration
+        T::REGS.dcr1().modify(|w| {
+            w.set_devsize(config.device_size.into());
+            w.set_mtyp(Mtyp::from_bits(config.memory_type.into()));
+            w.set_csht(Csht::from_bits(config.chip_select_high_time.into()));
+            w.set_frck(false);
+            w.set_ckmode(Ckmode::from_bits(config.clock_mode.into()));
+        });
+        T::REGS.dcr2().modify(|w| {
+            w.set_wrapsize(Wrapsize::from_bits(config.wrap_size.into()));
+        });
+        T::REGS.dcr3().modify(|w| {
+            w.set_csbound(Csbound::from_bits(config.chip_select_boundary.into()));
+            #[cfg(xspi_v1)]
+            {
+                w.set_maxtran(Maxtran::from_bits(config.max_transfer.into()));
+            }
+        });
+        T::REGS.dcr4().modify(|w| {
+            w.set_refresh(Refresh::from_bits(config.refresh.into()));
+        });
+        T::REGS.cr().modify(|w| {
+            w.set_fthres(Fthres::from_bits(config.fifo_threshold.into()));
+        });
+        // Wait for busy flag to clear
+        while T::REGS.sr().read().busy() {}
+        T::REGS.dcr2().modify(|w| {
+            w.set_prescaler(config.clock_prescaler);
+        });
+        // Wait for busy flag to clear after changing prescaler, during calibration
+        while T::REGS.sr().read().busy() {}
+        T::REGS.cr().modify(|w| {
+            w.set_dmm(dual_quad);
+            assert!(ncs_alt.is_none(), "ncs_alt TODO");
+            let cssel = if ncs_cssel == 0 { Cssel::B_0X0 } else { Cssel::B_0X1 };
+            w.set_cssel(cssel);
+        });
+        T::REGS.tcr().modify(|w| {
+            w.set_sshift(config.sample_shifting);
+            w.set_dhqc(config.delay_hold_quarter_cycle);
+        });
+        // Enable peripheral
+        T::REGS.cr().modify(|w| {
+            w.set_en(true);
+        });
+        // Free running clock needs to be set after peripheral enable
+        if config.free_running_clock {
+            T::REGS.dcr1().modify(|w| {
+                w.set_frck(config.free_running_clock);
+            });
+        }
+        Self {
+            _peri: peri,
+            clk,
+            d0,
+            d1,
+            d2,
+            d3,
+            d4,
+            d5,
+            d6,
+            d7,
+            d8,
+            d9,
+            d10,
+            d11,
+            d12,
+            d13,
+            d14,
+            d15,
+            ncs,
+            ncs_alt,
+            _cssel_swap: ncs_cssel == 1,
+            dqs0,
+            dqs1,
+            dma,
+            _phantom: PhantomData,
+            config,
+            width,
+        }
+    }
+    // Function to configure the peripheral for the requested command
+    fn configure_command(&mut self, command: &TransferConfig, data_len: Option<usize>) -> Result<(), XspiError> {
+        // Check that transaction doesn't use more than hardware initialized pins
+        if <enums::XspiWidth as Into<u8>>::into(command.iwidth) > <enums::XspiWidth as Into<u8>>::into(self.width)
+            || <enums::XspiWidth as Into<u8>>::into(command.adwidth) > <enums::XspiWidth as Into<u8>>::into(self.width)
+            || <enums::XspiWidth as Into<u8>>::into(command.abwidth) > <enums::XspiWidth as Into<u8>>::into(self.width)
+            || <enums::XspiWidth as Into<u8>>::into(command.dwidth) > <enums::XspiWidth as Into<u8>>::into(self.width)
+        {
+            return Err(XspiError::InvalidCommand);
+        }
+        T::REGS.cr().modify(|w| {
+            w.set_fmode(0.into());
+        });
+        // Configure alternate bytes
+        if let Some(ab) = command.alternate_bytes {
+            T::REGS.abr().write(|v| v.set_alternate(ab));
+            T::REGS.ccr().modify(|w| {
+                w.set_abmode(CcrAbmode::from_bits(command.abwidth.into()));
+                w.set_abdtr(command.abdtr);
+                w.set_absize(CcrAbsize::from_bits(command.absize.into()));
+            })
+        }
+        // Configure dummy cycles
+        T::REGS.tcr().modify(|w| {
+            w.set_dcyc(command.dummy.into());
+        });
+        // Configure data
+        if let Some(data_length) = data_len {
+            T::REGS.dlr().write(|v| {
+                v.set_dl((data_length - 1) as u32);
+            })
+        } else {
+            T::REGS.dlr().write(|v| {
+                v.set_dl((0) as u32);
+            })
+        }
+        // Configure instruction/address/data modes
+        T::REGS.ccr().modify(|w| {
+            w.set_imode(CcrImode::from_bits(command.iwidth.into()));
+            w.set_idtr(command.idtr);
+            w.set_isize(CcrIsize::from_bits(command.isize.into()));
+            w.set_admode(CcrAdmode::from_bits(command.adwidth.into()));
+            w.set_addtr(command.addtr);
+            w.set_adsize(CcrAdsize::from_bits(command.adsize.into()));
+            w.set_dmode(CcrDmode::from_bits(command.dwidth.into()));
+            w.set_ddtr(command.ddtr);
+        });
+        // Set information required to initiate transaction
+        if let Some(instruction) = command.instruction {
+            if let Some(address) = command.address {
+                T::REGS.ir().write(|v| {
+                    v.set_instruction(instruction);
+                });
+                T::REGS.ar().write(|v| {
+                    v.set_address(address);
+                });
+            } else {
+                // Double check requirements for delay hold and sample shifting
+                // if let None = command.data_len {
+                //     if self.config.delay_hold_quarter_cycle && command.idtr {
+                //         T::REGS.ccr().modify(|w| {
+                //             w.set_ddtr(true);
+                //         });
+                //     }
+                // }
+                // warn!("instruction: {:#x}", instruction);
+                T::REGS.ir().write(|v| {
+                    v.set_instruction(instruction);
+                });
+            }
+        } else {
+            if let Some(address) = command.address {
+                T::REGS.ar().write(|v| {
+                    v.set_address(address);
+                });
+            } else {
+                // The only single phase transaction supported is instruction only
+                return Err(XspiError::InvalidCommand);
+            }
+        }
+        Ok(())
+    }
+    /// Function used to control or configure the target device without data transfer
+    pub fn blocking_command(&mut self, command: &TransferConfig) -> Result<(), XspiError> {
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        // Need additional validation that command configuration doesn't have data set
+        self.configure_command(command, None)?;
+        // Transaction initiated by setting final configuration, i.e the instruction register
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|w| {
+            w.set_ctcf(true);
+        });
+        Ok(())
+    }
+    /// Blocking read with byte by byte data transfer
+    pub fn blocking_read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        // Ensure DMA is not enabled for this transaction
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        // self.configure_command(&transaction, Some(buf.len()))?;
+        self.configure_command(&transaction, Some(buf.len())).unwrap();
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectRead.into())));
+        if T::REGS.ccr().read().admode() == CcrAdmode::B_0X0 {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        for idx in 0..buf.len() {
+            while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
+            buf[idx] = unsafe { (T::REGS.dr().as_ptr() as *mut W).read_volatile() };
+        }
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|v| v.set_ctcf(true));
+        Ok(())
+    }
+    /// Blocking write with byte by byte data transfer
+    pub fn blocking_write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
+        for idx in 0..buf.len() {
+            while !T::REGS.sr().read().ftf() {}
+            unsafe { (T::REGS.dr().as_ptr() as *mut W).write_volatile(buf[idx]) };
+        }
+        while !T::REGS.sr().read().tcf() {}
+        T::REGS.fcr().write(|v| v.set_ctcf(true));
+        Ok(())
+    }
+    /// Set new bus configuration
+    pub fn set_config(&mut self, config: &Config) {
+        // Wait for busy flag to clear
+        while T::REGS.sr().read().busy() {}
+        // Disable DMA channel while configuring the peripheral
+        T::REGS.cr().modify(|w| {
+            w.set_dmaen(false);
+        });
+        // Device configuration
+        T::REGS.dcr1().modify(|w| {
+            w.set_devsize(config.device_size.into());
+            w.set_mtyp(Mtyp::from_bits(config.memory_type.into()));
+            w.set_csht(Csht::from_bits(config.chip_select_high_time.into()));
+            w.set_frck(false);
+            w.set_ckmode(match config.clock_mode {
+                true => Ckmode::B_0X1,
+                false => Ckmode::B_0X0,
+            });
+        });
+        T::REGS.dcr2().modify(|w| {
+            w.set_wrapsize(Wrapsize::from_bits(config.wrap_size.into()));
+        });
+        T::REGS.dcr3().modify(|w| {
+            w.set_csbound(Csbound::from_bits(config.chip_select_boundary.into()));
+            #[cfg(xspi_v1)]
+            {
+                w.set_maxtran(Maxtran::from_bits(config.max_transfer.into()));
+            }
+        });
+        T::REGS.dcr4().modify(|w| {
+            w.set_refresh(Refresh::from_bits(config.refresh.into()));
+        });
+        T::REGS.cr().modify(|w| {
+            w.set_fthres(Fthres::from_bits(config.fifo_threshold.into()));
+        });
+        // Wait for busy flag to clear
+        while T::REGS.sr().read().busy() {}
+        T::REGS.dcr2().modify(|w| {
+            w.set_prescaler(config.clock_prescaler);
+        });
+        T::REGS.tcr().modify(|w| {
+            w.set_sshift(config.sample_shifting);
+            w.set_dhqc(config.delay_hold_quarter_cycle);
+        });
+        // Enable peripheral
+        T::REGS.cr().modify(|w| {
+            w.set_en(true);
+        });
+        // Free running clock needs to be set after peripheral enable
+        if config.free_running_clock {
+            T::REGS.dcr1().modify(|w| {
+                w.set_frck(config.free_running_clock);
+            });
+        }
+        self.config = *config;
+    }
+    /// Get current configuration
+    pub fn get_config(&self) -> Config {
+        self.config
+    }
+}
+impl<'d, T: Instance> Xspi<'d, T, Blocking> {
+    /// Create new blocking XSPI driver for a single spi external chip
+    pub fn new_blocking_singlespi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::input(Pull::None)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            None,
+            config,
+            XspiWidth::SING,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for a dualspi external chip
+    pub fn new_blocking_dualspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            None,
+            config,
+            XspiWidth::DUAL,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for a quadspi external chip
+    pub fn new_blocking_quadspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            None,
+            config,
+            XspiWidth::QUAD,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for two quadspi external chips
+    pub fn new_blocking_dualquadspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            None,
+            config,
+            XspiWidth::QUAD,
+            true,
+        )
+    }
+    /// Create new blocking XSPI driver for xspi external chips
+    pub fn new_blocking_xspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            None,
+            config,
+            XspiWidth::OCTO,
+            false,
+        )
+    }
+}
+impl<'d, T: Instance> Xspi<'d, T, Async> {
+    /// Create new blocking XSPI driver for a single spi external chip
+    pub fn new_singlespi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        dma: Peri<'d, impl XDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::input(Pull::None)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            XspiWidth::SING,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for a dualspi external chip
+    pub fn new_dualspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        dma: Peri<'d, impl XDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            XspiWidth::DUAL,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for a quadspi external chip
+    pub fn new_quadspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        dma: Peri<'d, impl XDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            XspiWidth::QUAD,
+            false,
+        )
+    }
+    /// Create new blocking XSPI driver for two quadspi external chips
+    pub fn new_dualquadspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        dma: Peri<'d, impl XDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            XspiWidth::QUAD,
+            true,
+        )
+    }
+    /// Create new blocking XSPI driver for xspi external chips
+    pub fn new_xspi(
+        peri: Peri<'d, T>,
+        clk: Peri<'d, impl CLKPin<T>>,
+        d0: Peri<'d, impl D0Pin<T>>,
+        d1: Peri<'d, impl D1Pin<T>>,
+        d2: Peri<'d, impl D2Pin<T>>,
+        d3: Peri<'d, impl D3Pin<T>>,
+        d4: Peri<'d, impl D4Pin<T>>,
+        d5: Peri<'d, impl D5Pin<T>>,
+        d6: Peri<'d, impl D6Pin<T>>,
+        d7: Peri<'d, impl D7Pin<T>>,
+        ncs: Peri<'d, impl NCSEither<T>>,
+        dma: Peri<'d, impl XDma<T>>,
+        config: Config,
+    ) -> Self {
+        Self::new_inner(
+            peri,
+            new_pin!(d0, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d1, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d2, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d3, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d4, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d5, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d6, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            new_pin!(d7, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            None,
+            new_pin!(clk, AfType::output(OutputType::PushPull, Speed::VeryHigh)),
+            ncs.sel(),
+            new_pin!(
+                ncs,
+                AfType::output_pull(OutputType::PushPull, Speed::VeryHigh, Pull::Up)
+            ),
+            None,
+            None,
+            None,
+            new_dma!(dma),
+            config,
+            XspiWidth::OCTO,
+            false,
+        )
+    }
+    /// Blocking read with DMA transfer
+    pub fn blocking_read_dma<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectRead.into())));
+        if T::REGS.ccr().read().admode() == CcrAdmode::B_0X0 {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.blocking_wait();
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Blocking write with DMA transfer
+    pub fn blocking_write_dma<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.blocking_wait();
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Asynchronous read from external device
+    pub async fn read<W: Word>(&mut self, buf: &mut [W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        let current_address = T::REGS.ar().read().address();
+        let current_instruction = T::REGS.ir().read().instruction();
+        // For a indirect read transaction, the transaction begins when the instruction/address is set
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectRead.into())));
+        if T::REGS.ccr().read().admode() == CcrAdmode::B_0X0 {
+            T::REGS.ir().write(|v| v.set_instruction(current_instruction));
+        } else {
+            T::REGS.ar().write(|v| v.set_address(current_address));
+        }
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .read(T::REGS.dr().as_ptr() as *mut W, buf, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.await;
+        finish_dma(T::REGS);
+        Ok(())
+    }
+    /// Asynchronous write to external device
+    pub async fn write<W: Word>(&mut self, buf: &[W], transaction: TransferConfig) -> Result<(), XspiError> {
+        if buf.is_empty() {
+            return Err(XspiError::EmptyBuffer);
+        }
+        // Wait for peripheral to be free
+        while T::REGS.sr().read().busy() {}
+        self.configure_command(&transaction, Some(buf.len()))?;
+        T::REGS
+            .cr()
+            .modify(|v| v.set_fmode(Fmode::from_bits(XspiMode::IndirectWrite.into())));
+        let transfer = unsafe {
+            self.dma
+                .as_mut()
+                .unwrap()
+                .write(buf, T::REGS.dr().as_ptr() as *mut W, Default::default())
+        };
+        T::REGS.cr().modify(|w| w.set_dmaen(true));
+        transfer.await;
+        finish_dma(T::REGS);
+        Ok(())
+    }
+}
+impl<'d, T: Instance, M: PeriMode> Drop for Xspi<'d, T, M> {
+    fn drop(&mut self) {
+        self.clk.as_ref().map(|x| x.set_as_disconnected());
+        self.d0.as_ref().map(|x| x.set_as_disconnected());
+        self.d1.as_ref().map(|x| x.set_as_disconnected());
+        self.d2.as_ref().map(|x| x.set_as_disconnected());
+        self.d3.as_ref().map(|x| x.set_as_disconnected());
+        self.d4.as_ref().map(|x| x.set_as_disconnected());
+        self.d5.as_ref().map(|x| x.set_as_disconnected());
+        self.d6.as_ref().map(|x| x.set_as_disconnected());
+        self.d7.as_ref().map(|x| x.set_as_disconnected());
+        self.d8.as_ref().map(|x| x.set_as_disconnected());
+        self.d9.as_ref().map(|x| x.set_as_disconnected());
+        self.d10.as_ref().map(|x| x.set_as_disconnected());
+        self.d11.as_ref().map(|x| x.set_as_disconnected());
+        self.d12.as_ref().map(|x| x.set_as_disconnected());
+        self.d13.as_ref().map(|x| x.set_as_disconnected());
+        self.d14.as_ref().map(|x| x.set_as_disconnected());
+        self.d15.as_ref().map(|x| x.set_as_disconnected());
+        self.ncs.as_ref().map(|x| x.set_as_disconnected());
+        self.ncs_alt.as_ref().map(|x| x.set_as_disconnected());
+        self.dqs0.as_ref().map(|x| x.set_as_disconnected());
+        self.dqs1.as_ref().map(|x| x.set_as_disconnected());
+        rcc::disable::<T>();
+    }
+}
+fn finish_dma(regs: Regs) {
+    while !regs.sr().read().tcf() {}
+    regs.fcr().write(|v| v.set_ctcf(true));
+    regs.cr().modify(|w| {
+        w.set_dmaen(false);
+    });
+}
+/// XSPI I/O manager instance trait.
+#[cfg(xspim_v1)]
+pub(crate) trait SealedXspimInstance {
+    const SPIM_REGS: Xspim;
+    const SPI_IDX: u8;
+}
+/// XSPI instance trait.
+pub(crate) trait SealedInstance {
+    const REGS: Regs;
+}
+/// XSPI instance trait.
+#[cfg(xspim_v1)]
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral + SealedXspimInstance {}
+/// XSPI instance trait.
+#[cfg(not(xspim_v1))]
+#[allow(private_bounds)]
+pub trait Instance: SealedInstance + PeripheralType + RccPeripheral {}
+pin_trait!(D0Pin, Instance);
+pin_trait!(D1Pin, Instance);
+pin_trait!(D2Pin, Instance);
+pin_trait!(D3Pin, Instance);
+pin_trait!(D4Pin, Instance);
+pin_trait!(D5Pin, Instance);
+pin_trait!(D6Pin, Instance);
+pin_trait!(D7Pin, Instance);
+pin_trait!(D8Pin, Instance);
+pin_trait!(D9Pin, Instance);
+pin_trait!(D10Pin, Instance);
+pin_trait!(D11Pin, Instance);
+pin_trait!(D12Pin, Instance);
+pin_trait!(D13Pin, Instance);
+pin_trait!(D14Pin, Instance);
+pin_trait!(D15Pin, Instance);
+pin_trait!(DQS0Pin, Instance);
+pin_trait!(DQS1Pin, Instance);
+pin_trait!(NCSPin, Instance);
+pin_trait!(CLKPin, Instance);
+pin_trait!(NCLKPin, Instance);
+dma_trait!(XDma, Instance);
+/// Trait for either NCS1 or NCS2 pins
+pub trait NCSEither<T: Instance>: NCSPin<T> {
+    /// Get the CSSEL for this NCS pin
+    fn sel(&self) -> u8;
+}
+// Hard-coded the xspi index, for SPIM
+#[cfg(xspim_v1)]
+impl SealedXspimInstance for peripherals::XSPI1 {
+    const SPIM_REGS: Xspim = crate::pac::XSPIM;
+    const SPI_IDX: u8 = 1;
+}
+// Some cubedb files are missing XSPI2, for example STM32H7R3Z8
+#[cfg(all(xspim_v1, peri_xspi2))]
+impl SealedXspimInstance for peripherals::XSPI2 {
+    const SPIM_REGS: Xspim = crate::pac::XSPIM;
+    const SPI_IDX: u8 = 2;
+}
+#[cfg(xspim_v1)]
+foreach_peripheral!(
+    (xspi, $inst:ident) => {
+        impl SealedInstance for peripherals::$inst {
+            const REGS: Regs = crate::pac::$inst;
+        }
+        impl Instance for peripherals::$inst {}
+    };
+);
+#[cfg(not(xspim_v1))]
+foreach_peripheral!(
+    (xspi, $inst:ident) => {
+        impl SealedInstance for peripherals::$inst {
+            const REGS: Regs = crate::pac::$inst;
+        }
+        impl Instance for peripherals::$inst {}
+    };
+);
+impl<'d, T: Instance, M: PeriMode> SetConfig for Xspi<'d, T, M> {
+    type Config = Config;
+    type ConfigError = ();
+    fn set_config(&mut self, config: &Self::Config) -> Result<(), ()> {
+        self.set_config(config);
+        Ok(())
+    }
+}
+impl<'d, T: Instance, M: PeriMode> GetConfig for Xspi<'d, T, M> {
+    type Config = Config;
+    fn get_config(&self) -> Self::Config {
+        self.get_config()
+    }
+}
+/// Word sizes usable for XSPI.
+#[allow(private_bounds)]
+pub trait Word: word::Word {}
+macro_rules! impl_word {
+    ($T:ty) => {
+        impl Word for $T {}
+    };
+}
+impl_word!(u8);
+impl_word!(u16);
+impl_word!(u32);
author	jrmoulton <[email protected]>	2025-06-10 15:47:54 -0600
committer	jrmoulton <[email protected]>	2025-06-10 15:48:36 -0600
commit	cfad9798ff99d4de0571a512d156b5fe1ef1d427 (patch)
tree	fc3bf670f82d139de19466cddad1e909db7f3d2e /embassy-stm32
parent	fc342915e6155dec7bafa3e135da7f37a9a07f5c (diff)
parent	6186d111a5c150946ee5b7e9e68d987a38c1a463 (diff)