stm32/rcc: rename HSE32 to HSE

2 files changed, 8 insertions, 8 deletions

diff --git a/embassy-stm32/src/rcc/wba.rs b/embassy-stm32/src/rcc/wba.rs
index 9ade369f5..d79b3063e 100644
--- a/embassy-stm32/src/rcc/wba.rs
+++ b/embassy-stm32/src/rcc/wba.rs
@@ -28,7 +28,7 @@ pub enum PllSrc {
 impl Into<Pllsrc> for PllSrc {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::HSE(..) => Pllsrc::HSE32,
+            PllSrc::HSE(..) => Pllsrc::HSE,
             PllSrc::HSI16 => Pllsrc::HSI16,
         }
     }
@@ -37,7 +37,7 @@ impl Into<Pllsrc> for PllSrc {
 impl Into<Sw> for ClockSrc {
     fn into(self) -> Sw {
         match self {
-            ClockSrc::HSE(..) => Sw::HSE32,
+            ClockSrc::HSE(..) => Sw::HSE,
             ClockSrc::HSI16 => Sw::HSI16,
         }
     }
diff --git a/embassy-stm32/src/rcc/wl.rs b/embassy-stm32/src/rcc/wl.rs
index f12588a59..4c3fe5051 100644
--- a/embassy-stm32/src/rcc/wl.rs
+++ b/embassy-stm32/src/rcc/wl.rs
@@ -15,14 +15,14 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
 /// LSI speed
 pub const LSI_FREQ: Hertz = Hertz(32_000);
 
-/// HSE32 speed
-pub const HSE32_FREQ: Hertz = Hertz(32_000_000);
+/// HSE speed
+pub const HSE_FREQ: Hertz = Hertz(32_000_000);
 
 /// System clock mux source
 #[derive(Clone, Copy)]
 pub enum ClockSrc {
     MSI(MSIRange),
-    HSE32,
+    HSE,
     HSI16,
 }
 
@@ -59,7 +59,7 @@ impl Default for Config {
 pub(crate) unsafe fn init(config: Config) {
     let (sys_clk, sw, vos) = match config.mux {
         ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI16, VoltageScale::RANGE2),
-        ClockSrc::HSE32 => (HSE32_FREQ, Sw::HSE32, VoltageScale::RANGE1),
+        ClockSrc::HSE => (HSE_FREQ, Sw::HSE, VoltageScale::RANGE1),
         ClockSrc::MSI(range) => (msirange_to_hertz(range), Sw::MSI, msirange_to_vos(range)),
     };
 
@@ -113,8 +113,8 @@ pub(crate) unsafe fn init(config: Config) {
             RCC.cr().write(|w| w.set_hsion(true));
             while !RCC.cr().read().hsirdy() {}
         }
-        ClockSrc::HSE32 => {
-            // Enable HSE32
+        ClockSrc::HSE => {
+            // Enable HSE
             RCC.cr().write(|w| {
                 w.set_hsebyppwr(true);
                 w.set_hseon(true);