diff options
| author | everdrone <[email protected]> | 2025-09-21 14:50:54 +0200 |
|---|---|---|
| committer | everdrone <[email protected]> | 2025-09-21 14:50:54 +0200 |
| commit | e6e42001a65e2c77cdb6995b7f689fbb4d10d045 (patch) | |
| tree | ca2fba4573e100df13392cd6b3d58e5bc1d37d38 /embassy-stm32 | |
| parent | 5f4a411978b97fbb55475eb7dafafdedb452eb6a (diff) | |
Use N6 registers for MCOxSEL and MCOxPRE
Diffstat (limited to 'embassy-stm32')
| -rw-r--r-- | embassy-stm32/src/rcc/mco.rs | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs index 3d0f510c0..a8f8cfcff 100644 --- a/embassy-stm32/src/rcc/mco.rs +++ b/embassy-stm32/src/rcc/mco.rs | |||
| @@ -61,10 +61,12 @@ macro_rules! impl_peri { | |||
| 61 | type Source = $source; | 61 | type Source = $source; |
| 62 | 62 | ||
| 63 | unsafe fn _apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) { | 63 | unsafe fn _apply_clock_settings(source: Self::Source, _prescaler: McoPrescaler) { |
| 64 | #[cfg(not(any(stm32u5, stm32wba)))] | 64 | #[cfg(not(any(stm32u5, stm32wba, stm32n6)))] |
| 65 | let r = RCC.cfgr(); | 65 | let r = RCC.cfgr(); |
| 66 | #[cfg(any(stm32u5, stm32wba))] | 66 | #[cfg(any(stm32u5, stm32wba))] |
| 67 | let r = RCC.cfgr1(); | 67 | let r = RCC.cfgr1(); |
| 68 | #[cfg(any(stm32n6))] | ||
| 69 | let r = RCC.ccipr5(); | ||
| 68 | 70 | ||
| 69 | r.modify(|w| { | 71 | r.modify(|w| { |
| 70 | w.$set_source(source); | 72 | w.$set_source(source); |
