Added sample shifting to qspi config for stm32

2 files changed, 20 insertions, 1 deletions

diff --git a/embassy-stm32/src/qspi/enums.rs b/embassy-stm32/src/qspi/enums.rs
index 9ec4c1b43..3905fcbf8 100644
--- a/embassy-stm32/src/qspi/enums.rs
+++ b/embassy-stm32/src/qspi/enums.rs
@@ -331,3 +331,19 @@ impl From<DummyCycles> for u8 {
         }
     }
 }
+
+#[allow(missing_docs)]
+#[derive(Copy, Clone)]
+pub enum SampleShifting {
+    None,
+    HalfCycle
+}
+
+impl From<SampleShifting> for bool {
+    fn from(value: SampleShifting) -> Self {
+        match value {
+            SampleShifting::None => false,
+            SampleShifting::HalfCycle => true
+        }
+    }
+}
\ No newline at end of file
diff --git a/embassy-stm32/src/qspi/mod.rs b/embassy-stm32/src/qspi/mod.rs
index 0df057c53..52b1f3084 100644
--- a/embassy-stm32/src/qspi/mod.rs
+++ b/embassy-stm32/src/qspi/mod.rs
@@ -58,6 +58,8 @@ pub struct Config {
     pub fifo_threshold: FIFOThresholdLevel,
     /// Minimum number of cycles that chip select must be high between issued commands
     pub cs_high_time: ChipSelectHighTime,
+    /// Shift sampling point of input data (none, or half-cycle)
+    pub sample_shifting: SampleShifting,
 }
 
 impl Default for Config {
@@ -68,6 +70,7 @@ impl Default for Config {
             prescaler: 128,
             fifo_threshold: FIFOThresholdLevel::_17Bytes,
             cs_high_time: ChipSelectHighTime::_5Cycle,
+            sample_shifting: SampleShifting::None
         }
     }
 }
@@ -120,7 +123,7 @@ impl<'d, T: Instance, M: PeriMode> Qspi<'d, T, M> {
         T::REGS.cr().modify(|w| {
             w.set_en(true);
             //w.set_tcen(false);
-            w.set_sshift(false);
+            w.set_sshift(config.sample_shifting.into());
             w.set_fthres(config.fifo_threshold.into());
             w.set_prescaler(config.prescaler);
             w.set_fsel(fsel.into());