stm32: add support for STM32H7[RS] "bootflash line", add HIL tests.

14 files changed, 327 insertions, 189 deletions

diff --git a/embassy-stm32/Cargo.toml b/embassy-stm32/Cargo.toml
index 6492d69f7..cc126b3af 100644
--- a/embassy-stm32/Cargo.toml
+++ b/embassy-stm32/Cargo.toml
@@ -72,7 +72,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 critical-section = "1.1"
 #stm32-metapac = { version = "15" }
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-37a0941112fd16fee53aaa2005fd67b77adab59c" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-afee4331adc717f4cc52caab16838c95334535be" }
 
 vcell = "0.1.3"
 nb = "1.0.0"
@@ -98,7 +98,7 @@ proc-macro2 = "1.0.36"
 quote = "1.0.15"
 
 #stm32-metapac = { version = "15", default-features = false, features = ["metadata"]}
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-37a0941112fd16fee53aaa2005fd67b77adab59c", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-afee4331adc717f4cc52caab16838c95334535be", default-features = false, features = ["metadata"]}
 
 [features]
 default = ["rt"]
@@ -1095,6 +1095,26 @@ stm32h7b3qi = [ "stm32-metapac/stm32h7b3qi" ]
 stm32h7b3ri = [ "stm32-metapac/stm32h7b3ri" ]
 stm32h7b3vi = [ "stm32-metapac/stm32h7b3vi" ]
 stm32h7b3zi = [ "stm32-metapac/stm32h7b3zi" ]
+stm32h7r3a8 = [ "stm32-metapac/stm32h7r3a8" ]
+stm32h7r3i8 = [ "stm32-metapac/stm32h7r3i8" ]
+stm32h7r3l8 = [ "stm32-metapac/stm32h7r3l8" ]
+stm32h7r3r8 = [ "stm32-metapac/stm32h7r3r8" ]
+stm32h7r3v8 = [ "stm32-metapac/stm32h7r3v8" ]
+stm32h7r3z8 = [ "stm32-metapac/stm32h7r3z8" ]
+stm32h7r7a8 = [ "stm32-metapac/stm32h7r7a8" ]
+stm32h7r7i8 = [ "stm32-metapac/stm32h7r7i8" ]
+stm32h7r7l8 = [ "stm32-metapac/stm32h7r7l8" ]
+stm32h7r7z8 = [ "stm32-metapac/stm32h7r7z8" ]
+stm32h7s3a8 = [ "stm32-metapac/stm32h7s3a8" ]
+stm32h7s3i8 = [ "stm32-metapac/stm32h7s3i8" ]
+stm32h7s3l8 = [ "stm32-metapac/stm32h7s3l8" ]
+stm32h7s3r8 = [ "stm32-metapac/stm32h7s3r8" ]
+stm32h7s3v8 = [ "stm32-metapac/stm32h7s3v8" ]
+stm32h7s3z8 = [ "stm32-metapac/stm32h7s3z8" ]
+stm32h7s7a8 = [ "stm32-metapac/stm32h7s7a8" ]
+stm32h7s7i8 = [ "stm32-metapac/stm32h7s7i8" ]
+stm32h7s7l8 = [ "stm32-metapac/stm32h7s7l8" ]
+stm32h7s7z8 = [ "stm32-metapac/stm32h7s7z8" ]
 stm32l010c6 = [ "stm32-metapac/stm32l010c6" ]
 stm32l010f4 = [ "stm32-metapac/stm32l010f4" ]
 stm32l010k4 = [ "stm32-metapac/stm32l010k4" ]
diff --git a/embassy-stm32/build.rs b/embassy-stm32/build.rs
index ba3af2550..ba118f338 100644
--- a/embassy-stm32/build.rs
+++ b/embassy-stm32/build.rs
@@ -406,7 +406,16 @@ fn main() {
             },
         );
     }
-    if chip_name.starts_with("stm32h7") {
+
+    if chip_name.starts_with("stm32h7r") || chip_name.starts_with("stm32h7s") {
+        clock_gen.chained_muxes.insert(
+            "PER",
+            &PeripheralRccRegister {
+                register: "AHBPERCKSELR",
+                field: "PERSEL",
+            },
+        );
+    } else if chip_name.starts_with("stm32h7") {
         clock_gen.chained_muxes.insert(
             "PER",
             &PeripheralRccRegister {
@@ -1585,7 +1594,11 @@ fn main() {
         println!("cargo:rustc-cfg=package_{}", &chip_name[10..11]);
         println!("cargo:rustc-cfg=flashsize_{}", &chip_name[11..12]);
     } else {
-        println!("cargo:rustc-cfg={}", &chip_name[..7]); // stm32f4
+        if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" {
+            println!("cargo:rustc-cfg=stm32h7rs");
+        } else {
+            println!("cargo:rustc-cfg={}", &chip_name[..7]); // stm32f4
+        }
         println!("cargo:rustc-cfg={}", &chip_name[..9]); // stm32f429
         println!("cargo:rustc-cfg={}x", &chip_name[..8]); // stm32f42x
         println!("cargo:rustc-cfg={}x{}", &chip_name[..7], &chip_name[8..9]); // stm32f4x9
diff --git a/embassy-stm32/src/can/fd/peripheral.rs b/embassy-stm32/src/can/fd/peripheral.rs
index e5cfee528..9cd5f0785 100644
--- a/embassy-stm32/src/can/fd/peripheral.rs
+++ b/embassy-stm32/src/can/fd/peripheral.rs
@@ -30,10 +30,10 @@ impl Registers {
         &mut self.msg_ram_mut().transmit.tbsa[bufidx]
     }
     pub fn msg_ram_mut(&self) -> &mut RegisterBlock {
-        #[cfg(stm32h7)]
+        #[cfg(can_fdcan_h7)]
         let ptr = self.msgram.ram(self.msg_ram_offset / 4).as_ptr() as *mut RegisterBlock;
 
-        #[cfg(not(stm32h7))]
+        #[cfg(not(can_fdcan_h7))]
         let ptr = self.msgram.as_ptr() as *mut RegisterBlock;
 
         unsafe { &mut (*ptr) }
@@ -105,7 +105,7 @@ impl Registers {
             return Some(BusError::BusWarning);
         } else {
             cfg_if! {
-                if #[cfg(stm32h7)] {
+                if #[cfg(can_fdcan_h7)] {
                     let lec = err.lec();
                 } else {
                     let lec = err.lec().to_bits();
@@ -334,14 +334,14 @@ impl Registers {
         // set extended filters list size to 8
         // REQUIRED: we use the memory map as if these settings are set
         // instead of re-calculating them.
-        #[cfg(not(stm32h7))]
+        #[cfg(not(can_fdcan_h7))]
         {
             self.regs.rxgfc().modify(|w| {
                 w.set_lss(crate::can::fd::message_ram::STANDARD_FILTER_MAX);
                 w.set_lse(crate::can::fd::message_ram::EXTENDED_FILTER_MAX);
             });
         }
-        #[cfg(stm32h7)]
+        #[cfg(can_fdcan_h7)]
         {
             self.regs
                 .sidfc()
@@ -354,11 +354,11 @@ impl Registers {
         self.configure_msg_ram();
 
         // Enable timestamping
-        #[cfg(not(stm32h7))]
+        #[cfg(not(can_fdcan_h7))]
         self.regs
             .tscc()
             .write(|w| w.set_tss(stm32_metapac::can::vals::Tss::INCREMENT));
-        #[cfg(stm32h7)]
+        #[cfg(can_fdcan_h7)]
         self.regs.tscc().write(|w| w.set_tss(0x01));
 
         // this isn't really documented in the reference manual
@@ -491,9 +491,9 @@ impl Registers {
 
         self.regs.cccr().modify(|w| {
             w.set_fdoe(fdoe);
-            #[cfg(stm32h7)]
+            #[cfg(can_fdcan_h7)]
             w.set_bse(brse);
-            #[cfg(not(stm32h7))]
+            #[cfg(not(can_fdcan_h7))]
             w.set_brse(brse);
         });
     }
@@ -508,14 +508,14 @@ impl Registers {
     #[inline]
     #[allow(unused)]
     pub fn set_timestamp_counter_source(&mut self, select: TimestampSource) {
-        #[cfg(stm32h7)]
+        #[cfg(can_fdcan_h7)]
         let (tcp, tss) = match select {
             TimestampSource::None => (0, 0),
             TimestampSource::Prescaler(p) => (p as u8, 1),
             TimestampSource::FromTIM3 => (0, 2),
         };
 
-        #[cfg(not(stm32h7))]
+        #[cfg(not(can_fdcan_h7))]
         let (tcp, tss) = match select {
             TimestampSource::None => (0, stm32_metapac::can::vals::Tss::ZERO),
             TimestampSource::Prescaler(p) => (p as u8, stm32_metapac::can::vals::Tss::INCREMENT),
@@ -528,7 +528,7 @@ impl Registers {
         });
     }
 
-    #[cfg(not(stm32h7))]
+    #[cfg(not(can_fdcan_h7))]
     /// Configures the global filter settings
     #[inline]
     pub fn set_global_filter(&mut self, filter: GlobalFilter) {
@@ -551,7 +551,7 @@ impl Registers {
         });
     }
 
-    #[cfg(stm32h7)]
+    #[cfg(can_fdcan_h7)]
     /// Configures the global filter settings
     #[inline]
     pub fn set_global_filter(&mut self, filter: GlobalFilter) {
@@ -575,10 +575,10 @@ impl Registers {
         });
     }
 
-    #[cfg(not(stm32h7))]
+    #[cfg(not(can_fdcan_h7))]
     fn configure_msg_ram(&mut self) {}
 
-    #[cfg(stm32h7)]
+    #[cfg(can_fdcan_h7)]
     fn configure_msg_ram(&mut self) {
         let r = self.regs;
 
diff --git a/embassy-stm32/src/can/fdcan.rs b/embassy-stm32/src/can/fdcan.rs
index 6144ba520..81ceb06aa 100644
--- a/embassy-stm32/src/can/fdcan.rs
+++ b/embassy-stm32/src/can/fdcan.rs
@@ -975,7 +975,7 @@ macro_rules! impl_fdcan {
     };
 }
 
-#[cfg(not(stm32h7))]
+#[cfg(not(can_fdcan_h7))]
 foreach_peripheral!(
     (can, FDCAN) => { impl_fdcan!(FDCAN, FDCANRAM); };
     (can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM1); };
@@ -983,7 +983,7 @@ foreach_peripheral!(
     (can, FDCAN3) => { impl_fdcan!(FDCAN3, FDCANRAM3); };
 );
 
-#[cfg(stm32h7)]
+#[cfg(can_fdcan_h7)]
 foreach_peripheral!(
     (can, FDCAN1) => { impl_fdcan!(FDCAN1, FDCANRAM, 0x0000); };
     (can, FDCAN2) => { impl_fdcan!(FDCAN2, FDCANRAM, 0x0C00); };
diff --git a/embassy-stm32/src/cryp/mod.rs b/embassy-stm32/src/cryp/mod.rs
index 18b5ec918..f19c94fda 100644
--- a/embassy-stm32/src/cryp/mod.rs
+++ b/embassy-stm32/src/cryp/mod.rs
@@ -1,5 +1,5 @@
 //! Crypto Accelerator (CRYP)
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 use core::cmp::min;
 use core::marker::PhantomData;
 use core::ptr;
@@ -7,7 +7,7 @@ use core::ptr;
 use embassy_hal_internal::{into_ref, PeripheralRef};
 use embassy_sync::waitqueue::AtomicWaker;
 
-use crate::dma::{NoDma, Priority, Transfer, TransferOptions};
+use crate::dma::{NoDma, Transfer, TransferOptions};
 use crate::interrupt::typelevel::Interrupt;
 use crate::{interrupt, pac, peripherals, Peripheral};
 
@@ -147,7 +147,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesEcb<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(0));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(0));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -189,7 +189,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for TdesCbc<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(1));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(1));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -231,7 +231,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesEcb<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(2));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(2));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -272,7 +272,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for DesCbc<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(3));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(3));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -313,7 +313,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(7));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(7));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -327,7 +327,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesEcb<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(2));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(2));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -370,7 +370,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(7));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(7));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -384,7 +384,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCbc<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(5));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(5));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -426,7 +426,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesCtr<'c, KEY_SIZE> {
         {
             p.cr().modify(|w| w.set_algomode(6));
         }
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         {
             p.cr().modify(|w| w.set_algomode0(6));
             p.cr().modify(|w| w.set_algomode3(false));
@@ -439,14 +439,14 @@ impl<'c> CipherSized for AesCtr<'c, { 192 / 8 }> {}
 impl<'c> CipherSized for AesCtr<'c, { 256 / 8 }> {}
 impl<'c, const KEY_SIZE: usize> IVSized for AesCtr<'c, KEY_SIZE> {}
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 ///AES-GCM Cipher Mode
 pub struct AesGcm<'c, const KEY_SIZE: usize> {
     iv: [u8; 16],
     key: &'c [u8; KEY_SIZE],
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
     /// Constucts a new AES-GCM cipher for a cryptographic operation.
     pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -457,7 +457,7 @@ impl<'c, const KEY_SIZE: usize> AesGcm<'c, KEY_SIZE> {
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
     const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
 
@@ -504,7 +504,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
         [0; 4]
     }
 
-    #[cfg(cryp_v3)]
+    #[cfg(any(cryp_v3, cryp_v4))]
     fn pre_final(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
         //Handle special GCM partial block process.
         p.cr().modify(|w| w.set_npblb(padding_len as u8));
@@ -573,25 +573,25 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGcm<'c, KEY_SIZE> {
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGcm<'c, { 128 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGcm<'c, { 192 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGcm<'c, { 256 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGcm<'c, KEY_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> IVSized for AesGcm<'c, KEY_SIZE> {}
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 /// AES-GMAC Cipher Mode
 pub struct AesGmac<'c, const KEY_SIZE: usize> {
     iv: [u8; 16],
     key: &'c [u8; KEY_SIZE],
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
     /// Constructs a new AES-GMAC cipher for a cryptographic operation.
     pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; 12]) -> Self {
@@ -602,7 +602,7 @@ impl<'c, const KEY_SIZE: usize> AesGmac<'c, KEY_SIZE> {
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
     const BLOCK_SIZE: usize = AES_BLOCK_SIZE;
 
@@ -649,7 +649,7 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
         [0; 4]
     }
 
-    #[cfg(cryp_v3)]
+    #[cfg(any(cryp_v3, cryp_v4))]
     fn pre_final(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
         //Handle special GCM partial block process.
         p.cr().modify(|w| w.set_npblb(padding_len as u8));
@@ -716,18 +716,18 @@ impl<'c, const KEY_SIZE: usize> Cipher<'c> for AesGmac<'c, KEY_SIZE> {
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGmac<'c, { 128 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGmac<'c, { 192 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c> CipherSized for AesGmac<'c, { 256 / 8 }> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> CipherAuthenticated<16> for AesGmac<'c, KEY_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize> IVSized for AesGmac<'c, KEY_SIZE> {}
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 /// AES-CCM Cipher Mode
 pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> {
     key: &'c [u8; KEY_SIZE],
@@ -737,7 +737,7 @@ pub struct AesCcm<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZ
     ctr: [u8; 16],
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE> {
     /// Constructs a new AES-CCM cipher for a cryptographic operation.
     pub fn new(key: &'c [u8; KEY_SIZE], iv: &'c [u8; IV_SIZE], aad_len: usize, payload_len: usize) -> Self {
@@ -801,7 +801,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Aes
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cipher<'c>
     for AesCcm<'c, KEY_SIZE, TAG_SIZE, IV_SIZE>
 {
@@ -865,7 +865,7 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
         return temp1;
     }
 
-    #[cfg(cryp_v3)]
+    #[cfg(any(cryp_v3, cryp_v4))]
     fn pre_final(&self, p: &pac::cryp::Cryp, _dir: Direction, padding_len: usize) -> [u32; 4] {
         //Handle special GCM partial block process.
         p.cr().modify(|w| w.set_npblb(padding_len as u8));
@@ -950,39 +950,39 @@ impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize, const IV_SIZE: usize> Cip
     }
 }
 
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 128 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 192 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const TAG_SIZE: usize, const IV_SIZE: usize> CipherSized for AesCcm<'c, { 256 / 8 }, TAG_SIZE, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<4> for AesCcm<'c, KEY_SIZE, 4, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<6> for AesCcm<'c, KEY_SIZE, 6, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<8> for AesCcm<'c, KEY_SIZE, 8, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<10> for AesCcm<'c, KEY_SIZE, 10, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<12> for AesCcm<'c, KEY_SIZE, 12, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<14> for AesCcm<'c, KEY_SIZE, 14, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const IV_SIZE: usize> CipherAuthenticated<16> for AesCcm<'c, KEY_SIZE, 16, IV_SIZE> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 7> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 8> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 9> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 10> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 11> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 12> {}
-#[cfg(any(cryp_v2, cryp_v3))]
+#[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
 impl<'c, const KEY_SIZE: usize, const TAG_SIZE: usize> IVSized for AesCcm<'c, KEY_SIZE, TAG_SIZE, 13> {}
 
 #[allow(dead_code)]
@@ -1205,7 +1205,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         ctx
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     /// Controls the header phase of cipher processing.
     /// This function is only valid for authenticated ciphers including GCM, CCM, and GMAC.
     /// All additional associated data (AAD) must be supplied to this function prior to starting the payload phase with `payload_blocking`.
@@ -1302,7 +1302,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         self.store_context(ctx);
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     /// Controls the header phase of cipher processing.
     /// This function is only valid for authenticated ciphers including GCM, CCM, and GMAC.
     /// All additional associated data (AAD) must be supplied to this function prior to starting the payload phase with `payload`.
@@ -1420,7 +1420,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         if !ctx.aad_complete && ctx.header_len > 0 {
             panic!("Additional associated data must be processed first!");
         } else if !ctx.aad_complete {
-            #[cfg(any(cryp_v2, cryp_v3))]
+            #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
             {
                 ctx.aad_complete = true;
                 T::regs().cr().modify(|w| w.set_crypen(false));
@@ -1512,7 +1512,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         if !ctx.aad_complete && ctx.header_len > 0 {
             panic!("Additional associated data must be processed first!");
         } else if !ctx.aad_complete {
-            #[cfg(any(cryp_v2, cryp_v3))]
+            #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
             {
                 ctx.aad_complete = true;
                 T::regs().cr().modify(|w| w.set_crypen(false));
@@ -1585,7 +1585,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         self.store_context(ctx);
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     /// Generates an authentication tag for authenticated ciphers including GCM, CCM, and GMAC.
     /// Called after the all data has been encrypted/decrypted by `payload`.
     pub fn finish_blocking<
@@ -1614,7 +1614,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
             payloadlen1.swap_bytes(),
             payloadlen2.swap_bytes(),
         ];
-        #[cfg(cryp_v3)]
+        #[cfg(any(cryp_v3, cryp_v4))]
         let footer: [u32; 4] = [headerlen1, headerlen2, payloadlen1, payloadlen2];
 
         self.write_words_blocking(C::BLOCK_SIZE, &footer);
@@ -1631,7 +1631,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         tag
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     // Generates an authentication tag for authenticated ciphers including GCM, CCM, and GMAC.
     /// Called after the all data has been encrypted/decrypted by `payload`.
     pub async fn finish<
@@ -1664,7 +1664,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
             payloadlen1.swap_bytes(),
             payloadlen2.swap_bytes(),
         ];
-        #[cfg(cryp_v3)]
+        #[cfg(any(cryp_v3, cryp_v4))]
         let footer: [u32; 4] = [headerlen1, headerlen2, payloadlen1, payloadlen2];
 
         let write = Self::write_words(&mut self.indma, C::BLOCK_SIZE, &footer);
@@ -1735,7 +1735,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         ctx.iv[2] = T::regs().init(1).ivlr().read();
         ctx.iv[3] = T::regs().init(1).ivrr().read();
 
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         for i in 0..8 {
             ctx.csgcmccm[i] = T::regs().csgcmccmr(i).read();
             ctx.csgcm[i] = T::regs().csgcmr(i).read();
@@ -1750,7 +1750,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         T::regs().init(1).ivlr().write_value(ctx.iv[2]);
         T::regs().init(1).ivrr().write_value(ctx.iv[3]);
 
-        #[cfg(any(cryp_v2, cryp_v3))]
+        #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
         for i in 0..8 {
             T::regs().csgcmccmr(i).write_value(ctx.csgcmccm[i]);
             T::regs().csgcmr(i).write_value(ctx.csgcm[i]);
@@ -1797,7 +1797,8 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         let num_words = blocks.len() / 4;
         let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
-            priority: Priority::High,
+            #[cfg(not(gpdma))]
+            priority: crate::dma::Priority::High,
             ..Default::default()
         };
         let dma_transfer = unsafe { Transfer::new_write_raw(dma, dma_request, src_ptr, dst_ptr, options) };
@@ -1806,7 +1807,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         dma_transfer.await;
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     fn write_words_blocking(&self, block_size: usize, blocks: &[u32]) {
         assert_eq!((blocks.len() * 4) % block_size, 0);
         let mut byte_counter: usize = 0;
@@ -1820,7 +1821,7 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         }
     }
 
-    #[cfg(any(cryp_v2, cryp_v3))]
+    #[cfg(any(cryp_v2, cryp_v3, cryp_v4))]
     async fn write_words(dma: &mut PeripheralRef<'_, DmaIn>, block_size: usize, blocks: &[u32])
     where
         DmaIn: crate::cryp::DmaIn<T>,
@@ -1836,7 +1837,8 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         let num_words = blocks.len();
         let src_ptr = ptr::slice_from_raw_parts(blocks.as_ptr().cast(), num_words);
         let options = TransferOptions {
-            priority: Priority::High,
+            #[cfg(not(gpdma))]
+            priority: crate::dma::Priority::High,
             ..Default::default()
         };
         let dma_transfer = unsafe { Transfer::new_write_raw(dma, dma_request, src_ptr, dst_ptr, options) };
@@ -1875,7 +1877,8 @@ impl<'d, T: Instance, DmaIn, DmaOut> Cryp<'d, T, DmaIn, DmaOut> {
         let num_words = blocks.len() / 4;
         let dst_ptr = ptr::slice_from_raw_parts_mut(blocks.as_mut_ptr().cast(), num_words);
         let options = TransferOptions {
-            priority: Priority::VeryHigh,
+            #[cfg(not(gpdma))]
+            priority: crate::dma::Priority::VeryHigh,
             ..Default::default()
         };
         let dma_transfer = unsafe { Transfer::new_read_raw(dma, dma_request, src_ptr, dst_ptr, options) };
diff --git a/embassy-stm32/src/eth/v2/mod.rs b/embassy-stm32/src/eth/v2/mod.rs
index 37f460574..a19aa42cf 100644
--- a/embassy-stm32/src/eth/v2/mod.rs
+++ b/embassy-stm32/src/eth/v2/mod.rs
@@ -4,6 +4,7 @@ use core::marker::PhantomData;
 use core::sync::atomic::{fence, Ordering};
 
 use embassy_hal_internal::{into_ref, PeripheralRef};
+use stm32_metapac::syscfg::vals::EthSelPhy;
 
 pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
 use super::*;
@@ -80,19 +81,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
-        // Enable the necessary Clocks
-        #[cfg(not(rcc_h5))]
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_eth1macen(true);
-                w.set_eth1txen(true);
-                w.set_eth1rxen(true);
-            });
-
-            crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
-        });
-
-        #[cfg(rcc_h5)]
+        // Enable the necessary clocks
         critical_section::with(|_| {
             crate::pac::RCC.ahb1enr().modify(|w| {
                 w.set_ethen(true);
@@ -100,9 +89,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
                 w.set_ethrxen(true);
             });
 
-            crate::pac::SYSCFG
-                .pmcr()
-                .modify(|w| w.set_eth_sel_phy(crate::pac::syscfg::vals::EthSelPhy::B_0X4));
+            crate::pac::SYSCFG.pmcr().modify(|w| w.set_eth_sel_phy(EthSelPhy::RMII));
         });
 
         into_ref!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
@@ -145,19 +132,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
         phy: P,
         mac_addr: [u8; 6],
     ) -> Self {
-        // Enable necessary clocks.
-        #[cfg(not(rcc_h5))]
-        critical_section::with(|_| {
-            crate::pac::RCC.ahb1enr().modify(|w| {
-                w.set_eth1macen(true);
-                w.set_eth1txen(true);
-                w.set_eth1rxen(true);
-            });
-
-            crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b000));
-        });
-
-        #[cfg(rcc_h5)]
+        // Enable the necessary clocks
         critical_section::with(|_| {
             crate::pac::RCC.ahb1enr().modify(|w| {
                 w.set_ethen(true);
@@ -165,10 +140,9 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
                 w.set_ethrxen(true);
             });
 
-            // TODO: This is for RMII - what would MII need here?
             crate::pac::SYSCFG
                 .pmcr()
-                .modify(|w| w.set_eth_sel_phy(crate::pac::syscfg::vals::EthSelPhy::B_0X4));
+                .modify(|w| w.set_eth_sel_phy(EthSelPhy::MII_GMII));
         });
 
         into_ref!(rx_clk, tx_clk, mdio, mdc, rxdv, rx_d0, rx_d1, rx_d2, rx_d3, tx_d0, tx_d1, tx_d2, tx_d3, tx_en);
diff --git a/embassy-stm32/src/lib.rs b/embassy-stm32/src/lib.rs
index 7d2b49ff4..1f4e9ab1e 100644
--- a/embassy-stm32/src/lib.rs
+++ b/embassy-stm32/src/lib.rs
@@ -2,7 +2,7 @@
 #![allow(async_fn_in_trait)]
 #![cfg_attr(
     docsrs,
-    doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-stm32'>browse the `embassy-stm32` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (STM32H755 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
+    doc = "<div style='padding:30px;background:#810;color:#fff;text-align:center;'><p>You might want to <a href='https://docs.embassy.dev/embassy-stm32'>browse the `embassy-stm32` documentation on the Embassy website</a> instead.</p><p>The documentation here on `docs.rs` is built for a single chip only (stm32h7, stm32h7rs55 in particular), while on the Embassy website you can pick your exact chip from the top menu. Available peripherals and their APIs change depending on the chip.</p></div>\n\n"
 )]
 #![doc = include_str!("../README.md")]
 #![warn(missing_docs)]
@@ -303,9 +303,9 @@ pub fn init(config: Config) -> Peripherals {
 
         #[cfg(not(any(stm32f1, stm32wb, stm32wl)))]
         peripherals::SYSCFG::enable_and_reset_with_cs(cs);
-        #[cfg(not(any(stm32h5, stm32h7, stm32wb, stm32wl)))]
+        #[cfg(not(any(stm32h5, stm32h7, stm32h7rs, stm32wb, stm32wl)))]
         peripherals::PWR::enable_and_reset_with_cs(cs);
-        #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7)))]
+        #[cfg(not(any(stm32f2, stm32f4, stm32f7, stm32l0, stm32h5, stm32h7, stm32h7rs)))]
         peripherals::FLASH::enable_and_reset_with_cs(cs);
 
         // Enable the VDDIO2 power supply on chips that have it.
diff --git a/embassy-stm32/src/rcc/bd.rs b/embassy-stm32/src/rcc/bd.rs
index 54d3c662b..f3ac4fdbe 100644
--- a/embassy-stm32/src/rcc/bd.rs
+++ b/embassy-stm32/src/rcc/bd.rs
@@ -198,7 +198,7 @@ impl LsConfig {
         }
 
         // If not OK, reset backup domain and configure it.
-        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32c0)))]
+        #[cfg(not(any(rcc_l0, rcc_l0_v2, rcc_l1, stm32h5, stm32h7rs, stm32c0)))]
         {
             bdcr().modify(|w| w.set_bdrst(true));
             bdcr().modify(|w| w.set_bdrst(false));
@@ -210,11 +210,12 @@ impl LsConfig {
         // letting half our RAM go magically *poof*.
         // STM32H503CB/EB/KB/RB device errata - 2.2.8 SRAM2 unduly erased upon a backup domain reset
         // STM32H562xx/563xx/573xx device errata - 2.2.14 SRAM2 is erased when the backup domain is reset
-        //#[cfg(any(stm32h5))]
-        //{
-        //    bdcr().modify(|w| w.set_vswrst(true));
-        //    bdcr().modify(|w| w.set_vswrst(false));
-        //}
+        //#[cfg(any(stm32h5, stm32h7rs))]
+        #[cfg(any(stm32h7rs))]
+        {
+            bdcr().modify(|w| w.set_vswrst(true));
+            bdcr().modify(|w| w.set_vswrst(false));
+        }
         #[cfg(any(stm32c0, stm32l0))]
         {
             bdcr().modify(|w| w.set_rtcrst(true));
diff --git a/embassy-stm32/src/rcc/h.rs b/embassy-stm32/src/rcc/h.rs
index aa8c4b1f7..5d47d400c 100644
--- a/embassy-stm32/src/rcc/h.rs
+++ b/embassy-stm32/src/rcc/h.rs
@@ -1,7 +1,6 @@
 use core::ops::RangeInclusive;
 
 use crate::pac;
-use crate::pac::pwr::vals::Vos;
 pub use crate::pac::rcc::vals::{
     Hsidiv as HSIPrescaler, Plldiv as PllDiv, Pllm as PllPreDiv, Plln as PllMul, Pllsrc as PllSource, Sw as Sysclk,
 };
@@ -22,9 +21,12 @@ const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(128_000_000)..=Hertz(560_000
 const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(836_000_000);
 #[cfg(any(pwr_h7rm0399, pwr_h7rm0433))]
 const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(960_000_000);
+#[cfg(any(stm32h7rs))]
+const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(384_000_000)..=Hertz(1672_000_000);
 
 pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Ppre as APBPrescaler};
 
+#[cfg(any(stm32h5, stm32h7))]
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum VoltageScale {
     Scale0,
@@ -32,6 +34,8 @@ pub enum VoltageScale {
     Scale2,
     Scale3,
 }
+#[cfg(any(stm32h7rs))]
+pub use crate::pac::pwr::vals::Vos as VoltageScale;
 
 #[derive(Clone, Copy, Eq, PartialEq)]
 pub enum HseMode {
@@ -40,7 +44,7 @@ pub enum HseMode {
     /// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
     Bypass,
     /// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
-    #[cfg(any(rcc_h5, rcc_h50))]
+    #[cfg(any(rcc_h5, rcc_h50, rcc_h7rs))]
     BypassDigital,
 }
 
@@ -65,8 +69,8 @@ pub struct Pll {
 
     /// PLL P division factor. If None, PLL P output is disabled.
     /// On PLL1, it must be even for most series (in particular,
-    /// it cannot be 1 in series other than STM32H723/733,
-    /// STM32H725/735 and STM32H730.)
+    /// it cannot be 1 in series other than stm32h7, stm32h7rs23/733,
+    /// stm32h7, stm32h7rs25/735 and stm32h7, stm32h7rs30.)
     pub divp: Option<PllDiv>,
     /// PLL Q division factor. If None, PLL Q output is disabled.
     pub divq: Option<PllDiv>,
@@ -115,7 +119,7 @@ impl From<TimerPrescaler> for Timpre {
 
 /// Power supply configuration
 /// See RM0433 Rev 4 7.4
-#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
+#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
 #[derive(PartialEq)]
 pub enum SupplyConfig {
     /// Default power supply configuration.
@@ -164,8 +168,15 @@ pub enum SupplyConfig {
 /// SMPS step-down converter voltage output level.
 /// This is only used in certain power supply configurations:
 /// SMPSLDO, SMPSExternalLDO, SMPSExternalLDOBypass.
-#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
-pub use pac::pwr::vals::Sdlevel as SMPSSupplyVoltage;
+#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
+#[derive(Clone, Copy, Eq, PartialEq, Debug)]
+pub enum SMPSSupplyVoltage {
+    /// 1.8v
+    V1_8,
+    /// 2.5v
+    #[cfg(not(pwr_h7rs))]
+    V2_5,
+}
 
 /// Configuration of the core clocks
 #[non_exhaustive]
@@ -178,22 +189,26 @@ pub struct Config {
 
     pub pll1: Option<Pll>,
     pub pll2: Option<Pll>,
-    #[cfg(any(rcc_h5, stm32h7))]
+    #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
     pub pll3: Option<Pll>,
 
+    #[cfg(any(stm32h7, stm32h7rs))]
     pub d1c_pre: AHBPrescaler,
     pub ahb_pre: AHBPrescaler,
     pub apb1_pre: APBPrescaler,
     pub apb2_pre: APBPrescaler,
+    #[cfg(not(stm32h7rs))]
     pub apb3_pre: APBPrescaler,
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     pub apb4_pre: APBPrescaler,
+    #[cfg(stm32h7rs)]
+    pub apb5_pre: APBPrescaler,
 
     pub timer_prescaler: TimerPrescaler,
     pub voltage_scale: VoltageScale,
     pub ls: super::LsConfig,
 
-    #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
+    #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
     pub supply_config: SupplyConfig,
 
     /// Per-peripheral kernel clock selection muxes
@@ -210,23 +225,30 @@ impl Default for Config {
             sys: Sysclk::HSI,
             pll1: None,
             pll2: None,
-            #[cfg(any(rcc_h5, stm32h7))]
+            #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
             pll3: None,
 
+            #[cfg(any(stm32h7, stm32h7rs))]
             d1c_pre: AHBPrescaler::DIV1,
             ahb_pre: AHBPrescaler::DIV1,
             apb1_pre: APBPrescaler::DIV1,
             apb2_pre: APBPrescaler::DIV1,
+            #[cfg(not(stm32h7rs))]
             apb3_pre: APBPrescaler::DIV1,
-            #[cfg(stm32h7)]
+            #[cfg(any(stm32h7, stm32h7rs))]
             apb4_pre: APBPrescaler::DIV1,
+            #[cfg(stm32h7rs)]
+            apb5_pre: APBPrescaler::DIV1,
 
             timer_prescaler: TimerPrescaler::DefaultX2,
+            #[cfg(not(rcc_h7rs))]
             voltage_scale: VoltageScale::Scale0,
+            #[cfg(rcc_h7rs)]
+            voltage_scale: VoltageScale::HIGH,
             ls: Default::default(),
 
-            #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
-            supply_config: SupplyConfig::Default,
+            #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
+            supply_config: SupplyConfig::LDO,
 
             mux: Default::default(),
         }
@@ -234,24 +256,30 @@ impl Default for Config {
 }
 
 pub(crate) unsafe fn init(config: Config) {
+    #[cfg(any(stm32h7))]
+    let pwr_reg = PWR.cr3();
+    #[cfg(any(stm32h7rs))]
+    let pwr_reg = PWR.csr2();
+
     // NB. The lower bytes of CR3 can only be written once after
     // POR, and must be written with a valid combination. Refer to
     // RM0433 Rev 7 6.8.4. This is partially enforced by dropping
     // `self` at the end of this method, but of course we cannot
     // know what happened between the previous POR and here.
     #[cfg(pwr_h7rm0433)]
-    PWR.cr3().modify(|w| {
+    pwr_reg.modify(|w| {
         w.set_scuen(true);
         w.set_ldoen(true);
         w.set_bypass(false);
     });
 
-    #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
+    #[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468, pwr_h7rs))]
     {
+        use pac::pwr::vals::Sdlevel;
         match config.supply_config {
             SupplyConfig::Default => {
-                PWR.cr3().modify(|w| {
-                    w.set_sdlevel(SMPSSupplyVoltage::RESET);
+                pwr_reg.modify(|w| {
+                    w.set_sdlevel(Sdlevel::RESET);
                     w.set_sdexthp(false);
                     w.set_sden(true);
                     w.set_ldoen(true);
@@ -259,25 +287,30 @@ pub(crate) unsafe fn init(config: Config) {
                 });
             }
             SupplyConfig::LDO => {
-                PWR.cr3().modify(|w| {
+                pwr_reg.modify(|w| {
                     w.set_sden(false);
                     w.set_ldoen(true);
                     w.set_bypass(false);
                 });
             }
             SupplyConfig::DirectSMPS => {
-                PWR.cr3().modify(|w| {
+                pwr_reg.modify(|w| {
                     w.set_sdexthp(false);
                     w.set_sden(true);
                     w.set_ldoen(false);
                     w.set_bypass(false);
                 });
             }
-            SupplyConfig::SMPSLDO(smps_supply_voltage)
-            | SupplyConfig::SMPSExternalLDO(smps_supply_voltage)
-            | SupplyConfig::SMPSExternalLDOBypass(smps_supply_voltage) => {
-                PWR.cr3().modify(|w| {
-                    w.set_sdlevel(smps_supply_voltage);
+            SupplyConfig::SMPSLDO(sdlevel)
+            | SupplyConfig::SMPSExternalLDO(sdlevel)
+            | SupplyConfig::SMPSExternalLDOBypass(sdlevel) => {
+                let sdlevel = match sdlevel {
+                    SMPSSupplyVoltage::V1_8 => Sdlevel::V1_8,
+                    #[cfg(not(pwr_h7rs))]
+                    SMPSSupplyVoltage::V2_5 => Sdlevel::V2_5,
+                };
+                pwr_reg.modify(|w| {
+                    w.set_sdlevel(sdlevel);
                     w.set_sdexthp(matches!(
                         config.supply_config,
                         SupplyConfig::SMPSExternalLDO(_) | SupplyConfig::SMPSExternalLDOBypass(_)
@@ -291,7 +324,7 @@ pub(crate) unsafe fn init(config: Config) {
                 });
             }
             SupplyConfig::SMPSDisabledLDOBypass => {
-                PWR.cr3().modify(|w| {
+                pwr_reg.modify(|w| {
                     w.set_sden(false);
                     w.set_ldoen(false);
                     w.set_bypass(true);
@@ -305,43 +338,49 @@ pub(crate) unsafe fn init(config: Config) {
     // in the D3CR.VOS and CR3.SDLEVEL fields. By default after reset
     // VOS = Scale 3, so check that the voltage on the VCAP pins =
     // 1.0V.
-    #[cfg(any(pwr_h7rm0433, pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
+    #[cfg(any(stm32h7))]
     while !PWR.csr1().read().actvosrdy() {}
+    #[cfg(any(stm32h7rs))]
+    while !PWR.sr1().read().actvosrdy() {}
 
     // Configure voltage scale.
     #[cfg(any(pwr_h5, pwr_h50))]
     {
         PWR.voscr().modify(|w| {
             w.set_vos(match config.voltage_scale {
-                VoltageScale::Scale0 => Vos::SCALE0,
-                VoltageScale::Scale1 => Vos::SCALE1,
-                VoltageScale::Scale2 => Vos::SCALE2,
-                VoltageScale::Scale3 => Vos::SCALE3,
+                VoltageScale::Scale0 => crate::pac::pwr::vals::Vos::SCALE0,
+                VoltageScale::Scale1 => crate::pac::pwr::vals::Vos::SCALE1,
+                VoltageScale::Scale2 => crate::pac::pwr::vals::Vos::SCALE2,
+                VoltageScale::Scale3 => crate::pac::pwr::vals::Vos::SCALE3,
             })
         });
         while !PWR.vossr().read().vosrdy() {}
     }
-
     #[cfg(syscfg_h7)]
     {
         // in chips without the overdrive bit, we can go from any scale to any scale directly.
         PWR.d3cr().modify(|w| {
             w.set_vos(match config.voltage_scale {
-                VoltageScale::Scale0 => Vos::SCALE0,
-                VoltageScale::Scale1 => Vos::SCALE1,
-                VoltageScale::Scale2 => Vos::SCALE2,
-                VoltageScale::Scale3 => Vos::SCALE3,
+                VoltageScale::Scale0 => crate::pac::pwr::vals::Vos::SCALE0,
+                VoltageScale::Scale1 => crate::pac::pwr::vals::Vos::SCALE1,
+                VoltageScale::Scale2 => crate::pac::pwr::vals::Vos::SCALE2,
+                VoltageScale::Scale3 => crate::pac::pwr::vals::Vos::SCALE3,
             })
         });
         while !PWR.d3cr().read().vosrdy() {}
     }
+    #[cfg(pwr_h7rs)]
+    {
+        PWR.csr4().modify(|w| w.set_vos(config.voltage_scale));
+        while !PWR.csr4().read().vosrdy() {}
+    }
 
     #[cfg(syscfg_h7od)]
     {
         match config.voltage_scale {
             VoltageScale::Scale0 => {
                 // to go to scale0, we must go to Scale1 first...
-                PWR.d3cr().modify(|w| w.set_vos(Vos::SCALE1));
+                PWR.d3cr().modify(|w| w.set_vos(crate::pac::pwr::vals::Vos::SCALE1));
                 while !PWR.d3cr().read().vosrdy() {}
 
                 // Then enable overdrive.
@@ -353,9 +392,9 @@ pub(crate) unsafe fn init(config: Config) {
                 PWR.d3cr().modify(|w| {
                     w.set_vos(match config.voltage_scale {
                         VoltageScale::Scale0 => unreachable!(),
-                        VoltageScale::Scale1 => Vos::SCALE1,
-                        VoltageScale::Scale2 => Vos::SCALE2,
-                        VoltageScale::Scale3 => Vos::SCALE3,
+                        VoltageScale::Scale1 => crate::pac::pwr::vals::Vos::SCALE1,
+                        VoltageScale::Scale2 => crate::pac::pwr::vals::Vos::SCALE2,
+                        VoltageScale::Scale3 => crate::pac::pwr::vals::Vos::SCALE3,
                     })
                 });
                 while !PWR.d3cr().read().vosrdy() {}
@@ -388,7 +427,7 @@ pub(crate) unsafe fn init(config: Config) {
         Some(hse) => {
             RCC.cr().modify(|w| {
                 w.set_hsebyp(hse.mode != HseMode::Oscillator);
-                #[cfg(any(rcc_h5, rcc_h50))]
+                #[cfg(any(rcc_h5, rcc_h50, rcc_h7rs))]
                 w.set_hseext(match hse.mode {
                     HseMode::Oscillator | HseMode::Bypass => pac::rcc::vals::Hseext::ANALOG,
                     HseMode::BypassDigital => pac::rcc::vals::Hseext::DIGITAL,
@@ -414,7 +453,7 @@ pub(crate) unsafe fn init(config: Config) {
     };
 
     // H7 has shared PLLSRC, check it's equal in all PLLs.
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     {
         let plls = [&config.pll1, &config.pll2, &config.pll3];
         if !super::util::all_equal(plls.into_iter().flatten().map(|p| p.source)) {
@@ -426,7 +465,7 @@ pub(crate) unsafe fn init(config: Config) {
     let pll_input = PllInput { csi, hse, hsi };
     let pll1 = init_pll(0, config.pll1, &pll_input);
     let pll2 = init_pll(1, config.pll2, &pll_input);
-    #[cfg(any(rcc_h5, stm32h7))]
+    #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
     let pll3 = init_pll(2, config.pll3, &pll_input);
 
     // Configure sysclk
@@ -474,8 +513,13 @@ pub(crate) unsafe fn init(config: Config) {
         VoltageScale::Scale2 => (Hertz(300_000_000), Hertz(150_000_000), Hertz(75_000_000)),
         VoltageScale::Scale3 => (Hertz(200_000_000), Hertz(100_000_000), Hertz(50_000_000)),
     };
+    #[cfg(stm32h7rs)]
+    let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
+        VoltageScale::HIGH => (Hertz(600_000_000), Hertz(300_000_000), Hertz(150_000_000)),
+        VoltageScale::LOW => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
+    };
 
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     let hclk = {
         let d1cpre_clk = sys / config.d1c_pre;
         assert!(d1cpre_clk <= d1cpre_clk_max);
@@ -491,12 +535,18 @@ pub(crate) unsafe fn init(config: Config) {
     let apb2 = hclk / config.apb2_pre;
     let apb2_tim = apb_div_tim(&config.apb2_pre, hclk, config.timer_prescaler);
     assert!(apb2 <= pclk_max);
+    #[cfg(not(stm32h7rs))]
     let apb3 = hclk / config.apb3_pre;
+    #[cfg(not(stm32h7rs))]
     assert!(apb3 <= pclk_max);
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     let apb4 = hclk / config.apb4_pre;
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     assert!(apb4 <= pclk_max);
+    #[cfg(stm32h7rs)]
+    let apb5 = hclk / config.apb5_pre;
+    #[cfg(stm32h7rs)]
+    assert!(apb5 <= pclk_max);
 
     flash_setup(hclk, config.voltage_scale);
 
@@ -520,6 +570,25 @@ pub(crate) unsafe fn init(config: Config) {
             w.set_d3ppre(config.apb4_pre);
         });
     }
+    #[cfg(stm32h7rs)]
+    {
+        RCC.cdcfgr().write(|w| {
+            w.set_cpre(config.d1c_pre);
+        });
+        while RCC.cdcfgr().read().cpre() != config.d1c_pre {}
+
+        RCC.bmcfgr().write(|w| {
+            w.set_bmpre(config.ahb_pre);
+        });
+        while RCC.bmcfgr().read().bmpre() != config.ahb_pre {}
+
+        RCC.apbcfgr().modify(|w| {
+            w.set_ppre1(config.apb1_pre);
+            w.set_ppre2(config.apb2_pre);
+            w.set_ppre4(config.apb4_pre);
+            w.set_ppre5(config.apb5_pre);
+        });
+    }
     #[cfg(stm32h5)]
     {
         // Set hpre
@@ -540,7 +609,7 @@ pub(crate) unsafe fn init(config: Config) {
     while RCC.cfgr().read().sws() != config.sys {}
 
     // IO compensation cell - Requires CSI clock and SYSCFG
-    #[cfg(stm32h7)] // TODO h5
+    #[cfg(any(stm32h7))] // TODO h5, h7rs
     if csi.is_some() {
         // Enable the compensation cell, using back-bias voltage code
         // provide by the cell.
@@ -551,7 +620,7 @@ pub(crate) unsafe fn init(config: Config) {
                 w.set_hslv(false);
             })
         });
-        while !pac::SYSCFG.cccsr().read().ready() {}
+        while !pac::SYSCFG.cccsr().read().rdy() {}
     }
 
     config.mux.init();
@@ -562,11 +631,17 @@ pub(crate) unsafe fn init(config: Config) {
         hclk2: Some(hclk),
         hclk3: Some(hclk),
         hclk4: Some(hclk),
+        #[cfg(stm32h7rs)]
+        hclk5: Some(hclk),
         pclk1: Some(apb1),
         pclk2: Some(apb2),
+        #[cfg(not(stm32h7rs))]
         pclk3: Some(apb3),
-        #[cfg(stm32h7)]
+        #[cfg(any(stm32h7, stm32h7rs))]
         pclk4: Some(apb4),
+        #[cfg(stm32h7rs)]
+        pclk5: Some(apb5),
+
         pclk1_tim: Some(apb1_tim),
         pclk2_tim: Some(apb2_tim),
         rtc: rtc,
@@ -584,11 +659,15 @@ pub(crate) unsafe fn init(config: Config) {
         pll2_p: pll2.p,
         pll2_q: pll2.q,
         pll2_r: pll2.r,
-        #[cfg(any(rcc_h5, stm32h7))]
+        #[cfg(stm32h7rs)]
+        pll2_s: None, // TODO
+        #[cfg(stm32h7rs)]
+        pll2_t: None, // TODO
+        #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
         pll3_p: pll3.p,
-        #[cfg(any(rcc_h5, stm32h7))]
+        #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
         pll3_q: pll3.q,
-        #[cfg(any(rcc_h5, stm32h7))]
+        #[cfg(any(rcc_h5, stm32h7, stm32h7rs))]
         pll3_r: pll3.r,
 
         #[cfg(rcc_h50)]
@@ -601,8 +680,14 @@ pub(crate) unsafe fn init(config: Config) {
         #[cfg(stm32h5)]
         audioclk: None,
         i2s_ckin: None,
-        #[cfg(stm32h7)]
+        #[cfg(any(stm32h7, stm32h7rs))]
         dsi_phy: None, // TODO
+        #[cfg(stm32h7rs)]
+        spdifrx_symb: None, // TODO
+        #[cfg(stm32h7rs)]
+        clk48mohci: None, // TODO
+        #[cfg(stm32h7rs)]
+        usb: None, // TODO
     );
 }
 
@@ -627,7 +712,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
         while RCC.cr().read().pllrdy(num) {}
 
         // "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
-        #[cfg(stm32h7)]
+        #[cfg(any(stm32h7, stm32h7rs))]
         RCC.pllckselr().write(|w| w.set_divm(num, PllPreDiv::from_bits(0)));
         #[cfg(stm32h5)]
         RCC.pllcfgr(num).write(|w| w.set_divm(PllPreDiv::from_bits(0)));
@@ -696,7 +781,7 @@ fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
         w.set_pllren(r.is_some());
     });
 
-    #[cfg(stm32h7)]
+    #[cfg(any(stm32h7, stm32h7rs))]
     {
         RCC.pllckselr().modify(|w| {
             w.set_divm(num, config.prediv);
@@ -850,6 +935,26 @@ fn flash_setup(clk: Hertz, vos: VoltageScale) {
         (VoltageScale::Scale3, ..=88) => (3, 1),
         _ => unreachable!(),
     };
+    #[cfg(flash_h7rs)]
+    let (latency, wrhighfreq) = match (vos, clk.0) {
+        // VOS high range VCORE 1.30V - 1.40V
+        (VoltageScale::HIGH, ..=40_000_000) => (0, 0),
+        (VoltageScale::HIGH, ..=80_000_000) => (1, 0),
+        (VoltageScale::HIGH, ..=120_000_000) => (2, 1),
+        (VoltageScale::HIGH, ..=160_000_000) => (3, 1),
+        (VoltageScale::HIGH, ..=200_000_000) => (4, 2),
+        (VoltageScale::HIGH, ..=240_000_000) => (5, 2),
+        (VoltageScale::HIGH, ..=280_000_000) => (6, 3),
+        (VoltageScale::HIGH, ..=320_000_000) => (7, 3),
+        // VOS low range VCORE 1.15V - 1.26V
+        (VoltageScale::LOW, ..=36_000_000) => (0, 0),
+        (VoltageScale::LOW, ..=72_000_000) => (1, 0),
+        (VoltageScale::LOW, ..=108_000_000) => (2, 1),
+        (VoltageScale::LOW, ..=144_000_000) => (3, 1),
+        (VoltageScale::LOW, ..=180_000_000) => (4, 2),
+        (VoltageScale::LOW, ..=216_000_000) => (5, 2),
+        _ => unreachable!(),
+    };
 
     debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
 
diff --git a/embassy-stm32/src/rcc/hsi48.rs b/embassy-stm32/src/rcc/hsi48.rs
index 6f0d7b379..da81abc34 100644
--- a/embassy-stm32/src/rcc/hsi48.rs
+++ b/embassy-stm32/src/rcc/hsi48.rs
@@ -33,9 +33,9 @@ pub(crate) fn init_hsi48(config: Hsi48Config) -> Hertz {
     });
 
     // Enable HSI48
-    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32u5, stm32wba, stm32f0)))]
+    #[cfg(not(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba, stm32f0)))]
     let r = RCC.crrcr();
-    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32u5, stm32wba))]
+    #[cfg(any(stm32u5, stm32g0, stm32h5, stm32h7, stm32h7rs, stm32u5, stm32wba))]
     let r = RCC.cr();
     #[cfg(any(stm32f0))]
     let r = RCC.cr2();
diff --git a/embassy-stm32/src/rcc/mco.rs b/embassy-stm32/src/rcc/mco.rs
index 4b22a099d..40e963466 100644
--- a/embassy-stm32/src/rcc/mco.rs
+++ b/embassy-stm32/src/rcc/mco.rs
@@ -5,9 +5,31 @@ use embassy_hal_internal::into_ref;
 use crate::gpio::{AFType, Speed};
 #[cfg(not(any(stm32f1, rcc_f0v1, rcc_f3v1, rcc_f37)))]
 pub use crate::pac::rcc::vals::Mcopre as McoPrescaler;
-#[cfg(not(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7)))]
+#[cfg(not(any(
+    rcc_f2,
+    rcc_f410,
+    rcc_f4,
+    rcc_f7,
+    rcc_h50,
+    rcc_h5,
+    rcc_h7ab,
+    rcc_h7rm0433,
+    rcc_h7,
+    rcc_h7rs
+)))]
 pub use crate::pac::rcc::vals::Mcosel as McoSource;
-#[cfg(any(rcc_f2, rcc_f410, rcc_f4, rcc_f7, rcc_h50, rcc_h5, rcc_h7ab, rcc_h7rm0433, rcc_h7))]
+#[cfg(any(
+    rcc_f2,
+    rcc_f410,
+    rcc_f4,
+    rcc_f7,
+    rcc_h50,
+    rcc_h5,
+    rcc_h7ab,
+    rcc_h7rm0433,
+    rcc_h7,
+    rcc_h7rs
+))]
 pub use crate::pac::rcc::vals::{Mco1sel as Mco1Source, Mco2sel as Mco2Source};
 use crate::pac::RCC;
 use crate::{peripherals, Peripheral};
diff --git a/embassy-stm32/src/rcc/mod.rs b/embassy-stm32/src/rcc/mod.rs
index a4e497fe7..a585940bc 100644
--- a/embassy-stm32/src/rcc/mod.rs
+++ b/embassy-stm32/src/rcc/mod.rs
@@ -24,7 +24,7 @@ pub use hsi48::*;
 #[cfg_attr(stm32c0, path = "c0.rs")]
 #[cfg_attr(stm32g0, path = "g0.rs")]
 #[cfg_attr(stm32g4, path = "g4.rs")]
-#[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
+#[cfg_attr(any(stm32h5, stm32h7, stm32h7rs), path = "h.rs")]
 #[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl, stm32u0), path = "l.rs")]
 #[cfg_attr(stm32u5, path = "u5.rs")]
 #[cfg_attr(stm32wba, path = "wba.rs")]
diff --git a/embassy-stm32/src/ucpd.rs b/embassy-stm32/src/ucpd.rs
index fe614b811..63412f9b7 100644
--- a/embassy-stm32/src/ucpd.rs
+++ b/embassy-stm32/src/ucpd.rs
@@ -58,7 +58,7 @@ pub(crate) fn init(
         })
     }
 
-    #[cfg(any(stm32h5, stm32u5))]
+    #[cfg(any(stm32h5, stm32u5, stm32h7rs))]
     {
         crate::pac::PWR.ucpdr().modify(|w| {
             w.set_ucpd_dbdis(!ucpd1_db_enable);
diff --git a/embassy-stm32/src/usb/otg.rs b/embassy-stm32/src/usb/otg.rs
index 5d0e1116e..3debd5079 100644
--- a/embassy-stm32/src/usb/otg.rs
+++ b/embassy-stm32/src/usb/otg.rs
@@ -371,7 +371,7 @@ foreach_interrupt!(
                 } else if #[cfg(stm32g0x1)] {
                     const FIFO_DEPTH_WORDS: u16 = 512;
                     const ENDPOINT_COUNT: usize = 8;
-                } else if #[cfg(stm32h7)] {
+                } else if #[cfg(any(stm32h7, stm32h7rs))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;
                 } else if #[cfg(stm32u5)] {
@@ -420,7 +420,7 @@ foreach_interrupt!(
                     stm32f469,
                     stm32f479,
                     stm32f7,
-                    stm32h7,
+                    stm32h7, stm32h7rs,
                 ))] {
                     const FIFO_DEPTH_WORDS: u16 = 1024;
                     const ENDPOINT_COUNT: usize = 9;