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| author | Barnaby Walters <[email protected]> | 2024-02-23 01:59:24 +0100 |
|---|---|---|
| committer | Barnaby Walters <[email protected]> | 2024-02-23 01:59:24 +0100 |
| commit | b091ffcb55840a1349c62f1e4218746d9d51b6c3 (patch) | |
| tree | 4c105cecff093f86d158c025ee9069f058e7d30e /embassy-sync/src/waitqueue | |
| parent | 4481c5f3ccf29da071538ef4f1e48fc5372a72a5 (diff) | |
[embassy-stm32] G4 RCC refactor amendments and additions
* Added assertions for a variety of clock frequencies, based on the reference manual and
stm32g474 datasheet. The family and numbers are consistent enough that I’m assuming
these numbers will work for the other chips.
* Corrected value of pll1_q in set_clocks call, added pll1_r value
Diffstat (limited to 'embassy-sync/src/waitqueue')
0 files changed, 0 insertions, 0 deletions