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authorDániel Buga <[email protected]>2024-04-26 17:35:28 +0200
committerDániel Buga <[email protected]>2024-04-26 17:58:23 +0200
commit91c42e0b9e118d88a51fecf07dc3f41b61c0762c (patch)
tree8614303f101e8fc86263c9d7cf1a6812aa01d9f1 /embassy-usb-synopsys-otg/src
parent4d4cbc0dd3e84dfd7d29d1ecdd2b388568be081f (diff)
Extract synopsys otg driver
Diffstat (limited to 'embassy-usb-synopsys-otg/src')
-rw-r--r--embassy-usb-synopsys-otg/src/fmt.rs257
-rw-r--r--embassy-usb-synopsys-otg/src/lib.rs1300
-rw-r--r--embassy-usb-synopsys-otg/src/otg_v1.rs4482
3 files changed, 6039 insertions, 0 deletions
diff --git a/embassy-usb-synopsys-otg/src/fmt.rs b/embassy-usb-synopsys-otg/src/fmt.rs
new file mode 100644
index 000000000..2ac42c557
--- /dev/null
+++ b/embassy-usb-synopsys-otg/src/fmt.rs
@@ -0,0 +1,257 @@
1#![macro_use]
2#![allow(unused)]
3
4use core::fmt::{Debug, Display, LowerHex};
5
6#[cfg(all(feature = "defmt", feature = "log"))]
7compile_error!("You may not enable both `defmt` and `log` features.");
8
9macro_rules! assert {
10 ($($x:tt)*) => {
11 {
12 #[cfg(not(feature = "defmt"))]
13 ::core::assert!($($x)*);
14 #[cfg(feature = "defmt")]
15 ::defmt::assert!($($x)*);
16 }
17 };
18}
19
20macro_rules! assert_eq {
21 ($($x:tt)*) => {
22 {
23 #[cfg(not(feature = "defmt"))]
24 ::core::assert_eq!($($x)*);
25 #[cfg(feature = "defmt")]
26 ::defmt::assert_eq!($($x)*);
27 }
28 };
29}
30
31macro_rules! assert_ne {
32 ($($x:tt)*) => {
33 {
34 #[cfg(not(feature = "defmt"))]
35 ::core::assert_ne!($($x)*);
36 #[cfg(feature = "defmt")]
37 ::defmt::assert_ne!($($x)*);
38 }
39 };
40}
41
42macro_rules! debug_assert {
43 ($($x:tt)*) => {
44 {
45 #[cfg(not(feature = "defmt"))]
46 ::core::debug_assert!($($x)*);
47 #[cfg(feature = "defmt")]
48 ::defmt::debug_assert!($($x)*);
49 }
50 };
51}
52
53macro_rules! debug_assert_eq {
54 ($($x:tt)*) => {
55 {
56 #[cfg(not(feature = "defmt"))]
57 ::core::debug_assert_eq!($($x)*);
58 #[cfg(feature = "defmt")]
59 ::defmt::debug_assert_eq!($($x)*);
60 }
61 };
62}
63
64macro_rules! debug_assert_ne {
65 ($($x:tt)*) => {
66 {
67 #[cfg(not(feature = "defmt"))]
68 ::core::debug_assert_ne!($($x)*);
69 #[cfg(feature = "defmt")]
70 ::defmt::debug_assert_ne!($($x)*);
71 }
72 };
73}
74
75macro_rules! todo {
76 ($($x:tt)*) => {
77 {
78 #[cfg(not(feature = "defmt"))]
79 ::core::todo!($($x)*);
80 #[cfg(feature = "defmt")]
81 ::defmt::todo!($($x)*);
82 }
83 };
84}
85
86#[cfg(not(feature = "defmt"))]
87macro_rules! unreachable {
88 ($($x:tt)*) => {
89 ::core::unreachable!($($x)*)
90 };
91}
92
93#[cfg(feature = "defmt")]
94macro_rules! unreachable {
95 ($($x:tt)*) => {
96 ::defmt::unreachable!($($x)*)
97 };
98}
99
100macro_rules! panic {
101 ($($x:tt)*) => {
102 {
103 #[cfg(not(feature = "defmt"))]
104 ::core::panic!($($x)*);
105 #[cfg(feature = "defmt")]
106 ::defmt::panic!($($x)*);
107 }
108 };
109}
110
111macro_rules! trace {
112 ($s:literal $(, $x:expr)* $(,)?) => {
113 {
114 #[cfg(feature = "log")]
115 ::log::trace!($s $(, $x)*);
116 #[cfg(feature = "defmt")]
117 ::defmt::trace!($s $(, $x)*);
118 #[cfg(not(any(feature = "log", feature="defmt")))]
119 let _ = ($( & $x ),*);
120 }
121 };
122}
123
124macro_rules! debug {
125 ($s:literal $(, $x:expr)* $(,)?) => {
126 {
127 #[cfg(feature = "log")]
128 ::log::debug!($s $(, $x)*);
129 #[cfg(feature = "defmt")]
130 ::defmt::debug!($s $(, $x)*);
131 #[cfg(not(any(feature = "log", feature="defmt")))]
132 let _ = ($( & $x ),*);
133 }
134 };
135}
136
137macro_rules! info {
138 ($s:literal $(, $x:expr)* $(,)?) => {
139 {
140 #[cfg(feature = "log")]
141 ::log::info!($s $(, $x)*);
142 #[cfg(feature = "defmt")]
143 ::defmt::info!($s $(, $x)*);
144 #[cfg(not(any(feature = "log", feature="defmt")))]
145 let _ = ($( & $x ),*);
146 }
147 };
148}
149
150macro_rules! warn {
151 ($s:literal $(, $x:expr)* $(,)?) => {
152 {
153 #[cfg(feature = "log")]
154 ::log::warn!($s $(, $x)*);
155 #[cfg(feature = "defmt")]
156 ::defmt::warn!($s $(, $x)*);
157 #[cfg(not(any(feature = "log", feature="defmt")))]
158 let _ = ($( & $x ),*);
159 }
160 };
161}
162
163macro_rules! error {
164 ($s:literal $(, $x:expr)* $(,)?) => {
165 {
166 #[cfg(feature = "log")]
167 ::log::error!($s $(, $x)*);
168 #[cfg(feature = "defmt")]
169 ::defmt::error!($s $(, $x)*);
170 #[cfg(not(any(feature = "log", feature="defmt")))]
171 let _ = ($( & $x ),*);
172 }
173 };
174}
175
176#[cfg(feature = "defmt")]
177macro_rules! unwrap {
178 ($($x:tt)*) => {
179 ::defmt::unwrap!($($x)*)
180 };
181}
182
183#[cfg(not(feature = "defmt"))]
184macro_rules! unwrap {
185 ($arg:expr) => {
186 match $crate::fmt::Try::into_result($arg) {
187 ::core::result::Result::Ok(t) => t,
188 ::core::result::Result::Err(e) => {
189 ::core::panic!("unwrap of `{}` failed: {:?}", ::core::stringify!($arg), e);
190 }
191 }
192 };
193 ($arg:expr, $($msg:expr),+ $(,)? ) => {
194 match $crate::fmt::Try::into_result($arg) {
195 ::core::result::Result::Ok(t) => t,
196 ::core::result::Result::Err(e) => {
197 ::core::panic!("unwrap of `{}` failed: {}: {:?}", ::core::stringify!($arg), ::core::format_args!($($msg,)*), e);
198 }
199 }
200 }
201}
202
203#[derive(Debug, Copy, Clone, Eq, PartialEq)]
204pub struct NoneError;
205
206pub trait Try {
207 type Ok;
208 type Error;
209 fn into_result(self) -> Result<Self::Ok, Self::Error>;
210}
211
212impl<T> Try for Option<T> {
213 type Ok = T;
214 type Error = NoneError;
215
216 #[inline]
217 fn into_result(self) -> Result<T, NoneError> {
218 self.ok_or(NoneError)
219 }
220}
221
222impl<T, E> Try for Result<T, E> {
223 type Ok = T;
224 type Error = E;
225
226 #[inline]
227 fn into_result(self) -> Self {
228 self
229 }
230}
231
232pub(crate) struct Bytes<'a>(pub &'a [u8]);
233
234impl<'a> Debug for Bytes<'a> {
235 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
236 write!(f, "{:#02x?}", self.0)
237 }
238}
239
240impl<'a> Display for Bytes<'a> {
241 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
242 write!(f, "{:#02x?}", self.0)
243 }
244}
245
246impl<'a> LowerHex for Bytes<'a> {
247 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
248 write!(f, "{:#02x?}", self.0)
249 }
250}
251
252#[cfg(feature = "defmt")]
253impl<'a> defmt::Format for Bytes<'a> {
254 fn format(&self, fmt: defmt::Formatter) {
255 defmt::write!(fmt, "{:02x}", self.0)
256 }
257}
diff --git a/embassy-usb-synopsys-otg/src/lib.rs b/embassy-usb-synopsys-otg/src/lib.rs
new file mode 100644
index 000000000..6d6cc9b0f
--- /dev/null
+++ b/embassy-usb-synopsys-otg/src/lib.rs
@@ -0,0 +1,1300 @@
1#![cfg_attr(not(test), no_std)]
2#![allow(async_fn_in_trait)]
3#![doc = include_str!("../README.md")]
4#![warn(missing_docs)]
5
6// This must go FIRST so that all the other modules see its macros.
7mod fmt;
8
9use core::cell::UnsafeCell;
10use core::marker::PhantomData;
11use core::sync::atomic::{AtomicBool, AtomicU16, Ordering};
12use core::task::Poll;
13
14use embassy_sync::waitqueue::AtomicWaker;
15use embassy_usb_driver::{
16 Bus as _, Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointIn, EndpointInfo, EndpointOut,
17 EndpointType, Event, Unsupported,
18};
19use futures::future::poll_fn;
20
21pub mod otg_v1;
22
23use otg_v1::{regs, vals, Otg};
24
25/// Handle interrupts.
26pub unsafe fn on_interrupt(r: Otg, state: &State<{ MAX_EP_COUNT }>, ep_count: usize, quirk_setup_late_cnak: bool) {
27 let ints = r.gintsts().read();
28 if ints.wkupint() || ints.usbsusp() || ints.usbrst() || ints.enumdne() || ints.otgint() || ints.srqint() {
29 // Mask interrupts and notify `Bus` to process them
30 r.gintmsk().write(|_| {});
31 state.bus_waker.wake();
32 }
33
34 // Handle RX
35 while r.gintsts().read().rxflvl() {
36 let status = r.grxstsp().read();
37 trace!("=== status {:08x}", status.0);
38 let ep_num = status.epnum() as usize;
39 let len = status.bcnt() as usize;
40
41 assert!(ep_num < ep_count);
42
43 match status.pktstsd() {
44 vals::Pktstsd::SETUP_DATA_RX => {
45 trace!("SETUP_DATA_RX");
46 assert!(len == 8, "invalid SETUP packet length={}", len);
47 assert!(ep_num == 0, "invalid SETUP packet endpoint={}", ep_num);
48
49 // flushing TX if something stuck in control endpoint
50 if r.dieptsiz(ep_num).read().pktcnt() != 0 {
51 r.grstctl().modify(|w| {
52 w.set_txfnum(ep_num as _);
53 w.set_txfflsh(true);
54 });
55 while r.grstctl().read().txfflsh() {}
56 }
57
58 if state.ep0_setup_ready.load(Ordering::Relaxed) == false {
59 // SAFETY: exclusive access ensured by atomic bool
60 let data = unsafe { &mut *state.ep0_setup_data.get() };
61 data[0..4].copy_from_slice(&r.fifo(0).read().0.to_ne_bytes());
62 data[4..8].copy_from_slice(&r.fifo(0).read().0.to_ne_bytes());
63 state.ep0_setup_ready.store(true, Ordering::Release);
64 state.ep_out_wakers[0].wake();
65 } else {
66 error!("received SETUP before previous finished processing");
67 // discard FIFO
68 r.fifo(0).read();
69 r.fifo(0).read();
70 }
71 }
72 vals::Pktstsd::OUT_DATA_RX => {
73 trace!("OUT_DATA_RX ep={} len={}", ep_num, len);
74
75 if state.ep_out_size[ep_num].load(Ordering::Acquire) == EP_OUT_BUFFER_EMPTY {
76 // SAFETY: Buffer size is allocated to be equal to endpoint's maximum packet size
77 // We trust the peripheral to not exceed its configured MPSIZ
78 let buf = unsafe { core::slice::from_raw_parts_mut(*state.ep_out_buffers[ep_num].get(), len) };
79
80 for chunk in buf.chunks_mut(4) {
81 // RX FIFO is shared so always read from fifo(0)
82 let data = r.fifo(0).read().0;
83 chunk.copy_from_slice(&data.to_ne_bytes()[0..chunk.len()]);
84 }
85
86 state.ep_out_size[ep_num].store(len as u16, Ordering::Release);
87 state.ep_out_wakers[ep_num].wake();
88 } else {
89 error!("ep_out buffer overflow index={}", ep_num);
90
91 // discard FIFO data
92 let len_words = (len + 3) / 4;
93 for _ in 0..len_words {
94 r.fifo(0).read().data();
95 }
96 }
97 }
98 vals::Pktstsd::OUT_DATA_DONE => {
99 trace!("OUT_DATA_DONE ep={}", ep_num);
100 }
101 vals::Pktstsd::SETUP_DATA_DONE => {
102 trace!("SETUP_DATA_DONE ep={}", ep_num);
103
104 if quirk_setup_late_cnak {
105 // Clear NAK to indicate we are ready to receive more data
106 r.doepctl(ep_num).modify(|w| w.set_cnak(true));
107 }
108 }
109 x => trace!("unknown PKTSTS: {}", x.to_bits()),
110 }
111 }
112
113 // IN endpoint interrupt
114 if ints.iepint() {
115 let mut ep_mask = r.daint().read().iepint();
116 let mut ep_num = 0;
117
118 // Iterate over endpoints while there are non-zero bits in the mask
119 while ep_mask != 0 {
120 if ep_mask & 1 != 0 {
121 let ep_ints = r.diepint(ep_num).read();
122
123 // clear all
124 r.diepint(ep_num).write_value(ep_ints);
125
126 // TXFE is cleared in DIEPEMPMSK
127 if ep_ints.txfe() {
128 critical_section::with(|_| {
129 r.diepempmsk().modify(|w| {
130 w.set_ineptxfem(w.ineptxfem() & !(1 << ep_num));
131 });
132 });
133 }
134
135 state.ep_in_wakers[ep_num].wake();
136 trace!("in ep={} irq val={:08x}", ep_num, ep_ints.0);
137 }
138
139 ep_mask >>= 1;
140 ep_num += 1;
141 }
142 }
143
144 // not needed? reception handled in rxflvl
145 // OUT endpoint interrupt
146 // if ints.oepint() {
147 // let mut ep_mask = r.daint().read().oepint();
148 // let mut ep_num = 0;
149
150 // while ep_mask != 0 {
151 // if ep_mask & 1 != 0 {
152 // let ep_ints = r.doepint(ep_num).read();
153 // // clear all
154 // r.doepint(ep_num).write_value(ep_ints);
155 // state.ep_out_wakers[ep_num].wake();
156 // trace!("out ep={} irq val={:08x}", ep_num, ep_ints.0);
157 // }
158
159 // ep_mask >>= 1;
160 // ep_num += 1;
161 // }
162 // }
163}
164
165/// USB PHY type
166#[derive(Copy, Clone, Debug, Eq, PartialEq)]
167pub enum PhyType {
168 /// Internal Full-Speed PHY
169 ///
170 /// Available on most High-Speed peripherals.
171 InternalFullSpeed,
172 /// Internal High-Speed PHY
173 ///
174 /// Available on a few STM32 chips.
175 InternalHighSpeed,
176 /// External ULPI High-Speed PHY
177 ExternalHighSpeed,
178}
179
180impl PhyType {
181 /// Get whether this PHY is any of the internal types.
182 pub fn internal(&self) -> bool {
183 match self {
184 PhyType::InternalFullSpeed | PhyType::InternalHighSpeed => true,
185 PhyType::ExternalHighSpeed => false,
186 }
187 }
188
189 /// Get whether this PHY is any of the high-speed types.
190 pub fn high_speed(&self) -> bool {
191 match self {
192 PhyType::InternalFullSpeed => false,
193 PhyType::ExternalHighSpeed | PhyType::InternalHighSpeed => true,
194 }
195 }
196
197 fn to_dspd(&self) -> vals::Dspd {
198 match self {
199 PhyType::InternalFullSpeed => vals::Dspd::FULL_SPEED_INTERNAL,
200 PhyType::InternalHighSpeed => vals::Dspd::HIGH_SPEED,
201 PhyType::ExternalHighSpeed => vals::Dspd::HIGH_SPEED,
202 }
203 }
204}
205
206/// Indicates that [State::ep_out_buffers] is empty.
207const EP_OUT_BUFFER_EMPTY: u16 = u16::MAX;
208
209/// USB OTG driver state.
210pub struct State<const EP_COUNT: usize> {
211 /// Holds received SETUP packets. Available if [State::ep0_setup_ready] is true.
212 ep0_setup_data: UnsafeCell<[u8; 8]>,
213 ep0_setup_ready: AtomicBool,
214 ep_in_wakers: [AtomicWaker; EP_COUNT],
215 ep_out_wakers: [AtomicWaker; EP_COUNT],
216 /// RX FIFO is shared so extra buffers are needed to dequeue all data without waiting on each endpoint.
217 /// Buffers are ready when associated [State::ep_out_size] != [EP_OUT_BUFFER_EMPTY].
218 ep_out_buffers: [UnsafeCell<*mut u8>; EP_COUNT],
219 ep_out_size: [AtomicU16; EP_COUNT],
220 bus_waker: AtomicWaker,
221}
222
223unsafe impl<const EP_COUNT: usize> Send for State<EP_COUNT> {}
224unsafe impl<const EP_COUNT: usize> Sync for State<EP_COUNT> {}
225
226impl<const EP_COUNT: usize> State<EP_COUNT> {
227 /// Create a new State.
228 pub const fn new() -> Self {
229 const NEW_AW: AtomicWaker = AtomicWaker::new();
230 const NEW_BUF: UnsafeCell<*mut u8> = UnsafeCell::new(0 as _);
231 const NEW_SIZE: AtomicU16 = AtomicU16::new(EP_OUT_BUFFER_EMPTY);
232
233 Self {
234 ep0_setup_data: UnsafeCell::new([0u8; 8]),
235 ep0_setup_ready: AtomicBool::new(false),
236 ep_in_wakers: [NEW_AW; EP_COUNT],
237 ep_out_wakers: [NEW_AW; EP_COUNT],
238 ep_out_buffers: [NEW_BUF; EP_COUNT],
239 ep_out_size: [NEW_SIZE; EP_COUNT],
240 bus_waker: NEW_AW,
241 }
242 }
243}
244
245#[derive(Debug, Clone, Copy)]
246struct EndpointData {
247 ep_type: EndpointType,
248 max_packet_size: u16,
249 fifo_size_words: u16,
250}
251
252/// USB driver config.
253#[non_exhaustive]
254#[derive(Clone, Copy, PartialEq, Eq, Debug)]
255pub struct Config {
256 /// Enable VBUS detection.
257 ///
258 /// The USB spec requires USB devices monitor for USB cable plug/unplug and react accordingly.
259 /// This is done by checking whether there is 5V on the VBUS pin or not.
260 ///
261 /// If your device is bus-powered (powers itself from the USB host via VBUS), then this is optional.
262 /// (If there's no power in VBUS your device would be off anyway, so it's fine to always assume
263 /// there's power in VBUS, i.e. the USB cable is always plugged in.)
264 ///
265 /// If your device is self-powered (i.e. it gets power from a source other than the USB cable, and
266 /// therefore can stay powered through USB cable plug/unplug) then you MUST set this to true.
267 ///
268 /// If you set this to true, you must connect VBUS to PA9 for FS, PB13 for HS, possibly with a
269 /// voltage divider. See ST application note AN4879 and the reference manual for more details.
270 pub vbus_detection: bool,
271}
272
273impl Default for Config {
274 fn default() -> Self {
275 Self { vbus_detection: true }
276 }
277}
278
279/// USB driver.
280pub struct Driver<'d> {
281 config: Config,
282 ep_in: [Option<EndpointData>; MAX_EP_COUNT],
283 ep_out: [Option<EndpointData>; MAX_EP_COUNT],
284 ep_out_buffer: &'d mut [u8],
285 ep_out_buffer_offset: usize,
286 instance: OtgInstance<'d>,
287}
288
289impl<'d> Driver<'d> {
290 /// Initializes USB OTG peripheral.
291 ///
292 /// # Arguments
293 ///
294 /// * `ep_out_buffer` - An internal buffer used to temporarily store received packets.
295 /// Must be large enough to fit all OUT endpoint max packet sizes.
296 /// Endpoint allocation will fail if it is too small.
297 pub fn new(ep_out_buffer: &'d mut [u8], instance: OtgInstance<'d>, config: Config) -> Self {
298 Self {
299 config,
300 ep_in: [None; MAX_EP_COUNT],
301 ep_out: [None; MAX_EP_COUNT],
302 ep_out_buffer,
303 ep_out_buffer_offset: 0,
304 instance,
305 }
306 }
307
308 // Returns total amount of words (u32) allocated in dedicated FIFO
309 fn allocated_fifo_words(&self) -> u16 {
310 self.instance.extra_rx_fifo_words + ep_fifo_size(&self.ep_out) + ep_fifo_size(&self.ep_in)
311 }
312
313 /// Creates an [`Endpoint`] with the given parameters.
314 pub fn alloc_endpoint<D: Dir>(
315 &mut self,
316 ep_type: EndpointType,
317 max_packet_size: u16,
318 interval_ms: u8,
319 ) -> Result<Endpoint<'d, D>, EndpointAllocError> {
320 trace!(
321 "allocating type={:?} mps={:?} interval_ms={}, dir={:?}",
322 ep_type,
323 max_packet_size,
324 interval_ms,
325 D::dir()
326 );
327
328 if D::dir() == Direction::Out {
329 if self.ep_out_buffer_offset + max_packet_size as usize >= self.ep_out_buffer.len() {
330 error!("Not enough endpoint out buffer capacity");
331 return Err(EndpointAllocError);
332 }
333 };
334
335 let fifo_size_words = match D::dir() {
336 Direction::Out => (max_packet_size + 3) / 4,
337 // INEPTXFD requires minimum size of 16 words
338 Direction::In => u16::max((max_packet_size + 3) / 4, 16),
339 };
340
341 if fifo_size_words + self.allocated_fifo_words() > self.instance.fifo_depth_words {
342 error!("Not enough FIFO capacity");
343 return Err(EndpointAllocError);
344 }
345
346 let eps = match D::dir() {
347 Direction::Out => &mut self.ep_out,
348 Direction::In => &mut self.ep_in,
349 };
350
351 // Find free endpoint slot
352 let slot = eps.iter_mut().enumerate().find(|(i, ep)| {
353 if *i == 0 && ep_type != EndpointType::Control {
354 // reserved for control pipe
355 false
356 } else {
357 ep.is_none()
358 }
359 });
360
361 let index = match slot {
362 Some((index, ep)) => {
363 *ep = Some(EndpointData {
364 ep_type,
365 max_packet_size,
366 fifo_size_words,
367 });
368 index
369 }
370 None => {
371 error!("No free endpoints available");
372 return Err(EndpointAllocError);
373 }
374 };
375
376 trace!(" index={}", index);
377
378 if D::dir() == Direction::Out {
379 // Buffer capacity check was done above, now allocation cannot fail
380 unsafe {
381 *self.instance.state.ep_out_buffers[index].get() =
382 self.ep_out_buffer.as_mut_ptr().offset(self.ep_out_buffer_offset as _);
383 }
384 self.ep_out_buffer_offset += max_packet_size as usize;
385 }
386
387 Ok(Endpoint {
388 _phantom: PhantomData,
389 regs: self.instance.regs,
390 state: self.instance.state,
391 info: EndpointInfo {
392 addr: EndpointAddress::from_parts(index, D::dir()),
393 ep_type,
394 max_packet_size,
395 interval_ms,
396 },
397 })
398 }
399}
400
401impl<'d> embassy_usb_driver::Driver<'d> for Driver<'d> {
402 type EndpointOut = Endpoint<'d, Out>;
403 type EndpointIn = Endpoint<'d, In>;
404 type ControlPipe = ControlPipe<'d>;
405 type Bus = Bus<'d>;
406
407 fn alloc_endpoint_in(
408 &mut self,
409 ep_type: EndpointType,
410 max_packet_size: u16,
411 interval_ms: u8,
412 ) -> Result<Self::EndpointIn, EndpointAllocError> {
413 self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
414 }
415
416 fn alloc_endpoint_out(
417 &mut self,
418 ep_type: EndpointType,
419 max_packet_size: u16,
420 interval_ms: u8,
421 ) -> Result<Self::EndpointOut, EndpointAllocError> {
422 self.alloc_endpoint(ep_type, max_packet_size, interval_ms)
423 }
424
425 fn start(mut self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
426 let ep_out = self
427 .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
428 .unwrap();
429 let ep_in = self
430 .alloc_endpoint(EndpointType::Control, control_max_packet_size, 0)
431 .unwrap();
432 assert_eq!(ep_out.info.addr.index(), 0);
433 assert_eq!(ep_in.info.addr.index(), 0);
434
435 trace!("start");
436
437 let regs = self.instance.regs;
438 let quirk_setup_late_cnak = self.instance.quirk_setup_late_cnak;
439 (
440 Bus {
441 config: self.config,
442 ep_in: self.ep_in,
443 ep_out: self.ep_out,
444 inited: false,
445 instance: self.instance,
446 },
447 ControlPipe {
448 max_packet_size: control_max_packet_size,
449 ep_out,
450 ep_in,
451 regs,
452 quirk_setup_late_cnak,
453 },
454 )
455 }
456}
457
458/// USB bus.
459pub struct Bus<'d> {
460 config: Config,
461 ep_in: [Option<EndpointData>; MAX_EP_COUNT],
462 ep_out: [Option<EndpointData>; MAX_EP_COUNT],
463 instance: OtgInstance<'d>,
464 inited: bool,
465}
466
467impl<'d> Bus<'d> {
468 fn restore_irqs(&mut self) {
469 self.instance.regs.gintmsk().write(|w| {
470 w.set_usbrst(true);
471 w.set_enumdnem(true);
472 w.set_usbsuspm(true);
473 w.set_wuim(true);
474 w.set_iepint(true);
475 w.set_oepint(true);
476 w.set_rxflvlm(true);
477 w.set_srqim(true);
478 w.set_otgint(true);
479 });
480 }
481}
482
483impl<'d> Bus<'d> {
484 /// Returns the PHY type.
485 pub fn phy_type(&self) -> PhyType {
486 self.instance.phy_type
487 }
488
489 /// Configures the PHY as a device.
490 pub fn configure_as_device(&mut self) {
491 let r = self.instance.regs;
492 let phy_type = self.instance.phy_type;
493 r.gusbcfg().write(|w| {
494 // Force device mode
495 w.set_fdmod(true);
496 // Enable internal full-speed PHY
497 w.set_physel(phy_type.internal() && !phy_type.high_speed());
498 });
499 }
500
501 /// Applies configuration specific to
502 /// Core ID 0x0000_1100 and 0x0000_1200
503 pub fn config_v1(&mut self) {
504 let r = self.instance.regs;
505 let phy_type = self.instance.phy_type;
506 assert!(phy_type != PhyType::InternalHighSpeed);
507
508 r.gccfg_v1().modify(|w| {
509 // Enable internal full-speed PHY, logic is inverted
510 w.set_pwrdwn(phy_type.internal());
511 });
512
513 // F429-like chips have the GCCFG.NOVBUSSENS bit
514 r.gccfg_v1().modify(|w| {
515 w.set_novbussens(!self.config.vbus_detection);
516 w.set_vbusasen(false);
517 w.set_vbusbsen(self.config.vbus_detection);
518 w.set_sofouten(false);
519 });
520 }
521
522 /// Applies configuration specific to
523 /// Core ID 0x0000_2000, 0x0000_2100, 0x0000_2300, 0x0000_3000 and 0x0000_3100
524 pub fn config_v2v3(&mut self) {
525 let r = self.instance.regs;
526 let phy_type = self.instance.phy_type;
527
528 // F446-like chips have the GCCFG.VBDEN bit with the opposite meaning
529 r.gccfg_v2().modify(|w| {
530 // Enable internal full-speed PHY, logic is inverted
531 w.set_pwrdwn(phy_type.internal() && !phy_type.high_speed());
532 w.set_phyhsen(phy_type.internal() && phy_type.high_speed());
533 });
534
535 r.gccfg_v2().modify(|w| {
536 w.set_vbden(self.config.vbus_detection);
537 });
538
539 // Force B-peripheral session
540 r.gotgctl().modify(|w| {
541 w.set_bvaloen(!self.config.vbus_detection);
542 w.set_bvaloval(true);
543 });
544 }
545
546 fn init(&mut self) {
547 let r = self.instance.regs;
548 let phy_type = self.instance.phy_type;
549
550 // Soft disconnect.
551 r.dctl().write(|w| w.set_sdis(true));
552
553 // Set speed.
554 r.dcfg().write(|w| {
555 w.set_pfivl(vals::Pfivl::FRAME_INTERVAL_80);
556 w.set_dspd(phy_type.to_dspd());
557 });
558
559 // Unmask transfer complete EP interrupt
560 r.diepmsk().write(|w| {
561 w.set_xfrcm(true);
562 });
563
564 // Unmask and clear core interrupts
565 self.restore_irqs();
566 r.gintsts().write_value(regs::Gintsts(0xFFFF_FFFF));
567
568 // Unmask global interrupt
569 r.gahbcfg().write(|w| {
570 w.set_gint(true); // unmask global interrupt
571 });
572
573 // Connect
574 r.dctl().write(|w| w.set_sdis(false));
575 }
576
577 fn init_fifo(&mut self) {
578 trace!("init_fifo");
579
580 let regs = self.instance.regs;
581 // ERRATA NOTE: Don't interrupt FIFOs being written to. The interrupt
582 // handler COULD interrupt us here and do FIFO operations, so ensure
583 // the interrupt does not occur.
584 critical_section::with(|_| {
585 // Configure RX fifo size. All endpoints share the same FIFO area.
586 let rx_fifo_size_words = self.instance.extra_rx_fifo_words + ep_fifo_size(&self.ep_out);
587 trace!("configuring rx fifo size={}", rx_fifo_size_words);
588
589 regs.grxfsiz().modify(|w| w.set_rxfd(rx_fifo_size_words));
590
591 // Configure TX (USB in direction) fifo size for each endpoint
592 let mut fifo_top = rx_fifo_size_words;
593 for i in 0..self.instance.endpoint_count {
594 if let Some(ep) = self.ep_in[i] {
595 trace!(
596 "configuring tx fifo ep={}, offset={}, size={}",
597 i,
598 fifo_top,
599 ep.fifo_size_words
600 );
601
602 let dieptxf = if i == 0 { regs.dieptxf0() } else { regs.dieptxf(i - 1) };
603
604 dieptxf.write(|w| {
605 w.set_fd(ep.fifo_size_words);
606 w.set_sa(fifo_top);
607 });
608
609 fifo_top += ep.fifo_size_words;
610 }
611 }
612
613 assert!(
614 fifo_top <= self.instance.fifo_depth_words,
615 "FIFO allocations exceeded maximum capacity"
616 );
617
618 // Flush fifos
619 regs.grstctl().write(|w| {
620 w.set_rxfflsh(true);
621 w.set_txfflsh(true);
622 w.set_txfnum(0x10);
623 });
624 });
625
626 loop {
627 let x = regs.grstctl().read();
628 if !x.rxfflsh() && !x.txfflsh() {
629 break;
630 }
631 }
632 }
633
634 fn configure_endpoints(&mut self) {
635 trace!("configure_endpoints");
636
637 let regs = self.instance.regs;
638
639 // Configure IN endpoints
640 for (index, ep) in self.ep_in.iter().enumerate() {
641 if let Some(ep) = ep {
642 critical_section::with(|_| {
643 regs.diepctl(index).write(|w| {
644 if index == 0 {
645 w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
646 } else {
647 w.set_mpsiz(ep.max_packet_size);
648 w.set_eptyp(to_eptyp(ep.ep_type));
649 w.set_sd0pid_sevnfrm(true);
650 w.set_txfnum(index as _);
651 w.set_snak(true);
652 }
653 });
654 });
655 }
656 }
657
658 // Configure OUT endpoints
659 for (index, ep) in self.ep_out.iter().enumerate() {
660 if let Some(ep) = ep {
661 critical_section::with(|_| {
662 regs.doepctl(index).write(|w| {
663 if index == 0 {
664 w.set_mpsiz(ep0_mpsiz(ep.max_packet_size));
665 } else {
666 w.set_mpsiz(ep.max_packet_size);
667 w.set_eptyp(to_eptyp(ep.ep_type));
668 w.set_sd0pid_sevnfrm(true);
669 }
670 });
671
672 regs.doeptsiz(index).modify(|w| {
673 w.set_xfrsiz(ep.max_packet_size as _);
674 if index == 0 {
675 w.set_rxdpid_stupcnt(1);
676 } else {
677 w.set_pktcnt(1);
678 }
679 });
680 });
681 }
682 }
683
684 // Enable IRQs for allocated endpoints
685 regs.daintmsk().modify(|w| {
686 w.set_iepm(ep_irq_mask(&self.ep_in));
687 // OUT interrupts not used, handled in RXFLVL
688 // w.set_oepm(ep_irq_mask(&self.ep_out));
689 });
690 }
691
692 fn disable_all_endpoints(&mut self) {
693 for i in 0..self.instance.endpoint_count {
694 self.endpoint_set_enabled(EndpointAddress::from_parts(i, Direction::In), false);
695 self.endpoint_set_enabled(EndpointAddress::from_parts(i, Direction::Out), false);
696 }
697 }
698}
699
700impl<'d> embassy_usb_driver::Bus for Bus<'d> {
701 async fn poll(&mut self) -> Event {
702 poll_fn(move |cx| {
703 if !self.inited {
704 self.init();
705 self.inited = true;
706
707 // If no vbus detection, just return a single PowerDetected event at startup.
708 if !self.config.vbus_detection {
709 return Poll::Ready(Event::PowerDetected);
710 }
711 }
712
713 let regs = self.instance.regs;
714 self.instance.state.bus_waker.register(cx.waker());
715
716 let ints = regs.gintsts().read();
717
718 if ints.srqint() {
719 trace!("vbus detected");
720
721 regs.gintsts().write(|w| w.set_srqint(true)); // clear
722 self.restore_irqs();
723
724 if self.config.vbus_detection {
725 return Poll::Ready(Event::PowerDetected);
726 }
727 }
728
729 if ints.otgint() {
730 let otgints = regs.gotgint().read();
731 regs.gotgint().write_value(otgints); // clear all
732 self.restore_irqs();
733
734 if otgints.sedet() {
735 trace!("vbus removed");
736 if self.config.vbus_detection {
737 self.disable_all_endpoints();
738 return Poll::Ready(Event::PowerRemoved);
739 }
740 }
741 }
742
743 if ints.usbrst() {
744 trace!("reset");
745
746 self.init_fifo();
747 self.configure_endpoints();
748
749 // Reset address
750 critical_section::with(|_| {
751 regs.dcfg().modify(|w| {
752 w.set_dad(0);
753 });
754 });
755
756 regs.gintsts().write(|w| w.set_usbrst(true)); // clear
757 self.restore_irqs();
758 }
759
760 if ints.enumdne() {
761 trace!("enumdne");
762
763 let speed = regs.dsts().read().enumspd();
764 let trdt = (self.instance.calculate_trdt_fn)(speed);
765 trace!(" speed={} trdt={}", speed.to_bits(), trdt);
766 regs.gusbcfg().modify(|w| w.set_trdt(trdt));
767
768 regs.gintsts().write(|w| w.set_enumdne(true)); // clear
769 self.restore_irqs();
770
771 return Poll::Ready(Event::Reset);
772 }
773
774 if ints.usbsusp() {
775 trace!("suspend");
776 regs.gintsts().write(|w| w.set_usbsusp(true)); // clear
777 self.restore_irqs();
778 return Poll::Ready(Event::Suspend);
779 }
780
781 if ints.wkupint() {
782 trace!("resume");
783 regs.gintsts().write(|w| w.set_wkupint(true)); // clear
784 self.restore_irqs();
785 return Poll::Ready(Event::Resume);
786 }
787
788 Poll::Pending
789 })
790 .await
791 }
792
793 fn endpoint_set_stalled(&mut self, ep_addr: EndpointAddress, stalled: bool) {
794 trace!("endpoint_set_stalled ep={:?} en={}", ep_addr, stalled);
795
796 assert!(
797 ep_addr.index() < self.instance.endpoint_count,
798 "endpoint_set_stalled index {} out of range",
799 ep_addr.index()
800 );
801
802 let regs = self.instance.regs;
803 let state = self.instance.state;
804 match ep_addr.direction() {
805 Direction::Out => {
806 critical_section::with(|_| {
807 regs.doepctl(ep_addr.index()).modify(|w| {
808 w.set_stall(stalled);
809 });
810 });
811
812 state.ep_out_wakers[ep_addr.index()].wake();
813 }
814 Direction::In => {
815 critical_section::with(|_| {
816 regs.diepctl(ep_addr.index()).modify(|w| {
817 w.set_stall(stalled);
818 });
819 });
820
821 state.ep_in_wakers[ep_addr.index()].wake();
822 }
823 }
824 }
825
826 fn endpoint_is_stalled(&mut self, ep_addr: EndpointAddress) -> bool {
827 assert!(
828 ep_addr.index() < self.instance.endpoint_count,
829 "endpoint_is_stalled index {} out of range",
830 ep_addr.index()
831 );
832
833 let regs = self.instance.regs;
834 match ep_addr.direction() {
835 Direction::Out => regs.doepctl(ep_addr.index()).read().stall(),
836 Direction::In => regs.diepctl(ep_addr.index()).read().stall(),
837 }
838 }
839
840 fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
841 trace!("endpoint_set_enabled ep={:?} en={}", ep_addr, enabled);
842
843 assert!(
844 ep_addr.index() < self.instance.endpoint_count,
845 "endpoint_set_enabled index {} out of range",
846 ep_addr.index()
847 );
848
849 let regs = self.instance.regs;
850 let state = self.instance.state;
851 match ep_addr.direction() {
852 Direction::Out => {
853 critical_section::with(|_| {
854 // cancel transfer if active
855 if !enabled && regs.doepctl(ep_addr.index()).read().epena() {
856 regs.doepctl(ep_addr.index()).modify(|w| {
857 w.set_snak(true);
858 w.set_epdis(true);
859 })
860 }
861
862 regs.doepctl(ep_addr.index()).modify(|w| {
863 w.set_usbaep(enabled);
864 });
865
866 // Flush tx fifo
867 regs.grstctl().write(|w| {
868 w.set_txfflsh(true);
869 w.set_txfnum(ep_addr.index() as _);
870 });
871 loop {
872 let x = regs.grstctl().read();
873 if !x.txfflsh() {
874 break;
875 }
876 }
877 });
878
879 // Wake `Endpoint::wait_enabled()`
880 state.ep_out_wakers[ep_addr.index()].wake();
881 }
882 Direction::In => {
883 critical_section::with(|_| {
884 // cancel transfer if active
885 if !enabled && regs.diepctl(ep_addr.index()).read().epena() {
886 regs.diepctl(ep_addr.index()).modify(|w| {
887 w.set_snak(true); // set NAK
888 w.set_epdis(true);
889 })
890 }
891
892 regs.diepctl(ep_addr.index()).modify(|w| {
893 w.set_usbaep(enabled);
894 w.set_cnak(enabled); // clear NAK that might've been set by SNAK above.
895 })
896 });
897
898 // Wake `Endpoint::wait_enabled()`
899 state.ep_in_wakers[ep_addr.index()].wake();
900 }
901 }
902 }
903
904 async fn enable(&mut self) {
905 trace!("enable");
906 // TODO: enable the peripheral once enable/disable semantics are cleared up in embassy-usb
907 }
908
909 async fn disable(&mut self) {
910 trace!("disable");
911
912 // TODO: disable the peripheral once enable/disable semantics are cleared up in embassy-usb
913 //Bus::disable(self);
914 }
915
916 async fn remote_wakeup(&mut self) -> Result<(), Unsupported> {
917 Err(Unsupported)
918 }
919}
920
921/// USB endpoint direction.
922pub trait Dir {
923 /// Returns the direction value.
924 fn dir() -> Direction;
925}
926
927/// Marker type for the "IN" direction.
928pub enum In {}
929impl Dir for In {
930 fn dir() -> Direction {
931 Direction::In
932 }
933}
934
935/// Marker type for the "OUT" direction.
936pub enum Out {}
937impl Dir for Out {
938 fn dir() -> Direction {
939 Direction::Out
940 }
941}
942
943/// USB endpoint.
944pub struct Endpoint<'d, D> {
945 _phantom: PhantomData<D>,
946 regs: Otg,
947 info: EndpointInfo,
948 state: &'d State<{ MAX_EP_COUNT }>,
949}
950
951impl<'d> embassy_usb_driver::Endpoint for Endpoint<'d, In> {
952 fn info(&self) -> &EndpointInfo {
953 &self.info
954 }
955
956 async fn wait_enabled(&mut self) {
957 poll_fn(|cx| {
958 let ep_index = self.info.addr.index();
959
960 self.state.ep_in_wakers[ep_index].register(cx.waker());
961
962 if self.regs.diepctl(ep_index).read().usbaep() {
963 Poll::Ready(())
964 } else {
965 Poll::Pending
966 }
967 })
968 .await
969 }
970}
971
972impl<'d> embassy_usb_driver::Endpoint for Endpoint<'d, Out> {
973 fn info(&self) -> &EndpointInfo {
974 &self.info
975 }
976
977 async fn wait_enabled(&mut self) {
978 poll_fn(|cx| {
979 let ep_index = self.info.addr.index();
980
981 self.state.ep_out_wakers[ep_index].register(cx.waker());
982
983 if self.regs.doepctl(ep_index).read().usbaep() {
984 Poll::Ready(())
985 } else {
986 Poll::Pending
987 }
988 })
989 .await
990 }
991}
992
993impl<'d> embassy_usb_driver::EndpointOut for Endpoint<'d, Out> {
994 async fn read(&mut self, buf: &mut [u8]) -> Result<usize, EndpointError> {
995 trace!("read start len={}", buf.len());
996
997 poll_fn(|cx| {
998 let index = self.info.addr.index();
999 self.state.ep_out_wakers[index].register(cx.waker());
1000
1001 let doepctl = self.regs.doepctl(index).read();
1002 trace!("read ep={:?}: doepctl {:08x}", self.info.addr, doepctl.0,);
1003 if !doepctl.usbaep() {
1004 trace!("read ep={:?} error disabled", self.info.addr);
1005 return Poll::Ready(Err(EndpointError::Disabled));
1006 }
1007
1008 let len = self.state.ep_out_size[index].load(Ordering::Relaxed);
1009 if len != EP_OUT_BUFFER_EMPTY {
1010 trace!("read ep={:?} done len={}", self.info.addr, len);
1011
1012 if len as usize > buf.len() {
1013 return Poll::Ready(Err(EndpointError::BufferOverflow));
1014 }
1015
1016 // SAFETY: exclusive access ensured by `ep_out_size` atomic variable
1017 let data =
1018 unsafe { core::slice::from_raw_parts(*self.state.ep_out_buffers[index].get(), len as usize) };
1019 buf[..len as usize].copy_from_slice(data);
1020
1021 // Release buffer
1022 self.state.ep_out_size[index].store(EP_OUT_BUFFER_EMPTY, Ordering::Release);
1023
1024 critical_section::with(|_| {
1025 // Receive 1 packet
1026 self.regs.doeptsiz(index).modify(|w| {
1027 w.set_xfrsiz(self.info.max_packet_size as _);
1028 w.set_pktcnt(1);
1029 });
1030
1031 // Clear NAK to indicate we are ready to receive more data
1032 self.regs.doepctl(index).modify(|w| {
1033 w.set_cnak(true);
1034 });
1035 });
1036
1037 Poll::Ready(Ok(len as usize))
1038 } else {
1039 Poll::Pending
1040 }
1041 })
1042 .await
1043 }
1044}
1045
1046impl<'d> embassy_usb_driver::EndpointIn for Endpoint<'d, In> {
1047 async fn write(&mut self, buf: &[u8]) -> Result<(), EndpointError> {
1048 trace!("write ep={:?} data={:?}", self.info.addr, buf);
1049
1050 if buf.len() > self.info.max_packet_size as usize {
1051 return Err(EndpointError::BufferOverflow);
1052 }
1053
1054 let index = self.info.addr.index();
1055 // Wait for previous transfer to complete and check if endpoint is disabled
1056 poll_fn(|cx| {
1057 self.state.ep_in_wakers[index].register(cx.waker());
1058
1059 let diepctl = self.regs.diepctl(index).read();
1060 let dtxfsts = self.regs.dtxfsts(index).read();
1061 trace!(
1062 "write ep={:?}: diepctl {:08x} ftxfsts {:08x}",
1063 self.info.addr,
1064 diepctl.0,
1065 dtxfsts.0
1066 );
1067 if !diepctl.usbaep() {
1068 trace!("write ep={:?} wait for prev: error disabled", self.info.addr);
1069 Poll::Ready(Err(EndpointError::Disabled))
1070 } else if !diepctl.epena() {
1071 trace!("write ep={:?} wait for prev: ready", self.info.addr);
1072 Poll::Ready(Ok(()))
1073 } else {
1074 trace!("write ep={:?} wait for prev: pending", self.info.addr);
1075 Poll::Pending
1076 }
1077 })
1078 .await?;
1079
1080 if buf.len() > 0 {
1081 poll_fn(|cx| {
1082 self.state.ep_in_wakers[index].register(cx.waker());
1083
1084 let size_words = (buf.len() + 3) / 4;
1085
1086 let fifo_space = self.regs.dtxfsts(index).read().ineptfsav() as usize;
1087 if size_words > fifo_space {
1088 // Not enough space in fifo, enable tx fifo empty interrupt
1089 critical_section::with(|_| {
1090 self.regs.diepempmsk().modify(|w| {
1091 w.set_ineptxfem(w.ineptxfem() | (1 << index));
1092 });
1093 });
1094
1095 trace!("tx fifo for ep={} full, waiting for txfe", index);
1096
1097 Poll::Pending
1098 } else {
1099 trace!("write ep={:?} wait for fifo: ready", self.info.addr);
1100 Poll::Ready(())
1101 }
1102 })
1103 .await
1104 }
1105
1106 // ERRATA: Transmit data FIFO is corrupted when a write sequence to the FIFO is interrupted with
1107 // accesses to certain OTG_FS registers.
1108 //
1109 // Prevent the interrupt (which might poke FIFOs) from executing while copying data to FIFOs.
1110 critical_section::with(|_| {
1111 // Setup transfer size
1112 self.regs.dieptsiz(index).write(|w| {
1113 w.set_mcnt(1);
1114 w.set_pktcnt(1);
1115 w.set_xfrsiz(buf.len() as _);
1116 });
1117
1118 // Enable endpoint
1119 self.regs.diepctl(index).modify(|w| {
1120 w.set_cnak(true);
1121 w.set_epena(true);
1122 });
1123
1124 // Write data to FIFO
1125 for chunk in buf.chunks(4) {
1126 let mut tmp = [0u8; 4];
1127 tmp[0..chunk.len()].copy_from_slice(chunk);
1128 self.regs.fifo(index).write_value(regs::Fifo(u32::from_ne_bytes(tmp)));
1129 }
1130 });
1131
1132 trace!("write done ep={:?}", self.info.addr);
1133
1134 Ok(())
1135 }
1136}
1137
1138/// USB control pipe.
1139pub struct ControlPipe<'d> {
1140 max_packet_size: u16,
1141 regs: Otg,
1142 ep_in: Endpoint<'d, In>,
1143 ep_out: Endpoint<'d, Out>,
1144 quirk_setup_late_cnak: bool,
1145}
1146
1147impl<'d> embassy_usb_driver::ControlPipe for ControlPipe<'d> {
1148 fn max_packet_size(&self) -> usize {
1149 usize::from(self.max_packet_size)
1150 }
1151
1152 async fn setup(&mut self) -> [u8; 8] {
1153 poll_fn(|cx| {
1154 self.ep_out.state.ep_out_wakers[0].register(cx.waker());
1155
1156 if self.ep_out.state.ep0_setup_ready.load(Ordering::Relaxed) {
1157 let data = unsafe { *self.ep_out.state.ep0_setup_data.get() };
1158 self.ep_out.state.ep0_setup_ready.store(false, Ordering::Release);
1159
1160 // EP0 should not be controlled by `Bus` so this RMW does not need a critical section
1161 // Receive 1 SETUP packet
1162 self.regs.doeptsiz(self.ep_out.info.addr.index()).modify(|w| {
1163 w.set_rxdpid_stupcnt(1);
1164 });
1165
1166 // Clear NAK to indicate we are ready to receive more data
1167 if !self.quirk_setup_late_cnak {
1168 self.regs
1169 .doepctl(self.ep_out.info.addr.index())
1170 .modify(|w| w.set_cnak(true));
1171 }
1172
1173 trace!("SETUP received: {:?}", data);
1174 Poll::Ready(data)
1175 } else {
1176 trace!("SETUP waiting");
1177 Poll::Pending
1178 }
1179 })
1180 .await
1181 }
1182
1183 async fn data_out(&mut self, buf: &mut [u8], _first: bool, _last: bool) -> Result<usize, EndpointError> {
1184 trace!("control: data_out");
1185 let len = self.ep_out.read(buf).await?;
1186 trace!("control: data_out read: {:?}", &buf[..len]);
1187 Ok(len)
1188 }
1189
1190 async fn data_in(&mut self, data: &[u8], _first: bool, last: bool) -> Result<(), EndpointError> {
1191 trace!("control: data_in write: {:?}", data);
1192 self.ep_in.write(data).await?;
1193
1194 // wait for status response from host after sending the last packet
1195 if last {
1196 trace!("control: data_in waiting for status");
1197 self.ep_out.read(&mut []).await?;
1198 trace!("control: complete");
1199 }
1200
1201 Ok(())
1202 }
1203
1204 async fn accept(&mut self) {
1205 trace!("control: accept");
1206
1207 self.ep_in.write(&[]).await.ok();
1208
1209 trace!("control: accept OK");
1210 }
1211
1212 async fn reject(&mut self) {
1213 trace!("control: reject");
1214
1215 // EP0 should not be controlled by `Bus` so this RMW does not need a critical section
1216 self.regs.diepctl(self.ep_in.info.addr.index()).modify(|w| {
1217 w.set_stall(true);
1218 });
1219 self.regs.doepctl(self.ep_out.info.addr.index()).modify(|w| {
1220 w.set_stall(true);
1221 });
1222 }
1223
1224 async fn accept_set_address(&mut self, addr: u8) {
1225 trace!("setting addr: {}", addr);
1226 critical_section::with(|_| {
1227 self.regs.dcfg().modify(|w| {
1228 w.set_dad(addr);
1229 });
1230 });
1231
1232 // synopsys driver requires accept to be sent after changing address
1233 self.accept().await
1234 }
1235}
1236
1237/// Translates HAL [EndpointType] into PAC [vals::Eptyp]
1238fn to_eptyp(ep_type: EndpointType) -> vals::Eptyp {
1239 match ep_type {
1240 EndpointType::Control => vals::Eptyp::CONTROL,
1241 EndpointType::Isochronous => vals::Eptyp::ISOCHRONOUS,
1242 EndpointType::Bulk => vals::Eptyp::BULK,
1243 EndpointType::Interrupt => vals::Eptyp::INTERRUPT,
1244 }
1245}
1246
1247/// Calculates total allocated FIFO size in words
1248fn ep_fifo_size(eps: &[Option<EndpointData>]) -> u16 {
1249 eps.iter().map(|ep| ep.map(|ep| ep.fifo_size_words).unwrap_or(0)).sum()
1250}
1251
1252/// Generates IRQ mask for enabled endpoints
1253fn ep_irq_mask(eps: &[Option<EndpointData>]) -> u16 {
1254 eps.iter().enumerate().fold(
1255 0,
1256 |mask, (index, ep)| {
1257 if ep.is_some() {
1258 mask | (1 << index)
1259 } else {
1260 mask
1261 }
1262 },
1263 )
1264}
1265
1266/// Calculates MPSIZ value for EP0, which uses special values.
1267fn ep0_mpsiz(max_packet_size: u16) -> u16 {
1268 match max_packet_size {
1269 8 => 0b11,
1270 16 => 0b10,
1271 32 => 0b01,
1272 64 => 0b00,
1273 other => panic!("Unsupported EP0 size: {}", other),
1274 }
1275}
1276
1277/// The number of maximum configurable EPs.
1278// TODO: this should at least be configurable, but ideally not a constant.
1279// Using OtgInstance::ENDPOINT_COUNT requires feature(const_generic_expr) so just define maximum eps
1280pub const MAX_EP_COUNT: usize = 9;
1281
1282/// USB instance.
1283pub struct OtgInstance<'d> {
1284 /// The USB peripheral.
1285 pub regs: Otg,
1286 /// The USB state.
1287 pub state: &'d State<{ MAX_EP_COUNT }>,
1288 /// FIFO depth in words.
1289 pub fifo_depth_words: u16,
1290 /// Number of used endpoints.
1291 pub endpoint_count: usize,
1292 /// The PHY type.
1293 pub phy_type: PhyType,
1294 /// Extra RX FIFO words needed by some implementations.
1295 pub extra_rx_fifo_words: u16,
1296 /// Whether to set up late cnak
1297 pub quirk_setup_late_cnak: bool,
1298 /// Function to calculate TRDT value based on some internal clock speed.
1299 pub calculate_trdt_fn: fn(speed: vals::Dspd) -> u8,
1300}
diff --git a/embassy-usb-synopsys-otg/src/otg_v1.rs b/embassy-usb-synopsys-otg/src/otg_v1.rs
new file mode 100644
index 000000000..111bc4a63
--- /dev/null
+++ b/embassy-usb-synopsys-otg/src/otg_v1.rs
@@ -0,0 +1,4482 @@
1//! Register definitions for Synopsys DesignWare USB OTG core
2
3#![allow(missing_docs)]
4
5use core::marker::PhantomData;
6
7#[derive(Copy, Clone, PartialEq, Eq)]
8pub struct RW;
9#[derive(Copy, Clone, PartialEq, Eq)]
10pub struct R;
11#[derive(Copy, Clone, PartialEq, Eq)]
12pub struct W;
13
14mod sealed {
15 use super::*;
16 pub trait Access {}
17 impl Access for R {}
18 impl Access for W {}
19 impl Access for RW {}
20}
21
22pub trait Access: sealed::Access + Copy {}
23impl Access for R {}
24impl Access for W {}
25impl Access for RW {}
26
27pub trait Read: Access {}
28impl Read for RW {}
29impl Read for R {}
30
31pub trait Write: Access {}
32impl Write for RW {}
33impl Write for W {}
34
35#[derive(Copy, Clone, PartialEq, Eq)]
36pub struct Reg<T: Copy, A: Access> {
37 ptr: *mut u8,
38 phantom: PhantomData<*mut (T, A)>,
39}
40unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
41unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
42
43impl<T: Copy, A: Access> Reg<T, A> {
44 #[allow(clippy::missing_safety_doc)]
45 #[inline(always)]
46 pub const unsafe fn from_ptr(ptr: *mut T) -> Self {
47 Self {
48 ptr: ptr as _,
49 phantom: PhantomData,
50 }
51 }
52
53 #[inline(always)]
54 pub const fn as_ptr(&self) -> *mut T {
55 self.ptr as _
56 }
57}
58
59impl<T: Copy, A: Read> Reg<T, A> {
60 #[inline(always)]
61 pub fn read(&self) -> T {
62 unsafe { (self.ptr as *mut T).read_volatile() }
63 }
64}
65
66impl<T: Copy, A: Write> Reg<T, A> {
67 #[inline(always)]
68 pub fn write_value(&self, val: T) {
69 unsafe { (self.ptr as *mut T).write_volatile(val) }
70 }
71}
72
73impl<T: Default + Copy, A: Write> Reg<T, A> {
74 #[inline(always)]
75 pub fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
76 let mut val = Default::default();
77 let res = f(&mut val);
78 self.write_value(val);
79 res
80 }
81}
82
83impl<T: Copy, A: Read + Write> Reg<T, A> {
84 #[inline(always)]
85 pub fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
86 let mut val = self.read();
87 let res = f(&mut val);
88 self.write_value(val);
89 res
90 }
91}
92
93#[doc = "USB on the go"]
94#[derive(Copy, Clone, Eq, PartialEq)]
95pub struct Otg {
96 ptr: *mut u8,
97}
98unsafe impl Send for Otg {}
99unsafe impl Sync for Otg {}
100impl Otg {
101 #[inline(always)]
102 pub const unsafe fn from_ptr(ptr: *mut ()) -> Self {
103 Self { ptr: ptr as _ }
104 }
105 #[inline(always)]
106 pub const fn as_ptr(&self) -> *mut () {
107 self.ptr as _
108 }
109 #[doc = "Control and status register"]
110 #[inline(always)]
111 pub const fn gotgctl(self) -> Reg<regs::Gotgctl, RW> {
112 unsafe { Reg::from_ptr(self.ptr.add(0x0usize) as _) }
113 }
114 #[doc = "Interrupt register"]
115 #[inline(always)]
116 pub const fn gotgint(self) -> Reg<regs::Gotgint, RW> {
117 unsafe { Reg::from_ptr(self.ptr.add(0x04usize) as _) }
118 }
119 #[doc = "AHB configuration register"]
120 #[inline(always)]
121 pub const fn gahbcfg(self) -> Reg<regs::Gahbcfg, RW> {
122 unsafe { Reg::from_ptr(self.ptr.add(0x08usize) as _) }
123 }
124 #[doc = "USB configuration register"]
125 #[inline(always)]
126 pub const fn gusbcfg(self) -> Reg<regs::Gusbcfg, RW> {
127 unsafe { Reg::from_ptr(self.ptr.add(0x0cusize) as _) }
128 }
129 #[doc = "Reset register"]
130 #[inline(always)]
131 pub const fn grstctl(self) -> Reg<regs::Grstctl, RW> {
132 unsafe { Reg::from_ptr(self.ptr.add(0x10usize) as _) }
133 }
134 #[doc = "Core interrupt register"]
135 #[inline(always)]
136 pub const fn gintsts(self) -> Reg<regs::Gintsts, RW> {
137 unsafe { Reg::from_ptr(self.ptr.add(0x14usize) as _) }
138 }
139 #[doc = "Interrupt mask register"]
140 #[inline(always)]
141 pub const fn gintmsk(self) -> Reg<regs::Gintmsk, RW> {
142 unsafe { Reg::from_ptr(self.ptr.add(0x18usize) as _) }
143 }
144 #[doc = "Receive status debug read register"]
145 #[inline(always)]
146 pub const fn grxstsr(self) -> Reg<regs::Grxsts, R> {
147 unsafe { Reg::from_ptr(self.ptr.add(0x1cusize) as _) }
148 }
149 #[doc = "Status read and pop register"]
150 #[inline(always)]
151 pub const fn grxstsp(self) -> Reg<regs::Grxsts, R> {
152 unsafe { Reg::from_ptr(self.ptr.add(0x20usize) as _) }
153 }
154 #[doc = "Receive FIFO size register"]
155 #[inline(always)]
156 pub const fn grxfsiz(self) -> Reg<regs::Grxfsiz, RW> {
157 unsafe { Reg::from_ptr(self.ptr.add(0x24usize) as _) }
158 }
159 #[doc = "Endpoint 0 transmit FIFO size register (device mode)"]
160 #[inline(always)]
161 pub const fn dieptxf0(self) -> Reg<regs::Fsiz, RW> {
162 unsafe { Reg::from_ptr(self.ptr.add(0x28usize) as _) }
163 }
164 #[doc = "Non-periodic transmit FIFO size register (host mode)"]
165 #[inline(always)]
166 pub const fn hnptxfsiz(self) -> Reg<regs::Fsiz, RW> {
167 unsafe { Reg::from_ptr(self.ptr.add(0x28usize) as _) }
168 }
169 #[doc = "Non-periodic transmit FIFO/queue status register (host mode)"]
170 #[inline(always)]
171 pub const fn hnptxsts(self) -> Reg<regs::Hnptxsts, R> {
172 unsafe { Reg::from_ptr(self.ptr.add(0x2cusize) as _) }
173 }
174 #[doc = "OTG I2C access register"]
175 #[inline(always)]
176 pub const fn gi2cctl(self) -> Reg<regs::Gi2cctl, RW> {
177 unsafe { Reg::from_ptr(self.ptr.add(0x30usize) as _) }
178 }
179 #[doc = "General core configuration register, for core_id 0x0000_1xxx"]
180 #[inline(always)]
181 pub const fn gccfg_v1(self) -> Reg<regs::GccfgV1, RW> {
182 unsafe { Reg::from_ptr(self.ptr.add(0x38usize) as _) }
183 }
184 #[doc = "General core configuration register, for core_id 0x0000_\\[23\\]xxx"]
185 #[inline(always)]
186 pub const fn gccfg_v2(self) -> Reg<regs::GccfgV2, RW> {
187 unsafe { Reg::from_ptr(self.ptr.add(0x38usize) as _) }
188 }
189 #[doc = "Core ID register"]
190 #[inline(always)]
191 pub const fn cid(self) -> Reg<regs::Cid, RW> {
192 unsafe { Reg::from_ptr(self.ptr.add(0x3cusize) as _) }
193 }
194 #[doc = "OTG core LPM configuration register"]
195 #[inline(always)]
196 pub const fn glpmcfg(self) -> Reg<regs::Glpmcfg, RW> {
197 unsafe { Reg::from_ptr(self.ptr.add(0x54usize) as _) }
198 }
199 #[doc = "Host periodic transmit FIFO size register"]
200 #[inline(always)]
201 pub const fn hptxfsiz(self) -> Reg<regs::Fsiz, RW> {
202 unsafe { Reg::from_ptr(self.ptr.add(0x0100usize) as _) }
203 }
204 #[doc = "Device IN endpoint transmit FIFO size register"]
205 #[inline(always)]
206 pub const fn dieptxf(self, n: usize) -> Reg<regs::Fsiz, RW> {
207 assert!(n < 7usize);
208 unsafe { Reg::from_ptr(self.ptr.add(0x0104usize + n * 4usize) as _) }
209 }
210 #[doc = "Host configuration register"]
211 #[inline(always)]
212 pub const fn hcfg(self) -> Reg<regs::Hcfg, RW> {
213 unsafe { Reg::from_ptr(self.ptr.add(0x0400usize) as _) }
214 }
215 #[doc = "Host frame interval register"]
216 #[inline(always)]
217 pub const fn hfir(self) -> Reg<regs::Hfir, RW> {
218 unsafe { Reg::from_ptr(self.ptr.add(0x0404usize) as _) }
219 }
220 #[doc = "Host frame number/frame time remaining register"]
221 #[inline(always)]
222 pub const fn hfnum(self) -> Reg<regs::Hfnum, R> {
223 unsafe { Reg::from_ptr(self.ptr.add(0x0408usize) as _) }
224 }
225 #[doc = "Periodic transmit FIFO/queue status register"]
226 #[inline(always)]
227 pub const fn hptxsts(self) -> Reg<regs::Hptxsts, RW> {
228 unsafe { Reg::from_ptr(self.ptr.add(0x0410usize) as _) }
229 }
230 #[doc = "Host all channels interrupt register"]
231 #[inline(always)]
232 pub const fn haint(self) -> Reg<regs::Haint, R> {
233 unsafe { Reg::from_ptr(self.ptr.add(0x0414usize) as _) }
234 }
235 #[doc = "Host all channels interrupt mask register"]
236 #[inline(always)]
237 pub const fn haintmsk(self) -> Reg<regs::Haintmsk, RW> {
238 unsafe { Reg::from_ptr(self.ptr.add(0x0418usize) as _) }
239 }
240 #[doc = "Host port control and status register"]
241 #[inline(always)]
242 pub const fn hprt(self) -> Reg<regs::Hprt, RW> {
243 unsafe { Reg::from_ptr(self.ptr.add(0x0440usize) as _) }
244 }
245 #[doc = "Host channel characteristics register"]
246 #[inline(always)]
247 pub const fn hcchar(self, n: usize) -> Reg<regs::Hcchar, RW> {
248 assert!(n < 12usize);
249 unsafe { Reg::from_ptr(self.ptr.add(0x0500usize + n * 32usize) as _) }
250 }
251 #[doc = "Host channel split control register"]
252 #[inline(always)]
253 pub const fn hcsplt(self, n: usize) -> Reg<u32, RW> {
254 assert!(n < 12usize);
255 unsafe { Reg::from_ptr(self.ptr.add(0x0504usize + n * 32usize) as _) }
256 }
257 #[doc = "Host channel interrupt register"]
258 #[inline(always)]
259 pub const fn hcint(self, n: usize) -> Reg<regs::Hcint, RW> {
260 assert!(n < 12usize);
261 unsafe { Reg::from_ptr(self.ptr.add(0x0508usize + n * 32usize) as _) }
262 }
263 #[doc = "Host channel mask register"]
264 #[inline(always)]
265 pub const fn hcintmsk(self, n: usize) -> Reg<regs::Hcintmsk, RW> {
266 assert!(n < 12usize);
267 unsafe { Reg::from_ptr(self.ptr.add(0x050cusize + n * 32usize) as _) }
268 }
269 #[doc = "Host channel transfer size register"]
270 #[inline(always)]
271 pub const fn hctsiz(self, n: usize) -> Reg<regs::Hctsiz, RW> {
272 assert!(n < 12usize);
273 unsafe { Reg::from_ptr(self.ptr.add(0x0510usize + n * 32usize) as _) }
274 }
275 #[doc = "Device configuration register"]
276 #[inline(always)]
277 pub const fn dcfg(self) -> Reg<regs::Dcfg, RW> {
278 unsafe { Reg::from_ptr(self.ptr.add(0x0800usize) as _) }
279 }
280 #[doc = "Device control register"]
281 #[inline(always)]
282 pub const fn dctl(self) -> Reg<regs::Dctl, RW> {
283 unsafe { Reg::from_ptr(self.ptr.add(0x0804usize) as _) }
284 }
285 #[doc = "Device status register"]
286 #[inline(always)]
287 pub const fn dsts(self) -> Reg<regs::Dsts, R> {
288 unsafe { Reg::from_ptr(self.ptr.add(0x0808usize) as _) }
289 }
290 #[doc = "Device IN endpoint common interrupt mask register"]
291 #[inline(always)]
292 pub const fn diepmsk(self) -> Reg<regs::Diepmsk, RW> {
293 unsafe { Reg::from_ptr(self.ptr.add(0x0810usize) as _) }
294 }
295 #[doc = "Device OUT endpoint common interrupt mask register"]
296 #[inline(always)]
297 pub const fn doepmsk(self) -> Reg<regs::Doepmsk, RW> {
298 unsafe { Reg::from_ptr(self.ptr.add(0x0814usize) as _) }
299 }
300 #[doc = "Device all endpoints interrupt register"]
301 #[inline(always)]
302 pub const fn daint(self) -> Reg<regs::Daint, R> {
303 unsafe { Reg::from_ptr(self.ptr.add(0x0818usize) as _) }
304 }
305 #[doc = "All endpoints interrupt mask register"]
306 #[inline(always)]
307 pub const fn daintmsk(self) -> Reg<regs::Daintmsk, RW> {
308 unsafe { Reg::from_ptr(self.ptr.add(0x081cusize) as _) }
309 }
310 #[doc = "Device VBUS discharge time register"]
311 #[inline(always)]
312 pub const fn dvbusdis(self) -> Reg<regs::Dvbusdis, RW> {
313 unsafe { Reg::from_ptr(self.ptr.add(0x0828usize) as _) }
314 }
315 #[doc = "Device VBUS pulsing time register"]
316 #[inline(always)]
317 pub const fn dvbuspulse(self) -> Reg<regs::Dvbuspulse, RW> {
318 unsafe { Reg::from_ptr(self.ptr.add(0x082cusize) as _) }
319 }
320 #[doc = "Device IN endpoint FIFO empty interrupt mask register"]
321 #[inline(always)]
322 pub const fn diepempmsk(self) -> Reg<regs::Diepempmsk, RW> {
323 unsafe { Reg::from_ptr(self.ptr.add(0x0834usize) as _) }
324 }
325 #[doc = "Device IN endpoint control register"]
326 #[inline(always)]
327 pub const fn diepctl(self, n: usize) -> Reg<regs::Diepctl, RW> {
328 assert!(n < 16usize);
329 unsafe { Reg::from_ptr(self.ptr.add(0x0900usize + n * 32usize) as _) }
330 }
331 #[doc = "Device IN endpoint interrupt register"]
332 #[inline(always)]
333 pub const fn diepint(self, n: usize) -> Reg<regs::Diepint, RW> {
334 assert!(n < 16usize);
335 unsafe { Reg::from_ptr(self.ptr.add(0x0908usize + n * 32usize) as _) }
336 }
337 #[doc = "Device IN endpoint transfer size register"]
338 #[inline(always)]
339 pub const fn dieptsiz(self, n: usize) -> Reg<regs::Dieptsiz, RW> {
340 assert!(n < 16usize);
341 unsafe { Reg::from_ptr(self.ptr.add(0x0910usize + n * 32usize) as _) }
342 }
343 #[doc = "Device IN endpoint transmit FIFO status register"]
344 #[inline(always)]
345 pub const fn dtxfsts(self, n: usize) -> Reg<regs::Dtxfsts, R> {
346 assert!(n < 16usize);
347 unsafe { Reg::from_ptr(self.ptr.add(0x0918usize + n * 32usize) as _) }
348 }
349 #[doc = "Device OUT endpoint control register"]
350 #[inline(always)]
351 pub const fn doepctl(self, n: usize) -> Reg<regs::Doepctl, RW> {
352 assert!(n < 16usize);
353 unsafe { Reg::from_ptr(self.ptr.add(0x0b00usize + n * 32usize) as _) }
354 }
355 #[doc = "Device OUT endpoint interrupt register"]
356 #[inline(always)]
357 pub const fn doepint(self, n: usize) -> Reg<regs::Doepint, RW> {
358 assert!(n < 16usize);
359 unsafe { Reg::from_ptr(self.ptr.add(0x0b08usize + n * 32usize) as _) }
360 }
361 #[doc = "Device OUT endpoint transfer size register"]
362 #[inline(always)]
363 pub const fn doeptsiz(self, n: usize) -> Reg<regs::Doeptsiz, RW> {
364 assert!(n < 16usize);
365 unsafe { Reg::from_ptr(self.ptr.add(0x0b10usize + n * 32usize) as _) }
366 }
367 #[doc = "Power and clock gating control register"]
368 #[inline(always)]
369 pub const fn pcgcctl(self) -> Reg<regs::Pcgcctl, RW> {
370 unsafe { Reg::from_ptr(self.ptr.add(0x0e00usize) as _) }
371 }
372 #[doc = "Device endpoint / host channel FIFO register"]
373 #[inline(always)]
374 pub const fn fifo(self, n: usize) -> Reg<regs::Fifo, RW> {
375 assert!(n < 16usize);
376 unsafe { Reg::from_ptr(self.ptr.add(0x1000usize + n * 4096usize) as _) }
377 }
378}
379pub mod regs {
380 #[doc = "Core ID register"]
381 #[repr(transparent)]
382 #[derive(Copy, Clone, Eq, PartialEq)]
383 pub struct Cid(pub u32);
384 impl Cid {
385 #[doc = "Product ID field"]
386 #[inline(always)]
387 pub const fn product_id(&self) -> u32 {
388 let val = (self.0 >> 0usize) & 0xffff_ffff;
389 val as u32
390 }
391 #[doc = "Product ID field"]
392 #[inline(always)]
393 pub fn set_product_id(&mut self, val: u32) {
394 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
395 }
396 }
397 impl Default for Cid {
398 #[inline(always)]
399 fn default() -> Cid {
400 Cid(0)
401 }
402 }
403 #[doc = "Device all endpoints interrupt register"]
404 #[repr(transparent)]
405 #[derive(Copy, Clone, Eq, PartialEq)]
406 pub struct Daint(pub u32);
407 impl Daint {
408 #[doc = "IN endpoint interrupt bits"]
409 #[inline(always)]
410 pub const fn iepint(&self) -> u16 {
411 let val = (self.0 >> 0usize) & 0xffff;
412 val as u16
413 }
414 #[doc = "IN endpoint interrupt bits"]
415 #[inline(always)]
416 pub fn set_iepint(&mut self, val: u16) {
417 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
418 }
419 #[doc = "OUT endpoint interrupt bits"]
420 #[inline(always)]
421 pub const fn oepint(&self) -> u16 {
422 let val = (self.0 >> 16usize) & 0xffff;
423 val as u16
424 }
425 #[doc = "OUT endpoint interrupt bits"]
426 #[inline(always)]
427 pub fn set_oepint(&mut self, val: u16) {
428 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
429 }
430 }
431 impl Default for Daint {
432 #[inline(always)]
433 fn default() -> Daint {
434 Daint(0)
435 }
436 }
437 #[doc = "All endpoints interrupt mask register"]
438 #[repr(transparent)]
439 #[derive(Copy, Clone, Eq, PartialEq)]
440 pub struct Daintmsk(pub u32);
441 impl Daintmsk {
442 #[doc = "IN EP interrupt mask bits"]
443 #[inline(always)]
444 pub const fn iepm(&self) -> u16 {
445 let val = (self.0 >> 0usize) & 0xffff;
446 val as u16
447 }
448 #[doc = "IN EP interrupt mask bits"]
449 #[inline(always)]
450 pub fn set_iepm(&mut self, val: u16) {
451 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
452 }
453 #[doc = "OUT EP interrupt mask bits"]
454 #[inline(always)]
455 pub const fn oepm(&self) -> u16 {
456 let val = (self.0 >> 16usize) & 0xffff;
457 val as u16
458 }
459 #[doc = "OUT EP interrupt mask bits"]
460 #[inline(always)]
461 pub fn set_oepm(&mut self, val: u16) {
462 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
463 }
464 }
465 impl Default for Daintmsk {
466 #[inline(always)]
467 fn default() -> Daintmsk {
468 Daintmsk(0)
469 }
470 }
471 #[doc = "Device configuration register"]
472 #[repr(transparent)]
473 #[derive(Copy, Clone, Eq, PartialEq)]
474 pub struct Dcfg(pub u32);
475 impl Dcfg {
476 #[doc = "Device speed"]
477 #[inline(always)]
478 pub const fn dspd(&self) -> super::vals::Dspd {
479 let val = (self.0 >> 0usize) & 0x03;
480 super::vals::Dspd::from_bits(val as u8)
481 }
482 #[doc = "Device speed"]
483 #[inline(always)]
484 pub fn set_dspd(&mut self, val: super::vals::Dspd) {
485 self.0 = (self.0 & !(0x03 << 0usize)) | (((val.to_bits() as u32) & 0x03) << 0usize);
486 }
487 #[doc = "Non-zero-length status OUT handshake"]
488 #[inline(always)]
489 pub const fn nzlsohsk(&self) -> bool {
490 let val = (self.0 >> 2usize) & 0x01;
491 val != 0
492 }
493 #[doc = "Non-zero-length status OUT handshake"]
494 #[inline(always)]
495 pub fn set_nzlsohsk(&mut self, val: bool) {
496 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
497 }
498 #[doc = "Device address"]
499 #[inline(always)]
500 pub const fn dad(&self) -> u8 {
501 let val = (self.0 >> 4usize) & 0x7f;
502 val as u8
503 }
504 #[doc = "Device address"]
505 #[inline(always)]
506 pub fn set_dad(&mut self, val: u8) {
507 self.0 = (self.0 & !(0x7f << 4usize)) | (((val as u32) & 0x7f) << 4usize);
508 }
509 #[doc = "Periodic frame interval"]
510 #[inline(always)]
511 pub const fn pfivl(&self) -> super::vals::Pfivl {
512 let val = (self.0 >> 11usize) & 0x03;
513 super::vals::Pfivl::from_bits(val as u8)
514 }
515 #[doc = "Periodic frame interval"]
516 #[inline(always)]
517 pub fn set_pfivl(&mut self, val: super::vals::Pfivl) {
518 self.0 = (self.0 & !(0x03 << 11usize)) | (((val.to_bits() as u32) & 0x03) << 11usize);
519 }
520 #[doc = "Transceiver delay"]
521 #[inline(always)]
522 pub const fn xcvrdly(&self) -> bool {
523 let val = (self.0 >> 14usize) & 0x01;
524 val != 0
525 }
526 #[doc = "Transceiver delay"]
527 #[inline(always)]
528 pub fn set_xcvrdly(&mut self, val: bool) {
529 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
530 }
531 }
532 impl Default for Dcfg {
533 #[inline(always)]
534 fn default() -> Dcfg {
535 Dcfg(0)
536 }
537 }
538 #[doc = "Device control register"]
539 #[repr(transparent)]
540 #[derive(Copy, Clone, Eq, PartialEq)]
541 pub struct Dctl(pub u32);
542 impl Dctl {
543 #[doc = "Remote wakeup signaling"]
544 #[inline(always)]
545 pub const fn rwusig(&self) -> bool {
546 let val = (self.0 >> 0usize) & 0x01;
547 val != 0
548 }
549 #[doc = "Remote wakeup signaling"]
550 #[inline(always)]
551 pub fn set_rwusig(&mut self, val: bool) {
552 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
553 }
554 #[doc = "Soft disconnect"]
555 #[inline(always)]
556 pub const fn sdis(&self) -> bool {
557 let val = (self.0 >> 1usize) & 0x01;
558 val != 0
559 }
560 #[doc = "Soft disconnect"]
561 #[inline(always)]
562 pub fn set_sdis(&mut self, val: bool) {
563 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
564 }
565 #[doc = "Global IN NAK status"]
566 #[inline(always)]
567 pub const fn ginsts(&self) -> bool {
568 let val = (self.0 >> 2usize) & 0x01;
569 val != 0
570 }
571 #[doc = "Global IN NAK status"]
572 #[inline(always)]
573 pub fn set_ginsts(&mut self, val: bool) {
574 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
575 }
576 #[doc = "Global OUT NAK status"]
577 #[inline(always)]
578 pub const fn gonsts(&self) -> bool {
579 let val = (self.0 >> 3usize) & 0x01;
580 val != 0
581 }
582 #[doc = "Global OUT NAK status"]
583 #[inline(always)]
584 pub fn set_gonsts(&mut self, val: bool) {
585 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
586 }
587 #[doc = "Test control"]
588 #[inline(always)]
589 pub const fn tctl(&self) -> u8 {
590 let val = (self.0 >> 4usize) & 0x07;
591 val as u8
592 }
593 #[doc = "Test control"]
594 #[inline(always)]
595 pub fn set_tctl(&mut self, val: u8) {
596 self.0 = (self.0 & !(0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize);
597 }
598 #[doc = "Set global IN NAK"]
599 #[inline(always)]
600 pub const fn sginak(&self) -> bool {
601 let val = (self.0 >> 7usize) & 0x01;
602 val != 0
603 }
604 #[doc = "Set global IN NAK"]
605 #[inline(always)]
606 pub fn set_sginak(&mut self, val: bool) {
607 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
608 }
609 #[doc = "Clear global IN NAK"]
610 #[inline(always)]
611 pub const fn cginak(&self) -> bool {
612 let val = (self.0 >> 8usize) & 0x01;
613 val != 0
614 }
615 #[doc = "Clear global IN NAK"]
616 #[inline(always)]
617 pub fn set_cginak(&mut self, val: bool) {
618 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
619 }
620 #[doc = "Set global OUT NAK"]
621 #[inline(always)]
622 pub const fn sgonak(&self) -> bool {
623 let val = (self.0 >> 9usize) & 0x01;
624 val != 0
625 }
626 #[doc = "Set global OUT NAK"]
627 #[inline(always)]
628 pub fn set_sgonak(&mut self, val: bool) {
629 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
630 }
631 #[doc = "Clear global OUT NAK"]
632 #[inline(always)]
633 pub const fn cgonak(&self) -> bool {
634 let val = (self.0 >> 10usize) & 0x01;
635 val != 0
636 }
637 #[doc = "Clear global OUT NAK"]
638 #[inline(always)]
639 pub fn set_cgonak(&mut self, val: bool) {
640 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
641 }
642 #[doc = "Power-on programming done"]
643 #[inline(always)]
644 pub const fn poprgdne(&self) -> bool {
645 let val = (self.0 >> 11usize) & 0x01;
646 val != 0
647 }
648 #[doc = "Power-on programming done"]
649 #[inline(always)]
650 pub fn set_poprgdne(&mut self, val: bool) {
651 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
652 }
653 }
654 impl Default for Dctl {
655 #[inline(always)]
656 fn default() -> Dctl {
657 Dctl(0)
658 }
659 }
660 #[doc = "Device endpoint control register"]
661 #[repr(transparent)]
662 #[derive(Copy, Clone, Eq, PartialEq)]
663 pub struct Diepctl(pub u32);
664 impl Diepctl {
665 #[doc = "MPSIZ"]
666 #[inline(always)]
667 pub const fn mpsiz(&self) -> u16 {
668 let val = (self.0 >> 0usize) & 0x07ff;
669 val as u16
670 }
671 #[doc = "MPSIZ"]
672 #[inline(always)]
673 pub fn set_mpsiz(&mut self, val: u16) {
674 self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
675 }
676 #[doc = "USBAEP"]
677 #[inline(always)]
678 pub const fn usbaep(&self) -> bool {
679 let val = (self.0 >> 15usize) & 0x01;
680 val != 0
681 }
682 #[doc = "USBAEP"]
683 #[inline(always)]
684 pub fn set_usbaep(&mut self, val: bool) {
685 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
686 }
687 #[doc = "EONUM/DPID"]
688 #[inline(always)]
689 pub const fn eonum_dpid(&self) -> bool {
690 let val = (self.0 >> 16usize) & 0x01;
691 val != 0
692 }
693 #[doc = "EONUM/DPID"]
694 #[inline(always)]
695 pub fn set_eonum_dpid(&mut self, val: bool) {
696 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
697 }
698 #[doc = "NAKSTS"]
699 #[inline(always)]
700 pub const fn naksts(&self) -> bool {
701 let val = (self.0 >> 17usize) & 0x01;
702 val != 0
703 }
704 #[doc = "NAKSTS"]
705 #[inline(always)]
706 pub fn set_naksts(&mut self, val: bool) {
707 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
708 }
709 #[doc = "EPTYP"]
710 #[inline(always)]
711 pub const fn eptyp(&self) -> super::vals::Eptyp {
712 let val = (self.0 >> 18usize) & 0x03;
713 super::vals::Eptyp::from_bits(val as u8)
714 }
715 #[doc = "EPTYP"]
716 #[inline(always)]
717 pub fn set_eptyp(&mut self, val: super::vals::Eptyp) {
718 self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
719 }
720 #[doc = "SNPM"]
721 #[inline(always)]
722 pub const fn snpm(&self) -> bool {
723 let val = (self.0 >> 20usize) & 0x01;
724 val != 0
725 }
726 #[doc = "SNPM"]
727 #[inline(always)]
728 pub fn set_snpm(&mut self, val: bool) {
729 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
730 }
731 #[doc = "STALL"]
732 #[inline(always)]
733 pub const fn stall(&self) -> bool {
734 let val = (self.0 >> 21usize) & 0x01;
735 val != 0
736 }
737 #[doc = "STALL"]
738 #[inline(always)]
739 pub fn set_stall(&mut self, val: bool) {
740 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
741 }
742 #[doc = "TXFNUM"]
743 #[inline(always)]
744 pub const fn txfnum(&self) -> u8 {
745 let val = (self.0 >> 22usize) & 0x0f;
746 val as u8
747 }
748 #[doc = "TXFNUM"]
749 #[inline(always)]
750 pub fn set_txfnum(&mut self, val: u8) {
751 self.0 = (self.0 & !(0x0f << 22usize)) | (((val as u32) & 0x0f) << 22usize);
752 }
753 #[doc = "CNAK"]
754 #[inline(always)]
755 pub const fn cnak(&self) -> bool {
756 let val = (self.0 >> 26usize) & 0x01;
757 val != 0
758 }
759 #[doc = "CNAK"]
760 #[inline(always)]
761 pub fn set_cnak(&mut self, val: bool) {
762 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
763 }
764 #[doc = "SNAK"]
765 #[inline(always)]
766 pub const fn snak(&self) -> bool {
767 let val = (self.0 >> 27usize) & 0x01;
768 val != 0
769 }
770 #[doc = "SNAK"]
771 #[inline(always)]
772 pub fn set_snak(&mut self, val: bool) {
773 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
774 }
775 #[doc = "SD0PID/SEVNFRM"]
776 #[inline(always)]
777 pub const fn sd0pid_sevnfrm(&self) -> bool {
778 let val = (self.0 >> 28usize) & 0x01;
779 val != 0
780 }
781 #[doc = "SD0PID/SEVNFRM"]
782 #[inline(always)]
783 pub fn set_sd0pid_sevnfrm(&mut self, val: bool) {
784 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
785 }
786 #[doc = "SODDFRM/SD1PID"]
787 #[inline(always)]
788 pub const fn soddfrm_sd1pid(&self) -> bool {
789 let val = (self.0 >> 29usize) & 0x01;
790 val != 0
791 }
792 #[doc = "SODDFRM/SD1PID"]
793 #[inline(always)]
794 pub fn set_soddfrm_sd1pid(&mut self, val: bool) {
795 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
796 }
797 #[doc = "EPDIS"]
798 #[inline(always)]
799 pub const fn epdis(&self) -> bool {
800 let val = (self.0 >> 30usize) & 0x01;
801 val != 0
802 }
803 #[doc = "EPDIS"]
804 #[inline(always)]
805 pub fn set_epdis(&mut self, val: bool) {
806 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
807 }
808 #[doc = "EPENA"]
809 #[inline(always)]
810 pub const fn epena(&self) -> bool {
811 let val = (self.0 >> 31usize) & 0x01;
812 val != 0
813 }
814 #[doc = "EPENA"]
815 #[inline(always)]
816 pub fn set_epena(&mut self, val: bool) {
817 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
818 }
819 }
820 impl Default for Diepctl {
821 #[inline(always)]
822 fn default() -> Diepctl {
823 Diepctl(0)
824 }
825 }
826 #[doc = "Device IN endpoint FIFO empty interrupt mask register"]
827 #[repr(transparent)]
828 #[derive(Copy, Clone, Eq, PartialEq)]
829 pub struct Diepempmsk(pub u32);
830 impl Diepempmsk {
831 #[doc = "IN EP Tx FIFO empty interrupt mask bits"]
832 #[inline(always)]
833 pub const fn ineptxfem(&self) -> u16 {
834 let val = (self.0 >> 0usize) & 0xffff;
835 val as u16
836 }
837 #[doc = "IN EP Tx FIFO empty interrupt mask bits"]
838 #[inline(always)]
839 pub fn set_ineptxfem(&mut self, val: u16) {
840 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
841 }
842 }
843 impl Default for Diepempmsk {
844 #[inline(always)]
845 fn default() -> Diepempmsk {
846 Diepempmsk(0)
847 }
848 }
849 #[doc = "Device endpoint interrupt register"]
850 #[repr(transparent)]
851 #[derive(Copy, Clone, Eq, PartialEq)]
852 pub struct Diepint(pub u32);
853 impl Diepint {
854 #[doc = "XFRC"]
855 #[inline(always)]
856 pub const fn xfrc(&self) -> bool {
857 let val = (self.0 >> 0usize) & 0x01;
858 val != 0
859 }
860 #[doc = "XFRC"]
861 #[inline(always)]
862 pub fn set_xfrc(&mut self, val: bool) {
863 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
864 }
865 #[doc = "EPDISD"]
866 #[inline(always)]
867 pub const fn epdisd(&self) -> bool {
868 let val = (self.0 >> 1usize) & 0x01;
869 val != 0
870 }
871 #[doc = "EPDISD"]
872 #[inline(always)]
873 pub fn set_epdisd(&mut self, val: bool) {
874 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
875 }
876 #[doc = "TOC"]
877 #[inline(always)]
878 pub const fn toc(&self) -> bool {
879 let val = (self.0 >> 3usize) & 0x01;
880 val != 0
881 }
882 #[doc = "TOC"]
883 #[inline(always)]
884 pub fn set_toc(&mut self, val: bool) {
885 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
886 }
887 #[doc = "ITTXFE"]
888 #[inline(always)]
889 pub const fn ittxfe(&self) -> bool {
890 let val = (self.0 >> 4usize) & 0x01;
891 val != 0
892 }
893 #[doc = "ITTXFE"]
894 #[inline(always)]
895 pub fn set_ittxfe(&mut self, val: bool) {
896 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
897 }
898 #[doc = "INEPNE"]
899 #[inline(always)]
900 pub const fn inepne(&self) -> bool {
901 let val = (self.0 >> 6usize) & 0x01;
902 val != 0
903 }
904 #[doc = "INEPNE"]
905 #[inline(always)]
906 pub fn set_inepne(&mut self, val: bool) {
907 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
908 }
909 #[doc = "TXFE"]
910 #[inline(always)]
911 pub const fn txfe(&self) -> bool {
912 let val = (self.0 >> 7usize) & 0x01;
913 val != 0
914 }
915 #[doc = "TXFE"]
916 #[inline(always)]
917 pub fn set_txfe(&mut self, val: bool) {
918 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
919 }
920 }
921 impl Default for Diepint {
922 #[inline(always)]
923 fn default() -> Diepint {
924 Diepint(0)
925 }
926 }
927 #[doc = "Device IN endpoint common interrupt mask register"]
928 #[repr(transparent)]
929 #[derive(Copy, Clone, Eq, PartialEq)]
930 pub struct Diepmsk(pub u32);
931 impl Diepmsk {
932 #[doc = "Transfer completed interrupt mask"]
933 #[inline(always)]
934 pub const fn xfrcm(&self) -> bool {
935 let val = (self.0 >> 0usize) & 0x01;
936 val != 0
937 }
938 #[doc = "Transfer completed interrupt mask"]
939 #[inline(always)]
940 pub fn set_xfrcm(&mut self, val: bool) {
941 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
942 }
943 #[doc = "Endpoint disabled interrupt mask"]
944 #[inline(always)]
945 pub const fn epdm(&self) -> bool {
946 let val = (self.0 >> 1usize) & 0x01;
947 val != 0
948 }
949 #[doc = "Endpoint disabled interrupt mask"]
950 #[inline(always)]
951 pub fn set_epdm(&mut self, val: bool) {
952 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
953 }
954 #[doc = "Timeout condition mask (Non-isochronous endpoints)"]
955 #[inline(always)]
956 pub const fn tom(&self) -> bool {
957 let val = (self.0 >> 3usize) & 0x01;
958 val != 0
959 }
960 #[doc = "Timeout condition mask (Non-isochronous endpoints)"]
961 #[inline(always)]
962 pub fn set_tom(&mut self, val: bool) {
963 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
964 }
965 #[doc = "IN token received when TxFIFO empty mask"]
966 #[inline(always)]
967 pub const fn ittxfemsk(&self) -> bool {
968 let val = (self.0 >> 4usize) & 0x01;
969 val != 0
970 }
971 #[doc = "IN token received when TxFIFO empty mask"]
972 #[inline(always)]
973 pub fn set_ittxfemsk(&mut self, val: bool) {
974 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
975 }
976 #[doc = "IN token received with EP mismatch mask"]
977 #[inline(always)]
978 pub const fn inepnmm(&self) -> bool {
979 let val = (self.0 >> 5usize) & 0x01;
980 val != 0
981 }
982 #[doc = "IN token received with EP mismatch mask"]
983 #[inline(always)]
984 pub fn set_inepnmm(&mut self, val: bool) {
985 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
986 }
987 #[doc = "IN endpoint NAK effective mask"]
988 #[inline(always)]
989 pub const fn inepnem(&self) -> bool {
990 let val = (self.0 >> 6usize) & 0x01;
991 val != 0
992 }
993 #[doc = "IN endpoint NAK effective mask"]
994 #[inline(always)]
995 pub fn set_inepnem(&mut self, val: bool) {
996 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
997 }
998 }
999 impl Default for Diepmsk {
1000 #[inline(always)]
1001 fn default() -> Diepmsk {
1002 Diepmsk(0)
1003 }
1004 }
1005 #[doc = "Device endpoint transfer size register"]
1006 #[repr(transparent)]
1007 #[derive(Copy, Clone, Eq, PartialEq)]
1008 pub struct Dieptsiz(pub u32);
1009 impl Dieptsiz {
1010 #[doc = "Transfer size"]
1011 #[inline(always)]
1012 pub const fn xfrsiz(&self) -> u32 {
1013 let val = (self.0 >> 0usize) & 0x0007_ffff;
1014 val as u32
1015 }
1016 #[doc = "Transfer size"]
1017 #[inline(always)]
1018 pub fn set_xfrsiz(&mut self, val: u32) {
1019 self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
1020 }
1021 #[doc = "Packet count"]
1022 #[inline(always)]
1023 pub const fn pktcnt(&self) -> u16 {
1024 let val = (self.0 >> 19usize) & 0x03ff;
1025 val as u16
1026 }
1027 #[doc = "Packet count"]
1028 #[inline(always)]
1029 pub fn set_pktcnt(&mut self, val: u16) {
1030 self.0 = (self.0 & !(0x03ff << 19usize)) | (((val as u32) & 0x03ff) << 19usize);
1031 }
1032 #[doc = "Multi count"]
1033 #[inline(always)]
1034 pub const fn mcnt(&self) -> u8 {
1035 let val = (self.0 >> 29usize) & 0x03;
1036 val as u8
1037 }
1038 #[doc = "Multi count"]
1039 #[inline(always)]
1040 pub fn set_mcnt(&mut self, val: u8) {
1041 self.0 = (self.0 & !(0x03 << 29usize)) | (((val as u32) & 0x03) << 29usize);
1042 }
1043 }
1044 impl Default for Dieptsiz {
1045 #[inline(always)]
1046 fn default() -> Dieptsiz {
1047 Dieptsiz(0)
1048 }
1049 }
1050 #[doc = "Device endpoint control register"]
1051 #[repr(transparent)]
1052 #[derive(Copy, Clone, Eq, PartialEq)]
1053 pub struct Doepctl(pub u32);
1054 impl Doepctl {
1055 #[doc = "MPSIZ"]
1056 #[inline(always)]
1057 pub const fn mpsiz(&self) -> u16 {
1058 let val = (self.0 >> 0usize) & 0x07ff;
1059 val as u16
1060 }
1061 #[doc = "MPSIZ"]
1062 #[inline(always)]
1063 pub fn set_mpsiz(&mut self, val: u16) {
1064 self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
1065 }
1066 #[doc = "USBAEP"]
1067 #[inline(always)]
1068 pub const fn usbaep(&self) -> bool {
1069 let val = (self.0 >> 15usize) & 0x01;
1070 val != 0
1071 }
1072 #[doc = "USBAEP"]
1073 #[inline(always)]
1074 pub fn set_usbaep(&mut self, val: bool) {
1075 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
1076 }
1077 #[doc = "EONUM/DPID"]
1078 #[inline(always)]
1079 pub const fn eonum_dpid(&self) -> bool {
1080 let val = (self.0 >> 16usize) & 0x01;
1081 val != 0
1082 }
1083 #[doc = "EONUM/DPID"]
1084 #[inline(always)]
1085 pub fn set_eonum_dpid(&mut self, val: bool) {
1086 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1087 }
1088 #[doc = "NAKSTS"]
1089 #[inline(always)]
1090 pub const fn naksts(&self) -> bool {
1091 let val = (self.0 >> 17usize) & 0x01;
1092 val != 0
1093 }
1094 #[doc = "NAKSTS"]
1095 #[inline(always)]
1096 pub fn set_naksts(&mut self, val: bool) {
1097 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1098 }
1099 #[doc = "EPTYP"]
1100 #[inline(always)]
1101 pub const fn eptyp(&self) -> super::vals::Eptyp {
1102 let val = (self.0 >> 18usize) & 0x03;
1103 super::vals::Eptyp::from_bits(val as u8)
1104 }
1105 #[doc = "EPTYP"]
1106 #[inline(always)]
1107 pub fn set_eptyp(&mut self, val: super::vals::Eptyp) {
1108 self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
1109 }
1110 #[doc = "SNPM"]
1111 #[inline(always)]
1112 pub const fn snpm(&self) -> bool {
1113 let val = (self.0 >> 20usize) & 0x01;
1114 val != 0
1115 }
1116 #[doc = "SNPM"]
1117 #[inline(always)]
1118 pub fn set_snpm(&mut self, val: bool) {
1119 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1120 }
1121 #[doc = "STALL"]
1122 #[inline(always)]
1123 pub const fn stall(&self) -> bool {
1124 let val = (self.0 >> 21usize) & 0x01;
1125 val != 0
1126 }
1127 #[doc = "STALL"]
1128 #[inline(always)]
1129 pub fn set_stall(&mut self, val: bool) {
1130 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1131 }
1132 #[doc = "CNAK"]
1133 #[inline(always)]
1134 pub const fn cnak(&self) -> bool {
1135 let val = (self.0 >> 26usize) & 0x01;
1136 val != 0
1137 }
1138 #[doc = "CNAK"]
1139 #[inline(always)]
1140 pub fn set_cnak(&mut self, val: bool) {
1141 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
1142 }
1143 #[doc = "SNAK"]
1144 #[inline(always)]
1145 pub const fn snak(&self) -> bool {
1146 let val = (self.0 >> 27usize) & 0x01;
1147 val != 0
1148 }
1149 #[doc = "SNAK"]
1150 #[inline(always)]
1151 pub fn set_snak(&mut self, val: bool) {
1152 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
1153 }
1154 #[doc = "SD0PID/SEVNFRM"]
1155 #[inline(always)]
1156 pub const fn sd0pid_sevnfrm(&self) -> bool {
1157 let val = (self.0 >> 28usize) & 0x01;
1158 val != 0
1159 }
1160 #[doc = "SD0PID/SEVNFRM"]
1161 #[inline(always)]
1162 pub fn set_sd0pid_sevnfrm(&mut self, val: bool) {
1163 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1164 }
1165 #[doc = "SODDFRM"]
1166 #[inline(always)]
1167 pub const fn soddfrm(&self) -> bool {
1168 let val = (self.0 >> 29usize) & 0x01;
1169 val != 0
1170 }
1171 #[doc = "SODDFRM"]
1172 #[inline(always)]
1173 pub fn set_soddfrm(&mut self, val: bool) {
1174 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
1175 }
1176 #[doc = "EPDIS"]
1177 #[inline(always)]
1178 pub const fn epdis(&self) -> bool {
1179 let val = (self.0 >> 30usize) & 0x01;
1180 val != 0
1181 }
1182 #[doc = "EPDIS"]
1183 #[inline(always)]
1184 pub fn set_epdis(&mut self, val: bool) {
1185 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
1186 }
1187 #[doc = "EPENA"]
1188 #[inline(always)]
1189 pub const fn epena(&self) -> bool {
1190 let val = (self.0 >> 31usize) & 0x01;
1191 val != 0
1192 }
1193 #[doc = "EPENA"]
1194 #[inline(always)]
1195 pub fn set_epena(&mut self, val: bool) {
1196 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1197 }
1198 }
1199 impl Default for Doepctl {
1200 #[inline(always)]
1201 fn default() -> Doepctl {
1202 Doepctl(0)
1203 }
1204 }
1205 #[doc = "Device endpoint interrupt register"]
1206 #[repr(transparent)]
1207 #[derive(Copy, Clone, Eq, PartialEq)]
1208 pub struct Doepint(pub u32);
1209 impl Doepint {
1210 #[doc = "XFRC"]
1211 #[inline(always)]
1212 pub const fn xfrc(&self) -> bool {
1213 let val = (self.0 >> 0usize) & 0x01;
1214 val != 0
1215 }
1216 #[doc = "XFRC"]
1217 #[inline(always)]
1218 pub fn set_xfrc(&mut self, val: bool) {
1219 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1220 }
1221 #[doc = "EPDISD"]
1222 #[inline(always)]
1223 pub const fn epdisd(&self) -> bool {
1224 let val = (self.0 >> 1usize) & 0x01;
1225 val != 0
1226 }
1227 #[doc = "EPDISD"]
1228 #[inline(always)]
1229 pub fn set_epdisd(&mut self, val: bool) {
1230 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1231 }
1232 #[doc = "STUP"]
1233 #[inline(always)]
1234 pub const fn stup(&self) -> bool {
1235 let val = (self.0 >> 3usize) & 0x01;
1236 val != 0
1237 }
1238 #[doc = "STUP"]
1239 #[inline(always)]
1240 pub fn set_stup(&mut self, val: bool) {
1241 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1242 }
1243 #[doc = "OTEPDIS"]
1244 #[inline(always)]
1245 pub const fn otepdis(&self) -> bool {
1246 let val = (self.0 >> 4usize) & 0x01;
1247 val != 0
1248 }
1249 #[doc = "OTEPDIS"]
1250 #[inline(always)]
1251 pub fn set_otepdis(&mut self, val: bool) {
1252 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1253 }
1254 #[doc = "B2BSTUP"]
1255 #[inline(always)]
1256 pub const fn b2bstup(&self) -> bool {
1257 let val = (self.0 >> 6usize) & 0x01;
1258 val != 0
1259 }
1260 #[doc = "B2BSTUP"]
1261 #[inline(always)]
1262 pub fn set_b2bstup(&mut self, val: bool) {
1263 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
1264 }
1265 }
1266 impl Default for Doepint {
1267 #[inline(always)]
1268 fn default() -> Doepint {
1269 Doepint(0)
1270 }
1271 }
1272 #[doc = "Device OUT endpoint common interrupt mask register"]
1273 #[repr(transparent)]
1274 #[derive(Copy, Clone, Eq, PartialEq)]
1275 pub struct Doepmsk(pub u32);
1276 impl Doepmsk {
1277 #[doc = "Transfer completed interrupt mask"]
1278 #[inline(always)]
1279 pub const fn xfrcm(&self) -> bool {
1280 let val = (self.0 >> 0usize) & 0x01;
1281 val != 0
1282 }
1283 #[doc = "Transfer completed interrupt mask"]
1284 #[inline(always)]
1285 pub fn set_xfrcm(&mut self, val: bool) {
1286 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1287 }
1288 #[doc = "Endpoint disabled interrupt mask"]
1289 #[inline(always)]
1290 pub const fn epdm(&self) -> bool {
1291 let val = (self.0 >> 1usize) & 0x01;
1292 val != 0
1293 }
1294 #[doc = "Endpoint disabled interrupt mask"]
1295 #[inline(always)]
1296 pub fn set_epdm(&mut self, val: bool) {
1297 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1298 }
1299 #[doc = "SETUP phase done mask"]
1300 #[inline(always)]
1301 pub const fn stupm(&self) -> bool {
1302 let val = (self.0 >> 3usize) & 0x01;
1303 val != 0
1304 }
1305 #[doc = "SETUP phase done mask"]
1306 #[inline(always)]
1307 pub fn set_stupm(&mut self, val: bool) {
1308 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1309 }
1310 #[doc = "OUT token received when endpoint disabled mask"]
1311 #[inline(always)]
1312 pub const fn otepdm(&self) -> bool {
1313 let val = (self.0 >> 4usize) & 0x01;
1314 val != 0
1315 }
1316 #[doc = "OUT token received when endpoint disabled mask"]
1317 #[inline(always)]
1318 pub fn set_otepdm(&mut self, val: bool) {
1319 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1320 }
1321 }
1322 impl Default for Doepmsk {
1323 #[inline(always)]
1324 fn default() -> Doepmsk {
1325 Doepmsk(0)
1326 }
1327 }
1328 #[doc = "Device OUT endpoint transfer size register"]
1329 #[repr(transparent)]
1330 #[derive(Copy, Clone, Eq, PartialEq)]
1331 pub struct Doeptsiz(pub u32);
1332 impl Doeptsiz {
1333 #[doc = "Transfer size"]
1334 #[inline(always)]
1335 pub const fn xfrsiz(&self) -> u32 {
1336 let val = (self.0 >> 0usize) & 0x0007_ffff;
1337 val as u32
1338 }
1339 #[doc = "Transfer size"]
1340 #[inline(always)]
1341 pub fn set_xfrsiz(&mut self, val: u32) {
1342 self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
1343 }
1344 #[doc = "Packet count"]
1345 #[inline(always)]
1346 pub const fn pktcnt(&self) -> u16 {
1347 let val = (self.0 >> 19usize) & 0x03ff;
1348 val as u16
1349 }
1350 #[doc = "Packet count"]
1351 #[inline(always)]
1352 pub fn set_pktcnt(&mut self, val: u16) {
1353 self.0 = (self.0 & !(0x03ff << 19usize)) | (((val as u32) & 0x03ff) << 19usize);
1354 }
1355 #[doc = "Received data PID/SETUP packet count"]
1356 #[inline(always)]
1357 pub const fn rxdpid_stupcnt(&self) -> u8 {
1358 let val = (self.0 >> 29usize) & 0x03;
1359 val as u8
1360 }
1361 #[doc = "Received data PID/SETUP packet count"]
1362 #[inline(always)]
1363 pub fn set_rxdpid_stupcnt(&mut self, val: u8) {
1364 self.0 = (self.0 & !(0x03 << 29usize)) | (((val as u32) & 0x03) << 29usize);
1365 }
1366 }
1367 impl Default for Doeptsiz {
1368 #[inline(always)]
1369 fn default() -> Doeptsiz {
1370 Doeptsiz(0)
1371 }
1372 }
1373 #[doc = "Device status register"]
1374 #[repr(transparent)]
1375 #[derive(Copy, Clone, Eq, PartialEq)]
1376 pub struct Dsts(pub u32);
1377 impl Dsts {
1378 #[doc = "Suspend status"]
1379 #[inline(always)]
1380 pub const fn suspsts(&self) -> bool {
1381 let val = (self.0 >> 0usize) & 0x01;
1382 val != 0
1383 }
1384 #[doc = "Suspend status"]
1385 #[inline(always)]
1386 pub fn set_suspsts(&mut self, val: bool) {
1387 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1388 }
1389 #[doc = "Enumerated speed"]
1390 #[inline(always)]
1391 pub const fn enumspd(&self) -> super::vals::Dspd {
1392 let val = (self.0 >> 1usize) & 0x03;
1393 super::vals::Dspd::from_bits(val as u8)
1394 }
1395 #[doc = "Enumerated speed"]
1396 #[inline(always)]
1397 pub fn set_enumspd(&mut self, val: super::vals::Dspd) {
1398 self.0 = (self.0 & !(0x03 << 1usize)) | (((val.to_bits() as u32) & 0x03) << 1usize);
1399 }
1400 #[doc = "Erratic error"]
1401 #[inline(always)]
1402 pub const fn eerr(&self) -> bool {
1403 let val = (self.0 >> 3usize) & 0x01;
1404 val != 0
1405 }
1406 #[doc = "Erratic error"]
1407 #[inline(always)]
1408 pub fn set_eerr(&mut self, val: bool) {
1409 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1410 }
1411 #[doc = "Frame number of the received SOF"]
1412 #[inline(always)]
1413 pub const fn fnsof(&self) -> u16 {
1414 let val = (self.0 >> 8usize) & 0x3fff;
1415 val as u16
1416 }
1417 #[doc = "Frame number of the received SOF"]
1418 #[inline(always)]
1419 pub fn set_fnsof(&mut self, val: u16) {
1420 self.0 = (self.0 & !(0x3fff << 8usize)) | (((val as u32) & 0x3fff) << 8usize);
1421 }
1422 }
1423 impl Default for Dsts {
1424 #[inline(always)]
1425 fn default() -> Dsts {
1426 Dsts(0)
1427 }
1428 }
1429 #[doc = "Device IN endpoint transmit FIFO status register"]
1430 #[repr(transparent)]
1431 #[derive(Copy, Clone, Eq, PartialEq)]
1432 pub struct Dtxfsts(pub u32);
1433 impl Dtxfsts {
1434 #[doc = "IN endpoint TxFIFO space available"]
1435 #[inline(always)]
1436 pub const fn ineptfsav(&self) -> u16 {
1437 let val = (self.0 >> 0usize) & 0xffff;
1438 val as u16
1439 }
1440 #[doc = "IN endpoint TxFIFO space available"]
1441 #[inline(always)]
1442 pub fn set_ineptfsav(&mut self, val: u16) {
1443 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1444 }
1445 }
1446 impl Default for Dtxfsts {
1447 #[inline(always)]
1448 fn default() -> Dtxfsts {
1449 Dtxfsts(0)
1450 }
1451 }
1452 #[doc = "Device VBUS discharge time register"]
1453 #[repr(transparent)]
1454 #[derive(Copy, Clone, Eq, PartialEq)]
1455 pub struct Dvbusdis(pub u32);
1456 impl Dvbusdis {
1457 #[doc = "Device VBUS discharge time"]
1458 #[inline(always)]
1459 pub const fn vbusdt(&self) -> u16 {
1460 let val = (self.0 >> 0usize) & 0xffff;
1461 val as u16
1462 }
1463 #[doc = "Device VBUS discharge time"]
1464 #[inline(always)]
1465 pub fn set_vbusdt(&mut self, val: u16) {
1466 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1467 }
1468 }
1469 impl Default for Dvbusdis {
1470 #[inline(always)]
1471 fn default() -> Dvbusdis {
1472 Dvbusdis(0)
1473 }
1474 }
1475 #[doc = "Device VBUS pulsing time register"]
1476 #[repr(transparent)]
1477 #[derive(Copy, Clone, Eq, PartialEq)]
1478 pub struct Dvbuspulse(pub u32);
1479 impl Dvbuspulse {
1480 #[doc = "Device VBUS pulsing time"]
1481 #[inline(always)]
1482 pub const fn dvbusp(&self) -> u16 {
1483 let val = (self.0 >> 0usize) & 0x0fff;
1484 val as u16
1485 }
1486 #[doc = "Device VBUS pulsing time"]
1487 #[inline(always)]
1488 pub fn set_dvbusp(&mut self, val: u16) {
1489 self.0 = (self.0 & !(0x0fff << 0usize)) | (((val as u32) & 0x0fff) << 0usize);
1490 }
1491 }
1492 impl Default for Dvbuspulse {
1493 #[inline(always)]
1494 fn default() -> Dvbuspulse {
1495 Dvbuspulse(0)
1496 }
1497 }
1498 #[doc = "FIFO register"]
1499 #[repr(transparent)]
1500 #[derive(Copy, Clone, Eq, PartialEq)]
1501 pub struct Fifo(pub u32);
1502 impl Fifo {
1503 #[doc = "Data"]
1504 #[inline(always)]
1505 pub const fn data(&self) -> u32 {
1506 let val = (self.0 >> 0usize) & 0xffff_ffff;
1507 val as u32
1508 }
1509 #[doc = "Data"]
1510 #[inline(always)]
1511 pub fn set_data(&mut self, val: u32) {
1512 self.0 = (self.0 & !(0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize);
1513 }
1514 }
1515 impl Default for Fifo {
1516 #[inline(always)]
1517 fn default() -> Fifo {
1518 Fifo(0)
1519 }
1520 }
1521 #[doc = "FIFO size register"]
1522 #[repr(transparent)]
1523 #[derive(Copy, Clone, Eq, PartialEq)]
1524 pub struct Fsiz(pub u32);
1525 impl Fsiz {
1526 #[doc = "RAM start address"]
1527 #[inline(always)]
1528 pub const fn sa(&self) -> u16 {
1529 let val = (self.0 >> 0usize) & 0xffff;
1530 val as u16
1531 }
1532 #[doc = "RAM start address"]
1533 #[inline(always)]
1534 pub fn set_sa(&mut self, val: u16) {
1535 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
1536 }
1537 #[doc = "FIFO depth"]
1538 #[inline(always)]
1539 pub const fn fd(&self) -> u16 {
1540 let val = (self.0 >> 16usize) & 0xffff;
1541 val as u16
1542 }
1543 #[doc = "FIFO depth"]
1544 #[inline(always)]
1545 pub fn set_fd(&mut self, val: u16) {
1546 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
1547 }
1548 }
1549 impl Default for Fsiz {
1550 #[inline(always)]
1551 fn default() -> Fsiz {
1552 Fsiz(0)
1553 }
1554 }
1555 #[doc = "AHB configuration register"]
1556 #[repr(transparent)]
1557 #[derive(Copy, Clone, Eq, PartialEq)]
1558 pub struct Gahbcfg(pub u32);
1559 impl Gahbcfg {
1560 #[doc = "Global interrupt mask"]
1561 #[inline(always)]
1562 pub const fn gint(&self) -> bool {
1563 let val = (self.0 >> 0usize) & 0x01;
1564 val != 0
1565 }
1566 #[doc = "Global interrupt mask"]
1567 #[inline(always)]
1568 pub fn set_gint(&mut self, val: bool) {
1569 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1570 }
1571 #[doc = "Burst length/type"]
1572 #[inline(always)]
1573 pub const fn hbstlen(&self) -> u8 {
1574 let val = (self.0 >> 1usize) & 0x0f;
1575 val as u8
1576 }
1577 #[doc = "Burst length/type"]
1578 #[inline(always)]
1579 pub fn set_hbstlen(&mut self, val: u8) {
1580 self.0 = (self.0 & !(0x0f << 1usize)) | (((val as u32) & 0x0f) << 1usize);
1581 }
1582 #[doc = "DMA enable"]
1583 #[inline(always)]
1584 pub const fn dmaen(&self) -> bool {
1585 let val = (self.0 >> 5usize) & 0x01;
1586 val != 0
1587 }
1588 #[doc = "DMA enable"]
1589 #[inline(always)]
1590 pub fn set_dmaen(&mut self, val: bool) {
1591 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1592 }
1593 #[doc = "TxFIFO empty level"]
1594 #[inline(always)]
1595 pub const fn txfelvl(&self) -> bool {
1596 let val = (self.0 >> 7usize) & 0x01;
1597 val != 0
1598 }
1599 #[doc = "TxFIFO empty level"]
1600 #[inline(always)]
1601 pub fn set_txfelvl(&mut self, val: bool) {
1602 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
1603 }
1604 #[doc = "Periodic TxFIFO empty level"]
1605 #[inline(always)]
1606 pub const fn ptxfelvl(&self) -> bool {
1607 let val = (self.0 >> 8usize) & 0x01;
1608 val != 0
1609 }
1610 #[doc = "Periodic TxFIFO empty level"]
1611 #[inline(always)]
1612 pub fn set_ptxfelvl(&mut self, val: bool) {
1613 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
1614 }
1615 }
1616 impl Default for Gahbcfg {
1617 #[inline(always)]
1618 fn default() -> Gahbcfg {
1619 Gahbcfg(0)
1620 }
1621 }
1622 #[doc = "General core configuration register"]
1623 #[repr(transparent)]
1624 #[derive(Copy, Clone, Eq, PartialEq)]
1625 pub struct GccfgV1(pub u32);
1626 impl GccfgV1 {
1627 #[doc = "Power down"]
1628 #[inline(always)]
1629 pub const fn pwrdwn(&self) -> bool {
1630 let val = (self.0 >> 16usize) & 0x01;
1631 val != 0
1632 }
1633 #[doc = "Power down"]
1634 #[inline(always)]
1635 pub fn set_pwrdwn(&mut self, val: bool) {
1636 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1637 }
1638 #[doc = "Enable the VBUS \"A\" sensing device"]
1639 #[inline(always)]
1640 pub const fn vbusasen(&self) -> bool {
1641 let val = (self.0 >> 18usize) & 0x01;
1642 val != 0
1643 }
1644 #[doc = "Enable the VBUS \"A\" sensing device"]
1645 #[inline(always)]
1646 pub fn set_vbusasen(&mut self, val: bool) {
1647 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1648 }
1649 #[doc = "Enable the VBUS \"B\" sensing device"]
1650 #[inline(always)]
1651 pub const fn vbusbsen(&self) -> bool {
1652 let val = (self.0 >> 19usize) & 0x01;
1653 val != 0
1654 }
1655 #[doc = "Enable the VBUS \"B\" sensing device"]
1656 #[inline(always)]
1657 pub fn set_vbusbsen(&mut self, val: bool) {
1658 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1659 }
1660 #[doc = "SOF output enable"]
1661 #[inline(always)]
1662 pub const fn sofouten(&self) -> bool {
1663 let val = (self.0 >> 20usize) & 0x01;
1664 val != 0
1665 }
1666 #[doc = "SOF output enable"]
1667 #[inline(always)]
1668 pub fn set_sofouten(&mut self, val: bool) {
1669 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1670 }
1671 #[doc = "VBUS sensing disable"]
1672 #[inline(always)]
1673 pub const fn novbussens(&self) -> bool {
1674 let val = (self.0 >> 21usize) & 0x01;
1675 val != 0
1676 }
1677 #[doc = "VBUS sensing disable"]
1678 #[inline(always)]
1679 pub fn set_novbussens(&mut self, val: bool) {
1680 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1681 }
1682 }
1683 impl Default for GccfgV1 {
1684 #[inline(always)]
1685 fn default() -> GccfgV1 {
1686 GccfgV1(0)
1687 }
1688 }
1689 #[doc = "General core configuration register"]
1690 #[repr(transparent)]
1691 #[derive(Copy, Clone, Eq, PartialEq)]
1692 pub struct GccfgV2(pub u32);
1693 impl GccfgV2 {
1694 #[doc = "Data contact detection (DCD) status"]
1695 #[inline(always)]
1696 pub const fn dcdet(&self) -> bool {
1697 let val = (self.0 >> 0usize) & 0x01;
1698 val != 0
1699 }
1700 #[doc = "Data contact detection (DCD) status"]
1701 #[inline(always)]
1702 pub fn set_dcdet(&mut self, val: bool) {
1703 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
1704 }
1705 #[doc = "Primary detection (PD) status"]
1706 #[inline(always)]
1707 pub const fn pdet(&self) -> bool {
1708 let val = (self.0 >> 1usize) & 0x01;
1709 val != 0
1710 }
1711 #[doc = "Primary detection (PD) status"]
1712 #[inline(always)]
1713 pub fn set_pdet(&mut self, val: bool) {
1714 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1715 }
1716 #[doc = "Secondary detection (SD) status"]
1717 #[inline(always)]
1718 pub const fn sdet(&self) -> bool {
1719 let val = (self.0 >> 2usize) & 0x01;
1720 val != 0
1721 }
1722 #[doc = "Secondary detection (SD) status"]
1723 #[inline(always)]
1724 pub fn set_sdet(&mut self, val: bool) {
1725 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1726 }
1727 #[doc = "DM pull-up detection status"]
1728 #[inline(always)]
1729 pub const fn ps2det(&self) -> bool {
1730 let val = (self.0 >> 3usize) & 0x01;
1731 val != 0
1732 }
1733 #[doc = "DM pull-up detection status"]
1734 #[inline(always)]
1735 pub fn set_ps2det(&mut self, val: bool) {
1736 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1737 }
1738 #[doc = "Power down"]
1739 #[inline(always)]
1740 pub const fn pwrdwn(&self) -> bool {
1741 let val = (self.0 >> 16usize) & 0x01;
1742 val != 0
1743 }
1744 #[doc = "Power down"]
1745 #[inline(always)]
1746 pub fn set_pwrdwn(&mut self, val: bool) {
1747 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
1748 }
1749 #[doc = "Battery charging detector (BCD) enable"]
1750 #[inline(always)]
1751 pub const fn bcden(&self) -> bool {
1752 let val = (self.0 >> 17usize) & 0x01;
1753 val != 0
1754 }
1755 #[doc = "Battery charging detector (BCD) enable"]
1756 #[inline(always)]
1757 pub fn set_bcden(&mut self, val: bool) {
1758 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
1759 }
1760 #[doc = "Data contact detection (DCD) mode enable"]
1761 #[inline(always)]
1762 pub const fn dcden(&self) -> bool {
1763 let val = (self.0 >> 18usize) & 0x01;
1764 val != 0
1765 }
1766 #[doc = "Data contact detection (DCD) mode enable"]
1767 #[inline(always)]
1768 pub fn set_dcden(&mut self, val: bool) {
1769 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
1770 }
1771 #[doc = "Primary detection (PD) mode enable"]
1772 #[inline(always)]
1773 pub const fn pden(&self) -> bool {
1774 let val = (self.0 >> 19usize) & 0x01;
1775 val != 0
1776 }
1777 #[doc = "Primary detection (PD) mode enable"]
1778 #[inline(always)]
1779 pub fn set_pden(&mut self, val: bool) {
1780 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
1781 }
1782 #[doc = "Secondary detection (SD) mode enable"]
1783 #[inline(always)]
1784 pub const fn sden(&self) -> bool {
1785 let val = (self.0 >> 20usize) & 0x01;
1786 val != 0
1787 }
1788 #[doc = "Secondary detection (SD) mode enable"]
1789 #[inline(always)]
1790 pub fn set_sden(&mut self, val: bool) {
1791 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
1792 }
1793 #[doc = "USB VBUS detection enable"]
1794 #[inline(always)]
1795 pub const fn vbden(&self) -> bool {
1796 let val = (self.0 >> 21usize) & 0x01;
1797 val != 0
1798 }
1799 #[doc = "USB VBUS detection enable"]
1800 #[inline(always)]
1801 pub fn set_vbden(&mut self, val: bool) {
1802 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
1803 }
1804 #[doc = "Internal high-speed PHY enable."]
1805 #[inline(always)]
1806 pub const fn phyhsen(&self) -> bool {
1807 let val = (self.0 >> 23usize) & 0x01;
1808 val != 0
1809 }
1810 #[doc = "Internal high-speed PHY enable."]
1811 #[inline(always)]
1812 pub fn set_phyhsen(&mut self, val: bool) {
1813 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1814 }
1815 }
1816 impl Default for GccfgV2 {
1817 #[inline(always)]
1818 fn default() -> GccfgV2 {
1819 GccfgV2(0)
1820 }
1821 }
1822 #[doc = "I2C access register"]
1823 #[repr(transparent)]
1824 #[derive(Copy, Clone, Eq, PartialEq)]
1825 pub struct Gi2cctl(pub u32);
1826 impl Gi2cctl {
1827 #[doc = "I2C Read/Write Data"]
1828 #[inline(always)]
1829 pub const fn rwdata(&self) -> u8 {
1830 let val = (self.0 >> 0usize) & 0xff;
1831 val as u8
1832 }
1833 #[doc = "I2C Read/Write Data"]
1834 #[inline(always)]
1835 pub fn set_rwdata(&mut self, val: u8) {
1836 self.0 = (self.0 & !(0xff << 0usize)) | (((val as u32) & 0xff) << 0usize);
1837 }
1838 #[doc = "I2C Register Address"]
1839 #[inline(always)]
1840 pub const fn regaddr(&self) -> u8 {
1841 let val = (self.0 >> 8usize) & 0xff;
1842 val as u8
1843 }
1844 #[doc = "I2C Register Address"]
1845 #[inline(always)]
1846 pub fn set_regaddr(&mut self, val: u8) {
1847 self.0 = (self.0 & !(0xff << 8usize)) | (((val as u32) & 0xff) << 8usize);
1848 }
1849 #[doc = "I2C Address"]
1850 #[inline(always)]
1851 pub const fn addr(&self) -> u8 {
1852 let val = (self.0 >> 16usize) & 0x7f;
1853 val as u8
1854 }
1855 #[doc = "I2C Address"]
1856 #[inline(always)]
1857 pub fn set_addr(&mut self, val: u8) {
1858 self.0 = (self.0 & !(0x7f << 16usize)) | (((val as u32) & 0x7f) << 16usize);
1859 }
1860 #[doc = "I2C Enable"]
1861 #[inline(always)]
1862 pub const fn i2cen(&self) -> bool {
1863 let val = (self.0 >> 23usize) & 0x01;
1864 val != 0
1865 }
1866 #[doc = "I2C Enable"]
1867 #[inline(always)]
1868 pub fn set_i2cen(&mut self, val: bool) {
1869 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
1870 }
1871 #[doc = "I2C ACK"]
1872 #[inline(always)]
1873 pub const fn ack(&self) -> bool {
1874 let val = (self.0 >> 24usize) & 0x01;
1875 val != 0
1876 }
1877 #[doc = "I2C ACK"]
1878 #[inline(always)]
1879 pub fn set_ack(&mut self, val: bool) {
1880 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
1881 }
1882 #[doc = "I2C Device Address"]
1883 #[inline(always)]
1884 pub const fn i2cdevadr(&self) -> u8 {
1885 let val = (self.0 >> 26usize) & 0x03;
1886 val as u8
1887 }
1888 #[doc = "I2C Device Address"]
1889 #[inline(always)]
1890 pub fn set_i2cdevadr(&mut self, val: u8) {
1891 self.0 = (self.0 & !(0x03 << 26usize)) | (((val as u32) & 0x03) << 26usize);
1892 }
1893 #[doc = "I2C DatSe0 USB mode"]
1894 #[inline(always)]
1895 pub const fn i2cdatse0(&self) -> bool {
1896 let val = (self.0 >> 28usize) & 0x01;
1897 val != 0
1898 }
1899 #[doc = "I2C DatSe0 USB mode"]
1900 #[inline(always)]
1901 pub fn set_i2cdatse0(&mut self, val: bool) {
1902 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
1903 }
1904 #[doc = "Read/Write Indicator"]
1905 #[inline(always)]
1906 pub const fn rw(&self) -> bool {
1907 let val = (self.0 >> 30usize) & 0x01;
1908 val != 0
1909 }
1910 #[doc = "Read/Write Indicator"]
1911 #[inline(always)]
1912 pub fn set_rw(&mut self, val: bool) {
1913 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
1914 }
1915 #[doc = "I2C Busy/Done"]
1916 #[inline(always)]
1917 pub const fn bsydne(&self) -> bool {
1918 let val = (self.0 >> 31usize) & 0x01;
1919 val != 0
1920 }
1921 #[doc = "I2C Busy/Done"]
1922 #[inline(always)]
1923 pub fn set_bsydne(&mut self, val: bool) {
1924 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
1925 }
1926 }
1927 impl Default for Gi2cctl {
1928 #[inline(always)]
1929 fn default() -> Gi2cctl {
1930 Gi2cctl(0)
1931 }
1932 }
1933 #[doc = "Interrupt mask register"]
1934 #[repr(transparent)]
1935 #[derive(Copy, Clone, Eq, PartialEq)]
1936 pub struct Gintmsk(pub u32);
1937 impl Gintmsk {
1938 #[doc = "Mode mismatch interrupt mask"]
1939 #[inline(always)]
1940 pub const fn mmism(&self) -> bool {
1941 let val = (self.0 >> 1usize) & 0x01;
1942 val != 0
1943 }
1944 #[doc = "Mode mismatch interrupt mask"]
1945 #[inline(always)]
1946 pub fn set_mmism(&mut self, val: bool) {
1947 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
1948 }
1949 #[doc = "OTG interrupt mask"]
1950 #[inline(always)]
1951 pub const fn otgint(&self) -> bool {
1952 let val = (self.0 >> 2usize) & 0x01;
1953 val != 0
1954 }
1955 #[doc = "OTG interrupt mask"]
1956 #[inline(always)]
1957 pub fn set_otgint(&mut self, val: bool) {
1958 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
1959 }
1960 #[doc = "Start of frame mask"]
1961 #[inline(always)]
1962 pub const fn sofm(&self) -> bool {
1963 let val = (self.0 >> 3usize) & 0x01;
1964 val != 0
1965 }
1966 #[doc = "Start of frame mask"]
1967 #[inline(always)]
1968 pub fn set_sofm(&mut self, val: bool) {
1969 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
1970 }
1971 #[doc = "Receive FIFO non-empty mask"]
1972 #[inline(always)]
1973 pub const fn rxflvlm(&self) -> bool {
1974 let val = (self.0 >> 4usize) & 0x01;
1975 val != 0
1976 }
1977 #[doc = "Receive FIFO non-empty mask"]
1978 #[inline(always)]
1979 pub fn set_rxflvlm(&mut self, val: bool) {
1980 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
1981 }
1982 #[doc = "Non-periodic TxFIFO empty mask"]
1983 #[inline(always)]
1984 pub const fn nptxfem(&self) -> bool {
1985 let val = (self.0 >> 5usize) & 0x01;
1986 val != 0
1987 }
1988 #[doc = "Non-periodic TxFIFO empty mask"]
1989 #[inline(always)]
1990 pub fn set_nptxfem(&mut self, val: bool) {
1991 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
1992 }
1993 #[doc = "Global non-periodic IN NAK effective mask"]
1994 #[inline(always)]
1995 pub const fn ginakeffm(&self) -> bool {
1996 let val = (self.0 >> 6usize) & 0x01;
1997 val != 0
1998 }
1999 #[doc = "Global non-periodic IN NAK effective mask"]
2000 #[inline(always)]
2001 pub fn set_ginakeffm(&mut self, val: bool) {
2002 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2003 }
2004 #[doc = "Global OUT NAK effective mask"]
2005 #[inline(always)]
2006 pub const fn gonakeffm(&self) -> bool {
2007 let val = (self.0 >> 7usize) & 0x01;
2008 val != 0
2009 }
2010 #[doc = "Global OUT NAK effective mask"]
2011 #[inline(always)]
2012 pub fn set_gonakeffm(&mut self, val: bool) {
2013 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2014 }
2015 #[doc = "Early suspend mask"]
2016 #[inline(always)]
2017 pub const fn esuspm(&self) -> bool {
2018 let val = (self.0 >> 10usize) & 0x01;
2019 val != 0
2020 }
2021 #[doc = "Early suspend mask"]
2022 #[inline(always)]
2023 pub fn set_esuspm(&mut self, val: bool) {
2024 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2025 }
2026 #[doc = "USB suspend mask"]
2027 #[inline(always)]
2028 pub const fn usbsuspm(&self) -> bool {
2029 let val = (self.0 >> 11usize) & 0x01;
2030 val != 0
2031 }
2032 #[doc = "USB suspend mask"]
2033 #[inline(always)]
2034 pub fn set_usbsuspm(&mut self, val: bool) {
2035 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2036 }
2037 #[doc = "USB reset mask"]
2038 #[inline(always)]
2039 pub const fn usbrst(&self) -> bool {
2040 let val = (self.0 >> 12usize) & 0x01;
2041 val != 0
2042 }
2043 #[doc = "USB reset mask"]
2044 #[inline(always)]
2045 pub fn set_usbrst(&mut self, val: bool) {
2046 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2047 }
2048 #[doc = "Enumeration done mask"]
2049 #[inline(always)]
2050 pub const fn enumdnem(&self) -> bool {
2051 let val = (self.0 >> 13usize) & 0x01;
2052 val != 0
2053 }
2054 #[doc = "Enumeration done mask"]
2055 #[inline(always)]
2056 pub fn set_enumdnem(&mut self, val: bool) {
2057 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2058 }
2059 #[doc = "Isochronous OUT packet dropped interrupt mask"]
2060 #[inline(always)]
2061 pub const fn isoodrpm(&self) -> bool {
2062 let val = (self.0 >> 14usize) & 0x01;
2063 val != 0
2064 }
2065 #[doc = "Isochronous OUT packet dropped interrupt mask"]
2066 #[inline(always)]
2067 pub fn set_isoodrpm(&mut self, val: bool) {
2068 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2069 }
2070 #[doc = "End of periodic frame interrupt mask"]
2071 #[inline(always)]
2072 pub const fn eopfm(&self) -> bool {
2073 let val = (self.0 >> 15usize) & 0x01;
2074 val != 0
2075 }
2076 #[doc = "End of periodic frame interrupt mask"]
2077 #[inline(always)]
2078 pub fn set_eopfm(&mut self, val: bool) {
2079 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2080 }
2081 #[doc = "Endpoint mismatch interrupt mask"]
2082 #[inline(always)]
2083 pub const fn epmism(&self) -> bool {
2084 let val = (self.0 >> 17usize) & 0x01;
2085 val != 0
2086 }
2087 #[doc = "Endpoint mismatch interrupt mask"]
2088 #[inline(always)]
2089 pub fn set_epmism(&mut self, val: bool) {
2090 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2091 }
2092 #[doc = "IN endpoints interrupt mask"]
2093 #[inline(always)]
2094 pub const fn iepint(&self) -> bool {
2095 let val = (self.0 >> 18usize) & 0x01;
2096 val != 0
2097 }
2098 #[doc = "IN endpoints interrupt mask"]
2099 #[inline(always)]
2100 pub fn set_iepint(&mut self, val: bool) {
2101 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2102 }
2103 #[doc = "OUT endpoints interrupt mask"]
2104 #[inline(always)]
2105 pub const fn oepint(&self) -> bool {
2106 let val = (self.0 >> 19usize) & 0x01;
2107 val != 0
2108 }
2109 #[doc = "OUT endpoints interrupt mask"]
2110 #[inline(always)]
2111 pub fn set_oepint(&mut self, val: bool) {
2112 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2113 }
2114 #[doc = "Incomplete isochronous IN transfer mask"]
2115 #[inline(always)]
2116 pub const fn iisoixfrm(&self) -> bool {
2117 let val = (self.0 >> 20usize) & 0x01;
2118 val != 0
2119 }
2120 #[doc = "Incomplete isochronous IN transfer mask"]
2121 #[inline(always)]
2122 pub fn set_iisoixfrm(&mut self, val: bool) {
2123 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2124 }
2125 #[doc = "Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode)"]
2126 #[inline(always)]
2127 pub const fn ipxfrm_iisooxfrm(&self) -> bool {
2128 let val = (self.0 >> 21usize) & 0x01;
2129 val != 0
2130 }
2131 #[doc = "Incomplete periodic transfer mask (host mode) / Incomplete isochronous OUT transfer mask (device mode)"]
2132 #[inline(always)]
2133 pub fn set_ipxfrm_iisooxfrm(&mut self, val: bool) {
2134 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
2135 }
2136 #[doc = "Data fetch suspended mask"]
2137 #[inline(always)]
2138 pub const fn fsuspm(&self) -> bool {
2139 let val = (self.0 >> 22usize) & 0x01;
2140 val != 0
2141 }
2142 #[doc = "Data fetch suspended mask"]
2143 #[inline(always)]
2144 pub fn set_fsuspm(&mut self, val: bool) {
2145 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
2146 }
2147 #[doc = "Reset detected interrupt mask"]
2148 #[inline(always)]
2149 pub const fn rstde(&self) -> bool {
2150 let val = (self.0 >> 23usize) & 0x01;
2151 val != 0
2152 }
2153 #[doc = "Reset detected interrupt mask"]
2154 #[inline(always)]
2155 pub fn set_rstde(&mut self, val: bool) {
2156 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
2157 }
2158 #[doc = "Host port interrupt mask"]
2159 #[inline(always)]
2160 pub const fn prtim(&self) -> bool {
2161 let val = (self.0 >> 24usize) & 0x01;
2162 val != 0
2163 }
2164 #[doc = "Host port interrupt mask"]
2165 #[inline(always)]
2166 pub fn set_prtim(&mut self, val: bool) {
2167 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2168 }
2169 #[doc = "Host channels interrupt mask"]
2170 #[inline(always)]
2171 pub const fn hcim(&self) -> bool {
2172 let val = (self.0 >> 25usize) & 0x01;
2173 val != 0
2174 }
2175 #[doc = "Host channels interrupt mask"]
2176 #[inline(always)]
2177 pub fn set_hcim(&mut self, val: bool) {
2178 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
2179 }
2180 #[doc = "Periodic TxFIFO empty mask"]
2181 #[inline(always)]
2182 pub const fn ptxfem(&self) -> bool {
2183 let val = (self.0 >> 26usize) & 0x01;
2184 val != 0
2185 }
2186 #[doc = "Periodic TxFIFO empty mask"]
2187 #[inline(always)]
2188 pub fn set_ptxfem(&mut self, val: bool) {
2189 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
2190 }
2191 #[doc = "LPM interrupt mask"]
2192 #[inline(always)]
2193 pub const fn lpmintm(&self) -> bool {
2194 let val = (self.0 >> 27usize) & 0x01;
2195 val != 0
2196 }
2197 #[doc = "LPM interrupt mask"]
2198 #[inline(always)]
2199 pub fn set_lpmintm(&mut self, val: bool) {
2200 self.0 = (self.0 & !(0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize);
2201 }
2202 #[doc = "Connector ID status change mask"]
2203 #[inline(always)]
2204 pub const fn cidschgm(&self) -> bool {
2205 let val = (self.0 >> 28usize) & 0x01;
2206 val != 0
2207 }
2208 #[doc = "Connector ID status change mask"]
2209 #[inline(always)]
2210 pub fn set_cidschgm(&mut self, val: bool) {
2211 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2212 }
2213 #[doc = "Disconnect detected interrupt mask"]
2214 #[inline(always)]
2215 pub const fn discint(&self) -> bool {
2216 let val = (self.0 >> 29usize) & 0x01;
2217 val != 0
2218 }
2219 #[doc = "Disconnect detected interrupt mask"]
2220 #[inline(always)]
2221 pub fn set_discint(&mut self, val: bool) {
2222 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2223 }
2224 #[doc = "Session request/new session detected interrupt mask"]
2225 #[inline(always)]
2226 pub const fn srqim(&self) -> bool {
2227 let val = (self.0 >> 30usize) & 0x01;
2228 val != 0
2229 }
2230 #[doc = "Session request/new session detected interrupt mask"]
2231 #[inline(always)]
2232 pub fn set_srqim(&mut self, val: bool) {
2233 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
2234 }
2235 #[doc = "Resume/remote wakeup detected interrupt mask"]
2236 #[inline(always)]
2237 pub const fn wuim(&self) -> bool {
2238 let val = (self.0 >> 31usize) & 0x01;
2239 val != 0
2240 }
2241 #[doc = "Resume/remote wakeup detected interrupt mask"]
2242 #[inline(always)]
2243 pub fn set_wuim(&mut self, val: bool) {
2244 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2245 }
2246 }
2247 impl Default for Gintmsk {
2248 #[inline(always)]
2249 fn default() -> Gintmsk {
2250 Gintmsk(0)
2251 }
2252 }
2253 #[doc = "Core interrupt register"]
2254 #[repr(transparent)]
2255 #[derive(Copy, Clone, Eq, PartialEq)]
2256 pub struct Gintsts(pub u32);
2257 impl Gintsts {
2258 #[doc = "Current mode of operation"]
2259 #[inline(always)]
2260 pub const fn cmod(&self) -> bool {
2261 let val = (self.0 >> 0usize) & 0x01;
2262 val != 0
2263 }
2264 #[doc = "Current mode of operation"]
2265 #[inline(always)]
2266 pub fn set_cmod(&mut self, val: bool) {
2267 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2268 }
2269 #[doc = "Mode mismatch interrupt"]
2270 #[inline(always)]
2271 pub const fn mmis(&self) -> bool {
2272 let val = (self.0 >> 1usize) & 0x01;
2273 val != 0
2274 }
2275 #[doc = "Mode mismatch interrupt"]
2276 #[inline(always)]
2277 pub fn set_mmis(&mut self, val: bool) {
2278 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2279 }
2280 #[doc = "OTG interrupt"]
2281 #[inline(always)]
2282 pub const fn otgint(&self) -> bool {
2283 let val = (self.0 >> 2usize) & 0x01;
2284 val != 0
2285 }
2286 #[doc = "OTG interrupt"]
2287 #[inline(always)]
2288 pub fn set_otgint(&mut self, val: bool) {
2289 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2290 }
2291 #[doc = "Start of frame"]
2292 #[inline(always)]
2293 pub const fn sof(&self) -> bool {
2294 let val = (self.0 >> 3usize) & 0x01;
2295 val != 0
2296 }
2297 #[doc = "Start of frame"]
2298 #[inline(always)]
2299 pub fn set_sof(&mut self, val: bool) {
2300 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2301 }
2302 #[doc = "RxFIFO non-empty"]
2303 #[inline(always)]
2304 pub const fn rxflvl(&self) -> bool {
2305 let val = (self.0 >> 4usize) & 0x01;
2306 val != 0
2307 }
2308 #[doc = "RxFIFO non-empty"]
2309 #[inline(always)]
2310 pub fn set_rxflvl(&mut self, val: bool) {
2311 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2312 }
2313 #[doc = "Non-periodic TxFIFO empty"]
2314 #[inline(always)]
2315 pub const fn nptxfe(&self) -> bool {
2316 let val = (self.0 >> 5usize) & 0x01;
2317 val != 0
2318 }
2319 #[doc = "Non-periodic TxFIFO empty"]
2320 #[inline(always)]
2321 pub fn set_nptxfe(&mut self, val: bool) {
2322 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2323 }
2324 #[doc = "Global IN non-periodic NAK effective"]
2325 #[inline(always)]
2326 pub const fn ginakeff(&self) -> bool {
2327 let val = (self.0 >> 6usize) & 0x01;
2328 val != 0
2329 }
2330 #[doc = "Global IN non-periodic NAK effective"]
2331 #[inline(always)]
2332 pub fn set_ginakeff(&mut self, val: bool) {
2333 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2334 }
2335 #[doc = "Global OUT NAK effective"]
2336 #[inline(always)]
2337 pub const fn goutnakeff(&self) -> bool {
2338 let val = (self.0 >> 7usize) & 0x01;
2339 val != 0
2340 }
2341 #[doc = "Global OUT NAK effective"]
2342 #[inline(always)]
2343 pub fn set_goutnakeff(&mut self, val: bool) {
2344 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2345 }
2346 #[doc = "Early suspend"]
2347 #[inline(always)]
2348 pub const fn esusp(&self) -> bool {
2349 let val = (self.0 >> 10usize) & 0x01;
2350 val != 0
2351 }
2352 #[doc = "Early suspend"]
2353 #[inline(always)]
2354 pub fn set_esusp(&mut self, val: bool) {
2355 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2356 }
2357 #[doc = "USB suspend"]
2358 #[inline(always)]
2359 pub const fn usbsusp(&self) -> bool {
2360 let val = (self.0 >> 11usize) & 0x01;
2361 val != 0
2362 }
2363 #[doc = "USB suspend"]
2364 #[inline(always)]
2365 pub fn set_usbsusp(&mut self, val: bool) {
2366 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2367 }
2368 #[doc = "USB reset"]
2369 #[inline(always)]
2370 pub const fn usbrst(&self) -> bool {
2371 let val = (self.0 >> 12usize) & 0x01;
2372 val != 0
2373 }
2374 #[doc = "USB reset"]
2375 #[inline(always)]
2376 pub fn set_usbrst(&mut self, val: bool) {
2377 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2378 }
2379 #[doc = "Enumeration done"]
2380 #[inline(always)]
2381 pub const fn enumdne(&self) -> bool {
2382 let val = (self.0 >> 13usize) & 0x01;
2383 val != 0
2384 }
2385 #[doc = "Enumeration done"]
2386 #[inline(always)]
2387 pub fn set_enumdne(&mut self, val: bool) {
2388 self.0 = (self.0 & !(0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize);
2389 }
2390 #[doc = "Isochronous OUT packet dropped interrupt"]
2391 #[inline(always)]
2392 pub const fn isoodrp(&self) -> bool {
2393 let val = (self.0 >> 14usize) & 0x01;
2394 val != 0
2395 }
2396 #[doc = "Isochronous OUT packet dropped interrupt"]
2397 #[inline(always)]
2398 pub fn set_isoodrp(&mut self, val: bool) {
2399 self.0 = (self.0 & !(0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize);
2400 }
2401 #[doc = "End of periodic frame interrupt"]
2402 #[inline(always)]
2403 pub const fn eopf(&self) -> bool {
2404 let val = (self.0 >> 15usize) & 0x01;
2405 val != 0
2406 }
2407 #[doc = "End of periodic frame interrupt"]
2408 #[inline(always)]
2409 pub fn set_eopf(&mut self, val: bool) {
2410 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2411 }
2412 #[doc = "IN endpoint interrupt"]
2413 #[inline(always)]
2414 pub const fn iepint(&self) -> bool {
2415 let val = (self.0 >> 18usize) & 0x01;
2416 val != 0
2417 }
2418 #[doc = "IN endpoint interrupt"]
2419 #[inline(always)]
2420 pub fn set_iepint(&mut self, val: bool) {
2421 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2422 }
2423 #[doc = "OUT endpoint interrupt"]
2424 #[inline(always)]
2425 pub const fn oepint(&self) -> bool {
2426 let val = (self.0 >> 19usize) & 0x01;
2427 val != 0
2428 }
2429 #[doc = "OUT endpoint interrupt"]
2430 #[inline(always)]
2431 pub fn set_oepint(&mut self, val: bool) {
2432 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2433 }
2434 #[doc = "Incomplete isochronous IN transfer"]
2435 #[inline(always)]
2436 pub const fn iisoixfr(&self) -> bool {
2437 let val = (self.0 >> 20usize) & 0x01;
2438 val != 0
2439 }
2440 #[doc = "Incomplete isochronous IN transfer"]
2441 #[inline(always)]
2442 pub fn set_iisoixfr(&mut self, val: bool) {
2443 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
2444 }
2445 #[doc = "Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode)"]
2446 #[inline(always)]
2447 pub const fn ipxfr_incompisoout(&self) -> bool {
2448 let val = (self.0 >> 21usize) & 0x01;
2449 val != 0
2450 }
2451 #[doc = "Incomplete periodic transfer (host mode) / Incomplete isochronous OUT transfer (device mode)"]
2452 #[inline(always)]
2453 pub fn set_ipxfr_incompisoout(&mut self, val: bool) {
2454 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
2455 }
2456 #[doc = "Data fetch suspended"]
2457 #[inline(always)]
2458 pub const fn datafsusp(&self) -> bool {
2459 let val = (self.0 >> 22usize) & 0x01;
2460 val != 0
2461 }
2462 #[doc = "Data fetch suspended"]
2463 #[inline(always)]
2464 pub fn set_datafsusp(&mut self, val: bool) {
2465 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
2466 }
2467 #[doc = "Host port interrupt"]
2468 #[inline(always)]
2469 pub const fn hprtint(&self) -> bool {
2470 let val = (self.0 >> 24usize) & 0x01;
2471 val != 0
2472 }
2473 #[doc = "Host port interrupt"]
2474 #[inline(always)]
2475 pub fn set_hprtint(&mut self, val: bool) {
2476 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2477 }
2478 #[doc = "Host channels interrupt"]
2479 #[inline(always)]
2480 pub const fn hcint(&self) -> bool {
2481 let val = (self.0 >> 25usize) & 0x01;
2482 val != 0
2483 }
2484 #[doc = "Host channels interrupt"]
2485 #[inline(always)]
2486 pub fn set_hcint(&mut self, val: bool) {
2487 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
2488 }
2489 #[doc = "Periodic TxFIFO empty"]
2490 #[inline(always)]
2491 pub const fn ptxfe(&self) -> bool {
2492 let val = (self.0 >> 26usize) & 0x01;
2493 val != 0
2494 }
2495 #[doc = "Periodic TxFIFO empty"]
2496 #[inline(always)]
2497 pub fn set_ptxfe(&mut self, val: bool) {
2498 self.0 = (self.0 & !(0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize);
2499 }
2500 #[doc = "Connector ID status change"]
2501 #[inline(always)]
2502 pub const fn cidschg(&self) -> bool {
2503 let val = (self.0 >> 28usize) & 0x01;
2504 val != 0
2505 }
2506 #[doc = "Connector ID status change"]
2507 #[inline(always)]
2508 pub fn set_cidschg(&mut self, val: bool) {
2509 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2510 }
2511 #[doc = "Disconnect detected interrupt"]
2512 #[inline(always)]
2513 pub const fn discint(&self) -> bool {
2514 let val = (self.0 >> 29usize) & 0x01;
2515 val != 0
2516 }
2517 #[doc = "Disconnect detected interrupt"]
2518 #[inline(always)]
2519 pub fn set_discint(&mut self, val: bool) {
2520 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
2521 }
2522 #[doc = "Session request/new session detected interrupt"]
2523 #[inline(always)]
2524 pub const fn srqint(&self) -> bool {
2525 let val = (self.0 >> 30usize) & 0x01;
2526 val != 0
2527 }
2528 #[doc = "Session request/new session detected interrupt"]
2529 #[inline(always)]
2530 pub fn set_srqint(&mut self, val: bool) {
2531 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
2532 }
2533 #[doc = "Resume/remote wakeup detected interrupt"]
2534 #[inline(always)]
2535 pub const fn wkupint(&self) -> bool {
2536 let val = (self.0 >> 31usize) & 0x01;
2537 val != 0
2538 }
2539 #[doc = "Resume/remote wakeup detected interrupt"]
2540 #[inline(always)]
2541 pub fn set_wkupint(&mut self, val: bool) {
2542 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
2543 }
2544 }
2545 impl Default for Gintsts {
2546 #[inline(always)]
2547 fn default() -> Gintsts {
2548 Gintsts(0)
2549 }
2550 }
2551 #[doc = "Core LPM configuration register"]
2552 #[repr(transparent)]
2553 #[derive(Copy, Clone, Eq, PartialEq)]
2554 pub struct Glpmcfg(pub u32);
2555 impl Glpmcfg {
2556 #[doc = "LPM support enable"]
2557 #[inline(always)]
2558 pub const fn lpmen(&self) -> bool {
2559 let val = (self.0 >> 0usize) & 0x01;
2560 val != 0
2561 }
2562 #[doc = "LPM support enable"]
2563 #[inline(always)]
2564 pub fn set_lpmen(&mut self, val: bool) {
2565 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2566 }
2567 #[doc = "LPM token acknowledge enable"]
2568 #[inline(always)]
2569 pub const fn lpmack(&self) -> bool {
2570 let val = (self.0 >> 1usize) & 0x01;
2571 val != 0
2572 }
2573 #[doc = "LPM token acknowledge enable"]
2574 #[inline(always)]
2575 pub fn set_lpmack(&mut self, val: bool) {
2576 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2577 }
2578 #[doc = "Best effort service latency"]
2579 #[inline(always)]
2580 pub const fn besl(&self) -> u8 {
2581 let val = (self.0 >> 2usize) & 0x0f;
2582 val as u8
2583 }
2584 #[doc = "Best effort service latency"]
2585 #[inline(always)]
2586 pub fn set_besl(&mut self, val: u8) {
2587 self.0 = (self.0 & !(0x0f << 2usize)) | (((val as u32) & 0x0f) << 2usize);
2588 }
2589 #[doc = "bRemoteWake value"]
2590 #[inline(always)]
2591 pub const fn remwake(&self) -> bool {
2592 let val = (self.0 >> 6usize) & 0x01;
2593 val != 0
2594 }
2595 #[doc = "bRemoteWake value"]
2596 #[inline(always)]
2597 pub fn set_remwake(&mut self, val: bool) {
2598 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2599 }
2600 #[doc = "L1 Shallow Sleep enable"]
2601 #[inline(always)]
2602 pub const fn l1ssen(&self) -> bool {
2603 let val = (self.0 >> 7usize) & 0x01;
2604 val != 0
2605 }
2606 #[doc = "L1 Shallow Sleep enable"]
2607 #[inline(always)]
2608 pub fn set_l1ssen(&mut self, val: bool) {
2609 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2610 }
2611 #[doc = "BESL threshold"]
2612 #[inline(always)]
2613 pub const fn beslthrs(&self) -> u8 {
2614 let val = (self.0 >> 8usize) & 0x0f;
2615 val as u8
2616 }
2617 #[doc = "BESL threshold"]
2618 #[inline(always)]
2619 pub fn set_beslthrs(&mut self, val: u8) {
2620 self.0 = (self.0 & !(0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize);
2621 }
2622 #[doc = "L1 deep sleep enable"]
2623 #[inline(always)]
2624 pub const fn l1dsen(&self) -> bool {
2625 let val = (self.0 >> 12usize) & 0x01;
2626 val != 0
2627 }
2628 #[doc = "L1 deep sleep enable"]
2629 #[inline(always)]
2630 pub fn set_l1dsen(&mut self, val: bool) {
2631 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2632 }
2633 #[doc = "LPM response"]
2634 #[inline(always)]
2635 pub const fn lpmrst(&self) -> u8 {
2636 let val = (self.0 >> 13usize) & 0x03;
2637 val as u8
2638 }
2639 #[doc = "LPM response"]
2640 #[inline(always)]
2641 pub fn set_lpmrst(&mut self, val: u8) {
2642 self.0 = (self.0 & !(0x03 << 13usize)) | (((val as u32) & 0x03) << 13usize);
2643 }
2644 #[doc = "Port sleep status"]
2645 #[inline(always)]
2646 pub const fn slpsts(&self) -> bool {
2647 let val = (self.0 >> 15usize) & 0x01;
2648 val != 0
2649 }
2650 #[doc = "Port sleep status"]
2651 #[inline(always)]
2652 pub fn set_slpsts(&mut self, val: bool) {
2653 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
2654 }
2655 #[doc = "Sleep State Resume OK"]
2656 #[inline(always)]
2657 pub const fn l1rsmok(&self) -> bool {
2658 let val = (self.0 >> 16usize) & 0x01;
2659 val != 0
2660 }
2661 #[doc = "Sleep State Resume OK"]
2662 #[inline(always)]
2663 pub fn set_l1rsmok(&mut self, val: bool) {
2664 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2665 }
2666 #[doc = "LPM Channel Index"]
2667 #[inline(always)]
2668 pub const fn lpmchidx(&self) -> u8 {
2669 let val = (self.0 >> 17usize) & 0x0f;
2670 val as u8
2671 }
2672 #[doc = "LPM Channel Index"]
2673 #[inline(always)]
2674 pub fn set_lpmchidx(&mut self, val: u8) {
2675 self.0 = (self.0 & !(0x0f << 17usize)) | (((val as u32) & 0x0f) << 17usize);
2676 }
2677 #[doc = "LPM retry count"]
2678 #[inline(always)]
2679 pub const fn lpmrcnt(&self) -> u8 {
2680 let val = (self.0 >> 21usize) & 0x07;
2681 val as u8
2682 }
2683 #[doc = "LPM retry count"]
2684 #[inline(always)]
2685 pub fn set_lpmrcnt(&mut self, val: u8) {
2686 self.0 = (self.0 & !(0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize);
2687 }
2688 #[doc = "Send LPM transaction"]
2689 #[inline(always)]
2690 pub const fn sndlpm(&self) -> bool {
2691 let val = (self.0 >> 24usize) & 0x01;
2692 val != 0
2693 }
2694 #[doc = "Send LPM transaction"]
2695 #[inline(always)]
2696 pub fn set_sndlpm(&mut self, val: bool) {
2697 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
2698 }
2699 #[doc = "LPM retry count status"]
2700 #[inline(always)]
2701 pub const fn lpmrcntsts(&self) -> u8 {
2702 let val = (self.0 >> 25usize) & 0x07;
2703 val as u8
2704 }
2705 #[doc = "LPM retry count status"]
2706 #[inline(always)]
2707 pub fn set_lpmrcntsts(&mut self, val: u8) {
2708 self.0 = (self.0 & !(0x07 << 25usize)) | (((val as u32) & 0x07) << 25usize);
2709 }
2710 #[doc = "Enable best effort service latency"]
2711 #[inline(always)]
2712 pub const fn enbesl(&self) -> bool {
2713 let val = (self.0 >> 28usize) & 0x01;
2714 val != 0
2715 }
2716 #[doc = "Enable best effort service latency"]
2717 #[inline(always)]
2718 pub fn set_enbesl(&mut self, val: bool) {
2719 self.0 = (self.0 & !(0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize);
2720 }
2721 }
2722 impl Default for Glpmcfg {
2723 #[inline(always)]
2724 fn default() -> Glpmcfg {
2725 Glpmcfg(0)
2726 }
2727 }
2728 #[doc = "Control and status register"]
2729 #[repr(transparent)]
2730 #[derive(Copy, Clone, Eq, PartialEq)]
2731 pub struct Gotgctl(pub u32);
2732 impl Gotgctl {
2733 #[doc = "Session request success"]
2734 #[inline(always)]
2735 pub const fn srqscs(&self) -> bool {
2736 let val = (self.0 >> 0usize) & 0x01;
2737 val != 0
2738 }
2739 #[doc = "Session request success"]
2740 #[inline(always)]
2741 pub fn set_srqscs(&mut self, val: bool) {
2742 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
2743 }
2744 #[doc = "Session request"]
2745 #[inline(always)]
2746 pub const fn srq(&self) -> bool {
2747 let val = (self.0 >> 1usize) & 0x01;
2748 val != 0
2749 }
2750 #[doc = "Session request"]
2751 #[inline(always)]
2752 pub fn set_srq(&mut self, val: bool) {
2753 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
2754 }
2755 #[doc = "VBUS valid override enable"]
2756 #[inline(always)]
2757 pub const fn vbvaloen(&self) -> bool {
2758 let val = (self.0 >> 2usize) & 0x01;
2759 val != 0
2760 }
2761 #[doc = "VBUS valid override enable"]
2762 #[inline(always)]
2763 pub fn set_vbvaloen(&mut self, val: bool) {
2764 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2765 }
2766 #[doc = "VBUS valid override value"]
2767 #[inline(always)]
2768 pub const fn vbvaloval(&self) -> bool {
2769 let val = (self.0 >> 3usize) & 0x01;
2770 val != 0
2771 }
2772 #[doc = "VBUS valid override value"]
2773 #[inline(always)]
2774 pub fn set_vbvaloval(&mut self, val: bool) {
2775 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
2776 }
2777 #[doc = "A-peripheral session valid override enable"]
2778 #[inline(always)]
2779 pub const fn avaloen(&self) -> bool {
2780 let val = (self.0 >> 4usize) & 0x01;
2781 val != 0
2782 }
2783 #[doc = "A-peripheral session valid override enable"]
2784 #[inline(always)]
2785 pub fn set_avaloen(&mut self, val: bool) {
2786 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
2787 }
2788 #[doc = "A-peripheral session valid override value"]
2789 #[inline(always)]
2790 pub const fn avaloval(&self) -> bool {
2791 let val = (self.0 >> 5usize) & 0x01;
2792 val != 0
2793 }
2794 #[doc = "A-peripheral session valid override value"]
2795 #[inline(always)]
2796 pub fn set_avaloval(&mut self, val: bool) {
2797 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
2798 }
2799 #[doc = "B-peripheral session valid override enable"]
2800 #[inline(always)]
2801 pub const fn bvaloen(&self) -> bool {
2802 let val = (self.0 >> 6usize) & 0x01;
2803 val != 0
2804 }
2805 #[doc = "B-peripheral session valid override enable"]
2806 #[inline(always)]
2807 pub fn set_bvaloen(&mut self, val: bool) {
2808 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
2809 }
2810 #[doc = "B-peripheral session valid override value"]
2811 #[inline(always)]
2812 pub const fn bvaloval(&self) -> bool {
2813 let val = (self.0 >> 7usize) & 0x01;
2814 val != 0
2815 }
2816 #[doc = "B-peripheral session valid override value"]
2817 #[inline(always)]
2818 pub fn set_bvaloval(&mut self, val: bool) {
2819 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
2820 }
2821 #[doc = "Host negotiation success"]
2822 #[inline(always)]
2823 pub const fn hngscs(&self) -> bool {
2824 let val = (self.0 >> 8usize) & 0x01;
2825 val != 0
2826 }
2827 #[doc = "Host negotiation success"]
2828 #[inline(always)]
2829 pub fn set_hngscs(&mut self, val: bool) {
2830 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2831 }
2832 #[doc = "HNP request"]
2833 #[inline(always)]
2834 pub const fn hnprq(&self) -> bool {
2835 let val = (self.0 >> 9usize) & 0x01;
2836 val != 0
2837 }
2838 #[doc = "HNP request"]
2839 #[inline(always)]
2840 pub fn set_hnprq(&mut self, val: bool) {
2841 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2842 }
2843 #[doc = "Host set HNP enable"]
2844 #[inline(always)]
2845 pub const fn hshnpen(&self) -> bool {
2846 let val = (self.0 >> 10usize) & 0x01;
2847 val != 0
2848 }
2849 #[doc = "Host set HNP enable"]
2850 #[inline(always)]
2851 pub fn set_hshnpen(&mut self, val: bool) {
2852 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
2853 }
2854 #[doc = "Device HNP enabled"]
2855 #[inline(always)]
2856 pub const fn dhnpen(&self) -> bool {
2857 let val = (self.0 >> 11usize) & 0x01;
2858 val != 0
2859 }
2860 #[doc = "Device HNP enabled"]
2861 #[inline(always)]
2862 pub fn set_dhnpen(&mut self, val: bool) {
2863 self.0 = (self.0 & !(0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize);
2864 }
2865 #[doc = "Embedded host enable"]
2866 #[inline(always)]
2867 pub const fn ehen(&self) -> bool {
2868 let val = (self.0 >> 12usize) & 0x01;
2869 val != 0
2870 }
2871 #[doc = "Embedded host enable"]
2872 #[inline(always)]
2873 pub fn set_ehen(&mut self, val: bool) {
2874 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
2875 }
2876 #[doc = "Connector ID status"]
2877 #[inline(always)]
2878 pub const fn cidsts(&self) -> bool {
2879 let val = (self.0 >> 16usize) & 0x01;
2880 val != 0
2881 }
2882 #[doc = "Connector ID status"]
2883 #[inline(always)]
2884 pub fn set_cidsts(&mut self, val: bool) {
2885 self.0 = (self.0 & !(0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize);
2886 }
2887 #[doc = "Long/short debounce time"]
2888 #[inline(always)]
2889 pub const fn dbct(&self) -> bool {
2890 let val = (self.0 >> 17usize) & 0x01;
2891 val != 0
2892 }
2893 #[doc = "Long/short debounce time"]
2894 #[inline(always)]
2895 pub fn set_dbct(&mut self, val: bool) {
2896 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2897 }
2898 #[doc = "A-session valid"]
2899 #[inline(always)]
2900 pub const fn asvld(&self) -> bool {
2901 let val = (self.0 >> 18usize) & 0x01;
2902 val != 0
2903 }
2904 #[doc = "A-session valid"]
2905 #[inline(always)]
2906 pub fn set_asvld(&mut self, val: bool) {
2907 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2908 }
2909 #[doc = "B-session valid"]
2910 #[inline(always)]
2911 pub const fn bsvld(&self) -> bool {
2912 let val = (self.0 >> 19usize) & 0x01;
2913 val != 0
2914 }
2915 #[doc = "B-session valid"]
2916 #[inline(always)]
2917 pub fn set_bsvld(&mut self, val: bool) {
2918 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2919 }
2920 }
2921 impl Default for Gotgctl {
2922 #[inline(always)]
2923 fn default() -> Gotgctl {
2924 Gotgctl(0)
2925 }
2926 }
2927 #[doc = "Interrupt register"]
2928 #[repr(transparent)]
2929 #[derive(Copy, Clone, Eq, PartialEq)]
2930 pub struct Gotgint(pub u32);
2931 impl Gotgint {
2932 #[doc = "Session end detected"]
2933 #[inline(always)]
2934 pub const fn sedet(&self) -> bool {
2935 let val = (self.0 >> 2usize) & 0x01;
2936 val != 0
2937 }
2938 #[doc = "Session end detected"]
2939 #[inline(always)]
2940 pub fn set_sedet(&mut self, val: bool) {
2941 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
2942 }
2943 #[doc = "Session request success status change"]
2944 #[inline(always)]
2945 pub const fn srsschg(&self) -> bool {
2946 let val = (self.0 >> 8usize) & 0x01;
2947 val != 0
2948 }
2949 #[doc = "Session request success status change"]
2950 #[inline(always)]
2951 pub fn set_srsschg(&mut self, val: bool) {
2952 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
2953 }
2954 #[doc = "Host negotiation success status change"]
2955 #[inline(always)]
2956 pub const fn hnsschg(&self) -> bool {
2957 let val = (self.0 >> 9usize) & 0x01;
2958 val != 0
2959 }
2960 #[doc = "Host negotiation success status change"]
2961 #[inline(always)]
2962 pub fn set_hnsschg(&mut self, val: bool) {
2963 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
2964 }
2965 #[doc = "Host negotiation detected"]
2966 #[inline(always)]
2967 pub const fn hngdet(&self) -> bool {
2968 let val = (self.0 >> 17usize) & 0x01;
2969 val != 0
2970 }
2971 #[doc = "Host negotiation detected"]
2972 #[inline(always)]
2973 pub fn set_hngdet(&mut self, val: bool) {
2974 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
2975 }
2976 #[doc = "A-device timeout change"]
2977 #[inline(always)]
2978 pub const fn adtochg(&self) -> bool {
2979 let val = (self.0 >> 18usize) & 0x01;
2980 val != 0
2981 }
2982 #[doc = "A-device timeout change"]
2983 #[inline(always)]
2984 pub fn set_adtochg(&mut self, val: bool) {
2985 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
2986 }
2987 #[doc = "Debounce done"]
2988 #[inline(always)]
2989 pub const fn dbcdne(&self) -> bool {
2990 let val = (self.0 >> 19usize) & 0x01;
2991 val != 0
2992 }
2993 #[doc = "Debounce done"]
2994 #[inline(always)]
2995 pub fn set_dbcdne(&mut self, val: bool) {
2996 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
2997 }
2998 #[doc = "ID input pin changed"]
2999 #[inline(always)]
3000 pub const fn idchng(&self) -> bool {
3001 let val = (self.0 >> 20usize) & 0x01;
3002 val != 0
3003 }
3004 #[doc = "ID input pin changed"]
3005 #[inline(always)]
3006 pub fn set_idchng(&mut self, val: bool) {
3007 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3008 }
3009 }
3010 impl Default for Gotgint {
3011 #[inline(always)]
3012 fn default() -> Gotgint {
3013 Gotgint(0)
3014 }
3015 }
3016 #[doc = "Reset register"]
3017 #[repr(transparent)]
3018 #[derive(Copy, Clone, Eq, PartialEq)]
3019 pub struct Grstctl(pub u32);
3020 impl Grstctl {
3021 #[doc = "Core soft reset"]
3022 #[inline(always)]
3023 pub const fn csrst(&self) -> bool {
3024 let val = (self.0 >> 0usize) & 0x01;
3025 val != 0
3026 }
3027 #[doc = "Core soft reset"]
3028 #[inline(always)]
3029 pub fn set_csrst(&mut self, val: bool) {
3030 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3031 }
3032 #[doc = "HCLK soft reset"]
3033 #[inline(always)]
3034 pub const fn hsrst(&self) -> bool {
3035 let val = (self.0 >> 1usize) & 0x01;
3036 val != 0
3037 }
3038 #[doc = "HCLK soft reset"]
3039 #[inline(always)]
3040 pub fn set_hsrst(&mut self, val: bool) {
3041 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3042 }
3043 #[doc = "Host frame counter reset"]
3044 #[inline(always)]
3045 pub const fn fcrst(&self) -> bool {
3046 let val = (self.0 >> 2usize) & 0x01;
3047 val != 0
3048 }
3049 #[doc = "Host frame counter reset"]
3050 #[inline(always)]
3051 pub fn set_fcrst(&mut self, val: bool) {
3052 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3053 }
3054 #[doc = "RxFIFO flush"]
3055 #[inline(always)]
3056 pub const fn rxfflsh(&self) -> bool {
3057 let val = (self.0 >> 4usize) & 0x01;
3058 val != 0
3059 }
3060 #[doc = "RxFIFO flush"]
3061 #[inline(always)]
3062 pub fn set_rxfflsh(&mut self, val: bool) {
3063 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3064 }
3065 #[doc = "TxFIFO flush"]
3066 #[inline(always)]
3067 pub const fn txfflsh(&self) -> bool {
3068 let val = (self.0 >> 5usize) & 0x01;
3069 val != 0
3070 }
3071 #[doc = "TxFIFO flush"]
3072 #[inline(always)]
3073 pub fn set_txfflsh(&mut self, val: bool) {
3074 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3075 }
3076 #[doc = "TxFIFO number"]
3077 #[inline(always)]
3078 pub const fn txfnum(&self) -> u8 {
3079 let val = (self.0 >> 6usize) & 0x1f;
3080 val as u8
3081 }
3082 #[doc = "TxFIFO number"]
3083 #[inline(always)]
3084 pub fn set_txfnum(&mut self, val: u8) {
3085 self.0 = (self.0 & !(0x1f << 6usize)) | (((val as u32) & 0x1f) << 6usize);
3086 }
3087 #[doc = "DMA request signal enabled for USB OTG HS"]
3088 #[inline(always)]
3089 pub const fn dmareq(&self) -> bool {
3090 let val = (self.0 >> 30usize) & 0x01;
3091 val != 0
3092 }
3093 #[doc = "DMA request signal enabled for USB OTG HS"]
3094 #[inline(always)]
3095 pub fn set_dmareq(&mut self, val: bool) {
3096 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
3097 }
3098 #[doc = "AHB master idle"]
3099 #[inline(always)]
3100 pub const fn ahbidl(&self) -> bool {
3101 let val = (self.0 >> 31usize) & 0x01;
3102 val != 0
3103 }
3104 #[doc = "AHB master idle"]
3105 #[inline(always)]
3106 pub fn set_ahbidl(&mut self, val: bool) {
3107 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
3108 }
3109 }
3110 impl Default for Grstctl {
3111 #[inline(always)]
3112 fn default() -> Grstctl {
3113 Grstctl(0)
3114 }
3115 }
3116 #[doc = "Receive FIFO size register"]
3117 #[repr(transparent)]
3118 #[derive(Copy, Clone, Eq, PartialEq)]
3119 pub struct Grxfsiz(pub u32);
3120 impl Grxfsiz {
3121 #[doc = "RxFIFO depth"]
3122 #[inline(always)]
3123 pub const fn rxfd(&self) -> u16 {
3124 let val = (self.0 >> 0usize) & 0xffff;
3125 val as u16
3126 }
3127 #[doc = "RxFIFO depth"]
3128 #[inline(always)]
3129 pub fn set_rxfd(&mut self, val: u16) {
3130 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3131 }
3132 }
3133 impl Default for Grxfsiz {
3134 #[inline(always)]
3135 fn default() -> Grxfsiz {
3136 Grxfsiz(0)
3137 }
3138 }
3139 #[doc = "Status read and pop register"]
3140 #[repr(transparent)]
3141 #[derive(Copy, Clone, Eq, PartialEq)]
3142 pub struct Grxsts(pub u32);
3143 impl Grxsts {
3144 #[doc = "Endpoint number (device mode) / Channel number (host mode)"]
3145 #[inline(always)]
3146 pub const fn epnum(&self) -> u8 {
3147 let val = (self.0 >> 0usize) & 0x0f;
3148 val as u8
3149 }
3150 #[doc = "Endpoint number (device mode) / Channel number (host mode)"]
3151 #[inline(always)]
3152 pub fn set_epnum(&mut self, val: u8) {
3153 self.0 = (self.0 & !(0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize);
3154 }
3155 #[doc = "Byte count"]
3156 #[inline(always)]
3157 pub const fn bcnt(&self) -> u16 {
3158 let val = (self.0 >> 4usize) & 0x07ff;
3159 val as u16
3160 }
3161 #[doc = "Byte count"]
3162 #[inline(always)]
3163 pub fn set_bcnt(&mut self, val: u16) {
3164 self.0 = (self.0 & !(0x07ff << 4usize)) | (((val as u32) & 0x07ff) << 4usize);
3165 }
3166 #[doc = "Data PID"]
3167 #[inline(always)]
3168 pub const fn dpid(&self) -> super::vals::Dpid {
3169 let val = (self.0 >> 15usize) & 0x03;
3170 super::vals::Dpid::from_bits(val as u8)
3171 }
3172 #[doc = "Data PID"]
3173 #[inline(always)]
3174 pub fn set_dpid(&mut self, val: super::vals::Dpid) {
3175 self.0 = (self.0 & !(0x03 << 15usize)) | (((val.to_bits() as u32) & 0x03) << 15usize);
3176 }
3177 #[doc = "Packet status (device mode)"]
3178 #[inline(always)]
3179 pub const fn pktstsd(&self) -> super::vals::Pktstsd {
3180 let val = (self.0 >> 17usize) & 0x0f;
3181 super::vals::Pktstsd::from_bits(val as u8)
3182 }
3183 #[doc = "Packet status (device mode)"]
3184 #[inline(always)]
3185 pub fn set_pktstsd(&mut self, val: super::vals::Pktstsd) {
3186 self.0 = (self.0 & !(0x0f << 17usize)) | (((val.to_bits() as u32) & 0x0f) << 17usize);
3187 }
3188 #[doc = "Packet status (host mode)"]
3189 #[inline(always)]
3190 pub const fn pktstsh(&self) -> super::vals::Pktstsh {
3191 let val = (self.0 >> 17usize) & 0x0f;
3192 super::vals::Pktstsh::from_bits(val as u8)
3193 }
3194 #[doc = "Packet status (host mode)"]
3195 #[inline(always)]
3196 pub fn set_pktstsh(&mut self, val: super::vals::Pktstsh) {
3197 self.0 = (self.0 & !(0x0f << 17usize)) | (((val.to_bits() as u32) & 0x0f) << 17usize);
3198 }
3199 #[doc = "Frame number (device mode)"]
3200 #[inline(always)]
3201 pub const fn frmnum(&self) -> u8 {
3202 let val = (self.0 >> 21usize) & 0x0f;
3203 val as u8
3204 }
3205 #[doc = "Frame number (device mode)"]
3206 #[inline(always)]
3207 pub fn set_frmnum(&mut self, val: u8) {
3208 self.0 = (self.0 & !(0x0f << 21usize)) | (((val as u32) & 0x0f) << 21usize);
3209 }
3210 }
3211 impl Default for Grxsts {
3212 #[inline(always)]
3213 fn default() -> Grxsts {
3214 Grxsts(0)
3215 }
3216 }
3217 #[doc = "USB configuration register"]
3218 #[repr(transparent)]
3219 #[derive(Copy, Clone, Eq, PartialEq)]
3220 pub struct Gusbcfg(pub u32);
3221 impl Gusbcfg {
3222 #[doc = "FS timeout calibration"]
3223 #[inline(always)]
3224 pub const fn tocal(&self) -> u8 {
3225 let val = (self.0 >> 0usize) & 0x07;
3226 val as u8
3227 }
3228 #[doc = "FS timeout calibration"]
3229 #[inline(always)]
3230 pub fn set_tocal(&mut self, val: u8) {
3231 self.0 = (self.0 & !(0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize);
3232 }
3233 #[doc = "Full-speed internal serial transceiver enable"]
3234 #[inline(always)]
3235 pub const fn physel(&self) -> bool {
3236 let val = (self.0 >> 6usize) & 0x01;
3237 val != 0
3238 }
3239 #[doc = "Full-speed internal serial transceiver enable"]
3240 #[inline(always)]
3241 pub fn set_physel(&mut self, val: bool) {
3242 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3243 }
3244 #[doc = "SRP-capable"]
3245 #[inline(always)]
3246 pub const fn srpcap(&self) -> bool {
3247 let val = (self.0 >> 8usize) & 0x01;
3248 val != 0
3249 }
3250 #[doc = "SRP-capable"]
3251 #[inline(always)]
3252 pub fn set_srpcap(&mut self, val: bool) {
3253 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3254 }
3255 #[doc = "HNP-capable"]
3256 #[inline(always)]
3257 pub const fn hnpcap(&self) -> bool {
3258 let val = (self.0 >> 9usize) & 0x01;
3259 val != 0
3260 }
3261 #[doc = "HNP-capable"]
3262 #[inline(always)]
3263 pub fn set_hnpcap(&mut self, val: bool) {
3264 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3265 }
3266 #[doc = "USB turnaround time"]
3267 #[inline(always)]
3268 pub const fn trdt(&self) -> u8 {
3269 let val = (self.0 >> 10usize) & 0x0f;
3270 val as u8
3271 }
3272 #[doc = "USB turnaround time"]
3273 #[inline(always)]
3274 pub fn set_trdt(&mut self, val: u8) {
3275 self.0 = (self.0 & !(0x0f << 10usize)) | (((val as u32) & 0x0f) << 10usize);
3276 }
3277 #[doc = "PHY Low-power clock select"]
3278 #[inline(always)]
3279 pub const fn phylpcs(&self) -> bool {
3280 let val = (self.0 >> 15usize) & 0x01;
3281 val != 0
3282 }
3283 #[doc = "PHY Low-power clock select"]
3284 #[inline(always)]
3285 pub fn set_phylpcs(&mut self, val: bool) {
3286 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
3287 }
3288 #[doc = "ULPI FS/LS select"]
3289 #[inline(always)]
3290 pub const fn ulpifsls(&self) -> bool {
3291 let val = (self.0 >> 17usize) & 0x01;
3292 val != 0
3293 }
3294 #[doc = "ULPI FS/LS select"]
3295 #[inline(always)]
3296 pub fn set_ulpifsls(&mut self, val: bool) {
3297 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3298 }
3299 #[doc = "ULPI Auto-resume"]
3300 #[inline(always)]
3301 pub const fn ulpiar(&self) -> bool {
3302 let val = (self.0 >> 18usize) & 0x01;
3303 val != 0
3304 }
3305 #[doc = "ULPI Auto-resume"]
3306 #[inline(always)]
3307 pub fn set_ulpiar(&mut self, val: bool) {
3308 self.0 = (self.0 & !(0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize);
3309 }
3310 #[doc = "ULPI Clock SuspendM"]
3311 #[inline(always)]
3312 pub const fn ulpicsm(&self) -> bool {
3313 let val = (self.0 >> 19usize) & 0x01;
3314 val != 0
3315 }
3316 #[doc = "ULPI Clock SuspendM"]
3317 #[inline(always)]
3318 pub fn set_ulpicsm(&mut self, val: bool) {
3319 self.0 = (self.0 & !(0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize);
3320 }
3321 #[doc = "ULPI External VBUS Drive"]
3322 #[inline(always)]
3323 pub const fn ulpievbusd(&self) -> bool {
3324 let val = (self.0 >> 20usize) & 0x01;
3325 val != 0
3326 }
3327 #[doc = "ULPI External VBUS Drive"]
3328 #[inline(always)]
3329 pub fn set_ulpievbusd(&mut self, val: bool) {
3330 self.0 = (self.0 & !(0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize);
3331 }
3332 #[doc = "ULPI external VBUS indicator"]
3333 #[inline(always)]
3334 pub const fn ulpievbusi(&self) -> bool {
3335 let val = (self.0 >> 21usize) & 0x01;
3336 val != 0
3337 }
3338 #[doc = "ULPI external VBUS indicator"]
3339 #[inline(always)]
3340 pub fn set_ulpievbusi(&mut self, val: bool) {
3341 self.0 = (self.0 & !(0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize);
3342 }
3343 #[doc = "TermSel DLine pulsing selection"]
3344 #[inline(always)]
3345 pub const fn tsdps(&self) -> bool {
3346 let val = (self.0 >> 22usize) & 0x01;
3347 val != 0
3348 }
3349 #[doc = "TermSel DLine pulsing selection"]
3350 #[inline(always)]
3351 pub fn set_tsdps(&mut self, val: bool) {
3352 self.0 = (self.0 & !(0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize);
3353 }
3354 #[doc = "Indicator complement"]
3355 #[inline(always)]
3356 pub const fn pcci(&self) -> bool {
3357 let val = (self.0 >> 23usize) & 0x01;
3358 val != 0
3359 }
3360 #[doc = "Indicator complement"]
3361 #[inline(always)]
3362 pub fn set_pcci(&mut self, val: bool) {
3363 self.0 = (self.0 & !(0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize);
3364 }
3365 #[doc = "Indicator pass through"]
3366 #[inline(always)]
3367 pub const fn ptci(&self) -> bool {
3368 let val = (self.0 >> 24usize) & 0x01;
3369 val != 0
3370 }
3371 #[doc = "Indicator pass through"]
3372 #[inline(always)]
3373 pub fn set_ptci(&mut self, val: bool) {
3374 self.0 = (self.0 & !(0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize);
3375 }
3376 #[doc = "ULPI interface protect disable"]
3377 #[inline(always)]
3378 pub const fn ulpiipd(&self) -> bool {
3379 let val = (self.0 >> 25usize) & 0x01;
3380 val != 0
3381 }
3382 #[doc = "ULPI interface protect disable"]
3383 #[inline(always)]
3384 pub fn set_ulpiipd(&mut self, val: bool) {
3385 self.0 = (self.0 & !(0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize);
3386 }
3387 #[doc = "Force host mode"]
3388 #[inline(always)]
3389 pub const fn fhmod(&self) -> bool {
3390 let val = (self.0 >> 29usize) & 0x01;
3391 val != 0
3392 }
3393 #[doc = "Force host mode"]
3394 #[inline(always)]
3395 pub fn set_fhmod(&mut self, val: bool) {
3396 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
3397 }
3398 #[doc = "Force device mode"]
3399 #[inline(always)]
3400 pub const fn fdmod(&self) -> bool {
3401 let val = (self.0 >> 30usize) & 0x01;
3402 val != 0
3403 }
3404 #[doc = "Force device mode"]
3405 #[inline(always)]
3406 pub fn set_fdmod(&mut self, val: bool) {
3407 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
3408 }
3409 #[doc = "Corrupt Tx packet"]
3410 #[inline(always)]
3411 pub const fn ctxpkt(&self) -> bool {
3412 let val = (self.0 >> 31usize) & 0x01;
3413 val != 0
3414 }
3415 #[doc = "Corrupt Tx packet"]
3416 #[inline(always)]
3417 pub fn set_ctxpkt(&mut self, val: bool) {
3418 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
3419 }
3420 }
3421 impl Default for Gusbcfg {
3422 #[inline(always)]
3423 fn default() -> Gusbcfg {
3424 Gusbcfg(0)
3425 }
3426 }
3427 #[doc = "Host all channels interrupt register"]
3428 #[repr(transparent)]
3429 #[derive(Copy, Clone, Eq, PartialEq)]
3430 pub struct Haint(pub u32);
3431 impl Haint {
3432 #[doc = "Channel interrupts"]
3433 #[inline(always)]
3434 pub const fn haint(&self) -> u16 {
3435 let val = (self.0 >> 0usize) & 0xffff;
3436 val as u16
3437 }
3438 #[doc = "Channel interrupts"]
3439 #[inline(always)]
3440 pub fn set_haint(&mut self, val: u16) {
3441 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3442 }
3443 }
3444 impl Default for Haint {
3445 #[inline(always)]
3446 fn default() -> Haint {
3447 Haint(0)
3448 }
3449 }
3450 #[doc = "Host all channels interrupt mask register"]
3451 #[repr(transparent)]
3452 #[derive(Copy, Clone, Eq, PartialEq)]
3453 pub struct Haintmsk(pub u32);
3454 impl Haintmsk {
3455 #[doc = "Channel interrupt mask"]
3456 #[inline(always)]
3457 pub const fn haintm(&self) -> u16 {
3458 let val = (self.0 >> 0usize) & 0xffff;
3459 val as u16
3460 }
3461 #[doc = "Channel interrupt mask"]
3462 #[inline(always)]
3463 pub fn set_haintm(&mut self, val: u16) {
3464 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3465 }
3466 }
3467 impl Default for Haintmsk {
3468 #[inline(always)]
3469 fn default() -> Haintmsk {
3470 Haintmsk(0)
3471 }
3472 }
3473 #[doc = "Host channel characteristics register"]
3474 #[repr(transparent)]
3475 #[derive(Copy, Clone, Eq, PartialEq)]
3476 pub struct Hcchar(pub u32);
3477 impl Hcchar {
3478 #[doc = "Maximum packet size"]
3479 #[inline(always)]
3480 pub const fn mpsiz(&self) -> u16 {
3481 let val = (self.0 >> 0usize) & 0x07ff;
3482 val as u16
3483 }
3484 #[doc = "Maximum packet size"]
3485 #[inline(always)]
3486 pub fn set_mpsiz(&mut self, val: u16) {
3487 self.0 = (self.0 & !(0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize);
3488 }
3489 #[doc = "Endpoint number"]
3490 #[inline(always)]
3491 pub const fn epnum(&self) -> u8 {
3492 let val = (self.0 >> 11usize) & 0x0f;
3493 val as u8
3494 }
3495 #[doc = "Endpoint number"]
3496 #[inline(always)]
3497 pub fn set_epnum(&mut self, val: u8) {
3498 self.0 = (self.0 & !(0x0f << 11usize)) | (((val as u32) & 0x0f) << 11usize);
3499 }
3500 #[doc = "Endpoint direction"]
3501 #[inline(always)]
3502 pub const fn epdir(&self) -> bool {
3503 let val = (self.0 >> 15usize) & 0x01;
3504 val != 0
3505 }
3506 #[doc = "Endpoint direction"]
3507 #[inline(always)]
3508 pub fn set_epdir(&mut self, val: bool) {
3509 self.0 = (self.0 & !(0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize);
3510 }
3511 #[doc = "Low-speed device"]
3512 #[inline(always)]
3513 pub const fn lsdev(&self) -> bool {
3514 let val = (self.0 >> 17usize) & 0x01;
3515 val != 0
3516 }
3517 #[doc = "Low-speed device"]
3518 #[inline(always)]
3519 pub fn set_lsdev(&mut self, val: bool) {
3520 self.0 = (self.0 & !(0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize);
3521 }
3522 #[doc = "Endpoint type"]
3523 #[inline(always)]
3524 pub const fn eptyp(&self) -> super::vals::Eptyp {
3525 let val = (self.0 >> 18usize) & 0x03;
3526 super::vals::Eptyp::from_bits(val as u8)
3527 }
3528 #[doc = "Endpoint type"]
3529 #[inline(always)]
3530 pub fn set_eptyp(&mut self, val: super::vals::Eptyp) {
3531 self.0 = (self.0 & !(0x03 << 18usize)) | (((val.to_bits() as u32) & 0x03) << 18usize);
3532 }
3533 #[doc = "Multicount"]
3534 #[inline(always)]
3535 pub const fn mcnt(&self) -> u8 {
3536 let val = (self.0 >> 20usize) & 0x03;
3537 val as u8
3538 }
3539 #[doc = "Multicount"]
3540 #[inline(always)]
3541 pub fn set_mcnt(&mut self, val: u8) {
3542 self.0 = (self.0 & !(0x03 << 20usize)) | (((val as u32) & 0x03) << 20usize);
3543 }
3544 #[doc = "Device address"]
3545 #[inline(always)]
3546 pub const fn dad(&self) -> u8 {
3547 let val = (self.0 >> 22usize) & 0x7f;
3548 val as u8
3549 }
3550 #[doc = "Device address"]
3551 #[inline(always)]
3552 pub fn set_dad(&mut self, val: u8) {
3553 self.0 = (self.0 & !(0x7f << 22usize)) | (((val as u32) & 0x7f) << 22usize);
3554 }
3555 #[doc = "Odd frame"]
3556 #[inline(always)]
3557 pub const fn oddfrm(&self) -> bool {
3558 let val = (self.0 >> 29usize) & 0x01;
3559 val != 0
3560 }
3561 #[doc = "Odd frame"]
3562 #[inline(always)]
3563 pub fn set_oddfrm(&mut self, val: bool) {
3564 self.0 = (self.0 & !(0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize);
3565 }
3566 #[doc = "Channel disable"]
3567 #[inline(always)]
3568 pub const fn chdis(&self) -> bool {
3569 let val = (self.0 >> 30usize) & 0x01;
3570 val != 0
3571 }
3572 #[doc = "Channel disable"]
3573 #[inline(always)]
3574 pub fn set_chdis(&mut self, val: bool) {
3575 self.0 = (self.0 & !(0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize);
3576 }
3577 #[doc = "Channel enable"]
3578 #[inline(always)]
3579 pub const fn chena(&self) -> bool {
3580 let val = (self.0 >> 31usize) & 0x01;
3581 val != 0
3582 }
3583 #[doc = "Channel enable"]
3584 #[inline(always)]
3585 pub fn set_chena(&mut self, val: bool) {
3586 self.0 = (self.0 & !(0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize);
3587 }
3588 }
3589 impl Default for Hcchar {
3590 #[inline(always)]
3591 fn default() -> Hcchar {
3592 Hcchar(0)
3593 }
3594 }
3595 #[doc = "Host configuration register"]
3596 #[repr(transparent)]
3597 #[derive(Copy, Clone, Eq, PartialEq)]
3598 pub struct Hcfg(pub u32);
3599 impl Hcfg {
3600 #[doc = "FS/LS PHY clock select"]
3601 #[inline(always)]
3602 pub const fn fslspcs(&self) -> u8 {
3603 let val = (self.0 >> 0usize) & 0x03;
3604 val as u8
3605 }
3606 #[doc = "FS/LS PHY clock select"]
3607 #[inline(always)]
3608 pub fn set_fslspcs(&mut self, val: u8) {
3609 self.0 = (self.0 & !(0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize);
3610 }
3611 #[doc = "FS- and LS-only support"]
3612 #[inline(always)]
3613 pub const fn fslss(&self) -> bool {
3614 let val = (self.0 >> 2usize) & 0x01;
3615 val != 0
3616 }
3617 #[doc = "FS- and LS-only support"]
3618 #[inline(always)]
3619 pub fn set_fslss(&mut self, val: bool) {
3620 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
3621 }
3622 }
3623 impl Default for Hcfg {
3624 #[inline(always)]
3625 fn default() -> Hcfg {
3626 Hcfg(0)
3627 }
3628 }
3629 #[doc = "Host channel interrupt register"]
3630 #[repr(transparent)]
3631 #[derive(Copy, Clone, Eq, PartialEq)]
3632 pub struct Hcint(pub u32);
3633 impl Hcint {
3634 #[doc = "Transfer completed"]
3635 #[inline(always)]
3636 pub const fn xfrc(&self) -> bool {
3637 let val = (self.0 >> 0usize) & 0x01;
3638 val != 0
3639 }
3640 #[doc = "Transfer completed"]
3641 #[inline(always)]
3642 pub fn set_xfrc(&mut self, val: bool) {
3643 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3644 }
3645 #[doc = "Channel halted"]
3646 #[inline(always)]
3647 pub const fn chh(&self) -> bool {
3648 let val = (self.0 >> 1usize) & 0x01;
3649 val != 0
3650 }
3651 #[doc = "Channel halted"]
3652 #[inline(always)]
3653 pub fn set_chh(&mut self, val: bool) {
3654 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3655 }
3656 #[doc = "STALL response received interrupt"]
3657 #[inline(always)]
3658 pub const fn stall(&self) -> bool {
3659 let val = (self.0 >> 3usize) & 0x01;
3660 val != 0
3661 }
3662 #[doc = "STALL response received interrupt"]
3663 #[inline(always)]
3664 pub fn set_stall(&mut self, val: bool) {
3665 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3666 }
3667 #[doc = "NAK response received interrupt"]
3668 #[inline(always)]
3669 pub const fn nak(&self) -> bool {
3670 let val = (self.0 >> 4usize) & 0x01;
3671 val != 0
3672 }
3673 #[doc = "NAK response received interrupt"]
3674 #[inline(always)]
3675 pub fn set_nak(&mut self, val: bool) {
3676 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3677 }
3678 #[doc = "ACK response received/transmitted interrupt"]
3679 #[inline(always)]
3680 pub const fn ack(&self) -> bool {
3681 let val = (self.0 >> 5usize) & 0x01;
3682 val != 0
3683 }
3684 #[doc = "ACK response received/transmitted interrupt"]
3685 #[inline(always)]
3686 pub fn set_ack(&mut self, val: bool) {
3687 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3688 }
3689 #[doc = "Transaction error"]
3690 #[inline(always)]
3691 pub const fn txerr(&self) -> bool {
3692 let val = (self.0 >> 7usize) & 0x01;
3693 val != 0
3694 }
3695 #[doc = "Transaction error"]
3696 #[inline(always)]
3697 pub fn set_txerr(&mut self, val: bool) {
3698 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3699 }
3700 #[doc = "Babble error"]
3701 #[inline(always)]
3702 pub const fn bberr(&self) -> bool {
3703 let val = (self.0 >> 8usize) & 0x01;
3704 val != 0
3705 }
3706 #[doc = "Babble error"]
3707 #[inline(always)]
3708 pub fn set_bberr(&mut self, val: bool) {
3709 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3710 }
3711 #[doc = "Frame overrun"]
3712 #[inline(always)]
3713 pub const fn frmor(&self) -> bool {
3714 let val = (self.0 >> 9usize) & 0x01;
3715 val != 0
3716 }
3717 #[doc = "Frame overrun"]
3718 #[inline(always)]
3719 pub fn set_frmor(&mut self, val: bool) {
3720 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3721 }
3722 #[doc = "Data toggle error"]
3723 #[inline(always)]
3724 pub const fn dterr(&self) -> bool {
3725 let val = (self.0 >> 10usize) & 0x01;
3726 val != 0
3727 }
3728 #[doc = "Data toggle error"]
3729 #[inline(always)]
3730 pub fn set_dterr(&mut self, val: bool) {
3731 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
3732 }
3733 }
3734 impl Default for Hcint {
3735 #[inline(always)]
3736 fn default() -> Hcint {
3737 Hcint(0)
3738 }
3739 }
3740 #[doc = "Host channel mask register"]
3741 #[repr(transparent)]
3742 #[derive(Copy, Clone, Eq, PartialEq)]
3743 pub struct Hcintmsk(pub u32);
3744 impl Hcintmsk {
3745 #[doc = "Transfer completed mask"]
3746 #[inline(always)]
3747 pub const fn xfrcm(&self) -> bool {
3748 let val = (self.0 >> 0usize) & 0x01;
3749 val != 0
3750 }
3751 #[doc = "Transfer completed mask"]
3752 #[inline(always)]
3753 pub fn set_xfrcm(&mut self, val: bool) {
3754 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
3755 }
3756 #[doc = "Channel halted mask"]
3757 #[inline(always)]
3758 pub const fn chhm(&self) -> bool {
3759 let val = (self.0 >> 1usize) & 0x01;
3760 val != 0
3761 }
3762 #[doc = "Channel halted mask"]
3763 #[inline(always)]
3764 pub fn set_chhm(&mut self, val: bool) {
3765 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
3766 }
3767 #[doc = "STALL response received interrupt mask"]
3768 #[inline(always)]
3769 pub const fn stallm(&self) -> bool {
3770 let val = (self.0 >> 3usize) & 0x01;
3771 val != 0
3772 }
3773 #[doc = "STALL response received interrupt mask"]
3774 #[inline(always)]
3775 pub fn set_stallm(&mut self, val: bool) {
3776 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
3777 }
3778 #[doc = "NAK response received interrupt mask"]
3779 #[inline(always)]
3780 pub const fn nakm(&self) -> bool {
3781 let val = (self.0 >> 4usize) & 0x01;
3782 val != 0
3783 }
3784 #[doc = "NAK response received interrupt mask"]
3785 #[inline(always)]
3786 pub fn set_nakm(&mut self, val: bool) {
3787 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
3788 }
3789 #[doc = "ACK response received/transmitted interrupt mask"]
3790 #[inline(always)]
3791 pub const fn ackm(&self) -> bool {
3792 let val = (self.0 >> 5usize) & 0x01;
3793 val != 0
3794 }
3795 #[doc = "ACK response received/transmitted interrupt mask"]
3796 #[inline(always)]
3797 pub fn set_ackm(&mut self, val: bool) {
3798 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
3799 }
3800 #[doc = "Response received interrupt mask"]
3801 #[inline(always)]
3802 pub const fn nyet(&self) -> bool {
3803 let val = (self.0 >> 6usize) & 0x01;
3804 val != 0
3805 }
3806 #[doc = "Response received interrupt mask"]
3807 #[inline(always)]
3808 pub fn set_nyet(&mut self, val: bool) {
3809 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
3810 }
3811 #[doc = "Transaction error mask"]
3812 #[inline(always)]
3813 pub const fn txerrm(&self) -> bool {
3814 let val = (self.0 >> 7usize) & 0x01;
3815 val != 0
3816 }
3817 #[doc = "Transaction error mask"]
3818 #[inline(always)]
3819 pub fn set_txerrm(&mut self, val: bool) {
3820 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
3821 }
3822 #[doc = "Babble error mask"]
3823 #[inline(always)]
3824 pub const fn bberrm(&self) -> bool {
3825 let val = (self.0 >> 8usize) & 0x01;
3826 val != 0
3827 }
3828 #[doc = "Babble error mask"]
3829 #[inline(always)]
3830 pub fn set_bberrm(&mut self, val: bool) {
3831 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
3832 }
3833 #[doc = "Frame overrun mask"]
3834 #[inline(always)]
3835 pub const fn frmorm(&self) -> bool {
3836 let val = (self.0 >> 9usize) & 0x01;
3837 val != 0
3838 }
3839 #[doc = "Frame overrun mask"]
3840 #[inline(always)]
3841 pub fn set_frmorm(&mut self, val: bool) {
3842 self.0 = (self.0 & !(0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize);
3843 }
3844 #[doc = "Data toggle error mask"]
3845 #[inline(always)]
3846 pub const fn dterrm(&self) -> bool {
3847 let val = (self.0 >> 10usize) & 0x01;
3848 val != 0
3849 }
3850 #[doc = "Data toggle error mask"]
3851 #[inline(always)]
3852 pub fn set_dterrm(&mut self, val: bool) {
3853 self.0 = (self.0 & !(0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize);
3854 }
3855 }
3856 impl Default for Hcintmsk {
3857 #[inline(always)]
3858 fn default() -> Hcintmsk {
3859 Hcintmsk(0)
3860 }
3861 }
3862 #[doc = "Host channel transfer size register"]
3863 #[repr(transparent)]
3864 #[derive(Copy, Clone, Eq, PartialEq)]
3865 pub struct Hctsiz(pub u32);
3866 impl Hctsiz {
3867 #[doc = "Transfer size"]
3868 #[inline(always)]
3869 pub const fn xfrsiz(&self) -> u32 {
3870 let val = (self.0 >> 0usize) & 0x0007_ffff;
3871 val as u32
3872 }
3873 #[doc = "Transfer size"]
3874 #[inline(always)]
3875 pub fn set_xfrsiz(&mut self, val: u32) {
3876 self.0 = (self.0 & !(0x0007_ffff << 0usize)) | (((val as u32) & 0x0007_ffff) << 0usize);
3877 }
3878 #[doc = "Packet count"]
3879 #[inline(always)]
3880 pub const fn pktcnt(&self) -> u16 {
3881 let val = (self.0 >> 19usize) & 0x03ff;
3882 val as u16
3883 }
3884 #[doc = "Packet count"]
3885 #[inline(always)]
3886 pub fn set_pktcnt(&mut self, val: u16) {
3887 self.0 = (self.0 & !(0x03ff << 19usize)) | (((val as u32) & 0x03ff) << 19usize);
3888 }
3889 #[doc = "Data PID"]
3890 #[inline(always)]
3891 pub const fn dpid(&self) -> u8 {
3892 let val = (self.0 >> 29usize) & 0x03;
3893 val as u8
3894 }
3895 #[doc = "Data PID"]
3896 #[inline(always)]
3897 pub fn set_dpid(&mut self, val: u8) {
3898 self.0 = (self.0 & !(0x03 << 29usize)) | (((val as u32) & 0x03) << 29usize);
3899 }
3900 }
3901 impl Default for Hctsiz {
3902 #[inline(always)]
3903 fn default() -> Hctsiz {
3904 Hctsiz(0)
3905 }
3906 }
3907 #[doc = "Host frame interval register"]
3908 #[repr(transparent)]
3909 #[derive(Copy, Clone, Eq, PartialEq)]
3910 pub struct Hfir(pub u32);
3911 impl Hfir {
3912 #[doc = "Frame interval"]
3913 #[inline(always)]
3914 pub const fn frivl(&self) -> u16 {
3915 let val = (self.0 >> 0usize) & 0xffff;
3916 val as u16
3917 }
3918 #[doc = "Frame interval"]
3919 #[inline(always)]
3920 pub fn set_frivl(&mut self, val: u16) {
3921 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3922 }
3923 }
3924 impl Default for Hfir {
3925 #[inline(always)]
3926 fn default() -> Hfir {
3927 Hfir(0)
3928 }
3929 }
3930 #[doc = "Host frame number/frame time remaining register"]
3931 #[repr(transparent)]
3932 #[derive(Copy, Clone, Eq, PartialEq)]
3933 pub struct Hfnum(pub u32);
3934 impl Hfnum {
3935 #[doc = "Frame number"]
3936 #[inline(always)]
3937 pub const fn frnum(&self) -> u16 {
3938 let val = (self.0 >> 0usize) & 0xffff;
3939 val as u16
3940 }
3941 #[doc = "Frame number"]
3942 #[inline(always)]
3943 pub fn set_frnum(&mut self, val: u16) {
3944 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3945 }
3946 #[doc = "Frame time remaining"]
3947 #[inline(always)]
3948 pub const fn ftrem(&self) -> u16 {
3949 let val = (self.0 >> 16usize) & 0xffff;
3950 val as u16
3951 }
3952 #[doc = "Frame time remaining"]
3953 #[inline(always)]
3954 pub fn set_ftrem(&mut self, val: u16) {
3955 self.0 = (self.0 & !(0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize);
3956 }
3957 }
3958 impl Default for Hfnum {
3959 #[inline(always)]
3960 fn default() -> Hfnum {
3961 Hfnum(0)
3962 }
3963 }
3964 #[doc = "Non-periodic transmit FIFO/queue status register"]
3965 #[repr(transparent)]
3966 #[derive(Copy, Clone, Eq, PartialEq)]
3967 pub struct Hnptxsts(pub u32);
3968 impl Hnptxsts {
3969 #[doc = "Non-periodic TxFIFO space available"]
3970 #[inline(always)]
3971 pub const fn nptxfsav(&self) -> u16 {
3972 let val = (self.0 >> 0usize) & 0xffff;
3973 val as u16
3974 }
3975 #[doc = "Non-periodic TxFIFO space available"]
3976 #[inline(always)]
3977 pub fn set_nptxfsav(&mut self, val: u16) {
3978 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
3979 }
3980 #[doc = "Non-periodic transmit request queue space available"]
3981 #[inline(always)]
3982 pub const fn nptqxsav(&self) -> u8 {
3983 let val = (self.0 >> 16usize) & 0xff;
3984 val as u8
3985 }
3986 #[doc = "Non-periodic transmit request queue space available"]
3987 #[inline(always)]
3988 pub fn set_nptqxsav(&mut self, val: u8) {
3989 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
3990 }
3991 #[doc = "Top of the non-periodic transmit request queue"]
3992 #[inline(always)]
3993 pub const fn nptxqtop(&self) -> u8 {
3994 let val = (self.0 >> 24usize) & 0x7f;
3995 val as u8
3996 }
3997 #[doc = "Top of the non-periodic transmit request queue"]
3998 #[inline(always)]
3999 pub fn set_nptxqtop(&mut self, val: u8) {
4000 self.0 = (self.0 & !(0x7f << 24usize)) | (((val as u32) & 0x7f) << 24usize);
4001 }
4002 }
4003 impl Default for Hnptxsts {
4004 #[inline(always)]
4005 fn default() -> Hnptxsts {
4006 Hnptxsts(0)
4007 }
4008 }
4009 #[doc = "Host port control and status register"]
4010 #[repr(transparent)]
4011 #[derive(Copy, Clone, Eq, PartialEq)]
4012 pub struct Hprt(pub u32);
4013 impl Hprt {
4014 #[doc = "Port connect status"]
4015 #[inline(always)]
4016 pub const fn pcsts(&self) -> bool {
4017 let val = (self.0 >> 0usize) & 0x01;
4018 val != 0
4019 }
4020 #[doc = "Port connect status"]
4021 #[inline(always)]
4022 pub fn set_pcsts(&mut self, val: bool) {
4023 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4024 }
4025 #[doc = "Port connect detected"]
4026 #[inline(always)]
4027 pub const fn pcdet(&self) -> bool {
4028 let val = (self.0 >> 1usize) & 0x01;
4029 val != 0
4030 }
4031 #[doc = "Port connect detected"]
4032 #[inline(always)]
4033 pub fn set_pcdet(&mut self, val: bool) {
4034 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4035 }
4036 #[doc = "Port enable"]
4037 #[inline(always)]
4038 pub const fn pena(&self) -> bool {
4039 let val = (self.0 >> 2usize) & 0x01;
4040 val != 0
4041 }
4042 #[doc = "Port enable"]
4043 #[inline(always)]
4044 pub fn set_pena(&mut self, val: bool) {
4045 self.0 = (self.0 & !(0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize);
4046 }
4047 #[doc = "Port enable/disable change"]
4048 #[inline(always)]
4049 pub const fn penchng(&self) -> bool {
4050 let val = (self.0 >> 3usize) & 0x01;
4051 val != 0
4052 }
4053 #[doc = "Port enable/disable change"]
4054 #[inline(always)]
4055 pub fn set_penchng(&mut self, val: bool) {
4056 self.0 = (self.0 & !(0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize);
4057 }
4058 #[doc = "Port overcurrent active"]
4059 #[inline(always)]
4060 pub const fn poca(&self) -> bool {
4061 let val = (self.0 >> 4usize) & 0x01;
4062 val != 0
4063 }
4064 #[doc = "Port overcurrent active"]
4065 #[inline(always)]
4066 pub fn set_poca(&mut self, val: bool) {
4067 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4068 }
4069 #[doc = "Port overcurrent change"]
4070 #[inline(always)]
4071 pub const fn pocchng(&self) -> bool {
4072 let val = (self.0 >> 5usize) & 0x01;
4073 val != 0
4074 }
4075 #[doc = "Port overcurrent change"]
4076 #[inline(always)]
4077 pub fn set_pocchng(&mut self, val: bool) {
4078 self.0 = (self.0 & !(0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize);
4079 }
4080 #[doc = "Port resume"]
4081 #[inline(always)]
4082 pub const fn pres(&self) -> bool {
4083 let val = (self.0 >> 6usize) & 0x01;
4084 val != 0
4085 }
4086 #[doc = "Port resume"]
4087 #[inline(always)]
4088 pub fn set_pres(&mut self, val: bool) {
4089 self.0 = (self.0 & !(0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize);
4090 }
4091 #[doc = "Port suspend"]
4092 #[inline(always)]
4093 pub const fn psusp(&self) -> bool {
4094 let val = (self.0 >> 7usize) & 0x01;
4095 val != 0
4096 }
4097 #[doc = "Port suspend"]
4098 #[inline(always)]
4099 pub fn set_psusp(&mut self, val: bool) {
4100 self.0 = (self.0 & !(0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize);
4101 }
4102 #[doc = "Port reset"]
4103 #[inline(always)]
4104 pub const fn prst(&self) -> bool {
4105 let val = (self.0 >> 8usize) & 0x01;
4106 val != 0
4107 }
4108 #[doc = "Port reset"]
4109 #[inline(always)]
4110 pub fn set_prst(&mut self, val: bool) {
4111 self.0 = (self.0 & !(0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize);
4112 }
4113 #[doc = "Port line status"]
4114 #[inline(always)]
4115 pub const fn plsts(&self) -> u8 {
4116 let val = (self.0 >> 10usize) & 0x03;
4117 val as u8
4118 }
4119 #[doc = "Port line status"]
4120 #[inline(always)]
4121 pub fn set_plsts(&mut self, val: u8) {
4122 self.0 = (self.0 & !(0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize);
4123 }
4124 #[doc = "Port power"]
4125 #[inline(always)]
4126 pub const fn ppwr(&self) -> bool {
4127 let val = (self.0 >> 12usize) & 0x01;
4128 val != 0
4129 }
4130 #[doc = "Port power"]
4131 #[inline(always)]
4132 pub fn set_ppwr(&mut self, val: bool) {
4133 self.0 = (self.0 & !(0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize);
4134 }
4135 #[doc = "Port test control"]
4136 #[inline(always)]
4137 pub const fn ptctl(&self) -> u8 {
4138 let val = (self.0 >> 13usize) & 0x0f;
4139 val as u8
4140 }
4141 #[doc = "Port test control"]
4142 #[inline(always)]
4143 pub fn set_ptctl(&mut self, val: u8) {
4144 self.0 = (self.0 & !(0x0f << 13usize)) | (((val as u32) & 0x0f) << 13usize);
4145 }
4146 #[doc = "Port speed"]
4147 #[inline(always)]
4148 pub const fn pspd(&self) -> u8 {
4149 let val = (self.0 >> 17usize) & 0x03;
4150 val as u8
4151 }
4152 #[doc = "Port speed"]
4153 #[inline(always)]
4154 pub fn set_pspd(&mut self, val: u8) {
4155 self.0 = (self.0 & !(0x03 << 17usize)) | (((val as u32) & 0x03) << 17usize);
4156 }
4157 }
4158 impl Default for Hprt {
4159 #[inline(always)]
4160 fn default() -> Hprt {
4161 Hprt(0)
4162 }
4163 }
4164 #[doc = "Periodic transmit FIFO/queue status register"]
4165 #[repr(transparent)]
4166 #[derive(Copy, Clone, Eq, PartialEq)]
4167 pub struct Hptxsts(pub u32);
4168 impl Hptxsts {
4169 #[doc = "Periodic transmit data FIFO space available"]
4170 #[inline(always)]
4171 pub const fn ptxfsavl(&self) -> u16 {
4172 let val = (self.0 >> 0usize) & 0xffff;
4173 val as u16
4174 }
4175 #[doc = "Periodic transmit data FIFO space available"]
4176 #[inline(always)]
4177 pub fn set_ptxfsavl(&mut self, val: u16) {
4178 self.0 = (self.0 & !(0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize);
4179 }
4180 #[doc = "Periodic transmit request queue space available"]
4181 #[inline(always)]
4182 pub const fn ptxqsav(&self) -> u8 {
4183 let val = (self.0 >> 16usize) & 0xff;
4184 val as u8
4185 }
4186 #[doc = "Periodic transmit request queue space available"]
4187 #[inline(always)]
4188 pub fn set_ptxqsav(&mut self, val: u8) {
4189 self.0 = (self.0 & !(0xff << 16usize)) | (((val as u32) & 0xff) << 16usize);
4190 }
4191 #[doc = "Top of the periodic transmit request queue"]
4192 #[inline(always)]
4193 pub const fn ptxqtop(&self) -> u8 {
4194 let val = (self.0 >> 24usize) & 0xff;
4195 val as u8
4196 }
4197 #[doc = "Top of the periodic transmit request queue"]
4198 #[inline(always)]
4199 pub fn set_ptxqtop(&mut self, val: u8) {
4200 self.0 = (self.0 & !(0xff << 24usize)) | (((val as u32) & 0xff) << 24usize);
4201 }
4202 }
4203 impl Default for Hptxsts {
4204 #[inline(always)]
4205 fn default() -> Hptxsts {
4206 Hptxsts(0)
4207 }
4208 }
4209 #[doc = "Power and clock gating control register"]
4210 #[repr(transparent)]
4211 #[derive(Copy, Clone, Eq, PartialEq)]
4212 pub struct Pcgcctl(pub u32);
4213 impl Pcgcctl {
4214 #[doc = "Stop PHY clock"]
4215 #[inline(always)]
4216 pub const fn stppclk(&self) -> bool {
4217 let val = (self.0 >> 0usize) & 0x01;
4218 val != 0
4219 }
4220 #[doc = "Stop PHY clock"]
4221 #[inline(always)]
4222 pub fn set_stppclk(&mut self, val: bool) {
4223 self.0 = (self.0 & !(0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize);
4224 }
4225 #[doc = "Gate HCLK"]
4226 #[inline(always)]
4227 pub const fn gatehclk(&self) -> bool {
4228 let val = (self.0 >> 1usize) & 0x01;
4229 val != 0
4230 }
4231 #[doc = "Gate HCLK"]
4232 #[inline(always)]
4233 pub fn set_gatehclk(&mut self, val: bool) {
4234 self.0 = (self.0 & !(0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize);
4235 }
4236 #[doc = "PHY Suspended"]
4237 #[inline(always)]
4238 pub const fn physusp(&self) -> bool {
4239 let val = (self.0 >> 4usize) & 0x01;
4240 val != 0
4241 }
4242 #[doc = "PHY Suspended"]
4243 #[inline(always)]
4244 pub fn set_physusp(&mut self, val: bool) {
4245 self.0 = (self.0 & !(0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize);
4246 }
4247 }
4248 impl Default for Pcgcctl {
4249 #[inline(always)]
4250 fn default() -> Pcgcctl {
4251 Pcgcctl(0)
4252 }
4253 }
4254}
4255pub mod vals {
4256 #[repr(u8)]
4257 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4258 #[allow(non_camel_case_types)]
4259 pub enum Dpid {
4260 DATA0 = 0x0,
4261 DATA2 = 0x01,
4262 DATA1 = 0x02,
4263 MDATA = 0x03,
4264 }
4265 impl Dpid {
4266 #[inline(always)]
4267 pub const fn from_bits(val: u8) -> Dpid {
4268 unsafe { core::mem::transmute(val & 0x03) }
4269 }
4270 #[inline(always)]
4271 pub const fn to_bits(self) -> u8 {
4272 unsafe { core::mem::transmute(self) }
4273 }
4274 }
4275 impl From<u8> for Dpid {
4276 #[inline(always)]
4277 fn from(val: u8) -> Dpid {
4278 Dpid::from_bits(val)
4279 }
4280 }
4281 impl From<Dpid> for u8 {
4282 #[inline(always)]
4283 fn from(val: Dpid) -> u8 {
4284 Dpid::to_bits(val)
4285 }
4286 }
4287 #[repr(u8)]
4288 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4289 #[allow(non_camel_case_types)]
4290 pub enum Dspd {
4291 #[doc = "High speed"]
4292 HIGH_SPEED = 0x0,
4293 #[doc = "Full speed using external ULPI PHY"]
4294 FULL_SPEED_EXTERNAL = 0x01,
4295 _RESERVED_2 = 0x02,
4296 #[doc = "Full speed using internal embedded PHY"]
4297 FULL_SPEED_INTERNAL = 0x03,
4298 }
4299 impl Dspd {
4300 #[inline(always)]
4301 pub const fn from_bits(val: u8) -> Dspd {
4302 unsafe { core::mem::transmute(val & 0x03) }
4303 }
4304 #[inline(always)]
4305 pub const fn to_bits(self) -> u8 {
4306 unsafe { core::mem::transmute(self) }
4307 }
4308 }
4309 impl From<u8> for Dspd {
4310 #[inline(always)]
4311 fn from(val: u8) -> Dspd {
4312 Dspd::from_bits(val)
4313 }
4314 }
4315 impl From<Dspd> for u8 {
4316 #[inline(always)]
4317 fn from(val: Dspd) -> u8 {
4318 Dspd::to_bits(val)
4319 }
4320 }
4321 #[repr(u8)]
4322 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4323 #[allow(non_camel_case_types)]
4324 pub enum Eptyp {
4325 CONTROL = 0x0,
4326 ISOCHRONOUS = 0x01,
4327 BULK = 0x02,
4328 INTERRUPT = 0x03,
4329 }
4330 impl Eptyp {
4331 #[inline(always)]
4332 pub const fn from_bits(val: u8) -> Eptyp {
4333 unsafe { core::mem::transmute(val & 0x03) }
4334 }
4335 #[inline(always)]
4336 pub const fn to_bits(self) -> u8 {
4337 unsafe { core::mem::transmute(self) }
4338 }
4339 }
4340 impl From<u8> for Eptyp {
4341 #[inline(always)]
4342 fn from(val: u8) -> Eptyp {
4343 Eptyp::from_bits(val)
4344 }
4345 }
4346 impl From<Eptyp> for u8 {
4347 #[inline(always)]
4348 fn from(val: Eptyp) -> u8 {
4349 Eptyp::to_bits(val)
4350 }
4351 }
4352 #[repr(u8)]
4353 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4354 #[allow(non_camel_case_types)]
4355 pub enum Pfivl {
4356 #[doc = "80% of the frame interval"]
4357 FRAME_INTERVAL_80 = 0x0,
4358 #[doc = "85% of the frame interval"]
4359 FRAME_INTERVAL_85 = 0x01,
4360 #[doc = "90% of the frame interval"]
4361 FRAME_INTERVAL_90 = 0x02,
4362 #[doc = "95% of the frame interval"]
4363 FRAME_INTERVAL_95 = 0x03,
4364 }
4365 impl Pfivl {
4366 #[inline(always)]
4367 pub const fn from_bits(val: u8) -> Pfivl {
4368 unsafe { core::mem::transmute(val & 0x03) }
4369 }
4370 #[inline(always)]
4371 pub const fn to_bits(self) -> u8 {
4372 unsafe { core::mem::transmute(self) }
4373 }
4374 }
4375 impl From<u8> for Pfivl {
4376 #[inline(always)]
4377 fn from(val: u8) -> Pfivl {
4378 Pfivl::from_bits(val)
4379 }
4380 }
4381 impl From<Pfivl> for u8 {
4382 #[inline(always)]
4383 fn from(val: Pfivl) -> u8 {
4384 Pfivl::to_bits(val)
4385 }
4386 }
4387 #[repr(u8)]
4388 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4389 #[allow(non_camel_case_types)]
4390 pub enum Pktstsd {
4391 _RESERVED_0 = 0x0,
4392 #[doc = "Global OUT NAK (triggers an interrupt)"]
4393 OUT_NAK = 0x01,
4394 #[doc = "OUT data packet received"]
4395 OUT_DATA_RX = 0x02,
4396 #[doc = "OUT transfer completed (triggers an interrupt)"]
4397 OUT_DATA_DONE = 0x03,
4398 #[doc = "SETUP transaction completed (triggers an interrupt)"]
4399 SETUP_DATA_DONE = 0x04,
4400 _RESERVED_5 = 0x05,
4401 #[doc = "SETUP data packet received"]
4402 SETUP_DATA_RX = 0x06,
4403 _RESERVED_7 = 0x07,
4404 _RESERVED_8 = 0x08,
4405 _RESERVED_9 = 0x09,
4406 _RESERVED_a = 0x0a,
4407 _RESERVED_b = 0x0b,
4408 _RESERVED_c = 0x0c,
4409 _RESERVED_d = 0x0d,
4410 _RESERVED_e = 0x0e,
4411 _RESERVED_f = 0x0f,
4412 }
4413 impl Pktstsd {
4414 #[inline(always)]
4415 pub const fn from_bits(val: u8) -> Pktstsd {
4416 unsafe { core::mem::transmute(val & 0x0f) }
4417 }
4418 #[inline(always)]
4419 pub const fn to_bits(self) -> u8 {
4420 unsafe { core::mem::transmute(self) }
4421 }
4422 }
4423 impl From<u8> for Pktstsd {
4424 #[inline(always)]
4425 fn from(val: u8) -> Pktstsd {
4426 Pktstsd::from_bits(val)
4427 }
4428 }
4429 impl From<Pktstsd> for u8 {
4430 #[inline(always)]
4431 fn from(val: Pktstsd) -> u8 {
4432 Pktstsd::to_bits(val)
4433 }
4434 }
4435 #[repr(u8)]
4436 #[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd)]
4437 #[allow(non_camel_case_types)]
4438 pub enum Pktstsh {
4439 _RESERVED_0 = 0x0,
4440 _RESERVED_1 = 0x01,
4441 #[doc = "IN data packet received"]
4442 IN_DATA_RX = 0x02,
4443 #[doc = "IN transfer completed (triggers an interrupt)"]
4444 IN_DATA_DONE = 0x03,
4445 _RESERVED_4 = 0x04,
4446 #[doc = "Data toggle error (triggers an interrupt)"]
4447 DATA_TOGGLE_ERR = 0x05,
4448 _RESERVED_6 = 0x06,
4449 #[doc = "Channel halted (triggers an interrupt)"]
4450 CHANNEL_HALTED = 0x07,
4451 _RESERVED_8 = 0x08,
4452 _RESERVED_9 = 0x09,
4453 _RESERVED_a = 0x0a,
4454 _RESERVED_b = 0x0b,
4455 _RESERVED_c = 0x0c,
4456 _RESERVED_d = 0x0d,
4457 _RESERVED_e = 0x0e,
4458 _RESERVED_f = 0x0f,
4459 }
4460 impl Pktstsh {
4461 #[inline(always)]
4462 pub const fn from_bits(val: u8) -> Pktstsh {
4463 unsafe { core::mem::transmute(val & 0x0f) }
4464 }
4465 #[inline(always)]
4466 pub const fn to_bits(self) -> u8 {
4467 unsafe { core::mem::transmute(self) }
4468 }
4469 }
4470 impl From<u8> for Pktstsh {
4471 #[inline(always)]
4472 fn from(val: u8) -> Pktstsh {
4473 Pktstsh::from_bits(val)
4474 }
4475 }
4476 impl From<Pktstsh> for u8 {
4477 #[inline(always)]
4478 fn from(val: Pktstsh) -> u8 {
4479 Pktstsh::to_bits(val)
4480 }
4481 }
4482}
generated by cgit (git 2.34.1) at 2026-04-05 20:41:44 +0000