diff options
| author | Rafael Bachmann <[email protected]> | 2023-10-15 22:25:35 +0200 |
|---|---|---|
| committer | Rafael Bachmann <[email protected]> | 2023-10-15 22:25:35 +0200 |
| commit | 66e62e999409fd6967ab959a061f7eae660102d0 (patch) | |
| tree | 536acbc976e88dc88c2155f3e2bc5efb9016b92d /embassy-usb/src/class | |
| parent | eeedaf2e763c79a5758460936ba32f23ceb7956c (diff) | |
Fix clippy
Diffstat (limited to 'embassy-usb/src/class')
| -rw-r--r-- | embassy-usb/src/class/cdc_acm.rs | 8 | ||||
| -rw-r--r-- | embassy-usb/src/class/cdc_ncm/mod.rs | 15 | ||||
| -rw-r--r-- | embassy-usb/src/class/hid.rs | 16 |
3 files changed, 26 insertions, 13 deletions
diff --git a/embassy-usb/src/class/cdc_acm.rs b/embassy-usb/src/class/cdc_acm.rs index 0c708464d..790f6faab 100644 --- a/embassy-usb/src/class/cdc_acm.rs +++ b/embassy-usb/src/class/cdc_acm.rs | |||
| @@ -39,6 +39,12 @@ pub struct State<'a> { | |||
| 39 | shared: ControlShared, | 39 | shared: ControlShared, |
| 40 | } | 40 | } |
| 41 | 41 | ||
| 42 | impl<'a> Default for State<'a> { | ||
| 43 | fn default() -> Self { | ||
| 44 | Self::new() | ||
| 45 | } | ||
| 46 | } | ||
| 47 | |||
| 42 | impl<'a> State<'a> { | 48 | impl<'a> State<'a> { |
| 43 | /// Create a new `State`. | 49 | /// Create a new `State`. |
| 44 | pub fn new() -> Self { | 50 | pub fn new() -> Self { |
| @@ -242,7 +248,7 @@ impl<'d, D: Driver<'d>> CdcAcmClass<'d, D> { | |||
| 242 | &[ | 248 | &[ |
| 243 | CDC_TYPE_UNION, // bDescriptorSubtype | 249 | CDC_TYPE_UNION, // bDescriptorSubtype |
| 244 | comm_if.into(), // bControlInterface | 250 | comm_if.into(), // bControlInterface |
| 245 | data_if.into(), // bSubordinateInterface | 251 | data_if, // bSubordinateInterface |
| 246 | ], | 252 | ], |
| 247 | ); | 253 | ); |
| 248 | 254 | ||
diff --git a/embassy-usb/src/class/cdc_ncm/mod.rs b/embassy-usb/src/class/cdc_ncm/mod.rs index 830e9b768..27716b37d 100644 --- a/embassy-usb/src/class/cdc_ncm/mod.rs +++ b/embassy-usb/src/class/cdc_ncm/mod.rs | |||
| @@ -121,6 +121,12 @@ pub struct State<'a> { | |||
| 121 | shared: ControlShared, | 121 | shared: ControlShared, |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | impl<'a> Default for State<'a> { | ||
| 125 | fn default() -> Self { | ||
| 126 | Self::new() | ||
| 127 | } | ||
| 128 | } | ||
| 129 | |||
| 124 | impl<'a> State<'a> { | 130 | impl<'a> State<'a> { |
| 125 | /// Create a new `State`. | 131 | /// Create a new `State`. |
| 126 | pub fn new() -> Self { | 132 | pub fn new() -> Self { |
| @@ -132,16 +138,11 @@ impl<'a> State<'a> { | |||
| 132 | } | 138 | } |
| 133 | 139 | ||
| 134 | /// Shared data between Control and CdcAcmClass | 140 | /// Shared data between Control and CdcAcmClass |
| 141 | #[derive(Default)] | ||
| 135 | struct ControlShared { | 142 | struct ControlShared { |
| 136 | mac_addr: [u8; 6], | 143 | mac_addr: [u8; 6], |
| 137 | } | 144 | } |
| 138 | 145 | ||
| 139 | impl Default for ControlShared { | ||
| 140 | fn default() -> Self { | ||
| 141 | ControlShared { mac_addr: [0; 6] } | ||
| 142 | } | ||
| 143 | } | ||
| 144 | |||
| 145 | struct Control<'a> { | 146 | struct Control<'a> { |
| 146 | mac_addr_string: StringIndex, | 147 | mac_addr_string: StringIndex, |
| 147 | shared: &'a ControlShared, | 148 | shared: &'a ControlShared, |
| @@ -416,7 +417,7 @@ impl<'d, D: Driver<'d>> Sender<'d, D> { | |||
| 416 | self.write_ep.write(&buf[..self.max_packet_size]).await?; | 417 | self.write_ep.write(&buf[..self.max_packet_size]).await?; |
| 417 | 418 | ||
| 418 | for chunk in d2.chunks(self.max_packet_size) { | 419 | for chunk in d2.chunks(self.max_packet_size) { |
| 419 | self.write_ep.write(&chunk).await?; | 420 | self.write_ep.write(chunk).await?; |
| 420 | } | 421 | } |
| 421 | 422 | ||
| 422 | // Send ZLP if needed. | 423 | // Send ZLP if needed. |
diff --git a/embassy-usb/src/class/hid.rs b/embassy-usb/src/class/hid.rs index 889d66ec5..0da29b1a6 100644 --- a/embassy-usb/src/class/hid.rs +++ b/embassy-usb/src/class/hid.rs | |||
| @@ -79,6 +79,12 @@ pub struct State<'d> { | |||
| 79 | out_report_offset: AtomicUsize, | 79 | out_report_offset: AtomicUsize, |
| 80 | } | 80 | } |
| 81 | 81 | ||
| 82 | impl<'d> Default for State<'d> { | ||
| 83 | fn default() -> Self { | ||
| 84 | Self::new() | ||
| 85 | } | ||
| 86 | } | ||
| 87 | |||
| 82 | impl<'d> State<'d> { | 88 | impl<'d> State<'d> { |
| 83 | /// Create a new `State`. | 89 | /// Create a new `State`. |
| 84 | pub fn new() -> Self { | 90 | pub fn new() -> Self { |
| @@ -171,7 +177,7 @@ impl<'d, D: Driver<'d>, const READ_N: usize, const WRITE_N: usize> HidReaderWrit | |||
| 171 | } | 177 | } |
| 172 | 178 | ||
| 173 | /// Waits for both IN and OUT endpoints to be enabled. | 179 | /// Waits for both IN and OUT endpoints to be enabled. |
| 174 | pub async fn ready(&mut self) -> () { | 180 | pub async fn ready(&mut self) { |
| 175 | self.reader.ready().await; | 181 | self.reader.ready().await; |
| 176 | self.writer.ready().await; | 182 | self.writer.ready().await; |
| 177 | } | 183 | } |
| @@ -251,7 +257,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> { | |||
| 251 | } | 257 | } |
| 252 | 258 | ||
| 253 | /// Waits for the interrupt in endpoint to be enabled. | 259 | /// Waits for the interrupt in endpoint to be enabled. |
| 254 | pub async fn ready(&mut self) -> () { | 260 | pub async fn ready(&mut self) { |
| 255 | self.ep_in.wait_enabled().await | 261 | self.ep_in.wait_enabled().await |
| 256 | } | 262 | } |
| 257 | 263 | ||
| @@ -286,7 +292,7 @@ impl<'d, D: Driver<'d>, const N: usize> HidWriter<'d, D, N> { | |||
| 286 | 292 | ||
| 287 | impl<'d, D: Driver<'d>, const N: usize> HidReader<'d, D, N> { | 293 | impl<'d, D: Driver<'d>, const N: usize> HidReader<'d, D, N> { |
| 288 | /// Waits for the interrupt out endpoint to be enabled. | 294 | /// Waits for the interrupt out endpoint to be enabled. |
| 289 | pub async fn ready(&mut self) -> () { | 295 | pub async fn ready(&mut self) { |
| 290 | self.ep_out.wait_enabled().await | 296 | self.ep_out.wait_enabled().await |
| 291 | } | 297 | } |
| 292 | 298 | ||
| @@ -466,7 +472,7 @@ impl<'d> Handler for Control<'d> { | |||
| 466 | HID_REQ_SET_IDLE => { | 472 | HID_REQ_SET_IDLE => { |
| 467 | if let Some(handler) = self.request_handler { | 473 | if let Some(handler) = self.request_handler { |
| 468 | let id = req.value as u8; | 474 | let id = req.value as u8; |
| 469 | let id = (id != 0).then(|| ReportId::In(id)); | 475 | let id = (id != 0).then_some(ReportId::In(id)); |
| 470 | let dur = u32::from(req.value >> 8); | 476 | let dur = u32::from(req.value >> 8); |
| 471 | let dur = if dur == 0 { u32::MAX } else { 4 * dur }; | 477 | let dur = if dur == 0 { u32::MAX } else { 4 * dur }; |
| 472 | handler.set_idle_ms(id, dur); | 478 | handler.set_idle_ms(id, dur); |
| @@ -522,7 +528,7 @@ impl<'d> Handler for Control<'d> { | |||
| 522 | HID_REQ_GET_IDLE => { | 528 | HID_REQ_GET_IDLE => { |
| 523 | if let Some(handler) = self.request_handler { | 529 | if let Some(handler) = self.request_handler { |
| 524 | let id = req.value as u8; | 530 | let id = req.value as u8; |
| 525 | let id = (id != 0).then(|| ReportId::In(id)); | 531 | let id = (id != 0).then_some(ReportId::In(id)); |
| 526 | if let Some(dur) = handler.get_idle_ms(id) { | 532 | if let Some(dur) = handler.get_idle_ms(id) { |
| 527 | let dur = u8::try_from(dur / 4).unwrap_or(0); | 533 | let dur = u8::try_from(dur / 4).unwrap_or(0); |
| 528 | buf[0] = dur; | 534 | buf[0] = dur; |
