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authorchemicstry <[email protected]>2023-01-11 17:47:12 +0100
committerDario Nieuwenhuis <[email protected]>2023-01-11 17:47:12 +0100
commitce842fe28c27e6f57a05efc92bc417f6f7d7af64 (patch)
treeb825147f49704853d07cb0dd16b1da09980c1a2e /embassy-usb
parent96b97c4711af0851f7d3a6785be13b0202b6e902 (diff)
Refactor embassy-usb address handling to allow reordering of status resoponse
Diffstat (limited to 'embassy-usb')
-rw-r--r--embassy-usb/src/lib.rs23
1 files changed, 12 insertions, 11 deletions
diff --git a/embassy-usb/src/lib.rs b/embassy-usb/src/lib.rs
index 661b84119..096e8b07a 100644
--- a/embassy-usb/src/lib.rs
+++ b/embassy-usb/src/lib.rs
@@ -122,10 +122,9 @@ struct Inner<'d, D: Driver<'d>> {
122 122
123 /// Our device address, or 0 if none. 123 /// Our device address, or 0 if none.
124 address: u8, 124 address: u8,
125 /// When receiving a set addr control request, we have to apply it AFTER we've 125 /// SET_ADDRESS requests have special handling depending on the driver.
126 /// finished handling the control request, as the status stage still has to be 126 /// This flag indicates that requests must be handled by `ControlPipe::accept_set_address()`
127 /// handled with addr 0. 127 /// instead of regular `accept()`.
128 /// If true, do a set_addr after finishing the current control req.
129 set_address_pending: bool, 128 set_address_pending: bool,
130 129
131 interfaces: Vec<Interface<'d>, MAX_INTERFACE_COUNT>, 130 interfaces: Vec<Interface<'d>, MAX_INTERFACE_COUNT>,
@@ -254,11 +253,6 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
254 Direction::In => self.handle_control_in(req).await, 253 Direction::In => self.handle_control_in(req).await,
255 Direction::Out => self.handle_control_out(req).await, 254 Direction::Out => self.handle_control_out(req).await,
256 } 255 }
257
258 if self.inner.set_address_pending {
259 self.inner.bus.set_address(self.inner.address);
260 self.inner.set_address_pending = false;
261 }
262 } 256 }
263 257
264 async fn handle_control_in(&mut self, req: Request) { 258 async fn handle_control_in(&mut self, req: Request) {
@@ -328,7 +322,14 @@ impl<'d, D: Driver<'d>> UsbDevice<'d, D> {
328 trace!(" control out data: {:02x?}", data); 322 trace!(" control out data: {:02x?}", data);
329 323
330 match self.inner.handle_control_out(req, data) { 324 match self.inner.handle_control_out(req, data) {
331 OutResponse::Accepted => self.control.accept().await, 325 OutResponse::Accepted => {
326 if self.inner.set_address_pending {
327 self.control.accept_set_address(self.inner.address).await;
328 self.inner.set_address_pending = false;
329 } else {
330 self.control.accept().await
331 }
332 }
332 OutResponse::Rejected => self.control.reject().await, 333 OutResponse::Rejected => self.control.reject().await,
333 } 334 }
334 } 335 }
@@ -655,7 +656,7 @@ impl<'d, D: Driver<'d>> Inner<'d, D> {
655 buf[1] = descriptor_type::STRING; 656 buf[1] = descriptor_type::STRING;
656 let mut pos = 2; 657 let mut pos = 2;
657 for c in s.encode_utf16() { 658 for c in s.encode_utf16() {
658 if pos >= buf.len() { 659 if pos + 2 >= buf.len() {
659 panic!("control buffer too small"); 660 panic!("control buffer too small");
660 } 661 }
661 662