Merge branch 'main' into main

26 files changed, 2531 insertions, 0 deletions

diff --git a/examples/mcxa/src/bin/adc_interrupt.rs b/examples/mcxa/src/bin/adc_interrupt.rs
new file mode 100644
index 000000000..d2cda631c
--- /dev/null
+++ b/examples/mcxa/src/bin/adc_interrupt.rs
@@ -0,0 +1,65 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::{Duration, Ticker};
+use hal::adc::{Adc, InterruptHandler, LpadcConfig, TriggerPriorityPolicy};
+use hal::bind_interrupts;
+use hal::clocks::PoweredClock;
+use hal::clocks::config::Div8;
+use hal::clocks::periph_helpers::{AdcClockSel, Div4};
+use hal::config::Config;
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::Mode;
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::peripherals::ADC1;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    ADC1 => InterruptHandler<ADC1>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("ADC interrupt Example");
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        power: PoweredClock::NormalEnabledDeepSleepDisabled,
+        source: AdcClockSel::FroLfDiv,
+        div: Div4::no_div(),
+    };
+    let mut adc = Adc::new_async(p.ADC1, p.P1_10, Irqs, adc_config).unwrap();
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+    adc.set_resolution(Mode::Data16Bits);
+
+    defmt::info!("ADC configuration done...");
+    let mut ticker = Ticker::every(Duration::from_millis(100));
+
+    loop {
+        ticker.next().await;
+        match adc.read().await {
+            Ok(value) => {
+                defmt::info!("ADC value: {}", value);
+            }
+            Err(e) => {
+                defmt::error!("ADC read error: {:?}", e);
+            }
+        }
+    }
+}
diff --git a/examples/mcxa/src/bin/adc_polling.rs b/examples/mcxa/src/bin/adc_polling.rs
new file mode 100644
index 000000000..5c4d5524c
--- /dev/null
+++ b/examples/mcxa/src/bin/adc_polling.rs
@@ -0,0 +1,78 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::adc::{ConvCommandConfig, ConvTriggerConfig};
+use embassy_time::{Duration, Ticker};
+use hal::adc::{Adc, LpadcConfig, TriggerPriorityPolicy};
+use hal::clocks::PoweredClock;
+use hal::clocks::config::Div8;
+use hal::clocks::periph_helpers::{AdcClockSel, Div4};
+use hal::config::Config;
+use hal::pac::adc1::cfg::{Pwrsel, Refsel};
+use hal::pac::adc1::cmdl1::Mode;
+use hal::pac::adc1::ctrl::CalAvgs;
+use hal::pac::adc1::tctrl::Tcmd;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const G_LPADC_RESULT_SHIFT: u32 = 0;
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("=== ADC polling Example ===");
+
+    let adc_config = LpadcConfig {
+        enable_in_doze_mode: true,
+        conversion_average_mode: CalAvgs::Average128,
+        enable_analog_preliminary: true,
+        power_up_delay: 0x80,
+        reference_voltage_source: Refsel::Option3,
+        power_level_mode: Pwrsel::Lowest,
+        trigger_priority_policy: TriggerPriorityPolicy::ConvPreemptImmediatelyNotAutoResumed,
+        enable_conv_pause: false,
+        conv_pause_delay: 0,
+        power: PoweredClock::NormalEnabledDeepSleepDisabled,
+        source: AdcClockSel::FroLfDiv,
+        div: Div4::no_div(),
+    };
+    let adc = Adc::new_blocking(p.ADC1, p.P1_10, adc_config).unwrap();
+
+    adc.do_offset_calibration();
+    adc.do_auto_calibration();
+
+    let conv_command_config = ConvCommandConfig {
+        conversion_resolution_mode: Mode::Data16Bits,
+        ..ConvCommandConfig::default()
+    };
+    adc.set_conv_command_config(1, &conv_command_config).unwrap();
+
+    let conv_trigger_config = ConvTriggerConfig {
+        target_command_id: Tcmd::ExecuteCmd1,
+        enable_hardware_trigger: false,
+        ..Default::default()
+    };
+    adc.set_conv_trigger_config(0, &conv_trigger_config).unwrap();
+
+    defmt::info!("=== ADC configuration done... ===");
+    let mut tick = Ticker::every(Duration::from_millis(100));
+
+    loop {
+        tick.next().await;
+        adc.do_software_trigger(1).unwrap();
+        let result = loop {
+            match adc.get_conv_result() {
+                Ok(res) => break res,
+                Err(_) => {
+                    // Conversion not ready, continue polling
+                }
+            }
+        };
+        let value = result.conv_value >> G_LPADC_RESULT_SHIFT;
+        defmt::info!("ADC value: {=u16}", value);
+    }
+}
diff --git a/examples/mcxa/src/bin/blinky.rs b/examples/mcxa/src/bin/blinky.rs
new file mode 100644
index 000000000..dd08ec0d9
--- /dev/null
+++ b/examples/mcxa/src/bin/blinky.rs
@@ -0,0 +1,36 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{DriveStrength, Level, Output, SlewRate};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("Blink example");
+
+    let mut red = Output::new(p.P3_18, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut green = Output::new(p.P3_19, Level::High, DriveStrength::Normal, SlewRate::Fast);
+    let mut blue = Output::new(p.P3_21, Level::High, DriveStrength::Normal, SlewRate::Fast);
+
+    loop {
+        defmt::info!("Toggle LEDs");
+
+        red.toggle();
+        Timer::after_millis(250).await;
+
+        red.toggle();
+        green.toggle();
+        Timer::after_millis(250).await;
+
+        green.toggle();
+        blue.toggle();
+        Timer::after_millis(250).await;
+        blue.toggle();
+
+        Timer::after_millis(250).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/button.rs b/examples/mcxa/src/bin/button.rs
new file mode 100644
index 000000000..943edbb15
--- /dev/null
+++ b/examples/mcxa/src/bin/button.rs
@@ -0,0 +1,23 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{Input, Pull};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("Button example");
+
+    // This button is labeled "WAKEUP" on the FRDM-MCXA276
+    // The board already has a 10K pullup
+    let monitor = Input::new(p.P1_7, Pull::Disabled);
+
+    loop {
+        defmt::info!("Pin level is {:?}", monitor.get_level());
+        Timer::after_millis(1000).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/button_async.rs b/examples/mcxa/src/bin/button_async.rs
new file mode 100644
index 000000000..6cc7b62cd
--- /dev/null
+++ b/examples/mcxa/src/bin/button_async.rs
@@ -0,0 +1,29 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::gpio::{Input, Pull};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("GPIO interrupt example");
+
+    // This button is labeled "WAKEUP" on the FRDM-MCXA276
+    // The board already has a 10K pullup
+    let mut pin = Input::new(p.P1_7, Pull::Disabled);
+
+    let mut press_count = 0u32;
+
+    loop {
+        pin.wait_for_falling_edge().await;
+
+        press_count += 1;
+
+        defmt::info!("Button pressed! Count: {}", press_count);
+        Timer::after_millis(50).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/clkout.rs b/examples/mcxa/src/bin/clkout.rs
new file mode 100644
index 000000000..1e52912d3
--- /dev/null
+++ b/examples/mcxa/src/bin/clkout.rs
@@ -0,0 +1,68 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clkout::{ClockOut, ClockOutSel, Config, Div4};
+use embassy_mcxa::clocks::PoweredClock;
+use embassy_mcxa::gpio::{DriveStrength, Level, Output, SlewRate};
+use embassy_time::Timer;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+/// Demonstrate CLKOUT, using Pin P4.2
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+    let mut pin = p.P4_2;
+    let mut clkout = p.CLKOUT;
+
+    loop {
+        defmt::info!("Set Low...");
+        let mut output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow);
+        Timer::after_millis(500).await;
+
+        defmt::info!("Set High...");
+        output.set_high();
+        Timer::after_millis(400).await;
+
+        defmt::info!("Set Low...");
+        output.set_low();
+        Timer::after_millis(500).await;
+
+        defmt::info!("16k...");
+        // Run Clock Out with the 16K clock
+        let _clock_out = ClockOut::new(
+            clkout.reborrow(),
+            pin.reborrow(),
+            Config {
+                sel: ClockOutSel::Clk16K,
+                div: Div4::no_div(),
+                level: PoweredClock::NormalEnabledDeepSleepDisabled,
+            },
+        )
+        .unwrap();
+
+        Timer::after_millis(3000).await;
+
+        defmt::info!("Set Low...");
+        drop(_clock_out);
+
+        let _output = Output::new(pin.reborrow(), Level::Low, DriveStrength::Normal, SlewRate::Slow);
+        Timer::after_millis(500).await;
+
+        // Run Clock Out with the 12M clock, divided by 3
+        defmt::info!("4M...");
+        let _clock_out = ClockOut::new(
+            clkout.reborrow(),
+            pin.reborrow(),
+            Config {
+                sel: ClockOutSel::Fro12M,
+                div: const { Div4::from_divisor(3).unwrap() },
+                level: PoweredClock::NormalEnabledDeepSleepDisabled,
+            },
+        )
+        .unwrap();
+
+        // Let it run for 3 seconds...
+        Timer::after_millis(3000).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/crc.rs b/examples/mcxa/src/bin/crc.rs
new file mode 100644
index 000000000..0125e625c
--- /dev/null
+++ b/examples/mcxa/src/bin/crc.rs
@@ -0,0 +1,154 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::config::Config;
+use hal::crc::Crc;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const CCITT_FALSE: crc::Algorithm<u16> = crc::Algorithm {
+    width: 16,
+    poly: 0x1021,
+    init: 0xffff,
+    refin: false,
+    refout: false,
+    xorout: 0,
+    check: 0x29b1,
+    residue: 0x0000,
+};
+
+const POSIX: crc::Algorithm<u32> = crc::Algorithm {
+    width: 32,
+    poly: 0x04c1_1db7,
+    init: 0,
+    refin: false,
+    refout: false,
+    xorout: 0xffff_ffff,
+    check: 0x765e_7680,
+    residue: 0x0000,
+};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let mut p = hal::init(config);
+
+    defmt::info!("CRC example");
+
+    let buf_u8 = [0x00u8, 0x11, 0x22, 0x33];
+    let buf_u16 = [0x0000u16, 0x1111, 0x2222, 0x3333];
+    let buf_u32 = [0x0000_0000u32, 0x1111_1111, 0x2222_2222, 0x3333_3333];
+
+    // CCITT False
+
+    let sw_crc = crc::Crc::<u16>::new(&CCITT_FALSE);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xa467);
+
+    let mut crc = Crc::new_ccitt_false(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xe5c7);
+
+    // Maxim
+
+    let sw_crc = crc::Crc::<u16>::new(&crc::CRC_16_MAXIM_DOW);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x2afe);
+
+    let mut crc = Crc::new_maxim(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x17d7);
+
+    // Kermit
+
+    let sw_crc = crc::Crc::<u16>::new(&crc::CRC_16_KERMIT);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x66eb);
+
+    let mut crc = Crc::new_kermit(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x75ea);
+
+    // ISO HDLC
+
+    let sw_crc = crc::Crc::<u32>::new(&crc::CRC_32_ISO_HDLC);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x8a61_4178);
+
+    let mut crc = Crc::new_iso_hdlc(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0xfab5_d04e);
+
+    // POSIX
+
+    let sw_crc = crc::Crc::<u32>::new(&POSIX);
+    let mut digest = sw_crc.digest();
+    digest.update(&buf_u8);
+    let sw_sum = digest.finalize();
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u8);
+    let sum = crc.finalize();
+
+    assert_eq!(sum, sw_sum);
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u16);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x6d76_4f58);
+
+    let mut crc = Crc::new_posix(p.CRC0.reborrow());
+    crc.feed(&buf_u32);
+    let sum = crc.finalize();
+    assert_eq!(sum, 0x2a5b_cb90);
+
+    defmt::info!("CRC successful");
+}
diff --git a/examples/mcxa/src/bin/dma_mem_to_mem.rs b/examples/mcxa/src/bin/dma_mem_to_mem.rs
new file mode 100644
index 000000000..b38baccb5
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_mem_to_mem.rs
@@ -0,0 +1,118 @@
+//! DMA memory-to-memory transfer example for MCXA276.
+//!
+//! This example demonstrates using DMA to copy data between memory buffers
+//! using the Embassy-style async API with type-safe transfers.
+//!
+//! # Embassy-style features demonstrated:
+//! - `TransferOptions` for configuration
+//! - Type-safe `mem_to_mem<u32>()` method with async `.await`
+//! - `Transfer` Future that can be `.await`ed
+//! - `Word` trait for automatic transfer width detection
+//! - `memset()` method for filling memory with a pattern
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, TransferOptions};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 4;
+
+// Buffers in RAM (static mut is automatically placed in .bss/.data)
+static SRC_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([1, 2, 3, 4]);
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+static MEMSET_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA memory-to-memory example starting...");
+
+    defmt::info!("EDMA memory to memory example begin.");
+
+    let src = SRC_BUFFER.take();
+    let dst = DEST_BUFFER.take();
+    let mst = MEMSET_BUFFER.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure transfer options (Embassy-style)
+    // TransferOptions defaults to: complete_transfer_interrupt = true
+    let options = TransferOptions::default();
+
+    // =========================================================================
+    // Part 1: Embassy-style async API demonstration (mem_to_mem)
+    // =========================================================================
+    //
+    // Use the new type-safe `mem_to_mem<u32>()` method:
+    // - Automatically determines transfer width from buffer element type (u32)
+    // - Returns a `Transfer` future that can be `.await`ed
+    // - Uses TransferOptions for consistent configuration
+    //
+    // Using async `.await` - the executor can run other tasks while waiting!
+
+    // Perform type-safe memory-to-memory transfer using Embassy-style async API
+    // Using async `.await` - the executor can run other tasks while waiting!
+    let transfer = dma_ch0.mem_to_mem(src, dst, options).unwrap();
+    transfer.await.unwrap();
+
+    defmt::info!("DMA mem-to-mem transfer complete!");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify data
+    if src != dst {
+        defmt::error!("FAIL: mem_to_mem mismatch!");
+    } else {
+        defmt::info!("PASS: mem_to_mem verified.");
+    }
+
+    // =========================================================================
+    // Part 2: memset() demonstration
+    // =========================================================================
+    //
+    // The `memset()` method fills a buffer with a pattern value:
+    // - Fixed source address (pattern is read repeatedly)
+    // - Incrementing destination address
+    // - Uses the same Transfer future pattern
+
+    defmt::info!("--- Demonstrating memset() feature ---");
+
+    defmt::info!("Memset Buffer (before): {=[?]}", mst.as_slice());
+
+    // Fill buffer with a pattern value using DMA memset
+    let pattern: u32 = 0xDEADBEEF;
+    defmt::info!("Filling with pattern 0xDEADBEEF...");
+
+    // Using blocking_wait() for demonstration - also shows non-async usage
+    let transfer = dma_ch0.memset(&pattern, mst, options);
+    transfer.blocking_wait();
+
+    defmt::info!("DMA memset complete!");
+    defmt::info!("Memset Buffer (after): {=[?]}", mst.as_slice());
+
+    // Verify memset result
+    if !mst.iter().all(|&v| v == pattern) {
+        defmt::error!("FAIL: memset mismatch!");
+    } else {
+        defmt::info!("PASS: memset verified.");
+    }
+
+    defmt::info!("=== All DMA tests complete ===");
+}
diff --git a/examples/mcxa/src/bin/dma_scatter_gather_builder.rs b/examples/mcxa/src/bin/dma_scatter_gather_builder.rs
new file mode 100644
index 000000000..30ce20c96
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_scatter_gather_builder.rs
@@ -0,0 +1,130 @@
+//! DMA Scatter-Gather Builder example for MCXA276.
+//!
+//! This example demonstrates using the new `ScatterGatherBuilder` API for
+//! chaining multiple DMA transfers with a type-safe builder pattern.
+//!
+//! # Features demonstrated:
+//! - `ScatterGatherBuilder::new()` for creating a builder
+//! - `add_transfer()` for adding memory-to-memory segments
+//! - `build()` to start the chained transfer
+//! - Automatic TCD linking and ESG bit management
+//!
+//! # Comparison with manual scatter-gather:
+//! The manual approach (see `dma_scatter_gather.rs`) requires:
+//! - Manual TCD pool allocation and alignment
+//! - Manual CSR/ESG/INTMAJOR bit manipulation
+//! - Manual dlast_sga address calculations
+//!
+//! The builder approach handles all of this automatically!
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, ScatterGatherBuilder};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source buffers (multiple segments)
+static SRC1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0x11111111, 0x22222222, 0x33333333, 0x44444444]);
+static SRC2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0xAAAAAAAA, 0xBBBBBBBB, 0xCCCCCCCC, 0xDDDDDDDD]);
+static SRC3: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0x12345678, 0x9ABCDEF0, 0xFEDCBA98, 0x76543210]);
+
+// Destination buffers (one per segment)
+static DST1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DST2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DST3: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA Scatter-Gather Builder example starting...");
+
+    defmt::info!("DMA Scatter-Gather Builder Example");
+    defmt::info!("===================================");
+    let src1 = SRC1.take();
+    let src2 = SRC2.take();
+    let src3 = SRC3.take();
+    let dst1 = DST1.take();
+    let dst2 = DST2.take();
+    let dst3 = DST3.take();
+
+    // Show source buffers
+    defmt::info!("Source buffers:");
+    defmt::info!("  SRC1: {=[?]}", src1.as_slice());
+    defmt::info!("  SRC2: {=[?]}", src2.as_slice());
+    defmt::info!("  SRC3: {=[?]}", src3.as_slice());
+
+    defmt::info!("Destination buffers (before):");
+    defmt::info!("  DST1: {=[?]}", dst1.as_slice());
+    defmt::info!("  DST2: {=[?]}", dst2.as_slice());
+    defmt::info!("  DST3: {=[?]}", dst3.as_slice());
+
+    // Create DMA channel
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    defmt::info!("Building scatter-gather chain with builder API...");
+
+    // =========================================================================
+    // ScatterGatherBuilder API demonstration
+    // =========================================================================
+    //
+    // The builder pattern makes scatter-gather transfers much easier:
+    // 1. Create a builder
+    // 2. Add transfer segments with add_transfer()
+    // 3. Call build() to start the entire chain
+    // No manual TCD manipulation required!
+
+    let mut builder = ScatterGatherBuilder::<u32>::new();
+
+    // Add three transfer segments - the builder handles TCD linking automatically
+    builder.add_transfer(src1, dst1);
+    builder.add_transfer(src2, dst2);
+    builder.add_transfer(src3, dst3);
+
+    defmt::info!("Added 3 transfer segments to chain.");
+    defmt::info!("Starting scatter-gather transfer with .await...");
+
+    // Build and execute the scatter-gather chain
+    // The build() method:
+    // - Links all TCDs together with ESG bit
+    // - Sets INTMAJOR on all TCDs
+    // - Loads the first TCD into hardware
+    // - Returns a Transfer future
+    let transfer = builder.build(&dma_ch0).expect("Failed to build scatter-gather");
+    transfer.blocking_wait();
+
+    defmt::info!("Scatter-gather transfer complete!");
+
+    // Show results
+    defmt::info!("Destination buffers (after):");
+    defmt::info!("  DST1: {=[?]}", dst1.as_slice());
+    defmt::info!("  DST2: {=[?]}", dst2.as_slice());
+    defmt::info!("  DST3: {=[?]}", dst3.as_slice());
+
+    let comps = [(src1, dst1), (src2, dst2), (src3, dst3)];
+
+    // Verify all three segments
+    let mut all_ok = true;
+    for (src, dst) in comps {
+        all_ok &= src == dst;
+    }
+
+    if all_ok {
+        defmt::info!("PASS: All segments verified!");
+    } else {
+        defmt::error!("FAIL: Mismatch detected!");
+    }
+
+    defmt::info!("=== Scatter-Gather Builder example complete ===");
+}
diff --git a/examples/mcxa/src/bin/dma_wrap_transfer.rs b/examples/mcxa/src/bin/dma_wrap_transfer.rs
new file mode 100644
index 000000000..acfd29f08
--- /dev/null
+++ b/examples/mcxa/src/bin/dma_wrap_transfer.rs
@@ -0,0 +1,184 @@
+//! DMA wrap transfer example for MCXA276.
+//!
+//! This example demonstrates using DMA with modulo addressing to wrap around
+//! a source buffer, effectively repeating the source data in the destination.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - No need to pass register block around
+
+#![no_std]
+#![no_main]
+
+use core::fmt::Write as _;
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use embassy_mcxa::lpuart::{Blocking, Config, Lpuart, LpuartTx};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source buffer: 4 words (16 bytes), aligned to 16 bytes for modulo
+#[repr(align(16))]
+struct AlignedSrc([u32; 4]);
+
+static mut SRC: AlignedSrc = AlignedSrc([0; 4]);
+static mut DST: [u32; 8] = [0; 8];
+
+/// Helper to print a buffer to UART
+fn print_buffer(tx: &mut LpuartTx<'_, Blocking>, buf_ptr: *const u32, len: usize) {
+    write!(tx, "{:?}", unsafe { core::slice::from_raw_parts(buf_ptr, len) }).ok();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA wrap transfer example starting...");
+
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    let lpuart = Lpuart::new_blocking(p.LPUART2, p.P2_2, p.P2_3, config).unwrap();
+    let (mut tx, _rx) = lpuart.split();
+
+    tx.blocking_write(b"EDMA wrap transfer example begin.\r\n\r\n").unwrap();
+
+    // Initialize buffers
+    unsafe {
+        SRC.0 = [1, 2, 3, 4];
+        DST = [0; 8];
+    }
+
+    tx.blocking_write(b"Source Buffer:              ").unwrap();
+    print_buffer(&mut tx, unsafe { core::ptr::addr_of!(SRC.0) } as *const u32, 4);
+    tx.blocking_write(b"\r\n").unwrap();
+
+    tx.blocking_write(b"Destination Buffer (before): ").unwrap();
+    print_buffer(&mut tx, core::ptr::addr_of!(DST) as *const u32, 8);
+    tx.blocking_write(b"\r\n").unwrap();
+
+    tx.blocking_write(b"Configuring DMA with Embassy-style API...\r\n")
+        .unwrap();
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure wrap transfer using direct TCD access:
+    // SRC is 16 bytes (4 * u32). We want to transfer 32 bytes (8 * u32).
+    // SRC modulo is 16 bytes (2^4 = 16) - wraps source address.
+    // DST modulo is 0 (disabled).
+    // This causes the source address to wrap around after 16 bytes,
+    // effectively repeating the source data.
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr()
+            .write(|w| w.saddr().bits(core::ptr::addr_of!(SRC.0) as u32));
+        t.tcd_daddr()
+            .write(|w| w.daddr().bits(core::ptr::addr_of_mut!(DST) as u32));
+
+        // Offsets: both increment by 4 bytes
+        t.tcd_soff().write(|w| w.soff().bits(4));
+        t.tcd_doff().write(|w| w.doff().bits(4));
+
+        // Attributes: 32-bit transfers (size = 2)
+        // SMOD = 4 (2^4 = 16 byte modulo for source), DMOD = 0 (disabled)
+        t.tcd_attr().write(|w| {
+            w.ssize()
+                .bits(2)
+                .dsize()
+                .bits(2)
+                .smod()
+                .bits(4) // Source modulo: 2^4 = 16 bytes
+                .dmod()
+                .bits(0) // Dest modulo: disabled
+        });
+
+        // Transfer 32 bytes total in one minor loop
+        let nbytes = 32u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Source wraps via modulo, no adjustment needed
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(0));
+        // Reset dest address after major loop
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(nbytes as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        tx.blocking_write(b"Triggering transfer...\r\n").unwrap();
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    tx.blocking_write(b"\r\nEDMA wrap transfer example finish.\r\n\r\n")
+        .unwrap();
+    tx.blocking_write(b"Destination Buffer (after):  ").unwrap();
+    print_buffer(&mut tx, core::ptr::addr_of!(DST) as *const u32, 8);
+    tx.blocking_write(b"\r\n\r\n").unwrap();
+
+    // Verify: DST should be [1, 2, 3, 4, 1, 2, 3, 4]
+    let expected = [1u32, 2, 3, 4, 1, 2, 3, 4];
+    let mut mismatch = false;
+    unsafe {
+        for i in 0..8 {
+            if DST[i] != expected[i] {
+                mismatch = true;
+                break;
+            }
+        }
+    }
+
+    if mismatch {
+        tx.blocking_write(b"FAIL: Mismatch detected!\r\n").unwrap();
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        tx.blocking_write(b"PASS: Data verified.\r\n").unwrap();
+        defmt::info!("PASS: Data verified.");
+    }
+
+    loop {
+        cortex_m::asm::wfe();
+    }
+}
diff --git a/examples/mcxa/src/bin/hello.rs b/examples/mcxa/src/bin/hello.rs
new file mode 100644
index 000000000..e371d9413
--- /dev/null
+++ b/examples/mcxa/src/bin/hello.rs
@@ -0,0 +1,119 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use hal::lpuart::{Blocking, Config, Lpuart};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+/// Simple helper to write a byte as hex to UART
+fn write_hex_byte(uart: &mut Lpuart<'_, Blocking>, byte: u8) {
+    const HEX_DIGITS: &[u8] = b"0123456789ABCDEF";
+    let _ = uart.write_byte(HEX_DIGITS[(byte >> 4) as usize]);
+    let _ = uart.write_byte(HEX_DIGITS[(byte & 0xF) as usize]);
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("boot");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX
+    let mut uart = Lpuart::new_blocking(
+        p.LPUART2, // Peripheral
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        config,
+    )
+    .unwrap();
+
+    // Print welcome message before any async delays to guarantee early console output
+    uart.write_str_blocking("\r\n=== MCXA276 UART Echo Demo ===\r\n");
+    uart.write_str_blocking("Available commands:\r\n");
+    uart.write_str_blocking("  help     - Show this help\r\n");
+    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+    uart.write_str_blocking("Type a command: ");
+
+    let mut buffer = [0u8; 64];
+    let mut buf_idx = 0;
+
+    loop {
+        // Read a byte from UART
+        let byte = uart.read_byte_blocking();
+
+        // Echo the character back
+        if byte == b'\r' || byte == b'\n' {
+            // Enter pressed - process command
+            uart.write_str_blocking("\r\n");
+
+            if buf_idx > 0 {
+                let command = &buffer[0..buf_idx];
+
+                if command == b"help" {
+                    uart.write_str_blocking("Available commands:\r\n");
+                    uart.write_str_blocking("  help     - Show this help\r\n");
+                    uart.write_str_blocking("  echo <text> - Echo back the text\r\n");
+                    uart.write_str_blocking("  hex <byte> - Display byte in hex (0-255)\r\n");
+                } else if command.starts_with(b"echo ") && command.len() > 5 {
+                    uart.write_str_blocking("Echo: ");
+                    uart.write_str_blocking(core::str::from_utf8(&command[5..]).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                } else if command.starts_with(b"hex ") && command.len() > 4 {
+                    // Parse the byte value
+                    let num_str = &command[4..];
+                    if let Ok(num) = parse_u8(num_str) {
+                        uart.write_str_blocking("Hex: 0x");
+                        write_hex_byte(&mut uart, num);
+                        uart.write_str_blocking("\r\n");
+                    } else {
+                        uart.write_str_blocking("Invalid number for hex command\r\n");
+                    }
+                } else if !command.is_empty() {
+                    uart.write_str_blocking("Unknown command: ");
+                    uart.write_str_blocking(core::str::from_utf8(command).unwrap_or(""));
+                    uart.write_str_blocking("\r\n");
+                }
+            }
+
+            // Reset buffer and prompt
+            buf_idx = 0;
+            uart.write_str_blocking("Type a command: ");
+        } else if byte == 8 || byte == 127 {
+            // Backspace
+            if buf_idx > 0 {
+                buf_idx -= 1;
+                uart.write_str_blocking("\x08 \x08"); // Erase character
+            }
+        } else if buf_idx < buffer.len() - 1 {
+            // Regular character
+            buffer[buf_idx] = byte;
+            buf_idx += 1;
+            let _ = uart.write_byte(byte);
+        }
+    }
+}
+
+/// Simple parser for u8 from ASCII bytes
+fn parse_u8(bytes: &[u8]) -> Result<u8, ()> {
+    let mut result = 0u8;
+    for &b in bytes {
+        if b.is_ascii_digit() {
+            result = result.checked_mul(10).ok_or(())?;
+            result = result.checked_add(b - b'0').ok_or(())?;
+        } else {
+            return Err(());
+        }
+    }
+    Ok(result)
+}
diff --git a/examples/mcxa/src/bin/i2c-async.rs b/examples/mcxa/src/bin/i2c-async.rs
new file mode 100644
index 000000000..edcfd5f22
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-async.rs
@@ -0,0 +1,39 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::bind_interrupts;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::InterruptHandler;
+use hal::i2c::controller::{self, I2c, Speed};
+use hal::peripherals::LPI2C3;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(
+    struct Irqs {
+        LPI2C3 => InterruptHandler<LPI2C3>;
+    }
+);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+    let mut i2c = I2c::new_async(p.LPI2C3, p.P3_27, p.P3_28, Irqs, config).unwrap();
+    let mut buf = [0u8; 2];
+
+    loop {
+        i2c.async_write_read(0x48, &[0x00], &mut buf).await.unwrap();
+        defmt::info!("Buffer: {:02x}", buf);
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/i2c-blocking.rs b/examples/mcxa/src/bin/i2c-blocking.rs
new file mode 100644
index 000000000..0f6c8cbae
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-blocking.rs
@@ -0,0 +1,31 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_time::Timer;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::controller::{self, I2c, Speed};
+use tmp108::Tmp108;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+    let i2c = I2c::new_blocking(p.LPI2C3, p.P3_27, p.P3_28, config).unwrap();
+    let mut tmp = Tmp108::new_with_a0_gnd(i2c);
+
+    loop {
+        let temperature = tmp.temperature().unwrap();
+        defmt::info!("Temperature: {}C", temperature);
+        Timer::after_secs(1).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/i2c-scan-blocking.rs b/examples/mcxa/src/bin/i2c-scan-blocking.rs
new file mode 100644
index 000000000..bd706d712
--- /dev/null
+++ b/examples/mcxa/src/bin/i2c-scan-blocking.rs
@@ -0,0 +1,40 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::gpio::{Input, Pull};
+use embassy_time::Timer;
+use hal::clocks::config::Div8;
+use hal::config::Config;
+use hal::i2c::controller::{self, I2c, Speed};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut config = Config::default();
+    config.clock_cfg.sirc.fro_lf_div = Div8::from_divisor(1);
+
+    let p = hal::init(config);
+
+    defmt::info!("I2C example");
+
+    let mut config = controller::Config::default();
+    config.speed = Speed::Standard;
+
+    // Note: P0_2 is connected to P1_8 on the FRDM_MCXA276 via a resistor, and
+    // defaults to SWO on the debug peripheral. Explicitly make it a high-z
+    // input.
+    let _pin = Input::new(p.P0_2, Pull::Disabled);
+    let mut i2c = I2c::new_blocking(p.LPI2C2, p.P1_9, p.P1_8, config).unwrap();
+
+    for addr in 0x01..=0x7f {
+        let result = i2c.blocking_write(addr, &[]);
+        if result.is_ok() {
+            defmt::info!("Device found at addr {:02x}", addr);
+        }
+    }
+
+    loop {
+        Timer::after_secs(10).await;
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_buffered.rs b/examples/mcxa/src/bin/lpuart_buffered.rs
new file mode 100644
index 000000000..47b56b7c7
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_buffered.rs
@@ -0,0 +1,62 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::Config;
+use embassy_mcxa::lpuart::buffered::BufferedLpuart;
+use embassy_mcxa::{bind_interrupts, lpuart};
+use embedded_io_async::Write;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Bind OS_EVENT for timers plus LPUART2 IRQ for the buffered driver
+bind_interrupts!(struct Irqs {
+    LPUART2 => lpuart::buffered::BufferedInterruptHandler::<hal::peripherals::LPUART2>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    // Configure NVIC for LPUART2
+    hal::interrupt::LPUART2.configure_for_uart(hal::interrupt::Priority::P3);
+
+    // UART configuration (enable both TX and RX)
+    let config = Config {
+        baudrate_bps: 115_200,
+        rx_fifo_watermark: 0,
+        tx_fifo_watermark: 0,
+        ..Default::default()
+    };
+
+    let mut tx_buf = [0u8; 256];
+    let mut rx_buf = [0u8; 256];
+
+    // Create a buffered LPUART2 instance with both TX and RX
+    let mut uart = BufferedLpuart::new(
+        p.LPUART2,
+        p.P2_2, // TX pin
+        p.P2_3, // RX pin
+        Irqs,
+        &mut tx_buf,
+        &mut rx_buf,
+        config,
+    )
+    .unwrap();
+
+    // Split into TX and RX parts
+    let (tx, rx) = uart.split_ref();
+
+    tx.write(b"Hello buffered LPUART.\r\n").await.unwrap();
+    tx.write(b"Type characters to echo them back.\r\n").await.unwrap();
+
+    // Echo loop
+    let mut buf = [0u8; 4];
+    loop {
+        let used = rx.read(&mut buf).await.unwrap();
+        tx.write_all(&buf[..used]).await.unwrap();
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_dma.rs b/examples/mcxa/src/bin/lpuart_dma.rs
new file mode 100644
index 000000000..cc86f6a40
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_dma.rs
@@ -0,0 +1,68 @@
+//! LPUART DMA example for MCXA276.
+//!
+//! This example demonstrates using DMA for UART TX and RX operations.
+//! It sends a message using DMA, then waits for 16 characters to be received
+//! via DMA and echoes them back.
+//!
+//! The DMA request sources are automatically derived from the LPUART instance type.
+//! DMA clock/reset/init is handled automatically by the HAL.
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::{Config, LpuartDma};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("LPUART DMA example starting...");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance with DMA channels
+    let mut lpuart = LpuartDma::new(
+        p.LPUART2, // Instance
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        p.DMA_CH0, // TX DMA channel
+        p.DMA_CH1, // RX DMA channel
+        config,
+    )
+    .unwrap();
+
+    // Send a message using DMA (DMA request source is automatically derived from LPUART2)
+    let tx_msg = b"Hello from LPUART2 DMA TX!\r\n";
+    lpuart.write_dma(tx_msg).await.unwrap();
+
+    defmt::info!("TX DMA complete");
+
+    // Send prompt
+    let prompt = b"Type 16 characters to echo via DMA:\r\n";
+    lpuart.write_dma(prompt).await.unwrap();
+
+    // Receive 16 characters using DMA
+    let mut rx_buf = [0u8; 16];
+    lpuart.read_dma(&mut rx_buf).await.unwrap();
+
+    defmt::info!("RX DMA complete");
+
+    // Echo back the received data
+    let echo_prefix = b"\r\nReceived: ";
+    lpuart.write_dma(echo_prefix).await.unwrap();
+    lpuart.write_dma(&rx_buf).await.unwrap();
+    let done_msg = b"\r\nDone!\r\n";
+    lpuart.write_dma(done_msg).await.unwrap();
+
+    defmt::info!("Example complete");
+}
diff --git a/examples/mcxa/src/bin/lpuart_polling.rs b/examples/mcxa/src/bin/lpuart_polling.rs
new file mode 100644
index 000000000..b80668834
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_polling.rs
@@ -0,0 +1,47 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+use crate::hal::lpuart::{Config, Lpuart};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("boot");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create UART instance using LPUART2 with P2_2 as TX and P2_3 as RX
+    let lpuart = Lpuart::new_blocking(
+        p.LPUART2, // Peripheral
+        p.P2_2,    // TX pin
+        p.P2_3,    // RX pin
+        config,
+    )
+    .unwrap();
+
+    // Split into separate TX and RX parts
+    let (mut tx, mut rx) = lpuart.split();
+
+    // Write hello messages
+    tx.blocking_write(b"Hello world.\r\n").unwrap();
+    tx.blocking_write(b"Echoing. Type characters...\r\n").unwrap();
+
+    // Echo loop
+    loop {
+        let mut buf = [0u8; 1];
+        rx.blocking_read(&mut buf).unwrap();
+        tx.blocking_write(&buf).unwrap();
+    }
+}
diff --git a/examples/mcxa/src/bin/lpuart_ring_buffer.rs b/examples/mcxa/src/bin/lpuart_ring_buffer.rs
new file mode 100644
index 000000000..be7fd4534
--- /dev/null
+++ b/examples/mcxa/src/bin/lpuart_ring_buffer.rs
@@ -0,0 +1,115 @@
+//! LPUART Ring Buffer DMA example for MCXA276.
+//!
+//! This example demonstrates using the high-level `LpuartRxDma::setup_ring_buffer()`
+//! API for continuous circular DMA reception from a UART peripheral.
+//!
+//! # Features demonstrated:
+//! - `LpuartRxDma::setup_ring_buffer()` for continuous peripheral-to-memory DMA
+//! - `RingBuffer` for async reading of received data
+//! - Handling of potential overrun conditions
+//! - Half-transfer and complete-transfer interrupts for timely wakeups
+//!
+//! # How it works:
+//! 1. Create an `LpuartRxDma` driver with a DMA channel
+//! 2. Call `setup_ring_buffer()` which handles all low-level DMA configuration
+//! 3. Application asynchronously reads data as it arrives via `ring_buf.read()`
+//! 4. Both half-transfer and complete-transfer interrupts wake the reader
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::lpuart::{Config, LpuartDma, LpuartTxDma};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Ring buffer for RX - power of 2 is ideal for modulo efficiency
+static RX_RING_BUFFER: ConstStaticCell<[u8; 64]> = ConstStaticCell::new([0; 64]);
+
+/// Helper to write a byte as hex to UART
+fn write_hex<T: embassy_mcxa::lpuart::Instance, C: embassy_mcxa::dma::Channel>(
+    tx: &mut LpuartTxDma<'_, T, C>,
+    byte: u8,
+) {
+    const HEX: &[u8; 16] = b"0123456789ABCDEF";
+    let buf = [HEX[(byte >> 4) as usize], HEX[(byte & 0x0F) as usize]];
+    tx.blocking_write(&buf).ok();
+}
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("LPUART Ring Buffer DMA example starting...");
+
+    // Create UART configuration
+    let config = Config {
+        baudrate_bps: 115_200,
+        ..Default::default()
+    };
+
+    // Create LPUART with DMA support for both TX and RX, then split
+    // This is the proper Embassy pattern - create once, split into TX and RX
+    let lpuart = LpuartDma::new(p.LPUART2, p.P2_2, p.P2_3, p.DMA_CH1, p.DMA_CH0, config).unwrap();
+    let (mut tx, rx) = lpuart.split();
+
+    tx.blocking_write(b"LPUART Ring Buffer DMA Example\r\n").unwrap();
+    tx.blocking_write(b"==============================\r\n\r\n").unwrap();
+
+    tx.blocking_write(b"Setting up circular DMA for UART RX...\r\n")
+        .unwrap();
+
+    let buf = RX_RING_BUFFER.take();
+    // Set up the ring buffer with circular DMA
+    let mut ring_buf = rx.into_ring_dma_rx(buf);
+
+    tx.blocking_write(b"Ring buffer ready! Type characters to see them echoed.\r\n")
+        .unwrap();
+    tx.blocking_write(b"The DMA continuously receives in the background.\r\n\r\n")
+        .unwrap();
+
+    // Main loop: read from ring buffer and echo back
+    let mut read_buf = [0u8; 16];
+    let mut total_received: usize = 0;
+
+    loop {
+        // Async read - waits until data is available
+        match ring_buf.read(&mut read_buf).await {
+            Ok(n) if n > 0 => {
+                total_received += n;
+
+                // Echo back what we received
+                tx.blocking_write(b"RX[").unwrap();
+                for (i, &byte) in read_buf.iter().enumerate().take(n) {
+                    write_hex(&mut tx, byte);
+                    if i < n - 1 {
+                        tx.blocking_write(b" ").unwrap();
+                    }
+                }
+                tx.blocking_write(b"]: ").unwrap();
+                tx.blocking_write(&read_buf[..n]).unwrap();
+                tx.blocking_write(b"\r\n").unwrap();
+
+                defmt::info!("Received {} bytes, total: {}", n, total_received);
+            }
+            Ok(_) => {
+                // No data, shouldn't happen with async read
+            }
+            Err(_) => {
+                // Overrun detected
+                tx.blocking_write(b"ERROR: Ring buffer overrun!\r\n").unwrap();
+                defmt::error!("Ring buffer overrun!");
+                ring_buf.clear();
+            }
+        }
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_channel_link.rs b/examples/mcxa/src/bin/raw_dma_channel_link.rs
new file mode 100644
index 000000000..74785e4f3
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_channel_link.rs
@@ -0,0 +1,278 @@
+//! DMA channel linking example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates DMA channel linking (minor and major loop linking):
+//! - Channel 0: Transfers SRC_BUFFER to DEST_BUFFER0, with:
+//!   - Minor Link to Channel 1 (triggers CH1 after each minor loop)
+//!   - Major Link to Channel 2 (triggers CH2 after major loop completes)
+//! - Channel 1: Transfers SRC_BUFFER to DEST_BUFFER1 (triggered by CH0 minor link)
+//! - Channel 2: Transfers SRC_BUFFER to DEST_BUFFER2 (triggered by CH0 major link)
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - Channel linking with `set_minor_link()` and `set_major_link()`
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use embassy_mcxa::pac;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Buffers
+static SRC_BUFFER: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([1, 2, 3, 4]);
+static DEST_BUFFER0: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DEST_BUFFER1: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+static DEST_BUFFER2: ConstStaticCell<[u32; 4]> = ConstStaticCell::new([0; 4]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA channel link example starting...");
+
+    // DMA is initialized during hal::init() - no need to call ensure_init()
+
+    let pac_periphs = unsafe { pac::Peripherals::steal() };
+    let dma0 = &pac_periphs.dma0;
+    let edma = unsafe { &*pac::Edma0Tcd0::ptr() };
+
+    // Clear any residual state
+    for i in 0..3 {
+        let t = edma.tcd(i);
+        t.ch_csr().write(|w| w.erq().disable().done().clear_bit_by_one());
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+        t.ch_es().write(|w| w.err().clear_bit_by_one());
+        t.ch_mux().write(|w| unsafe { w.bits(0) });
+    }
+
+    // Clear Global Halt/Error state
+    dma0.mp_csr().modify(|_, w| {
+        w.halt()
+            .normal_operation()
+            .hae()
+            .normal_operation()
+            .ecx()
+            .normal_operation()
+            .cx()
+            .normal_operation()
+    });
+
+    defmt::info!("EDMA channel link example begin.");
+
+    // Initialize buffers
+    let src = SRC_BUFFER.take();
+    let dst0 = DEST_BUFFER0.take();
+    let dst1 = DEST_BUFFER1.take();
+    let dst2 = DEST_BUFFER2.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("DEST0 (before): {=[?]}", dst0.as_slice());
+    defmt::info!("DEST1 (before): {=[?]}", dst1.as_slice());
+    defmt::info!("DEST2 (before): {=[?]}", dst2.as_slice());
+
+    defmt::info!("Configuring DMA channels with Embassy-style API...");
+
+    let ch0 = DmaChannel::new(p.DMA_CH0);
+    let ch1 = DmaChannel::new(p.DMA_CH1);
+    let ch2 = DmaChannel::new(p.DMA_CH2);
+
+    // Configure channels using direct TCD access (advanced feature demo)
+    // This example demonstrates channel linking which requires direct TCD manipulation
+
+    // Helper to configure TCD for memory-to-memory transfer
+    // Parameters: channel, src, dst, width, nbytes (minor loop), count (major loop), interrupt
+    #[allow(clippy::too_many_arguments)]
+    unsafe fn configure_tcd(
+        edma: &embassy_mcxa::pac::edma_0_tcd0::RegisterBlock,
+        ch: usize,
+        src: u32,
+        dst: u32,
+        width: u8,
+        nbytes: u32,
+        count: u16,
+        enable_int: bool,
+    ) {
+        let t = edma.tcd(ch);
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr().write(|w| w.saddr().bits(src));
+        t.tcd_daddr().write(|w| w.daddr().bits(dst));
+
+        // Offsets: increment by width
+        t.tcd_soff().write(|w| w.soff().bits(width as u16));
+        t.tcd_doff().write(|w| w.doff().bits(width as u16));
+
+        // Attributes: size = log2(width)
+        let size = match width {
+            1 => 0,
+            2 => 1,
+            4 => 2,
+            _ => 0,
+        };
+        t.tcd_attr().write(|w| w.ssize().bits(size).dsize().bits(size));
+
+        // Number of bytes per minor loop
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Major loop: reset source address after major loop
+        let total_bytes = nbytes * count as u32;
+        t.tcd_slast_sda()
+            .write(|w| w.slast_sda().bits(-(total_bytes as i32) as u32));
+        t.tcd_dlast_sga()
+            .write(|w| w.dlast_sga().bits(-(total_bytes as i32) as u32));
+
+        // Major loop count
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(count));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(count));
+
+        // Control/status: enable interrupt if requested
+        if enable_int {
+            t.tcd_csr().write(|w| w.intmajor().set_bit());
+        } else {
+            t.tcd_csr().write(|w| w.intmajor().clear_bit());
+        }
+
+        cortex_m::asm::dsb();
+    }
+
+    unsafe {
+        // Channel 0: Transfer 16 bytes total (8 bytes per minor loop, 2 major iterations)
+        // Minor Link -> Channel 1
+        // Major Link -> Channel 2
+        configure_tcd(
+            edma,
+            0,
+            src.as_ptr() as u32,
+            dst0.as_mut_ptr() as u32,
+            4,     // src width
+            8,     // nbytes (minor loop = 2 words)
+            2,     // count (major loop = 2 iterations)
+            false, // no interrupt
+        );
+        ch0.set_minor_link(1); // Link to CH1 after each minor loop
+        ch0.set_major_link(2); // Link to CH2 after major loop
+
+        // Channel 1: Transfer 16 bytes (triggered by CH0 minor link)
+        configure_tcd(
+            edma,
+            1,
+            src.as_ptr() as u32,
+            dst1.as_mut_ptr() as u32,
+            4,
+            16, // full buffer in one minor loop
+            1,  // 1 major iteration
+            false,
+        );
+
+        // Channel 2: Transfer 16 bytes (triggered by CH0 major link)
+        configure_tcd(
+            edma,
+            2,
+            src.as_ptr() as u32,
+            dst2.as_mut_ptr() as u32,
+            4,
+            16,   // full buffer in one minor loop
+            1,    // 1 major iteration
+            true, // enable interrupt
+        );
+    }
+
+    defmt::info!("Triggering Channel 0 (1st minor loop)...");
+
+    // Trigger first minor loop of CH0
+    unsafe {
+        ch0.trigger_start();
+    }
+
+    // Wait for CH1 to complete (triggered by CH0 minor link)
+    while !ch1.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch1.clear_done();
+    }
+
+    defmt::info!("CH1 done (via minor link).");
+    defmt::info!("Triggering Channel 0 (2nd minor loop)...");
+
+    // Trigger second minor loop of CH0
+    unsafe {
+        ch0.trigger_start();
+    }
+
+    // Wait for CH0 major loop to complete
+    while !ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch0.clear_done();
+    }
+
+    defmt::info!("CH0 major loop done.");
+
+    // Wait for CH2 to complete (triggered by CH0 major link)
+    // Using is_done() instead of AtomicBool - the standard interrupt handler
+    // clears the interrupt flag and wakes wakers, but DONE bit remains set
+    while !ch2.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        ch2.clear_done();
+    }
+
+    defmt::info!("CH2 done (via major link).");
+
+    defmt::info!("EDMA channel link example finish.");
+
+    defmt::info!("DEST0 (after): {=[?]}", dst0.as_slice());
+    defmt::info!("DEST1 (after): {=[?]}", dst1.as_slice());
+    defmt::info!("DEST2 (after): {=[?]}", dst2.as_slice());
+
+    // Verify all buffers match source
+    let mut success = true;
+    for sli in [dst0, dst1, dst2] {
+        success &= sli == src;
+    }
+
+    if success {
+        defmt::info!("PASS: Data verified.");
+    } else {
+        defmt::error!("FAIL: Mismatch detected!");
+    }
+
+    loop {
+        cortex_m::asm::wfe();
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs b/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs
new file mode 100644
index 000000000..a383b6cf4
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_interleave_transfer.rs
@@ -0,0 +1,141 @@
+//! DMA interleaved transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA with custom source/destination offsets
+//! to interleave data during transfer.
+//!
+//! # Embassy-style features demonstrated:
+//! - `TransferOptions::default()` for configuration (used internally)
+//! - DMA channel with `DmaChannel::new()`
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 16;
+const HALF_BUFF_LENGTH: usize = BUFFER_LENGTH / 2;
+
+// Buffers in RAM
+static SRC_BUFFER: ConstStaticCell<[u32; HALF_BUFF_LENGTH]> = ConstStaticCell::new([0; HALF_BUFF_LENGTH]);
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA interleave transfer example starting...");
+
+    defmt::info!("EDMA interleave transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC_BUFFER.take();
+    *src = [1, 2, 3, 4, 5, 6, 7, 8];
+    let dst = DEST_BUFFER.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure interleaved transfer using direct TCD access:
+    // - src_offset = 4: advance source by 4 bytes after each read
+    // - dst_offset = 8: advance dest by 8 bytes after each write
+    // This spreads source data across every other word in destination
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source/destination addresses
+        t.tcd_saddr().write(|w| w.saddr().bits(src.as_ptr() as u32));
+        t.tcd_daddr().write(|w| w.daddr().bits(dst.as_mut_ptr() as u32));
+
+        // Custom offsets for interleaving
+        t.tcd_soff().write(|w| w.soff().bits(4)); // src: +4 bytes per read
+        t.tcd_doff().write(|w| w.doff().bits(8)); // dst: +8 bytes per write
+
+        // Attributes: 32-bit transfers (size = 2)
+        t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2));
+
+        // Transfer entire source buffer in one minor loop
+        let nbytes = (HALF_BUFF_LENGTH * 4) as u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Reset source address after major loop
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(-(nbytes as i32) as u32));
+        // Destination uses 2x offset, so adjust accordingly
+        let dst_total = (HALF_BUFF_LENGTH * 8) as u32;
+        t.tcd_dlast_sga()
+            .write(|w| w.dlast_sga().bits(-(dst_total as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        defmt::info!("Triggering transfer...");
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    defmt::info!("EDMA interleave transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: Even indices should match SRC_BUFFER[i/2], odd indices should be 0
+    let mut mismatch = false;
+    let diter = dst.chunks_exact(2);
+    let siter = src.iter();
+    for (ch, src) in diter.zip(siter) {
+        mismatch |= !matches!(ch, [a, 0] if a == src);
+    }
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_memset.rs b/examples/mcxa/src/bin/raw_dma_memset.rs
new file mode 100644
index 000000000..7b3c06ffa
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_memset.rs
@@ -0,0 +1,129 @@
+//! DMA memset example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA to fill a buffer with a repeated pattern.
+//! The source address stays fixed while the destination increments.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::is_done()` and `clear_done()` helper methods
+//! - No need to pass register block around
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::DmaChannel;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+const BUFFER_LENGTH: usize = 4;
+
+// Buffers in RAM
+static PATTERN: u32 = 0xDEADBEEF;
+static DEST_BUFFER: ConstStaticCell<[u32; BUFFER_LENGTH]> = ConstStaticCell::new([0; BUFFER_LENGTH]);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA memset example starting...");
+    defmt::info!("EDMA memset example begin.");
+
+    // Initialize buffers
+    let pat = &PATTERN;
+    let dst = DEST_BUFFER.take();
+    defmt::info!("Pattern Value: {=u32}", pat);
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring DMA with Embassy-style API...");
+
+    // Create DMA channel using Embassy-style API
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure memset transfer using direct TCD access:
+    // Source stays fixed (soff = 0, reads same pattern repeatedly)
+    // Destination increments (doff = 4)
+    unsafe {
+        let t = dma_ch0.tcd();
+
+        // Reset channel state
+        t.ch_csr().write(|w| {
+            w.erq()
+                .disable()
+                .earq()
+                .disable()
+                .eei()
+                .no_error()
+                .ebw()
+                .disable()
+                .done()
+                .clear_bit_by_one()
+        });
+        t.ch_es().write(|w| w.bits(0));
+        t.ch_int().write(|w| w.int().clear_bit_by_one());
+
+        // Source address (pattern) - fixed
+        t.tcd_saddr().write(|w| w.saddr().bits(pat as *const _ as u32));
+        // Destination address - increments
+        t.tcd_daddr().write(|w| w.daddr().bits(dst.as_mut_ptr() as u32));
+
+        // Source offset = 0 (stays fixed), Dest offset = 4 (increments)
+        t.tcd_soff().write(|w| w.soff().bits(0));
+        t.tcd_doff().write(|w| w.doff().bits(4));
+
+        // Attributes: 32-bit transfers (size = 2)
+        t.tcd_attr().write(|w| w.ssize().bits(2).dsize().bits(2));
+
+        // Transfer entire buffer in one minor loop
+        let nbytes = (BUFFER_LENGTH * 4) as u32;
+        t.tcd_nbytes_mloffno().write(|w| w.nbytes().bits(nbytes));
+
+        // Source doesn't need adjustment (stays fixed)
+        t.tcd_slast_sda().write(|w| w.slast_sda().bits(0));
+        // Reset dest address after major loop
+        t.tcd_dlast_sga().write(|w| w.dlast_sga().bits(-(nbytes as i32) as u32));
+
+        // Major loop count = 1
+        t.tcd_biter_elinkno().write(|w| w.biter().bits(1));
+        t.tcd_citer_elinkno().write(|w| w.citer().bits(1));
+
+        // Enable interrupt on major loop completion
+        t.tcd_csr().write(|w| w.intmajor().set_bit());
+
+        cortex_m::asm::dsb();
+
+        defmt::info!("Triggering transfer...");
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for completion using channel helper method
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+    unsafe {
+        dma_ch0.clear_done();
+    }
+
+    defmt::info!("EDMA memset example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: All elements should equal PATTERN
+    let mismatch = dst.iter().any(|i| *i != *pat);
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs b/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs
new file mode 100644
index 000000000..80df40449
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_ping_pong_transfer.rs
@@ -0,0 +1,244 @@
+//! DMA ping-pong/double-buffer transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates two approaches for ping-pong/double-buffering:
+//!
+//! ## Approach 1: Scatter/Gather with linked TCDs (manual)
+//! - Two TCDs link to each other for alternating transfers
+//! - Uses custom handler that delegates to on_interrupt() then signals completion
+//! - Note: With ESG=1, DONE bit is cleared by hardware when next TCD loads,
+//!   so we need an AtomicBool to track completion
+//!
+//! ## Approach 2: Half-transfer interrupt with wait_half() (NEW!)
+//! - Single continuous transfer over entire buffer
+//! - Uses half-transfer interrupt to know when first half is ready
+//! - Application can process first half while second half is being filled
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - Scatter/gather with linked TCDs
+//! - Custom handler that delegates to HAL's `on_interrupt()` (best practice)
+//! - Standard `DmaCh1InterruptHandler` with `bind_interrupts!` macro
+//! - NEW: `wait_half()` for half-transfer interrupt handling
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, Tcd, TransferOptions};
+use embassy_mcxa::pac;
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source and destination buffers for Approach 1 (scatter/gather)
+static SRC: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([1, 2, 3, 4, 5, 6, 7, 8]);
+static DST: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0; 8]);
+
+// Source and destination buffers for Approach 2 (wait_half)
+static SRC2: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0xA1, 0xA2, 0xA3, 0xA4, 0xB1, 0xB2, 0xB3, 0xB4]);
+static DST2: ConstStaticCell<[u32; 8]> = ConstStaticCell::new([0; 8]);
+
+// TCD pool for scatter/gather - must be 32-byte aligned
+#[repr(C, align(32))]
+struct TcdPool([Tcd; 2]);
+
+static TCD_POOL: ConstStaticCell<TcdPool> = ConstStaticCell::new(TcdPool(
+    [Tcd {
+        saddr: 0,
+        soff: 0,
+        attr: 0,
+        nbytes: 0,
+        slast: 0,
+        daddr: 0,
+        doff: 0,
+        citer: 0,
+        dlast_sga: 0,
+        csr: 0,
+        biter: 0,
+    }; 2],
+));
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA ping-pong transfer example starting...");
+
+    defmt::info!("EDMA ping-pong transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC.take();
+    let dst = DST.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+
+    defmt::info!("Configuring ping-pong DMA with Embassy-style API...");
+
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+
+    // Configure ping-pong transfer using direct TCD access:
+    // This sets up TCD0 and TCD1 in RAM, and loads TCD0 into the channel.
+    // TCD0 transfers first half (SRC[0..4] -> DST[0..4]), links to TCD1.
+    // TCD1 transfers second half (SRC[4..8] -> DST[4..8]), links to TCD0.
+    let tcds = &mut TCD_POOL.take().0;
+
+    let half_len = 4usize;
+    let half_bytes = (half_len * 4) as u32;
+
+    unsafe {
+        let tcd0_addr = &tcds[0] as *const _ as u32;
+        let tcd1_addr = &tcds[1] as *const _ as u32;
+
+        // TCD0: First half -> Links to TCD1
+        tcds[0] = Tcd {
+            saddr: src.as_ptr() as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: half_bytes,
+            slast: 0,
+            daddr: dst.as_mut_ptr() as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcd1_addr as i32,
+            csr: 0x0012, // ESG | INTMAJOR
+            biter: 1,
+        };
+
+        // TCD1: Second half -> Links to TCD0
+        tcds[1] = Tcd {
+            saddr: src.as_ptr().add(half_len) as u32,
+            soff: 4,
+            attr: 0x0202,
+            nbytes: half_bytes,
+            slast: 0,
+            daddr: dst.as_mut_ptr().add(half_len) as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcd0_addr as i32,
+            csr: 0x0012,
+            biter: 1,
+        };
+
+        // Load TCD0 into hardware registers
+        dma_ch0.load_tcd(&tcds[0]);
+    }
+
+    defmt::info!("Triggering first half transfer...");
+
+    // Trigger first transfer (first half: SRC[0..4] -> DST[0..4])
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    let tcd = dma_ch0.tcd();
+    // Wait for first half
+    loop {
+        if tcd.tcd_saddr().read().bits() != src.as_ptr() as u32 {
+            break;
+        }
+    }
+
+    defmt::info!("First half transferred.");
+    defmt::info!("Triggering second half transfer...");
+
+    // Trigger second transfer (second half: SRC[4..8] -> DST[4..8])
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for second half
+    loop {
+        if tcd.tcd_saddr().read().bits() != unsafe { src.as_ptr().add(half_len) } as u32 {
+            break;
+        }
+    }
+
+    defmt::info!("Second half transferred.");
+
+    defmt::info!("EDMA ping-pong transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: DST should match SRC
+    let mismatch = src != dst;
+
+    if mismatch {
+        defmt::error!("FAIL: Approach 1 mismatch detected!");
+    } else {
+        defmt::info!("PASS: Approach 1 data verified.");
+    }
+
+    // =========================================================================
+    // Approach 2: Half-Transfer Interrupt with wait_half() (NEW!)
+    // =========================================================================
+    //
+    // This approach uses a single continuous DMA transfer with half-transfer
+    // interrupt enabled. The wait_half() method allows you to be notified
+    // when the first half of the buffer is complete, so you can process it
+    // while the second half is still being filled.
+    //
+    // Benefits:
+    // - Simpler setup (no TCD pool needed)
+    // - True async/await support
+    // - Good for streaming data processing
+
+    defmt::info!("--- Approach 2: wait_half() demo ---");
+
+    // Enable DMA CH1 interrupt
+    unsafe {
+        cortex_m::peripheral::NVIC::unmask(pac::Interrupt::DMA_CH1);
+    }
+
+    // Initialize approach 2 buffers
+    let src2 = SRC2.take();
+    let dst2 = DST2.take();
+
+    defmt::info!("SRC2: {=[?]}", src2.as_slice());
+
+    let dma_ch1 = DmaChannel::new(p.DMA_CH1);
+
+    // Configure transfer with half-transfer interrupt enabled
+    let mut options = TransferOptions::default();
+    options.half_transfer_interrupt = true; // Enable half-transfer interrupt
+    options.complete_transfer_interrupt = true;
+
+    defmt::info!("Starting transfer with half_transfer_interrupt...");
+
+    // Create the transfer
+    let mut transfer = dma_ch1.mem_to_mem(src2, dst2, options).unwrap();
+
+    // Wait for half-transfer (first 4 elements)
+    defmt::info!("Waiting for first half...");
+    let _ok = transfer.wait_half().await.unwrap();
+
+    defmt::info!("Half-transfer complete!");
+
+    // Wait for complete transfer
+    defmt::info!("Waiting for second half...");
+    transfer.await.unwrap();
+
+    defmt::info!("Transfer complete! Full DST2: {=[?]}", dst2.as_slice());
+
+    // Verify approach 2
+    let mismatch2 = src2 != dst2;
+
+    if mismatch2 {
+        defmt::error!("FAIL: Approach 2 mismatch!");
+    } else {
+        defmt::info!("PASS: Approach 2 verified.");
+    }
+
+    defmt::info!("=== All ping-pong demos complete ===");
+}
diff --git a/examples/mcxa/src/bin/raw_dma_scatter_gather.rs b/examples/mcxa/src/bin/raw_dma_scatter_gather.rs
new file mode 100644
index 000000000..eb9960764
--- /dev/null
+++ b/examples/mcxa/src/bin/raw_dma_scatter_gather.rs
@@ -0,0 +1,165 @@
+//! DMA scatter-gather transfer example for MCXA276.
+//!
+//! NOTE: this is a "raw dma" example! It exists as a proof of concept, as we don't have
+//! a high-level and safe API for. It should not be taken as typical, recommended, or
+//! stable usage!
+//!
+//! This example demonstrates using DMA with scatter/gather to chain multiple
+//! transfer descriptors. The first TCD transfers the first half of the buffer,
+//! then automatically loads the second TCD to transfer the second half.
+//!
+//! # Embassy-style features demonstrated:
+//! - `DmaChannel::new()` for channel creation
+//! - Scatter/gather with chained TCDs
+//! - Custom handler that delegates to HAL's `on_interrupt()` (best practice)
+
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::clocks::config::Div8;
+use embassy_mcxa::dma::{DmaChannel, Tcd};
+use static_cell::ConstStaticCell;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+// Source and destination buffers
+static SRC: ConstStaticCell<[u32; 12]> = ConstStaticCell::new([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]);
+static DST: ConstStaticCell<[u32; 12]> = ConstStaticCell::new([0; 12]);
+
+// TCD pool for scatter/gather - must be 32-byte aligned
+#[repr(C, align(32))]
+struct TcdPool([Tcd; 2]);
+
+static TCD_POOL: ConstStaticCell<TcdPool> = ConstStaticCell::new(TcdPool(
+    [Tcd {
+        saddr: 0,
+        soff: 0,
+        attr: 0,
+        nbytes: 0,
+        slast: 0,
+        daddr: 0,
+        doff: 0,
+        citer: 0,
+        dlast_sga: 0,
+        csr: 0,
+        biter: 0,
+    }; 2],
+));
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    // Small delay to allow probe-rs to attach after reset
+    for _ in 0..100_000 {
+        cortex_m::asm::nop();
+    }
+
+    let mut cfg = hal::config::Config::default();
+    cfg.clock_cfg.sirc.fro_12m_enabled = true;
+    cfg.clock_cfg.sirc.fro_lf_div = Some(Div8::no_div());
+    let p = hal::init(cfg);
+
+    defmt::info!("DMA scatter-gather transfer example starting...");
+
+    defmt::info!("EDMA scatter-gather transfer example begin.");
+
+    // Initialize buffers
+    let src = SRC.take();
+    let dst = DST.take();
+
+    defmt::info!("Source Buffer: {=[?]}", src.as_slice());
+    defmt::info!("Destination Buffer (before): {=[?]}", dst.as_slice());
+    defmt::info!("Configuring scatter-gather DMA with Embassy-style API...");
+
+    let dma_ch0 = DmaChannel::new(p.DMA_CH0);
+    let src_ptr = src.as_ptr();
+    let dst_ptr = dst.as_mut_ptr();
+
+    // Configure scatter-gather transfer using direct TCD access:
+    // This sets up TCD0 and TCD1 in RAM, and loads TCD0 into the channel.
+    // TCD0 transfers first half (SRC[0..4] -> DST[0..4]), then loads TCD1.
+    // TCD1 transfers second half (SRC[4..12] -> DST[4..12]), last TCD.
+    unsafe {
+        let tcds = &mut TCD_POOL.take().0;
+
+        // In the first transfer, copy
+        tcds[0] = Tcd {
+            saddr: src_ptr as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: 4 * 4,
+            slast: 0,
+            daddr: dst_ptr as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: tcds.as_ptr().add(1) as i32,
+            // ESG (scatter/gather) for non-last, INTMAJOR for all
+            csr: 0x0012,
+            biter: 1,
+        };
+
+        tcds[1] = Tcd {
+            saddr: src_ptr.add(4) as u32,
+            soff: 4,
+            attr: 0x0202, // 32-bit src/dst
+            nbytes: 8 * 4,
+            slast: 0,
+            daddr: dst_ptr.add(4) as u32,
+            doff: 4,
+            citer: 1,
+            dlast_sga: 0,
+            // ESG (scatter/gather) for non-last, INTMAJOR for all
+            csr: 0x0002,
+            biter: 1,
+        };
+
+        // Load TCD0 into hardware registers
+        dma_ch0.load_tcd(&tcds[0]);
+    }
+
+    defmt::info!("Triggering first half transfer...");
+
+    let tcd = dma_ch0.tcd();
+
+    // Trigger first transfer (first half: SRC[0..4] -> DST[0..4])
+    // TCD0 is currently loaded.
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for first half
+    loop {
+        if tcd.tcd_saddr().read().bits() != src_ptr as u32 {
+            defmt::info!("saddr: {=u32}", tcd.tcd_saddr().read().bits());
+            defmt::info!("srptr: {=u32}", src_ptr as u32);
+            break;
+        }
+    }
+
+    defmt::info!("First half transferred.");
+    defmt::info!("Triggering second half transfer...");
+
+    // Trigger second transfer (second half: SRC[4..8] -> DST[4..8])
+    // TCD1 should have been loaded by the scatter/gather engine.
+    unsafe {
+        dma_ch0.trigger_start();
+    }
+
+    // Wait for second half
+    while !dma_ch0.is_done() {
+        cortex_m::asm::nop();
+    }
+
+    defmt::info!("Second half transferred.");
+
+    defmt::info!("EDMA scatter-gather transfer example finish.");
+    defmt::info!("Destination Buffer (after): {=[?]}", dst.as_slice());
+
+    // Verify: DST should match SRC
+    let mismatch = src != dst;
+
+    if mismatch {
+        defmt::error!("FAIL: Mismatch detected!");
+    } else {
+        defmt::info!("PASS: Data verified.");
+    }
+}
diff --git a/examples/mcxa/src/bin/reset-reason.rs b/examples/mcxa/src/bin/reset-reason.rs
new file mode 100644
index 000000000..c244fbe04
--- /dev/null
+++ b/examples/mcxa/src/bin/reset-reason.rs
@@ -0,0 +1,15 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::config::Config;
+use hal::reset_reason::reset_reason;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let _p = hal::init(config);
+
+    defmt::info!("Reset Reason: '{}'", reset_reason());
+}
diff --git a/examples/mcxa/src/bin/rtc_alarm.rs b/examples/mcxa/src/bin/rtc_alarm.rs
new file mode 100644
index 000000000..fe355888b
--- /dev/null
+++ b/examples/mcxa/src/bin/rtc_alarm.rs
@@ -0,0 +1,47 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use embassy_mcxa::bind_interrupts;
+use hal::rtc::{InterruptHandler, Rtc, RtcDateTime};
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(struct Irqs {
+    RTC => InterruptHandler<hal::rtc::Rtc0>;
+});
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let p = hal::init(hal::config::Config::default());
+
+    defmt::info!("=== RTC Alarm Example ===");
+
+    let rtc_config = hal::rtc::get_default_config();
+
+    let mut rtc = Rtc::new(p.RTC0, Irqs, rtc_config);
+
+    let now = RtcDateTime {
+        year: 2025,
+        month: 10,
+        day: 15,
+        hour: 14,
+        minute: 30,
+        second: 0,
+    };
+
+    rtc.stop();
+
+    defmt::info!("Time set to: 2025-10-15 14:30:00");
+    rtc.set_datetime(now);
+
+    let mut alarm = now;
+    alarm.second += 10;
+
+    defmt::info!("Alarm set for: 2025-10-15 14:30:10 (+10 seconds)");
+    defmt::info!("RTC started, waiting for alarm...");
+
+    rtc.wait_for_alarm(alarm).await;
+    defmt::info!("*** ALARM TRIGGERED! ***");
+
+    defmt::info!("Example complete - Test PASSED!");
+}
diff --git a/examples/mcxa/src/bin/trng.rs b/examples/mcxa/src/bin/trng.rs
new file mode 100644
index 000000000..5f6e2408c
--- /dev/null
+++ b/examples/mcxa/src/bin/trng.rs
@@ -0,0 +1,106 @@
+#![no_std]
+#![no_main]
+
+use embassy_executor::Spawner;
+use hal::bind_interrupts;
+use hal::config::Config;
+use hal::trng::{self, InterruptHandler, Trng};
+use rand_core::RngCore;
+use {defmt_rtt as _, embassy_mcxa as hal, panic_probe as _};
+
+bind_interrupts!(
+    struct Irqs {
+        TRNG0 => InterruptHandler;
+    }
+);
+
+#[embassy_executor::main]
+async fn main(_spawner: Spawner) {
+    let config = Config::default();
+    let mut p = hal::init(config);
+
+    defmt::info!("TRNG example");
+
+    let mut trng = Trng::new_blocking_128(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("128-bit {}", rand);
+
+    drop(trng);
+
+    let mut trng = Trng::new_blocking_256(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("256-bit {}", rand);
+
+    drop(trng);
+
+    let mut trng = Trng::new_blocking_512(p.TRNG0.reborrow());
+    let rand = trng.blocking_next_u32();
+    defmt::info!("512-bit {}", rand);
+
+    drop(trng);
+
+    let config = trng::Config::default();
+    let mut trng = Trng::new_blocking_with_custom_config(p.TRNG0.reborrow(), config);
+
+    defmt::info!("========== BLOCKING ==========");
+
+    defmt::info!("Generate 10 u32");
+    for _ in 0..10 {
+        let rand = trng.blocking_next_u32();
+        defmt::info!("{}", rand);
+    }
+
+    defmt::info!("Generate 10 u64");
+    for _ in 0..10 {
+        let rand = trng.blocking_next_u64();
+        defmt::info!("{}", rand);
+    }
+
+    let mut buf = [0_u8; 256];
+
+    defmt::info!("Generate 10 256-byte buffers");
+    for _ in 0..10 {
+        trng.blocking_fill_bytes(&mut buf);
+        defmt::info!("{:02x}", buf);
+    }
+
+    defmt::info!("RngCore");
+
+    for _ in 0..10 {
+        defmt::info!("u32: {}", trng.next_u32());
+        defmt::info!("u64: {}", trng.next_u64());
+    }
+
+    drop(trng);
+
+    defmt::info!("========== ASYNC ==========");
+
+    let mut trng = Trng::new_with_custom_config(p.TRNG0.reborrow(), Irqs, config);
+
+    defmt::info!("Generate 10 u32");
+    for _ in 0..10 {
+        let rand = trng.async_next_u32().await.unwrap();
+        defmt::info!("{}", rand);
+    }
+
+    defmt::info!("Generate 10 u64");
+    for _ in 0..10 {
+        let rand = trng.async_next_u64().await.unwrap();
+        defmt::info!("{}", rand);
+    }
+
+    let mut buf = [0_u8; 256];
+
+    defmt::info!("Generate 10 256-byte buffers");
+    for _ in 0..10 {
+        trng.async_fill_bytes(&mut buf).await.unwrap();
+        defmt::info!("{:02x}", buf);
+    }
+
+    defmt::info!("RngCore");
+
+    for _ in 0..10 {
+        defmt::info!("u32: {}", trng.next_u32());
+        defmt::info!("u64: {}", trng.next_u64());
+    }
+}