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| author | Ralf <[email protected]> | 2022-05-11 20:56:57 +0200 |
|---|---|---|
| committer | Ralf <[email protected]> | 2022-05-12 09:09:39 +0200 |
| commit | c90968bb70e626c5d2c375befbbf19423f48ba5e (patch) | |
| tree | 791582fe12d36516d837363946bfaf948d092084 /examples/nrf/src/bin/uart_split.rs | |
| parent | 1a216958ac121befa7da6912db307516d1ddcb07 (diff) | |
stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
Diffstat (limited to 'examples/nrf/src/bin/uart_split.rs')
0 files changed, 0 insertions, 0 deletions